Array substrate

Abstract

An array substrate is provided with a display area and a peripheral area located on the periphery of the display area. The array substrate further comprises a substrate, a first transistor, a connecting electrode, a first electrode and a second electrode. The first transistor is arranged on one side of the substrate and is arranged in the display area. The first transistor comprises a first semiconductor pattern and a first electrode structure arranged on the side, away from the substrate, of the first semiconductor pattern. And the connecting electrode is arranged on one side, far away from the substrate, of the first electrode structure and is electrically connected with the first semiconductor pattern. The first electrode is arranged on the side, away from the substrate, of the connecting electrode and electrically connected with the connecting electrode. The second electrode is arranged on the side, away from the substrate, of the first electrode. Wherein at least one of the connection electrode and the first electrode structure comprises a semiconductor material.

Description

array substrate Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate. Background Art

[0002] With the rise of the concept of the metaverse, virtual reality (VR) display products have developed rapidly. VR display products with good display effects on the market now usually use micro organic light-emitting display devices (Micro OLED) products with a pixel density (Pixels Per Inch; PPI) of 2000+. However, Micro OLED products are expensive and difficult to manufacture, making them difficult to popularize.

[0003] Liquid crystal display panels have outstanding advantages in low manufacturing cost and difficulty. Thanks to the simpler pixel circuit structure of liquid crystal display panels, the pixel circuit contains a smaller number of thin film transistors (such as one thin film transistor) and capacitors. Liquid crystal display panels have good development prospects in ultra-high pixel density (such as greater than or equal to 1000PPI).

[0004] Summary of the Invention

[0005] In one aspect, an array substrate is provided. The array substrate has a display area and a peripheral area located outside the display area. The array substrate further includes a substrate, a first transistor, a connecting electrode, a first electrode, and a second electrode. The first transistor is disposed on one side of the substrate and is disposed in the display area. The first transistor includes a first semiconductor pattern and a first electrode structure disposed on a side of the first semiconductor pattern away from the substrate. The connecting electrode is disposed on a side of the first electrode structure away from the substrate and is electrically connected to the first semiconductor pattern. The first electrode is disposed on a side of the connecting electrode away from the substrate and is electrically connected to the connecting electrode. The second electrode is disposed on a side of the first electrode away from the substrate. At least one of the connecting electrode and the first electrode structure includes a semiconductor material.

[0006] In some embodiments, the array substrate further includes a second transistor. The second transistor is located on the same side of the substrate as the first transistor and is disposed in the peripheral area. The second transistor includes a second semiconductor pattern and a third semiconductor pattern. The second semiconductor pattern includes a second channel region and two second polar regions located on opposite sides of the second channel region. The third semiconductor pattern includes a third channel region and two third polar regions located on opposite sides of the third channel region. The second channel region and the third channel region are spaced apart in a direction perpendicular to the substrate, and the orthographic projection of the second channel region on the substrate at least partially overlaps with the orthographic projection of the third channel region on the substrate. The second polar region and the third polar region located on the same side of the second channel region and the third channel region are electrically connected.

[0007] In some embodiments, the second semiconductor pattern and the first semiconductor pattern include the same material and are disposed in the same layer, and / or the third semiconductor pattern and one of the connecting electrode and the first electrode structure include the same material and are disposed in the same layer.

[0008] In some embodiments, the second transistor further includes a second electrode structure, and the second electrode structure is at least partially opposite to the second channel region and at least partially opposite to the third channel region.

[0009] In some embodiments, the connecting electrode comprises a semiconductor material, and the third semiconductor pattern and the connecting electrode comprise the same material and are disposed in the same layer.

[0010] In some embodiments, the second electrode structure includes a first sub-electrode disposed between the second semiconductor pattern and the third semiconductor pattern. The first sub-electrode is disposed opposite the second channel region and the third channel region, respectively, and an orthographic projection of the first sub-electrode on the substrate at least partially overlaps with an orthographic projection of the second channel region and the third channel region on the substrate, respectively.

[0011] In some embodiments, the first sub-electrode and the first electrode structure include the same material and are disposed in the same layer.

[0012] In some embodiments, the second transistor further includes at least one switching pattern. The switching pattern is disposed between the second polar region and the third polar region, which are adjacent to each other, and is electrically connected to the second polar region and the third polar region, respectively. The switching pattern and the first sub-electrode are made of the same material and disposed in the same layer.

[0013] In some embodiments, the second electrode structure further includes a second sub-electrode disposed on a side of the second semiconductor pattern closer to the substrate. The second sub-electrode is disposed opposite the second channel region, and an orthographic projection of the second sub-electrode on the substrate at least partially overlaps with an orthographic projection of the second channel region on the substrate.

[0014] In some embodiments, the orthographic projection of the second sub-electrode on the substrate covers the orthographic projections of the second channel region and the third channel region on the substrate, and partially overlaps with the orthographic projection of at least one of the two second polar regions and the two third polar regions on the substrate. The orthographic projection of the second sub-electrode on the substrate also covers the orthographic projection of the first sub-electrode on the substrate, and a boundary of the orthographic projection of the second sub-electrode is spaced from a boundary of the orthographic projection of the first sub-electrode.

[0015] In some embodiments, the display area further includes a first signal line, disposed on a side of the first semiconductor pattern proximal to the substrate. The first semiconductor pattern includes a first channel region and two first polar regions located on opposite sides of the first channel region, one of the two first polar regions being electrically connected to the connecting electrode, and the other being electrically connected to the first signal line. The first signal line and the second sub-electrode are comprised of the same material and disposed in the same layer.

[0016] In some embodiments, the connecting electrode includes a first sub-connecting electrode and a second sub-connecting electrode, with the second sub-connecting electrode located on a side of the first sub-connecting electrode away from the substrate. The array substrate further includes a first insulating layer, a second insulating layer, a first planar layer, and a second planar layer, as well as a first via and a second via. The first insulating layer is disposed between the first semiconductor pattern and the first electrode structure. The second insulating layer is disposed between the first electrode structure and the first sub-connecting electrode. The first via penetrates the second insulating layer and the first insulating layer, exposing a portion of the first semiconductor pattern. The first sub-connecting electrode includes a first portion and a second portion, the first portion electrically connected to the first semiconductor pattern through the first via, and the second portion located on a surface of the second insulating layer away from the substrate. The first planar layer is disposed between the first sub-connecting electrode and the second sub-connecting electrode. The second via penetrates the first planar layer. The second via exposes at least a portion of the second portion, and the second sub-connecting electrode is connected to the second portion through the second via. The portion of the second sub-connecting electrode located within the second via includes a groove recessed toward the side closer to the substrate. The second flat layer is disposed between the second sub-connecting electrode and the first electrode, and is disposed within the groove. A surface of the second flat layer away from the substrate is substantially flush with a surface of the second sub-connecting electrode away from the substrate. The third semiconductor pattern and the first sub-connecting electrode are comprised of the same material and disposed on the same layer.

[0017] In some embodiments, the first electrode structure includes an auxiliary electrode and an electrode portion, the electrode portion is located on a side of the auxiliary electrode away from the substrate, the auxiliary electrode includes a semiconductor material, and the third semiconductor pattern and the auxiliary electrode include the same material and are arranged in the same layer.

[0018] In some embodiments, the second electrode structure includes a third sub-electrode disposed on a side of the third semiconductor pattern away from the substrate, and a fourth sub-electrode disposed on a side of the second semiconductor pattern closer to the substrate. The third sub-electrode is disposed opposite the third semiconductor pattern, and an orthographic projection of the third sub-electrode on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate. The fourth sub-electrode is disposed opposite the second semiconductor pattern, and an orthographic projection of the fourth sub-electrode on the substrate at least partially overlaps with an orthographic projection of the second channel region on the substrate.

[0019] In some embodiments, the third sub-electrode and the electrode portion include the same material and are provided in the same layer.

[0020] In some embodiments, the display area further includes a first signal line, disposed on a side of the first semiconductor pattern proximal to the substrate. The first semiconductor pattern includes a first channel region and two first polar regions located on opposite sides of the first channel region, one of the two first polar regions being electrically connected to the connecting electrode, and the other being electrically connected to the first signal line. The first signal line and the fourth sub-electrode are comprised of the same material and disposed in the same layer.

[0021] In some embodiments, a third insulating layer is included between the auxiliary electrode and the electrode portion. The auxiliary electrode and the electrode portion are electrically connected in the display area; and / or the auxiliary electrode and the electrode portion are electrically connected in the peripheral area.

[0022] In some embodiments, the array substrate further comprises a first insulating layer, a second insulating layer, a first planar layer, and a second planar layer. The first insulating layer is disposed between the first semiconductor pattern and the first electrode structure. The second insulating layer and the first planar layer are disposed between the first electrode structure and the connecting electrode, with the first planar layer being located further away from the substrate than the second insulating layer. The third via penetrates the first planar layer, the second insulating layer, the third insulating layer, and the first insulating layer, exposing a portion of the first semiconductor pattern. The connecting electrode comprises a third portion and a fourth portion, the third portion being electrically connected to the first semiconductor pattern through the third via, and the fourth portion being located on a surface of the first planar layer away from the substrate and electrically connected to the first electrode. The third portion comprises a groove portion that is recessed toward a side closer to the substrate, the second planar layer being disposed between the connecting electrode and the first electrode, and the second planar layer being disposed within the groove portion, and the surface of the second planar layer away from the substrate being substantially flush with the surface of the fourth portion away from the substrate.

[0023] In some embodiments, the second semiconductor pattern and the third semiconductor pattern each include a metal oxide semiconductor material, the second semiconductor pattern has greater electron mobility than the third semiconductor pattern, and the third semiconductor pattern has greater light stability than the second semiconductor pattern.

[0024] In some embodiments, the second semiconductor pattern includes a high-mobility metal oxide semiconductor material; and / or the third semiconductor pattern includes indium gallium zinc oxide.

[0025] In some embodiments, the array substrate further includes a third transistor. The third transistor is disposed on a side of the first transistor closer to the substrate and in the peripheral region. The third transistor includes a fourth semiconductor pattern and a third electrode structure, wherein the third electrode structure is located on a side of the fourth semiconductor pattern farther from the substrate. The fourth semiconductor pattern and the first semiconductor pattern are comprised of different semiconductor materials.

[0026] In some embodiments, the first transistor is an oxide thin film transistor; and / or the third transistor is a low temperature polysilicon thin film transistor.

[0027] In some embodiments, the array substrate further includes a first signal line, a buffer layer, and a fourth via. The first signal line is disposed in the display area and on a side of the first semiconductor pattern closer to the substrate. The buffer layer is disposed between the first signal line and the first semiconductor pattern. The fourth via penetrates the buffer layer and exposes a portion of the first signal line. Part of the first semiconductor pattern is located within the fourth via and is electrically connected to the first signal line through the fourth via.

[0028] In some embodiments, the fourth via hole exposes two opposite sidewalls of the first signal line, and an orthographic projection of the first semiconductor pattern on the substrate covers at least 1 / 2 of the orthographic projection of the fourth via hole on the substrate.

[0029] In some embodiments, the buffer layer includes a first sublayer and a second sublayer stacked in a direction away from the substrate; a material of the first sublayer includes silicon nitride, and a material of the second sublayer includes silicon oxide.

[0030] In some embodiments, the thickness of the first sub-layer is greater than or equal to 50 nm. And / or, the array substrate further includes a first insulating layer. The first insulating layer is disposed between the first semiconductor pattern and the first electrode structure, and the thickness of the first insulating layer is 80 nm to 150 nm.

[0031] In some embodiments, when the array substrate includes a third transistor, the third electrode structure and the first signal line include the same material and are provided in the same layer.

[0032] In some embodiments, the array substrate further includes a plurality of opening areas, each of which is configured to form a light-emitting area of ​​a sub-pixel. Furthermore, the array substrate further includes a plurality of lens structures and a third planar layer. The plurality of lens structures are disposed on a side of the first transistor close to the substrate, each configured to converge light directed toward the lens structures; one lens structure covers at least one of the opening areas. The third planar layer is disposed between the lens structures and the first transistor. The refractive index of the lens structures is greater than the refractive index of the third planar layer.

[0033] In some embodiments, the refractive index of the lens structure is 1.8 to 2.3; and / or the refractive index of the third flat layer is 1.3 to 1.5.

[0034] In some embodiments, the thickness of the lens structure is 800 nm to 1500 nm; and / or the thickness of the third flat layer is 1.5 μm to 2.5 μm.

[0035] In some embodiments, one of the lens structures covers one of the opening areas; and / or, the array substrate includes a plurality of pixel units, each of the pixel units includes at least two opening areas that emit different light; and one of the lens structures covers the at least two opening areas of one of the pixel units.

[0036] In some embodiments, an orthographic projection of the lens structure on the substrate at least partially overlaps with an orthographic projection of the first signal line on the substrate.

[0037] In some embodiments, along the first direction, two adjacent lens structures are connected to each other; and / or, along the second direction, there is a gap between two adjacent lens structures.

[0038] In another aspect, a display device is provided, comprising the array substrate according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0040] FIG1A is a planar structural diagram of a display device according to some embodiments;

[0041] FIG1B is a schematic diagram of the overall structure of an AR / VR / MR display product according to some embodiments;

[0042] FIG1C is a schematic diagram of the structure of an AR / VR / MR display product according to some embodiments;

[0043] FIG2 is a structural diagram of a display device according to some embodiments;

[0044] FIG3A is a planar structural diagram of a display area of ​​an array substrate according to some embodiments; ...

[0045] FIG3B is another planar structural diagram of the display area of ​​the array substrate according to some embodiments;

[0046] FIG4A is a cross-sectional structural diagram of a display area of ​​an array substrate according to some embodiments;

[0047] FIG4B is a cross-sectional structural diagram of a display area of ​​an array substrate according to some embodiments;

[0048] FIG5 is a structural diagram of a second transistor of an array substrate according to some embodiments;

[0049] FIG6 is a diagram showing the relationship between the channel length and the threshold voltage of a metal oxide thin film transistor;

[0050] FIG7 is another structural diagram of a second transistor of an array substrate according to some embodiments;

[0051] FIG8 is another structural diagram of the second transistor of the array substrate according to some embodiments;

[0052] FIG9 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0053] FIG10 is a cross-sectional structural diagram of an array substrate according to some embodiments;

[0054] FIG11 is another planar structural diagram of the display area of ​​the array substrate according to some embodiments;

[0055] FIG12 is another planar structural diagram of the display area of ​​the array substrate according to some embodiments;

[0056] FIG13 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0057] FIG14 is a structural diagram of the first signal line when the first signal line is located above the first semiconductor pattern;

[0058] FIG15 is a structural diagram of a lens structure and an opening area according to some embodiments;

[0059] FIG16 is another structural diagram of a lens structure and an opening area according to some embodiments;

[0060] FIG17 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0061] FIG18 is another cross-sectional structural diagram of an array substrate according to some embodiments;

[0062] 19A to 19F are diagrams illustrating a manufacturing process of an array substrate according to some embodiments. DETAILED DESCRIPTION

[0063] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0064] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0065] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0066] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0067] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0068] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0069] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0070] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0071] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0072] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0073] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0074] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0075] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0076] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0077] 1A , an embodiment of the present disclosure provides a display device, wherein display device 1000 is a product having an image display function. For example, display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0078] In some embodiments, the display device may be an augmented reality (AR) device, a virtual reality (VR) device, or a mixed reality (MR) device. Alternatively, in other embodiments, the display device may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a camera view display (e.g., a rearview camera display in a vehicle), a wearable device, an in-vehicle display, an aircraft display, or any other product or component with a display function.

[0079] For example, referring to Figures 1B and 1C, when the display device is an AR / MR / VR display product, the display device 1000 may include a housing 501 and a wearable structure 503. The wearable structure 503 may be worn on a user 600, such as on the user's head. The housing 501 is used to carry and mount display components, which may include, for example, a display backplane (also referred to as a display panel) 502 and an optical assembly 504. Light emitted from the display backplane 502 is processed by the optical assembly 504 and then emitted into the user's eye 601.

[0080] In some embodiments, the display device 1000 may be a liquid crystal display (LCD) device, depending on the type of light emission. The display device 1000 may be a flat display device or a curved display device, for example, depending on the type of drive of the display device and the form of the display device 1000. The display device 1000 may be rectangular or circular, for example. Some embodiments of the present disclosure are described below using a rectangular, flat liquid crystal display device as an example. However, the present disclosure is not limited thereto, and any other display device may also be considered, as long as the same technical concept is applied.

[0081] In some embodiments, referring to FIG2 , the display device 1000 includes a display panel 1100 and a driving circuit board (not shown in the figure). The driving circuit board may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor divider circuit (generating Vcom) and other driving circuits. The driving circuit board may also include other circuit structures, which are not listed here one by one. The driving circuit board is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 may also include a touch structure, a camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording or fingerprint recognition, which are not listed here one by one.

[0082] Continuing with FIG2 , when the display device 1000 is a liquid crystal display device, the display device 1000 may further include a backlight source 1200 disposed on the backlight side of the display panel 1100. For example, the backlight source 1200 may be a direct-lit backlight source or an edge-lit backlight source, and is configured to provide light for the display panel 1100. The display panel 1100 includes a plurality of sub-pixels, each of which can adjust the amount of light passing through the display panel 1100, thereby enabling each sub-pixel to display the same or different grayscales, thereby achieving image display.

[0083] Continuing with FIG2 , in the case where the display panel 1100 is a liquid crystal display panel, the display panel 1100 may include an array substrate 100 and a color filter substrate 200 arranged opposite to each other, and a liquid crystal layer 300 arranged between the array substrate 100 and the color filter substrate 200, wherein the color filter substrate 200 may also be referred to as an opposing substrate or a packaging substrate. The color filter substrate 200 may filter the light incident on the color filter substrate 200 so that each sub-pixel emits light of a color (such as red, green, or blue). Different sub-pixels may emit light of the same or different colors, thereby enabling the display panel 1100 to achieve color display. The structure of the display panel 1100 is not limited to this. The display panel 1100 may also include other structures as long as the same technical concept is adopted. For example, the display panel 1100 may further include a first alignment film (not shown in the figure) arranged on the side of the array substrate 100 close to the liquid crystal layer 300, and a second alignment film (not shown in the figure) arranged on the side of the color filter substrate 200 close to the liquid crystal layer 300.

[0084] In some embodiments, the array substrate 100 may include a display area AA and a peripheral area BB disposed around the display area AA. The display area AA may include a plurality of pixel circuits, pixel electrodes, and a common electrode, and the peripheral area may include, for example, a gate driver on array (GOA) circuit configured to drive the pixel circuits.

[0085] 3A and 3B , the display area AA includes a plurality of first signal lines DL and a plurality of second signal lines GL. The plurality of first signal lines DL are spaced apart along a first direction X and extend as a whole along a second direction Y. The plurality of second signal lines GL are spaced apart along the second direction Y and extend as a whole along the first direction X. The plurality of first signal lines DL and the plurality of second signal lines GL intersect with each other to form a grid structure, each grid structure defining a pixel area 101. The first signal lines DL may be straight lines (as shown in FIG. 3A ) or fold lines (as shown in FIG. 3B ) in their extending directions, and / or the second signal lines GL may be straight lines (as shown in FIG. 3A and FIG. 3B ) or fold lines (not shown in the figures) in their extending directions. The first direction X and the second direction Y intersect with each other. For example, the first direction X and the second direction Y are perpendicular to each other.

[0086] A pixel region 101 may include a pixel circuit, which may include at least one thin-film transistor (TFT) and at least one capacitor. For example, the pixel circuit may be a "1T1C" circuit or a "2T1C" circuit. "T" refers to a thin-film transistor, and the number preceding "T" indicates the number of thin-film transistors; "C" refers to a capacitor, and the number preceding "C" indicates the number of capacitors.

[0087] In the following embodiments of the present disclosure, a "1T1C" pixel circuit is used as an example to illustrate the embodiments of the present disclosure. However, the embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied. In the case of a "1T1C" pixel circuit, the pixel circuit may include a first transistor T1 and a first capacitor Cst. The "1T1C" circuit can greatly reduce the number of thin-film transistors included in the pixel circuit, reducing the space occupied by the pixel circuit, which is conducive to improving the aperture ratio of the array substrate, and thus increasing the pixel density of the array substrate.

[0088] In some embodiments, the first transistor T1 may be an oxide thin-film transistor (OTFT). OTFTs have low leakage current, which helps reduce the leakage current of the first transistor T1, thereby simplifying the circuit structure of the pixel circuit, thereby increasing the aperture ratio of the array substrate 100 and improving the light transmittance of the array substrate 100.

[0089] The related art provides an array substrate, wherein the gate drive circuit in the peripheral area includes a second transistor, which also uses an oxide thin film transistor. However, the applicant's research has found that compared with low-temperature polysilicon (LTPS) thin film transistors, the electron mobility of the oxide thin film structure is relatively low. Based on this, the structure of the conventional gate drive circuit using oxide thin film transistors is relatively complex. For example, the use of an 18T3C gate drive circuit increases the area occupied by the gate drive circuit and affects the width of the peripheral area of ​​the array substrate, which is not conducive to the narrow-frame design of the display device. How to improve the on-state current and stability of the thin film transistors in the peripheral area is a technical problem that urgently needs to be solved.

[0090] To solve the above problems, some embodiments of the present disclosure provide an array substrate 100 . Referring to FIG. 4A and FIG. 4B , the array substrate 100 includes a substrate 11 , a first transistor T1 , a connecting electrode 21 , a first electrode 22 , and a second electrode 23 .

[0091] The first transistor T1 is disposed on the substrate 11 and in the display area AA. The first transistor T1 includes a first semiconductor pattern 12 and a first electrode structure 13 disposed on a side of the first semiconductor pattern 12 away from the substrate.

[0092] Exemplarily, the first semiconductor pattern 12 may include two first electrode regions 122 and a first channel region 121 located between the two first electrode regions 122. The first channel region 121 is configured to form a channel of the first transistor T1, one of the two first electrode regions 122 is configured to form a source connection region of the first transistor T1, and the other is configured to form a drain connection region of the first transistor T1. The first electrode structure 13 is configured to be electrically connected to the second signal line GL, or at least a portion of the second signal line GL forms the first electrode structure 13. The orthographic projection of the first electrode structure 13 on the substrate 11 covers the orthographic projection of the first channel region 121 on the substrate 11, and is used to form the gate (control electrode) of the first transistor T1. One of the two first polar regions 122 is configured to be electrically connected to the first signal line DL, and the other is configured to be electrically connected to the first electrode 22. For example, as shown in Figure 4A, the first polar region 122 located on the left is configured to be electrically connected to the first signal line DL, and the first polar region 122 located on the right is configured to be electrically connected to the first electrode 22 through the connecting electrode 21.

[0093] The connecting electrode 21 is disposed on a side of the first electrode structure 13 away from the substrate 11 and is electrically connected to the first semiconductor pattern 12. The connecting electrode 21 being disposed on a side of the first electrode structure 13 away from the substrate 11 may mean that the film layer on which the connecting electrode 21 is located is formed after the film layer on which the first electrode structure 13 is located. Spatially, the connecting electrode 21 is not always located on the side of the first electrode structure 13 away from the substrate 11. Exemplarily, the array substrate 100 further includes a first insulating layer GI1 located between the first semiconductor pattern 12 and the first electrode structure 13, a second insulating layer ILD located between the first electrode structure 13 and the connecting electrode 21, and a first via V1 extending through the first insulating layer GI1 and the second insulating layer ILD. A portion of the connecting electrode 21 is disposed on the surface of the first insulating layer GI1 and spatially located on the side of the first electrode structure 13 away from the substrate 11. Another portion is located within the first via V1 and is electrically connected to the first semiconductor pattern 12 through the first via V1. For example, the connecting electrode 21 is electrically connected to a first polar region 122 of the first semiconductor pattern 12.

[0094] In some embodiments, as shown in Figures 3A, 3B, and 4A, the orthographic projection of the first via hole V1 on the substrate 11 is located within the orthographic projection of the pixel area 101 on the substrate 11. For example, the orthographic projection area of ​​the pixel area 101 on the substrate 11 is larger than the orthographic projection area of ​​the first via hole V1 on the substrate 11, and the orthographic projection of the pixel area 101 on the substrate 11 covers the orthographic projection of the first via hole V1 on the substrate 11. Of course, in other embodiments, the first via hole V1 may not be located in the pixel area 101; alternatively, the first via hole V1 may be partially located in the pixel area 101 and partially located outside the pixel area 101.

[0095] The first electrode 22 is disposed on a side of the connecting electrode 21 away from the substrate 11 and is electrically connected to the connecting electrode 21. The second electrode 23 is disposed on a side of the first electrode 22 away from the substrate 11. The first electrode 22 is electrically connected to a first polar region 122 of the first semiconductor pattern 12 via the connecting electrode 21. For example, the first electrode 22 may be a pixel electrode. The second electrode 23 is configured to be electrically connected to a constant voltage signal and may be a common electrode. A first capacitor Cst is also formed between the first electrode 22 and the second electrode 23.

[0096] Exemplarily, the second signal line GL controls the first transistor T1 to be turned on or off through the first electrode structure 13. When the first electrode structure 13 controls the first transistor T1 to be turned on, the first semiconductor pattern 12 of the first transistor T1 electrically connects the first signal line DL to the connecting electrode 21, thereby transmitting the voltage signal (such as a data signal) transmitted on the first signal line DL to the connecting electrode 21, and then transmitting it to the first electrode 22 through the connecting electrode 21. An electric field is formed between the first electrode 22 and the second electrode 23 to drive the liquid crystal molecules in the liquid crystal layer to deflect, thereby adjusting the grayscale displayed by the sub-pixel.

[0097] In some embodiments, at least one of the connecting electrode 21 and the first electrode structure 13 comprises a semiconductor material. That is, the array substrate 100 can be formed into a structure comprising two layers of semiconductor material. Based on this, a transistor having a double semiconductor layer can be fabricated in the peripheral region. The transistor can include at least two conductive interfaces, which helps increase the on-state current of the transistor and thereby reduce the area of ​​the transistor. This also helps simplify the structure of the gate drive circuit, thereby reducing the space occupied by the gate drive circuit and the width of the peripheral region, thereby helping to achieve a narrow bezel for the array substrate 100 and the display device.

[0098] Exemplarily, the connecting electrode 21 comprises a semiconductor material, while the first electrode structure 13 does not. For example, the first electrode structure 13 comprises a metallic conductive material. Alternatively, the first electrode structure 13 comprises a semiconductor material, while the connecting electrode 21 does not. Since at least a portion of the connecting electrode 21 is located within the pixel region 101, the connecting electrode 21 may comprise a transparent conductive material. Alternatively, both the connecting electrode 21 and the first electrode structure 13 may comprise a semiconductor material.

[0099] It should be noted that in order to improve the conductivity of the connecting electrode 21 and the first electrode structure 13, at least one of the semiconductor materials in the connecting electrode 21 and the first electrode structure 13 can undergo a process (conductorization process) to make it more conductive. The process of making it more conductive can be found above and will not be repeated here.

[0100] In some embodiments, the first semiconductor pattern 12 may be manufactured using various suitable semiconductor materials and various suitable manufacturing methods, or in other words, the material of the first semiconductor pattern 12 may include at least one of various suitable semiconductor materials. In some embodiments, the semiconductor material includes M1O a N b , where M1 is a single metal or a combination of multiple metals, a>0, and b≥0, O represents oxygen, and N represents nitrogen. That is, the semiconductor material is a metal oxide material or a metal oxynitride material. Suitable metal oxide materials include, but are not limited to, indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxide (In-free OS), rare earth-doped oxide (Ln-OS, such as rare earth-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the first semiconductor pattern 12 may be amorphous, partially crystalline, single crystal, or polycrystalline, and may also be a single-layer or multi-layer structure.

[0101] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof.

[0102] In one embodiment, the material of the first semiconductor pattern 12 includes a high-mobility metal oxide semiconductor (HMOS) material. This helps improve the electron mobility of the first semiconductor pattern 12 and thus the on-state current of the first transistor T1. Furthermore, the HMOS material exhibits good light stability, which helps improve the light stability of the first transistor T1. Examples of HMOS materials include, but are not limited to, rare-earth element-doped IZO and IGZO, with the rare-earth element doping concentration ranging from 0.1% to 2%.

[0103] Among them, the first polar region 122 and the first channel region 121 are an integrated structure, and the materials of the first channel region 121 and the first polar region 122 both include M1OaNb. The difference between the first polar region 122 and the first channel region 121 is that the first polar region 122 undergoes a process (conductorization process) to make it more conductive. The conductivity of the first channel region 121 is different from the conductivity of the first polar region 122. Exemplarily, the first channel region 121 may include a semiconductor material, and the first polar region 122 may include a doped semiconductor material. In this way, the first polar region 122 can form a conductor and the first channel region 121 forms a semiconductor.

[0104] In one example, when the materials of the first channel region 121 and the first polar region 122 both include M1OaNb, the M1OaNb in the first polar region 122 undergoes a light doping process (e.g., a light doping ion implantation process). In another example, when the materials of the first channel region 121 and the first polar region 122 include M1OaNb, the M1OaNb in the first polar region 122 undergoes an annealing process. In another example, when the materials of the first channel region 121 and the first polar region 122 include M1OaNb, the M1OaNb in the first polar region 122 undergoes an oxide supplementation process. Exemplarily, a process in the range of about 1×10 15 atoms / cm 3 to about 1×10 20 atoms / cm 3 The doping concentration range is about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 , about 1×10 17 atoms / cm 3 to about 1×10 18 atoms / cm 3 , about 1×10 18 atoms / cm 3 to about 1×10 20 atoms / cm 3 , and about 1×10 19 atoms / cm 3 to about 1×10 20 atoms / cm 3, to perform a light doping process. Exemplarily, the light doping process is performed using an N-type dopant to enhance conductivity. Examples of N-type dopants may include elements from Group VA of the periodic table, including but not limited to nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Protective gas elements such as argon (Ar), helium (He), oxygen (O), hydrogen (H), and fluorine (F) may also be used to perform the light doping process.

[0105] In some embodiments, referring to FIG5 , the array substrate 100 further includes a second transistor T2. The second transistor T2 is located on the same side of the substrate 11 as the first transistor T1 and is disposed in the peripheral area BB. For example, the second transistor T2 can be a transistor configured to form a gate drive circuit, or a transistor configured to form a MUX circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other circuits can be prepared. The following describes the embodiments of the present disclosure using the example of the second transistor T2 being configured to form a gate drive circuit.

[0106] As shown in FIG5 , the second transistor T2 includes a second semiconductor pattern 32 and a third semiconductor pattern 33. The third semiconductor pattern 33 may be located on a side of the second semiconductor pattern 32 away from the substrate 11. The second semiconductor pattern 32 includes a second channel region 321 and two second polar regions 322 located on opposite sides of the second channel region 321. The third semiconductor pattern 33 includes a third channel region 331 and two third polar regions 332 located on opposite sides of the third channel region 331.

[0107] The second channel region 321 and the third channel region 331 are spaced apart in a direction perpendicular to the substrate 11 (third direction Z), so that conductive interfaces can be formed on the second channel region 321 and the third channel region 331 , respectively, thereby increasing the on-state current of the second transistor T2 .

[0108] The orthographic projection of the second channel region 321 on the substrate 11 at least partially overlaps with the orthographic projection of the third channel region 331 on the substrate 11. This not only helps reduce the area of ​​the orthographic projection of the second transistor T2 on the substrate 11, that is, reduces the area occupied by the second transistor T2 on the plane of the array substrate 100, thereby reducing the width of the peripheral area BB, which is beneficial for achieving a narrow bezel for the array substrate 100 and the display device. It also helps to electrically connect the second polar region 322 and the third polar region 332. For example, the second polar region 322 and the third polar region 332 located on the same side of the second channel region 321 and the third channel region 331 are electrically connected to facilitate the synchronous transmission of electrical signals to the second polar region 322 and the third polar region 332.

[0109] The second transistor T2 provided in the embodiments of the present disclosure includes two semiconductor patterns (a second semiconductor pattern 32 and a third semiconductor pattern 33) arranged in a direction perpendicular to the substrate 11 (a third direction Z). When the second transistor T2 is turned on, a conductive interface can be formed on at least one surface of each of the two semiconductor patterns to form at least two conductive interfaces, which is beneficial for improving the on-state current of the second transistor T2. Based on this, a smaller second transistor can be designed, the aspect ratio of the second transistor T2 can be reduced, and the area of ​​the second transistor T2 can be reduced. This also helps to simplify the structure of the gate drive circuit, reduce the area of ​​the gate drive circuit's positive projection on the substrate 11, and help reduce the width of the peripheral area, so as to facilitate the implementation of a narrow frame for the array substrate and the display device.

[0110] In some embodiments, both the second semiconductor pattern 32 and the third semiconductor pattern 33 comprise a metal oxide semiconductor material. In other words, the second transistor T2 may be a metal oxide thin-film transistor, which helps reduce the difficulty and cost of manufacturing the array substrate. Furthermore, compared to conventional metal oxide thin-film transistors comprising only one layer of semiconductor material, in the embodiments of the present disclosure, the second transistor T2 comprises the second semiconductor pattern 32 and the third semiconductor pattern 33, which helps increase the on-state current of the second transistor T.

[0111] The gate driving circuit generally includes a plurality of thin film transistors, at least one of which is the second transistor T2 described in the embodiment of the present disclosure.

[0112] The gate drive circuit typically includes multiple thin-film transistors. Depending on the function and position of the multiple thin-film transistors, the sizes of the multiple thin-film transistors (the width-to-length ratio of the channel structure) vary to a certain extent. That is, the channel lengths of different thin-film transistors in the multiple thin-film transistors are not exactly the same. The inventors have discovered that the threshold voltage of a metal oxide thin-film transistor has a certain relationship with the channel length of the thin-film transistor. For example, referring to FIG6 , the threshold voltages of multiple metal oxide thin-film transistors with channel lengths of 4.5 μm, 6 μm, and 8 μm were tested. It was found that when the channel length of the metal oxide thin-film transistor was 4.5 μm, the threshold voltage Vth of the thin-film transistor was approximately -1 V to 0 V. When the channel length of the metal oxide thin-film transistor was 6 μm, the threshold voltage Vth of the thin-film transistor was approximately 3 V to 5 V. When the channel length of the metal oxide thin-film transistor was 8 μm, the threshold voltage Vth of the thin-film transistor was approximately 5 V to 10 V. In this way, for metal oxide thin film transistors of different sizes in the gate drive circuit, the required gate drive voltages may be different, which is not conducive to ensuring the uniformity of the characteristics of the thin film transistors in the display area AA and the peripheral area BB under the same set of process steps, and is also not conducive to the control and drive of the array substrate. For example, different transistors require different gate voltages for driving.

[0113] The array substrate 100 provided in the embodiment of the present disclosure includes two semiconductor patterns (a second semiconductor pattern 32 and a third semiconductor pattern). Under the condition of the same channel width-to-length ratio, the on-state current of the second transistor T2 can be increased. Based on this, the second transistor T2 can have a larger process adjustment space. For example, the area of ​​the originally larger transistor can be reduced, thereby freeing up space in the peripheral area, and the area of ​​the originally smaller transistor can be increased. This is beneficial for improving the size uniformity between different thin-film transistors and solving the problem of different threshold voltages of different thin-film transistors.

[0114] In some embodiments, the electron mobility of the second semiconductor pattern 32 is greater than that of the third semiconductor pattern 33, which is beneficial for increasing the on-state current of the second semiconductor pattern 32. For example, the second semiconductor pattern may include a high-mobility metal oxide semiconductor material. The high-mobility metal oxide semiconductor material is described above and will not be further described here.

[0115] The electron mobility of the third semiconductor pattern 33 is less than or equal to that of the second semiconductor pattern 32. However, the third semiconductor pattern 33 has greater light stability than the second semiconductor pattern 32. The third semiconductor pattern 33 is more susceptible to light, including ambient light. Therefore, the third semiconductor pattern 33 is made of a material with greater light stability, which helps improve the light stability of the second transistor T2. For example, the material of the third semiconductor pattern 33 includes indium gallium zinc oxide (IGZO), which has good light stability.

[0116] The second channel region 321 and the second polar region 322 in the second semiconductor pattern 32 are integrally formed and made of the same semiconductor material. The second polar region 322 differs from the second channel region 321 in that the second polar region 322 undergoes a process (conductorization process) to make it more conductive. The conductorization process has been described above and will not be further described here.

[0117] The third channel region 331 and the third polar region 332 in the third semiconductor pattern 33 are integrally formed and made of the same semiconductor material. The third channel region 331 and the third polar region 332 differ in that the third polar region 332 undergoes a process (conductorization process) to make it more conductive. The conductorization process is described above and will not be further described here.

[0118] In some embodiments, the second transistor T2 further includes a second electrode structure 31, which is disposed at least partially opposite the second channel region 321 and at least partially opposite the third channel region 331. The second electrode structure 31 is configured to control the conduction between the second channel region 321 and the third channel region 331. The second electrode structure 31 is disposed at least partially opposite the second channel region 321 and the third channel region 331, respectively. When the second electrode structure 31 drives the second transistor T2 to conduct, at least one conductive interface can be formed on the second channel region 321 and the third channel region 331, respectively, thereby obtaining at least two conductive interfaces and increasing the on-state current of the second transistor T2.

[0119] In some embodiments, referring to Figure 5, the second electrode structure 31 may include a first sub-electrode 34 arranged between the second semiconductor pattern 32 and the third semiconductor pattern 33, and the first sub-electrode 34 is respectively arranged opposite to the second channel region 321 and the third channel region 331. The first sub-electrode 34 can simultaneously control the conduction or cutoff of the second channel region 321 and the third channel region 331.

[0120] For example, when an operating voltage (a voltage capable of driving the second channel region 321 and the third channel region 331 to conduct) is transmitted on the first sub-electrode 34, a current conduction interface is formed on the surface (upper surface) of the second channel region 321 close to the first sub-electrode 34, and a current conduction interface is formed on the surface (lower surface) of the third channel region 331 close to the first sub-electrode 34. Both the second channel region 321 and the third channel region 331 are conducted, which is conducive to simplifying the structure of the second electrode structure 31.

[0121] In other embodiments, referring to FIG. 7 , the second electrode structure 31 may include a first sub-electrode 34 disposed between the second semiconductor pattern 32 and the third semiconductor pattern 33 , and a second sub-electrode 35 disposed on a side of the second semiconductor pattern 32 close to the substrate 11 .

[0122] In this way, when the first sub-electrode 34 and the second sub-electrode 35 control the conduction of the second channel region 321 and the third channel region 331, the second channel region 321 and the third channel region 331 can form three current conduction interfaces, further increasing the on-state current of the second transistor T2, which is beneficial to further reduce the area of ​​the second transistor T2, thereby reducing the space occupied by the gate drive circuit and reducing the width of the peripheral area, which is beneficial to achieve a narrow frame for the array substrate 100 and the display device.

[0123] Continuing with Figure 7 , the first sub-electrode 34 is disposed opposite the second channel region 321 and the third channel region 331, respectively. The first sub-electrode 34 can simultaneously control the conduction or blocking of the second and third channel regions 321, 331. For example, when an operating voltage is transmitted to the first sub-electrode 34, the surface of the second channel region 321 proximal to the first sub-electrode 34 (the upper surface) and the surface of the third channel region 331 proximal to the first sub-electrode 34 (the lower surface) form a conductive interface, achieving conduction between the second and third channel regions 321, 331.

[0124] The second sub-electrode 35 is disposed opposite the second channel region 321, and the orthographic projection of the second sub-electrode 35 on the substrate 11 at least partially overlaps with the orthographic projection of the second channel region 321 on the substrate 11. Thus, the second sub-electrode 35 can be configured to control the conduction or cutoff of the second channel region 321. For example, when an operating voltage (a voltage capable of driving the second channel region 321 to conduct) is transmitted to the second sub-electrode 35, a current-conducting interface is formed on the surface (lower surface) of the second channel region 321 close to the second sub-electrode 35, and the second channel region 321 is turned on.

[0125] When the second electrode structure 31 drives the second transistor T2 to turn on, as shown in Figure 7, the first sub-electrode 34 and the second sub-electrode 35 simultaneously transmit the operating voltage, the upper and lower surfaces of the second channel region 321 respectively form current conduction interfaces, and the lower surface of the third channel region 331 forms a current conduction interface. The second transistor T2 can form a total of three current conduction interfaces. Under the same width-to-length ratio, the on-state current of the second transistor T2 can be increased by nearly three times, which is conducive to reducing the size of the second transistor T2, reducing the space occupied by the gate drive circuit, and enabling the array substrate and the display device to achieve a narrow frame.

[0126] It should be noted that, as shown in Figure 7, when the second electrode structure 31 includes a first sub-electrode 34 and a second sub-electrode 35, the second sub-electrode 35 may not transmit a voltage signal. At this time, the second sub-electrode 35 may be in a floating state, that is, the second sub-electrode 35 is not electrically connected to any other signal line, and the second sub-electrode 35 is only used to shield the second channel region 321.

[0127] In some embodiments, referring to FIG7 , the orthographic projection of the second sub-electrode 35 on the substrate 11 covers the orthographic projections of the second channel region 321 and the third channel region 331 on the substrate 11, and partially overlaps with the orthographic projection of at least one of the two second polar regions 322 and the two third polar regions 332 on the substrate 11; in this way, the second sub-electrode 35 can also greatly block the light emitted from the backlight source to the array substrate, reducing the risk of the above light entering the second channel region 321 and the third channel region 331, thereby reducing the risk of characteristic shift (such as Vth drift) of the second channel region 321 and the third channel region 331 under illumination, which is beneficial to improving the stability of the second channel region 321 and the third channel region 331, and thereby improving the stability of the second transistor T2.

[0128] The orthographic projection of the second sub-electrode 35 on the substrate 11 also covers the orthographic projection of the first sub-electrode 34 on the substrate 11, and a gap exists between the orthographic projection of the second sub-electrode 35 and the orthographic projection of the first sub-electrode 34. This greatly enhances the light shielding effect of the second sub-electrode 35 on the second channel region 321 and the third channel region 331.

[0129] Exemplarily, the orthographic projection of the second channel region 321 on the substrate 11 is within the range of the orthographic projection of the first sub-electrode 34 on the substrate 11. In other words, during the process of forming the second semiconductor pattern 32, the first sub-electrode 34 can be used as a mask to conduct the second semiconductor pattern 32 to form the second channel region 321 and the second polar region 322 on the second semiconductor pattern 32. The second sub-electrode 35 covering the first sub-electrode 34 can ensure that the second sub-electrode 35 completely covers the second channel region 321.

[0130] In some embodiments, referring to FIG. 8 , the second electrode structure 31 includes a third sub-electrode 36 disposed on a side of the third semiconductor pattern 33 away from the substrate 11, and a fourth sub-electrode 37 disposed on a side of the second semiconductor pattern 32 closer to the substrate 11. The third sub-electrode 36 is disposed opposite the third semiconductor pattern 33, and its orthographic projection on the substrate 11 at least partially overlaps with the orthographic projection of the third channel region 331 on the substrate 11. The third sub-electrode 36 is configured to drive the third channel region 331 of the third semiconductor pattern 33 on and off. The fourth sub-electrode 37 is disposed opposite the second semiconductor pattern 32, and its orthographic projection on the substrate 11 at least partially overlaps with the orthographic projection of the second channel region 321 on the substrate 11. The fourth sub-electrode 37 is configured to drive the second channel region 321 of the second semiconductor pattern 32 on and off.

[0131] Exemplarily, when the second electrode structure 31 drives the second channel region 321 and the third channel region 331 of the second transistor T2 to conduct, a first operating voltage (a voltage capable of driving the third channel region 331 to conduct) is transmitted to the third sub-electrode 36. Under the control of the first operating voltage, the third channel region 331 forms a current-conducting interface on the surface (upper surface) near the third sub-electrode 36. Simultaneously, a second operating voltage (a voltage capable of driving the second channel region 321 to conduct) is transmitted to the fourth sub-electrode 37. Under the control of the second operating voltage, the second channel region 321 forms a current-conducting interface on the surface (lower surface) near the fourth sub-electrode 37. In other words, the third sub-electrode 36 and the fourth sub-electrode 37 respectively drive the third channel region 331 and the second channel region 321 to conduct, and each forms a current-conducting interface. In this case, the second transistor T2 includes two current-conducting interfaces.

[0132] In some embodiments, referring to FIG8 , when the second electrode structure 31 includes a third sub-electrode 36 and a fourth sub-electrode 37, the fourth sub-electrode 37 can also be used to block light emitted from the backlight source toward the array substrate, thereby reducing the risk of the above light entering the second channel region 321 and the third channel region 331, thereby reducing the risk of characteristic deviation (such as Vth drift) in the second channel region 321 and the third channel region 331 under light conditions, which is beneficial to improving the stability of the second channel region 321 and the third channel region 331, and thereby improving the stability of the second transistor T2.

[0133] For example, the orthographic projection of the fourth sub-electrode 37 on the substrate 11 covers the orthographic projections of the second channel region 321 and the third channel region 331 on the substrate 11, and partially overlaps with the orthographic projection of at least one of the two second polar regions 322 and the two third polar regions 332 on the substrate 11. In this way, the light shielding effect of the second sub-electrode 35 on the second channel region 321 and the third channel region 331 can be greatly enhanced, thereby improving the stability of the second transistor T2.

[0134] Obviously, the specific structure of the second electrode structure 31 is not limited to the multiple embodiments described above (embodiments of Figures 5 to 8), and the second electrode structure 31 only needs to adopt the same technical ideas as the present application. For example, the second electrode structure may include a first sub-electrode located between the second semiconductor pattern and the third semiconductor pattern, a second sub-electrode located on the side of the second semiconductor pattern close to the substrate, and a third sub-electrode located on the side of the third semiconductor pattern away from the substrate (not shown in the figure). Alternatively, the second electrode structure may include a first sub-electrode located between the second semiconductor pattern and the third semiconductor pattern, and a third sub-electrode located on the side of the third semiconductor pattern away from the substrate (not shown in the figure). The second electrode structure of the embodiments of the present disclosure is not limited to this and will not be listed one by one here.

[0135] In some embodiments, referring to FIG. 5 , FIG. 7 , and FIG. 8 , at least one insulating layer is included between the second semiconductor pattern 32 and the third semiconductor pattern 33 .

[0136] Referring to Figure 5, the second semiconductor pattern 32 and the third semiconductor pattern 33 include a first insulating layer GI1 and a second insulating layer ILD. The array substrate 100 may also include a fifth via V5. The fifth via V5 penetrates the insulating layer (the first insulating layer GI1 and the second insulating layer ILD) between the second semiconductor pattern 32 and the third semiconductor pattern 33, and exposes at least a portion of the second polar region 322. The second polar region 322 and the third polar region 332 of the second semiconductor pattern 32 and the third semiconductor pattern 33 that are close to each other can be directly electrically connected through the fifth via V5.

[0137] Alternatively, in some embodiments, referring to Figures 7 and 8, the second transistor T2 further includes at least one transfer pattern 38, which is disposed between the adjacent second region 322 and third region 332 and electrically connected to the second region 322 and third region 332, respectively. This helps reduce the depth of the connecting via between the second region 322 and the third region 332, reduces the difficulty of connecting the second region 322 and the third region 332, and helps improve the conductorization effect of the third region 332. For example, the second transistor T2 includes two transfer patterns 38, each disposed between two pairs of interconnected second regions 322 and third regions 332.

[0138] Referring to FIG. 7 , when the second transistor T2 includes a transfer pattern 38 and the second electrode structure 31 includes a first sub-electrode 34, the transfer pattern 38 can be made of the same material and disposed in the same layer as the first sub-electrode 34. Exemplarily, the transfer pattern 38 and the first sub-electrode 34 are formed using the same mask and / or the same material in the same patterning process. This simplifies the fabrication process for the transfer pattern 38 and the first sub-electrode 34, reducing the manufacturing cost of the array substrate.

[0139] Referring to Figure 8, when the second electrode structure 31 includes a third sub-electrode 36 and a fourth sub-electrode 37, and does not include the first sub-electrode 34, the transfer pattern 38 can be set separately on a film layer, and the third semiconductor pattern 33 can be set on the transfer pattern 38 (as shown in Figure 8), or at least one insulating layer can be set between the transfer pattern 38 and the third semiconductor pattern 33, and a via is set on the insulating layer, and the transfer pattern 38 and the third semiconductor pattern 33 are connected through the via (not shown in the figure).

[0140] In some embodiments, referring to FIG. 9 , the second semiconductor pattern 32 and the first semiconductor pattern 12 comprise the same material and are disposed in the same layer. And / or, referring to FIG. 9 and FIG. 10 , the third semiconductor pattern 33 comprises the same material and is disposed in the same layer as one of the semiconductor materials of the connecting electrode 21 and the first electrode structure 13. Compared to forming the first semiconductor pattern 12, the second semiconductor pattern 32, the third semiconductor pattern 33, the connecting electrode 21, and the first electrode structure 13 using different processes and in different film layers, the second semiconductor pattern 32 and the first semiconductor pattern 12 comprise the same material and are disposed in the same layer. The third semiconductor pattern 33 comprises the same material and is disposed in the same layer as one of the semiconductor materials of the connecting electrode 21 and the first electrode structure 13. This greatly simplifies the manufacturing process of the array substrate 100 and simplifies the structure of the array substrate 100, thereby reducing the manufacturing cost of the array substrate 100.

[0141] For example, referring to Figures 9 and 10, the second semiconductor pattern 32 is formed using the same mask plate and / or the same material as the first semiconductor pattern 12 in the same patterning process. Referring to Figure 9, when the connecting electrode 21 includes a semiconductor material, the third semiconductor pattern 33 can be formed using the same mask plate and / or the same material as the connecting electrode 21 in the same patterning process. Alternatively, referring to Figure 10, when the first electrode structure 13 includes a semiconductor material, the third semiconductor pattern 33 can be formed using the same mask plate and / or the same material as the first electrode structure 13 in the same patterning process. When both the connecting electrode 21 and the first electrode structure 13 include semiconductor materials, the third semiconductor pattern 33 can be formed using the same mask plate and / or the same material as either the connecting electrode 21 or the first electrode structure 13 in the same patterning process.

[0142] In some embodiments, referring to FIG. 9 , the connection electrode 21 comprises a semiconductor material, and the third semiconductor pattern 33 comprises the same material and is disposed in the same layer as the connection electrode 21. Exemplarily, the connection electrode 21 and the third semiconductor pattern 33 are formed using the same mask and / or the same material in the same patterning process. This simplifies the fabrication process for the third semiconductor pattern 33 and reduces the manufacturing cost of the array substrate.

[0143] Continuing to refer to Figure 9, the connecting electrode 21 includes a first sub-connecting electrode 211 and a second sub-connecting electrode 212, and the second sub-connecting electrode 212 is located on the side of the first sub-connecting electrode 211 away from the substrate 11; that is, the first pole region 122 of the first semiconductor pattern 12 is electrically connected to the first electrode 22 through the first sub-connecting electrode 211 and the second sub-connecting electrode 212 in sequence.

[0144] As shown in FIG9 , the third semiconductor pattern 33 and the first sub-connecting electrode 211 are made of the same material and are provided in the same layer. This helps reduce the spacing between the third semiconductor pattern 33 and the second semiconductor pattern 32 in the third direction Z, and reduces the difficulty of connecting the second polar region 322 and the third polar region 332.

[0145] 9 , the array substrate 100 may further include a first planar layer PLN1, a second planar layer PLN2, and a second via V2. The first planar layer PLN1 is disposed between the first sub-connection electrode 211 and the second sub-connection electrode 212. For example, a third insulating layer PVX1 is further included between the first planar layer PLN1 and the first sub-connection electrode 211.

[0146] The first sub-connection electrode 211 may include a first portion and a second portion, the first portion being electrically connected to the first semiconductor pattern 12 through the first via hole V1 , and the second portion being located on a surface of the second insulating layer ILD away from the substrate 11 .

[0147] The second via V2 penetrates the first planar layer PLN1 and the third insulating layer PVX1, exposing at least a portion of the second portion of the first sub-electrode 211. The second sub-connecting electrode 212 passes through the second via V2 and connects to the second portion. The portion of the second sub-connecting electrode 212 located within the second via V2 includes a groove 213 that is recessed toward the side closer to the substrate 11. The second planar layer PLN2 is disposed between the second sub-connecting electrode and the first electrode, located within the second via V2, and disposed within the groove 213. The surface of the second planar layer PLN2 facing away from the substrate 11 is substantially flush with the surface of the second sub-connecting electrode 212 facing away from the substrate 11, thereby improving the flatness of the plane on which the first electrode 22 resides, thereby improving the flatness of the first electrode 22 and facilitating the uniformity of the electric field formed between the first electrode 22 and the second electrode 23.

[0148] It should be noted that the aforementioned "surface of the second flat layer PLN2 away from the substrate 11 is substantially flush with the surface of the second sub-connecting electrode 212 away from the substrate 11" may, for example, mean that the step difference between the surface of the second flat layer PLN2 away from the substrate 11 and the surface of the second sub-connecting electrode 212 away from the substrate 11 is less than a first threshold value, which may be, for example, 2 μm, 3 μm, 3.5 μm, or 5 μm, etc., which are not listed one by one in the embodiments of the present disclosure. In this way, on the one hand, the flatness of the surface of the array substrate can be effectively improved, thereby improving the uniformity of the cell thickness of the liquid crystal layer; on the other hand, the problem of light leakage at the second via hole V2 can be reduced.

[0149] In some embodiments, the orthographic projection of the second via V2 on the substrate 11 is located within the orthographic projection of the pixel area 101 on the substrate 11. Specifically, the orthographic projection area of ​​the pixel area 101 on the substrate 11 is larger than the orthographic projection area of ​​the second via V2 on the substrate 11. The orthographic projection of the pixel area 101 on the substrate 11 covers the orthographic projection of the second via V2 on the substrate 11, so that the first electrode 22 is electrically connected to the first semiconductor pattern 12 through the second via V2.

[0150] In the disclosed embodiment, compared to disposing the second via V2 in a non-pixel region (e.g., where the first signal line DL or the second signal line GL is located), the portion of the first electrode 22 located within the second via V2 is only used for electrical connection with the first semiconductor pattern (connection electrode 21) and cannot be used for display, resulting in a smaller effective area of ​​the first electrode 22. In contrast, in the disclosed embodiment, the second via V2 electrically connecting the first electrode 22 and the first semiconductor pattern 12 is disposed in the pixel region 101. The portion of the first electrode 22 located within the second via V2 can also generate an electric field with the second electrode 23 and can also be used for display. This can increase the effective area of ​​the first electrode 22, improve liquid crystal efficiency (the liquid crystal's ability to deflect linearly polarized light), and facilitate improving the light transmittance of the display panel.

[0151] In an embodiment of the present disclosure, the connecting electrode 21 includes a first sub-connecting electrode 211 and a second sub-connecting electrode 212, and the first sub-connecting electrode 211 is electrically connected to the first semiconductor pattern 12 through a first via hole V1, and the second sub-connecting electrode 212 is electrically connected to the first sub-connecting electrode 211 through a second via hole V2. The orthographic projections of the first via hole V1 and the second via hole V2 on the substrate 11 do not overlap (they are staggered), and the first via hole V1 and the second via hole V2 can be respectively prepared by a two-step etching process. Compared with a through via hole, this is beneficial to reducing the etching difficulty of the first via hole V1 and the second via hole V2, and is beneficial to improving the continuity of the first sub-connecting electrode 211 and the second sub-connecting electrode 212 in the first via hole V1 and the second via hole V2 respectively, thereby reducing the climbing difficulty of the first sub-connecting electrode 211 and the second sub-connecting electrode 212.

[0152] In some embodiments, the specific pattern of the second sub-connecting electrode 212 can be designed as needed. The orthographic projection of the second sub-connecting electrode 212 on the substrate 11 can be a triangle, a quadrilateral, a pentagon, a hexagon, a circle, an ellipse, or other irregular shapes. The specific pattern of the second sub-connecting electrode 212 must meet the following requirements: on the one hand, it can overlap with the first electrode 22; on the other hand, after the second sub-connecting electrode 212 and the first electrode 22 are stacked, the overall outer contour of the two covers the orthographic projections of the second via V2 and the first via V1 on the substrate 11.

[0153] In some embodiments, as shown in FIG4A , the second sub-connection electrode 212 may only cover the side of the first flat layer PLN1 located at the second via hole V2 at the second via hole V2, that is, the second sub-connection electrode 212 does not completely cover the sidewall of the second via hole V2. At this time, as shown in FIG4A , the second sub-connection electrode 212 may cover the entire bottom of the second via hole V2 at the bottom of the second via hole V2. Or it may cover the entire part of the bottom of the second via hole V2 (not shown in the figure). Alternatively, as shown in FIG9 , the second sub-connection electrode 212 may also cover the entire outer edge of the first flat layer PLN1 away from the substrate 11 at the second via hole V2, that is, the second sub-connection electrode 212 completely covers the sidewall of the second via hole V2.

[0154] In some embodiments, the orthographic projection of the first electrode 22 on the substrate 11 covers the orthographic projection of the second via hole V2 and the first via hole V1 on the substrate 11. Because the second sub-connecting electrode 212 is distributed within the second via hole V2 and the first sub-connecting electrode 211 is distributed within the first via hole V1, the connecting electrode 21 within the hole can form an electric field with the second electrode 23 above the first electrode 22, which may interfere with the normal electric field formed by the first electrode 22 and the second electrode 23, affecting the electric field applied to the liquid crystal layer. In the embodiment of the present disclosure, by covering the orthographic projections of the second via hole V2 and the first via hole V1 on the substrate 11 by the first electrode 22, the electric field within the hole can be shielded, thereby achieving the effect of stabilizing the electric field.

[0155] In some embodiments, referring to Figures 5, 7, and 8 simultaneously, when the second electrode structure 31 includes a first sub-electrode 34, the first sub-electrode 34 can be made of the same material and disposed in the same layer as the first electrode structure 13. Exemplarily, the first sub-electrode 34 and the first electrode structure 13 are formed using the same mask and / or the same material in the same patterning process. This allows the first sub-electrode 34 to be formed simultaneously with the fabrication of the first electrode structure 13, eliminating the need for a separate process to fabricate the first sub-electrode 34. This simplifies the fabrication process for the first sub-electrode 34 and reduces the difficulty and cost of fabricating the array substrate.

[0156] In some embodiments, as shown in FIG9 , the first signal line DL is disposed on a side of the first semiconductor pattern 12 close to the substrate 11. When the second electrode structure 31 includes a second sub-electrode 35, the first signal line DL and the second sub-electrode 35 include the same material and are disposed in the same layer. Exemplarily, the second sub-electrode 35 and the first signal line DL are formed using the same mask and / or the same material in the same patterning process. In this way, the second sub-electrode 35 can be formed at the same time as the first signal line DL is prepared, without the need to open a separate process to prepare the second sub-electrode 35. This can simplify the preparation process of the second sub-electrode 35 and reduce the difficulty and cost of preparing the array substrate.

[0157] As shown in Figure 9, the second transistor T2 includes a second electrode structure 31, a second semiconductor pattern 32, and a third semiconductor pattern 33. The second electrode structure 31 includes a first sub-electrode 34 and a second sub-electrode 35. In a direction away from the substrate 11, the second sub-electrode 35 can be made of the same material and disposed in the same layer as the first signal line DL, the second semiconductor pattern 32 can be made of the same material and disposed in the same layer as the first semiconductor pattern 12, the first sub-electrode 34 can be made of the same material and disposed through the first electrode structure 13, and the third semiconductor pattern 33 can be made of the same material and disposed through the first sub-connecting electrode 212. Based on this, the structure of the second transistor T2 can be fabricated simultaneously with the film layers of the display area. Without increasing the number of fabrication steps for the array substrate 100, the second transistor T2 can be configured as a thin-film transistor comprising two semiconductor patterns. While maintaining existing process conditions and fabrication procedures, this increases the on-state current of the second transistor T2, reduces the area of ​​the second transistor T2, and reduces the space occupied by the gate drive circuit, thereby achieving a narrow bezel for the array substrate and display device.

[0158] It is understandable that FIG9 is only a specific embodiment, and any at least one structure or film layer of the second transistor T2 may also be prepared and formed using a separate process, as long as the structure of the second transistor T2 adopts the same technical concept.

[0159] In some embodiments, referring to Figures 10 and 11 , the first electrode structure 13 includes an auxiliary electrode 131 and an electrode portion 132. The electrode portion 132 is located on a side of the auxiliary electrode 131 away from the substrate 11. The auxiliary electrode 131 is made of a semiconductor material. The third semiconductor pattern 33 and the auxiliary electrode 131 are made of the same material and are disposed in the same layer. Exemplarily, the third semiconductor pattern 33 and the auxiliary electrode 131 are formed using the same mask and / or the same material in the same patterning process. This simplifies the fabrication process for the third semiconductor pattern 33 and reduces the fabrication cost of the array substrate.

[0160] The auxiliary electrode 131 may be made of a transparent conductive material to improve the transmittance of the portion of the auxiliary electrode 131 extending beyond the electrode portion 132 and reduce the shielding of light from the pixel area 101 by the portion. Exemplarily, the transparent conductive material includes, but is not limited to, metal oxides (e.g., at least one of indium tin oxide, indium gallium zinc oxide, indium-doped zinc oxide (AZO), fluorine-doped tin oxide (AZO), aluminum-doped zinc oxide (AZO), and indium-doped cadmium oxide).

[0161] In some embodiments, as shown in FIG11 , the orthographic projection of the auxiliary electrode 131 on the substrate 11 covers the orthographic projection of the electrode portion 132 on the substrate 11 , and the auxiliary electrode 131 is configured to increase the size of the first channel region 121 in the first semiconductor pattern 12 to increase the width-to-length ratio of the first transistor T1 and increase the on-state current of the first transistor T1.

[0162] Specifically, for ultra-high-resolution array substrates, optimizing the line width of the traces (first signal lines and second signal lines) and the size of the vias can directly and effectively increase the aperture ratio of the pixel area, thereby optimizing the display effect. However, the impact of the reduction in channel length also poses corresponding challenges to the short-channel characteristics of the transistors in the display backplane. When the channel length is less than 2 μm, the oxide transistor will experience a more obvious short-channel effect, which mainly includes the drain-induced barrier lowering (DIBL) effect and the diffusion effect of the conductive doping. Both of these will affect the characteristics of the oxide transistor, resulting in the inability to ensure the characteristics. In the embodiment of the present disclosure, the first electrode structure 13 also includes an auxiliary electrode 131. Under the premise of reducing the line width of the electrode portion 132, on the one hand, it can block the injection of some ions when the first semiconductor pattern 12 is subsequently conductively conductive, extend the channel length, ensure the characteristics of the oxide transistor, avoid the drain-induced barrier lowering effect and the diffusion effect of the conductive doping, and on the other hand, the transparent auxiliary electrode 131 will not affect the transmittance of the light-transmitting area.

[0163] Illustratively, the orthographic projection of the auxiliary electrode 131 on the substrate 11 covers the orthographic projection of the electrode portion 132 on the substrate 11, and covers at least one side of the electrode portion 132 in the two side regions in the second direction Y. For example, as shown in Figures 11 and 12, the orthographic projection of the auxiliary electrode 131 on the substrate 11 covers the orthographic projection of the electrode portion 132 on the substrate 11, and covers the two side regions of the electrode portion 132 in the second direction Y.

[0164] In the embodiment of the present disclosure, as shown in FIG10 , in order to facilitate the arrangement of the third semiconductor pattern 33 and the third sub-electrode 36, a third insulating layer GI2 is provided between the auxiliary electrode 131 and the electrode portion 132. However, it should be understood that in some other embodiments, the auxiliary electrode 131 and the electrode portion 132 may be in direct contact (as shown in FIG4B ), and the positions of the auxiliary electrode 131 and the electrode portion 132 in the third direction may be interchangeable. The following description of the embodiments of the present application is based on the example of providing the third insulating layer GI2 between the auxiliary electrode 131 and the electrode portion 132 as shown in FIG10 , and the auxiliary electrode 131 is located on the side of the electrode portion 132 close to the substrate 11.

[0165] In some embodiments, the third sub-electrode 36 and the electrode portion 132 are made of the same material and are disposed in the same layer. Exemplarily, the third sub-electrode 36 and the electrode portion 132 are formed using the same mask and / or the same material in the same patterning process. This simplifies the fabrication process of the third semiconductor pattern 33 and reduces the fabrication cost of the array substrate.

[0166] In some embodiments, referring to Figure 10, when the first electrode structure 13 includes an auxiliary electrode 131 and an electrode portion 132, the array substrate 100 also includes a first insulating layer GI1, a third insulating layer GI2, a second insulating layer ILD, a first flat layer PLN1, a second flat layer PLN2 and a third via V3.

[0167] The first insulating layer GI1 is disposed between the first semiconductor pattern 12 and the first electrode structure 13. The third insulating layer GI2 is disposed between the auxiliary electrode 131 and the electrode portion 132. The second insulating layer ILD and the first planar layer PLN1 are disposed between the first electrode structure 13 (electrode portion 132) and the connecting electrode 21. The first planar layer PLN1 is further away from the substrate 11 than the second insulating layer ILD. In other words, the first planar layer PLN1 is located on the side of the second insulating layer ILD that is further away from the substrate 11.

[0168] The third via hole V3 penetrates the first planar layer PLN1 , the second insulating layer ILD, the third insulating layer GI2 and the first insulating layer GI1 and exposes a portion of the first semiconductor pattern 12 , such as a portion of a first polar region 122 of the first semiconductor pattern 12 .

[0169] The connecting electrode 21 includes a third portion and a fourth portion. The third portion is electrically connected to the first semiconductor pattern 12 through the third via V3. The fourth portion is located on the surface of the first planar layer PLN1 away from the substrate 11 and is electrically connected to the first electrode 21. The third portion includes a groove 213 that is recessed toward the substrate 11. The second planar layer PLN2 is disposed between the second sub-connecting electrode and the first electrode, located within the second via V2 and within the groove 213. The surface of the second planar layer PLN2 away from the substrate 11 is approximately flush with the surface of the second sub-connecting electrode 212 away from the substrate 11 (the step difference between the two surfaces is less than a first threshold). This improves the flatness of the plane on which the first electrode 22 resides, thereby enhancing the uniformity of the electric field formed between the first electrode 22 and the second electrode 23. This also effectively improves the surface flatness of the array substrate, thereby improving the uniformity of the cell thickness of the liquid crystal layer and reducing light leakage at the second via V2.

[0170] In some embodiments, referring to Figure 10, the third via hole V3 passes through the first flat layer PLN1, the second insulating layer ILD, the third insulating layer GI2 and the first insulating layer GI1. The third via hole V3 can be formed by etching in a one-step etching method, and the connecting electrode 21 only includes one conductive layer, which is beneficial to reduce a mask process, simplify the preparation process of the array substrate, and reduce the preparation cost of the array substrate.

[0171] In some embodiments, referring to FIG10 , the first signal line DL is disposed on a side of the first semiconductor pattern 12 close to the substrate 11. When the second electrode structure 31 includes a third sub-electrode 36 and a fourth sub-electrode 37, the first signal line DL and the fourth sub-electrode 37 include the same material and are disposed in the same layer. Exemplarily, the fourth sub-electrode 37 and the first signal line DL are formed using the same mask and / or the same material in the same patterning process. In this way, the fourth sub-electrode 37 can be formed at the same time as the first signal line DL is prepared, and there is no need to open a separate process to prepare the fourth sub-electrode 37. This can simplify the preparation process of the fourth sub-electrode 37 and reduce the preparation difficulty and preparation cost of the array substrate.

[0172] In some embodiments, the auxiliary electrode 131 and the electrode portion 132 are both configured to drive the first transistor T1 to be turned on or off, and the auxiliary electrode 131 and the electrode portion 132 can transmit the same voltage signal.

[0173] In some embodiments, as shown in Figures 10 and 11, the auxiliary electrode 131 and the electrode portion 132 are electrically connected within the display area AA. In this case, the third insulating layer GI2 includes a sixth via hole V6, and the electrode portion 132 includes a main portion 133 and a widened portion 134 alternately connected along the first direction X. The orthographic projection of the widened portion 134 on the substrate 11 at least partially overlaps with the sixth via hole V6, and the widened portion 134 is electrically connected to the auxiliary electrode through the sixth via hole.

[0174] In some embodiments, as shown in FIG11 , a first interval D1 is provided between adjacent boundaries of the auxiliary electrode 131 and the electrode portion 132 in their orthographic projection on the substrate 11. The first interval D1 is greater than or equal to 0.5 μm. For example, when the electrode portion 132 includes a main portion 133 and a widened portion 134, the first interval D1 may refer to the interval between adjacent boundaries of the auxiliary electrode 131 and the widened portion 134 in their orthographic projection on the substrate 11.

[0175] In other embodiments, referring to Figures 12 and 13 , the auxiliary electrode 131 and the electrode portion 132 are electrically connected within the peripheral region. In this case, the auxiliary electrode 131 and the electrode portion 132 are not connected via vias within the display area AA, and the electrode portion 132 has a uniform width (dimension along the second direction) along its extension direction (the first direction X).

[0176] FIG14 illustrates the structure of the first signal line DL when the first signal line DL is disposed on a side of the first semiconductor pattern 12 away from the substrate 11. Referring to FIG14 , the applicant has discovered that when the first signal line DL is disposed on a side of the first semiconductor pattern 12 away from the substrate 11, for example, when the first signal line DL and the first connecting sub-electrode are made of the same material and disposed in the same layer, the first signal line DL is electrically connected to the first semiconductor pattern 12 via a connecting via VX disposed between the first signal line DL and the first semiconductor pattern 12. The opening of the connecting via VX is typically larger than the line width of the first signal line DL. The width of the portion of the first signal line DL located within the connecting via VX is generally greater than the width of the remaining portion. Furthermore, the edge of the portion of the connecting via VX forms a certain angle with the extension direction of the first signal line DL. This means that the shape and size of the first signal line DL at the connecting via VX may differ from those at other locations (e.g., pattern distortion). Consequently, when polarized light strikes the portion of the first signal line located within the connecting via VX, the polarized light may undergo metal diffraction depolarization, leading to light leakage at the connecting via VX. In order to shield the connecting vias VX, a larger black matrix needs to be provided, which is not conducive to improving the aperture ratio of the array substrate and will cause the light extraction efficiency of the array substrate to decrease.

[0177] To address the above issues, in some embodiments of the present disclosure, referring to Figures 9, 10, and 13, a first signal line DL is disposed within the display area AA and on the side of the first semiconductor pattern 12 closest to the substrate 11. The array substrate 100 may further include a buffer layer BUF and a fourth via V4. The buffer layer BUF is disposed between the first semiconductor pattern 12 and the first signal line DL. The fourth via V4 penetrates the buffer layer BUF and exposes a portion of the first signal line DL. A portion of the first semiconductor pattern 12 is located within the fourth via V4 and is electrically connected to the first signal line DL through the fourth via V4. This allows the first signal line DL to be disposed on a relatively flat surface, eliminating the need for connecting vias beneath the first signal line DL. The shape and size of the first signal line DL are more uniform, reducing the size of the black matrix that would otherwise obstruct the first signal line DL. This also facilitates a thinner design for the first signal line DL, improving the aperture ratio of the array substrate and the transmittance of the array substrate 100.

[0178] In addition, referring to Figures 9, 10 and 13, the first signal line DL is arranged on the side of the first semiconductor pattern 12 close to the substrate 11, and the first signal line DL and the connecting electrode 21 can be respectively located on both sides of the first semiconductor pattern 12 in the third direction Z, thereby reducing the parasitic capacitance between the first signal line DL and the connecting electrode 21, which is beneficial to reducing the impact of voltage fluctuations on the first signal line DL on the connecting electrode 21 and the first electrode 22.

[0179] In some embodiments, referring to Figures 12 and 13, the fourth via V4 can expose two opposite sidewalls of the first signal line DL. In other words, along a direction perpendicular to the extension direction of the first signal line DL (along the first direction X), the size of the fourth via V4 is larger than the size of the first signal line DL, and both ends of the fourth via V4 expose the first signal line DL. In this way, the area of ​​the first signal line DL exposed by the fourth via V4 can be greatly increased. The orthographic projection of the first semiconductor pattern 12 on the substrate 11 covers at least 1 / 2 of the orthographic projection of the fourth via V4 on the substrate 11. This ensures that the first semiconductor pattern 12 is in full contact with the first signal line DL, which is beneficial for increasing the contact area between the first signal line DL and the first semiconductor pattern 12, improving the connection reliability between the first signal line DL and the first semiconductor pattern 12, and reducing the contact resistance between the first signal line DL and the first semiconductor pattern 12.

[0180] For example, the first semiconductor pattern 12 may completely cover the fourth via hole V2 , which can greatly increase the contact area between the first semiconductor pattern 12 and the first signal line DL and reduce the contact resistance between the first semiconductor pattern 12 and the first signal line DL.

[0181] Furthermore, in some embodiments, referring to FIG. 13 , the buffer layer BUF includes a first sublayer BUF1 and a second sublayer BUF2 stacked in a direction away from the substrate 11. The first sublayer BUF1 is made of silicon nitride SiNx (x > 0), and the second sublayer BUF2 is made of silicon oxide SiOy (y > 0). The first sublayer BUF1 directly contacts the first signal line DL, which helps reduce the oxygen content in the first sublayer BUF1. For example, the material of the first sublayer BUF1 does not include oxygen. Consequently, during the subsequent fabrication of the first semiconductor pattern 12 (in a high-temperature environment), the risk of oxidation of the first signal line DL can be reduced, thereby improving the stability and reliability of the first signal line DL.

[0182] In some embodiments, the thickness of the first sublayer BUF1 along a direction perpendicular to the substrate 11 (the third direction Z) is greater than or equal to 50 nm. For example, the thickness of the first sublayer BUF1 can range from 50 μm to 200 μm (inclusive), or from 200 μm to 500 μm (inclusive), etc., which are not listed in the embodiments of the present disclosure. For example, the thickness of the first sublayer BUF1 can be 50 μm, 80 μm, 100 μm, 150 μm, or 300 μm, etc., which are not listed here.

[0183] In some embodiments, the thickness of the first insulating layer GI is 80 nm to 150 nm along a direction perpendicular to the substrate 11 (the third direction Z). Thus, during the preparation of the array substrate and the annealing process, the first insulating layer GI can effectively protect the connection between the first signal line DL and the first semiconductor pattern 12, thereby reducing the contact resistance between the first signal line DL and the first semiconductor pattern 12. For example, the thickness of the first insulating layer GI can be 80 nm, 100 nm, 115 nm, 130 nm, or 150 nm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0184] In some embodiments, referring to Figures 9, 10 and 13, the first transistor T1 and the second transistor T2 are both oxide thin film transistors. Based on this, an array substrate can be prepared that uses all oxide thin film transistors, which is beneficial to reducing the difficulty and cost of preparing the array substrate.

[0185] The temperature of the preparation process of the oxide thin film transistor is lower (compared to the LTPS process). Based on this, in some embodiments, referring to Figures 9 and 13, the array substrate 100 may further include a lens structure 40 and a third flat layer SOG. The lens structure 40 is arranged on the side of the first transistor T1 close to the substrate 11, for example, on the side of the first signal line DL close to the substrate 11. The lens structure 40 is configured to converge the light directed toward the lens structure 40, which is conducive to enhancing the light directed into the pixel area 101, thereby improving the light transmittance of the array substrate. One lens structure 40 covers at least one pixel area 101.

[0186] The third flat layer SOG is arranged between the lens structure 40 and the first transistor T1. For example, the third flat layer SOG is arranged between the lens structure 40 and the first signal line DL. The refractive index of the lens structure 40 is greater than the refractive index of the third flat layer SOG. On the one hand, the third flat layer SOG can improve the flatness of the plane where the first signal line DL is located and reduce the shape and size errors of the first signal line DL. On the other hand, the light emitted from the lens structure 40 to the third flat layer SOG can be refracted at the interface between the lens structure 40 and the third flat layer SOG, which is beneficial to light convergence, improving the light intensity in the central area of ​​the pixel area 101, and improving the light transmittance of the array substrate.

[0187] Exemplarily, the surface of the lens structure 40 away from the substrate 11 may be an arc-shaped surface. For example, the surface is an arc-shaped surface that bulges from the center of the lens structure 40 toward the side away from the substrate 11 .

[0188] In some embodiments, the refractive index of the lens structure 40 is 1.8 to 2.3; and / or the refractive index of the third flat layer SOG is 1.3 to 1.5. This facilitates the refraction of light emitted from the lens structure 40 toward the third flat layer SOG at the interface between the lens structure 40 and the third flat layer SOG, and converges the light toward the center of the pixel area 101, thereby increasing the light intensity in the center of the pixel area 101 and improving the light transmittance of the display panel. For example, the refractive index of the lens structure 40 can be 1.8, 1.9, 2.0, 2.1, 2.2, or 2.3, etc.; the refractive index of the third flat layer SOG can be 1.3, 1.4, 1.45, or 1.5, etc., which are not listed in detail in the embodiments of the present disclosure.

[0189] In some embodiments, the thickness (maximum thickness) of the lens structure 40 along a direction perpendicular to the substrate 11 (third direction Z) is 800 nm to 1500 nm; and / or the thickness of the third planarization layer SOG is 1.5 μm to 2.5 μm. For example, the thickness of the lens structure 40 is 800 nm, 900 nm, 1000 nm, 1250 nm, 1400 nm, or 1500 nm; and the thickness of the third planarization layer SOG can be 1.5 μm, 1.7 μm, 1.9 μm, 2.0 μm, 2.3 μm, or 2.5 μm, etc., which are not listed in detail in the embodiments of the present disclosure.

[0190] The lens structure 40 can be made of a transparent material to improve the transmittance of the lens structure 40 and the transmittance of the array substrate 100. Exemplary transparent materials include, but are not limited to, silicon nitride (SiNx) and niobium oxide (e.g., niobium pentoxide (Nb2O5)). The material of the third planarization layer (SOG) can include, but is not limited to, silicon-on-glass (SOG) bonding materials.

[0191] In some embodiments, referring to Figures 15 and 16 , the array substrate 100 includes a plurality of opening regions 102. It should be noted that the opening region 102 refers to a region located within the pixel region 101 and used to form the actual light-emitting region of a sub-pixel. For example, the opening region 102 may be the region covered by the orthographic projection of the opening of the black matrix 210 on the color filter substrate on the array substrate 100.

[0192] In some embodiments, referring to FIG15 , a lens structure 40 covers an opening area 102 . This helps accurately improve the light transmittance of each opening area 102 . And / or, referring to FIG16 , the array substrate 100 includes multiple pixel units 103 , each of which includes at least two opening areas 102 that emit different light. This allows the light within each pixel unit 103 to converge at the center of the pixel unit 103 .

[0193] Exemplarily, one lens structure 40 covers all opening areas 102 of one pixel unit 103. For example, referring to FIG16 , the pixel unit 103 includes three opening areas 102, which are respectively configured to emit red, green, and blue light. One lens structure 40 covers the three opening areas 102 included in one pixel unit 103.

[0194] In some embodiments, referring to Figures 15 and 16, the orthographic projection of the lens structure 40 on the substrate 11 at least partially overlaps with the orthographic projection of at least one of the first signal line DL and the second signal line GL on the substrate 11. In this way, the area of ​​the lens structure 40 can be greatly increased so as to converge more light into the opening area 102, greatly improve the brightness of the opening area 102, and improve the luminous brightness of the array substrate 100.

[0195] In some embodiments, referring to Figures 15 and 16 , the size of the pixel region 101 in the first direction X is smaller than the size in the second direction Y, and the spacing between two adjacent pixel regions 101 along the first direction X is smaller than the spacing between two adjacent pixel regions 101 along the second direction Y. Based on this, two adjacent lens structures 40 are connected to each other along the first direction X. And / or, there is a spacing between two adjacent lens structures 40 along the second direction Y. This helps maximize the area of ​​the lens structure 40 and reduces the area outside the opening region 102 from which light is focused, thereby improving the transmittance of the opening region 102.

[0196] In some embodiments, referring to Figures 17 and 18 , the array substrate 100 further includes a third transistor T3, which is disposed on a side of the first transistor T1 closer to the substrate 11 and within the peripheral region BB. Exemplarily, the third transistor T3 is configured to form a gate-on-array (GOA) driver circuit. The third transistor T3 includes a fourth semiconductor pattern 41 and a third electrode structure 42, which is located on a side of the fourth semiconductor pattern 41 farther from the substrate 11. The fourth semiconductor pattern 41 and the first semiconductor pattern 12 comprise different semiconductor materials.

[0197] In some embodiments, the third transistor T3 may be a low temperature polysilicon thin-film transistor (LTPS TFT). LTPS TFTs have advantages such as high mobility and high response speed, which are beneficial to improving the response speed of the gate drive circuit.

[0198] The gate drive circuit can include both the third transistor T3 and the second transistor T2. That is, the gate drive circuit can be formed as a CMOS circuit. This further reduces the space occupied by the gate drive circuit and the width of the peripheral area, thereby facilitating the implementation of a narrow bezel for the array substrate and display device. Furthermore, a gate drive circuit with a CMOS architecture reduces the power consumption of the gate drive circuit and, consequently, the power consumption of the array substrate.

[0199] Referring to Figures 17 and 18 , when the first signal line DL is disposed on a side of the first semiconductor pattern 12 close to the substrate 11, the third electrode structure 42 of the third transistor T3 can be made of the same material and disposed in the same layer as the first signal line DL. In other words, the first signal line DL and the third electrode structure 42 can be formed using the same mask and / or the same material during the same patterning process. This simplifies the fabrication process of the third electrode structure 42, simplifies the fabrication process and difficulty of the array substrate, and reduces the fabrication cost of the array substrate.

[0200] In some embodiments, referring to Figures 17 and 18 , the fourth transistor T4 may further include a first electrode 43 and a second electrode 44, one of which may be a source electrode and the other of which may be a drain electrode. Referring to Figure 17 , the array substrate 100 may further include a second buffer layer 45 located between the fourth semiconductor pattern 41 and the third planarization layer SOG, and an interlayer gate dielectric layer 46 located between the fourth semiconductor pattern 41 and the third electrode structure 42.

[0201] In some embodiments, referring to Figures 17 and 18, the array substrate 100 may further include a fourth insulating layer PVX2 between the first electrode 22 and the second electrode 23, a light-shielding layer 24 located on the side of the second electrode 23 away from the substrate 11, and a spacer (PS) 25 located on the side of the light-shielding layer 24 away from the substrate 11.

[0202] Illustratively, the orthographic projection of the second electrode 23 on the substrate 11 covers the orthographic projection of the light-shielding layer 24 on the substrate 11, and the line width of the light-shielding layer 24 is smaller than the line width of the second electrode 23; the orthographic projection of the light-shielding layer 24 on the substrate 11 also covers the orthographic projection of the spacer 25 on the substrate 11, and the line width of the spacer 25 is smaller than the line width of the light-shielding layer 24.

[0203] Exemplarily, the light-shielding layer 24 may be made of a blackened metal material, which may be a metal material having a light-shielding rate greater than a second threshold value, and the second threshold value may be, for example, 80%, 85%, 90% or 95%, etc., which will not be listed one by one in the embodiments of the present disclosure. The blackened metal material includes, but is not limited to, at least one of molybdenum (Mo), aluminum (Al), molybdenum niobium (MoNb), and molybdenum nickel titanium (MTD). The spacer 25 may be made of an inorganic material and / or an organic material, wherein the inorganic material may include one or more of metal oxides and blackened metal materials; the metal oxide may include, but is not limited to, silicon nitride, silicon oxide, titanium nitride, molybdenum nitride, molybdenum oxide, niobium oxide, niobium nitride, etc. The light-shielding layer 24 and the spacer 25 may be formed by a mask process, for example, by wet etching plus dry etching, and by utilizing the difference in etching bias between the spacer 25 and the light-shielding layer 24, the light-shielding layer 24 and the spacer 25 are formed into a step shape.

[0204] For example, the thickness of the light shielding layer 24 can be 30 nm to 80 nm, and the thickness of the spacer 25 can be 0.4 μm to 1 μm. The light shielding layer 24 can, on the one hand, shield the first signal line DL and the second signal line GL, and on the other hand, reduce the electrical connection with the second electrode 23, and is used to transmit a voltage signal to the second electrode 23. Being arranged in parallel with the second electrode 23, it helps to reduce the resistance of the second electrode 23.

[0205] The spacers 25 are configured to support the array substrate 100 and the color filter substrate and to maintain the liquid crystal cell thickness between the array substrate 100 and the color filter substrate. Of course, the structure of the array substrate 100 is not limited thereto, as long as the same technical concept is used.

[0206] In some embodiments, referring to FIG3A , the first signal line DL can extend in a straight line. The array substrate 100 includes a plurality of first semiconductor patterns 12. The extending direction of the first semiconductor patterns 12 can form a certain angle with the second direction. This helps increase the facing area between the first semiconductor patterns 12 and the first electrode structure 13, increasing the width of the first channel region 121 and improving the characteristics of the first transistor T1. Furthermore, the plurality of first semiconductor patterns 12 are arranged in multiple rows, and the inclination direction of the first semiconductor patterns 12 in the multiple rows is the same.

[0207] In other embodiments, referring to FIG3B , the extension direction of the first signal line DL can be a zigzag line. The array substrate 100 includes a plurality of first semiconductor patterns 12. The extension direction of the first semiconductor patterns 12 can form a certain angle with the second direction. This helps increase the area of ​​contact between the first semiconductor patterns 12 and the first electrode structure 13, increases the width of the first channel region 121, and improves the characteristics of the first transistor T1. Furthermore, the plurality of first semiconductor patterns 12 are arranged in multiple rows, with the first semiconductor patterns 12 in adjacent rows tilted in opposite directions. As shown in FIG3B , the first semiconductor patterns 12 in the first row tilt rightward from top to bottom, while the first semiconductor patterns 12 in the second row tilt leftward from top to bottom.

[0208] It will be appreciated that the shape and extension direction of the first semiconductor pattern 12 are not limited to the above-described embodiment. For example, when the first signal line DL extends along a zigzag line (as shown in FIG3B ), the first semiconductor pattern 12 may also extend along the second direction Y. Alternatively, when the first signal line DL extends along a straight line (as shown in FIG3A ), the first semiconductor pattern 12 may extend along a zigzag line, for example, including a portion extending along the first direction and a portion extending along the second direction. The embodiments of the present disclosure are not limited thereto, as long as the same technical concept is employed.

[0209] The present disclosure also provides a method for preparing an array substrate, which is described by taking the preparation of the array substrate shown in Figure 9 as an example. As shown in Figures 19A to 19D , the method for preparing the array substrate may include steps S100 to S500.

[0210] S100 , referring to FIG. 19A , a lens structure 40 and a third planarization layer SOG are prepared on a substrate 11 .

[0211] For example, the material of the lens structure 40 may include a transparent material with a high refractive index (compared to the third planar layer SOG). For example, the material of the lens structure 40 may include, but is not limited to, silicon nitride (SiNx) or niobium oxide (such as niobium pentoxide (Nb2O5). For example, an initial material layer with a thickness of 800nm ​​to 1500nm may be prepared, and then the initial material layer may be subjected to photolithography and etching processes to form the lens structure 40.

[0212] For example, the third planarization layer SOG can be made of a transparent material with a low refractive index (compared to the lens structure 40). The third planarization layer SOG needs to be able to withstand a certain high temperature environment to prevent deformation of the third planarization layer SOG during the fabrication of the first semiconductor pattern 12. For example, the material of the third planarization layer SOG can include, but is not limited to, a silicon-on-glass (SOG) bonding structure. The thickness of the third planarization layer SOG can be 1.5 μm to 2.5 μm.

[0213] S200 , referring to FIG. 19B , a first conductive layer is formed on the third planarization layer SOG.

[0214] For example, the first conductive layer may include the first signal line DL located in the display area AA and the second sub-electrode 35 or the fourth sub-electrode 37 of the second electrode structure 31 located in the peripheral area. The material of the first conductive layer may include a metal material, for example, one or more of titanium, aluminum, copper, molybdenum, niobium, nickel, and alloys thereof, or the first conductive layer may also be a metal stacked structure. Exemplarily, the first conductive layer may include a titanium-aluminum-titanium (Ti / Al / Ti) stacked structure, a molybdenum-aluminum (Mo / Al) stacked structure, a molybdenum-aluminum-molybdenum (Mo / Al / Mo) stacked structure, a molybdenum niobium-titanium (MoNb / Ti) stacked structure, a molybdenum niobium-titanium-copper (MoNb / Ti / Cu) stacked structure, a molybdenum niobium-copper (MoNb / Cu) stacked structure, a molybdenum nickel titanium-copper (MTD / Cu) stacked structure, a molybdenum niobium-copper-molybdenum titanium nickel (MoNb / Cu / MTD) stacked structure, a molybdenum nickel titanium-copper-molybdenum nickel titanium (MTD / Cu / MTD) stacked structure, a molybdenum-neodymium-copper stacked structure, a MoNb-copper-MoNb stacked structure, and an AlNb-molybdenum-AlNd stacked structure, or a combination thereof. Of course, the embodiments of the present disclosure are not limited thereto, and the first conductive layer may also consider any other suitable metal or metal stacked structure.

[0215] For example, a whole metal material layer may be formed on the third planar layer SOG first, and then patterned using photolithography and etching processes to obtain the first signal line DL and the second sub-electrode 35 or the fourth sub-electrode 37 of the second electrode structure 31 .

[0216] S300 , referring to FIG. 19C , a buffer layer BUF and a first semiconductor layer are formed on a side of the first conductive layer away from the substrate 11 .

[0217] Exemplarily, the material of the buffer layer BUF may include a silicon oxide compound (SiOx, x>0), and the value of x may be 1 or 2. Alternatively, the material of the buffer layer BUF may also include a silicon nitride compound (SiNy, y>0), and the value of y may be 1 or 2, such as SiN and SiN1.33. The buffer layer BUF may be a single layer or a stacked layer structure. For example, the buffer layer BUF is a stacked layer structure including a silicon oxide compound and a silicon nitride compound. In addition, the thickness of the buffer layer BUF may be 200nm to 500nm. Exemplarily, the thickness of the buffer layer BUF may be 200nm, 300nm, 450nm or 500nm, etc., which will not be listed one by one in the embodiments of the present disclosure.

[0218] For example, a film deposition process may be used to form a whole buffer layer BUF, and then a photolithography and etching process may be used to form the fourth via hole V4 on the buffer layer BUF. The fourth via hole V4 may expose a portion of the first signal line DL.

[0219] The material of the first semiconductor layer refers to the material of the first semiconductor pattern 12 described above and is not further described here. The first semiconductor layer may include a first semiconductor pattern 12 located in the display area AA and a second semiconductor pattern 32 located in the peripheral area BB. At least a portion of the first semiconductor pattern 12 is located within the fourth via hole V4 and contacts the first signal line DL.

[0220] S400 , referring to FIG. 19D , a first insulating layer GI1 and a gate line layer are sequentially formed on a side of the first semiconductor layer away from the substrate 11 .

[0221] Exemplarily, the first insulating layer GI may include an insulating material, such as but not limited to aluminum oxide (Al2O3) silicon oxide (SiOx, x>0), where x can be 1 or 2. The first insulating layer GI includes a via hole located in the peripheral area BB, which exposes a portion of the second semiconductor pattern 32.

[0222] Exemplarily, the gate line layer may include a first electrode structure 13 located in the display area AA, a first sub-electrode 34 of the second electrode structure 31 located in the peripheral area BB, and a connecting pattern 38, which is connected to the second semiconductor pattern 32 through the above-mentioned via located in the first insulating layer GI.

[0223] S500, after the gate line layer is prepared and formed, a partial area of ​​the first semiconductor layer can be patterned using processes including but not limited to ion implantation, ion bombardment, and annealing processes, so that parts of the first semiconductor pattern 12 and the second semiconductor pattern 32 are conductive and parts remain as semiconductor materials.

[0224] S600 , referring to FIG. 19E , a second insulating layer ILD and a second semiconductor layer are sequentially formed on a side of the gate line layer away from the substrate 11 .

[0225] For example, the material of the second insulating layer ILD includes, but is not limited to, silicon oxide, silicon nitride (SiNy, y>0), aluminum oxide, and the like.

[0226] For example, the preparation process of the second insulating layer ILD may include: forming a whole layer of a second insulating film, performing photolithography and etching on the second insulating film to form a first via hole V1 in the display area and a seventh via hole V7 in the peripheral area that exposes the connection pattern 38. The depth of the seventh via hole V7 is less than that of the first via hole V1. Therefore, the connection pattern 38, as a stop layer for the seventh via hole V7, needs to withstand a certain amount of etching.

[0227] The material of the second semiconductor layer refers to the material of the third semiconductor pattern 33 described above, and will not be repeated here.

[0228] Exemplarily, the preparation process of the second semiconductor layer may include: forming a second semiconductor layer having a certain pattern, the second semiconductor layer including a first sub-connection electrode 211 located in the display area AA and a third semiconductor pattern 33 located in the peripheral area BB.

[0229] After forming the second semiconductor layer, a mask layer 400 is formed on the second semiconductor layer. The mask layer 400 covers a portion of the third semiconductor pattern 33 and exposes a portion of the third semiconductor pattern 33, as well as the first sub-connecting electrode 211. Then, the mask layer 400 is used as a mask to perform a conductive treatment on the areas of the third semiconductor layer not covered by the mask layer 400. This forms a third channel region 331 and two third polar regions 332 in the third semiconductor pattern 33, and also forms a conductive treatment on the first sub-connecting electrode 211.

[0230] S700, referring to FIG19F, a third insulating layer PVX1, a first flat layer PLN1, a second sub-connecting electrode 321, a second flat layer PLN2, a first electrode 22, a fourth insulating layer PVX2, a second electrode 23, a common voltage signal line CM and a spacer PS are sequentially formed on the side of the second semiconductor layer away from the substrate 11.

[0231] The structures of the third insulating layer PVX1, the first flat layer PLN1, the second sub-connecting electrode 321, the second flat layer PLN2, the first electrode 22, the fourth insulating layer PVX2, the second electrode 23, the light shielding layer 24 and the spacer 25 are described above and are not repeated here.

[0232] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate comprising a display area and a peripheral area located outside the display area; in, The array substrate further includes: substrate; A first transistor is disposed on one side of the substrate and in the display area; the first transistor comprises a first semiconductor pattern and a first electrode structure disposed on a side of the first semiconductor pattern away from the substrate; a connecting electrode, disposed on a side of the first electrode structure away from the substrate and electrically connected to the first semiconductor pattern; A first electrode is disposed on a side of the connecting electrode away from the substrate and is electrically connected to the connecting electrode; A second electrode is disposed on a side of the first electrode away from the substrate; Wherein, at least one of the connecting electrode and the first electrode structure comprises a semiconductor material.

2. The array substrate according to claim 1, in, The array substrate further includes: The second transistor is located on the same side of the substrate as the first transistor and is disposed in the peripheral region, and the second transistor includes a second semiconductor pattern and a third semiconductor pattern; wherein, The second semiconductor pattern includes a second channel region and two second pole regions located at opposite sides of the second channel region; The third semiconductor pattern includes a third channel region and two third pole regions located at opposite sides of the third channel region; The second channel region and the third channel region are spaced apart in a direction perpendicular to the substrate, and an orthographic projection of the second channel region on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate; the second polar region and the third polar region located on the same side of the second channel region and the third channel region are electrically connected.

3. The array substrate according to claim 2, in, The second semiconductor pattern and the first semiconductor pattern include the same material and are disposed in the same layer; and / or, The third semiconductor pattern includes the same material as one of the connection electrode and the first electrode structure including a semiconductor material and is disposed in the same layer.

4. The array substrate according to claim 3, in, The second transistor further includes a second electrode structure, wherein the second electrode structure is at least partially disposed opposite to the second channel region and at least partially disposed opposite to the third channel region.

5. The array substrate according to claim 4, in, The connection electrode comprises a semiconductor material, and the third semiconductor pattern and the connection electrode comprise the same material and are disposed in the same layer.

6. The array substrate according to claim 4 or 5, in, The second electrode structure includes a first sub-electrode arranged between the second semiconductor pattern and the third semiconductor pattern; the first sub-electrode is arranged opposite to the second channel region and the third channel region respectively, and the orthographic projection of the first sub-electrode on the substrate is respectively opposite to the second channel region and the third channel region on the substrate. The orthographic projections of at least partially overlap.

7. The array substrate according to claim 6, in, The first sub-electrode and the first electrode structure include the same material and are disposed in the same layer.

8. The array substrate according to claim 6 or 7, in, The second transistor further includes at least one switching pattern, which is disposed between the second polar region and the third polar region that are close to each other, and is electrically connected to the second polar region and the third polar region respectively; The transfer pattern and the first sub-electrode are made of the same material and are disposed in the same layer.

9. The array substrate according to any one of claims 6 to 8, in, The second electrode structure also includes a second sub-electrode arranged on a side of the second semiconductor pattern close to the substrate, the second sub-electrode is arranged opposite to the second channel region, and the orthographic projection of the second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

10. The array substrate according to claim 9, in, The orthographic projection of the second sub-electrode on the substrate covers the orthographic projections of the second channel region and the third channel region on the substrate, and partially overlaps with the orthographic projection of at least one of the two second polar regions and the two third polar regions on the substrate; The orthographic projection of the second sub-electrode on the substrate also covers the orthographic projection of the first sub-electrode on the substrate, and a boundary of the orthographic projection of the second sub-electrode is spaced from a boundary of the orthographic projection of the first sub-electrode.

11. The array substrate according to claim 9 or 10, in, The display area further includes a first signal line, and the first signal line is arranged on a side of the first semiconductor pattern close to the substrate; The first semiconductor pattern includes a first channel region and two first polar regions located at opposite sides of the first channel region, one of the two first polar regions is electrically connected to the connection electrode, and the other is electrically connected to the first signal line; The first signal line and the second sub-electrode are made of the same material and are disposed in the same layer.

12. The array substrate according to any one of claims 5 to 11, in, The connection electrode comprises a first sub-connection electrode and a second sub-connection electrode, wherein the second sub-connection electrode is located at a side of the first sub-connection electrode away from the substrate; The array substrate further includes: A first insulating layer, disposed between the first semiconductor pattern and the first electrode structure; A second insulating layer is disposed between the first electrode structure and the first sub-connecting electrode; a first via hole, penetrating the second insulating layer and the first insulating layer and exposing a partial area of ​​the first semiconductor pattern; A first planar layer is provided between the first sub-connecting electrode and the second sub-connecting electrode; a second via hole, penetrating the first planar layer; A second planar layer is provided between the second sub-connecting electrode and the first electrode; The first sub-connecting electrode comprises a first portion and a second portion, the first portion is electrically connected to the first semiconductor pattern through the first via hole, and the second portion is located on a surface of the second insulating layer away from the substrate; the second via hole exposes at least a portion of the second portion, the second sub-connecting electrode is connected to the second portion through the second via hole, and the portion of the second sub-connecting electrode located in the second via hole comprises a groove portion recessed toward a side close to the substrate; the second flat layer is disposed in the groove portion, and a surface of the second flat layer away from the substrate is substantially flush with a surface of the second sub-connecting electrode away from the substrate; The third semiconductor pattern and the first sub-connecting electrode include the same material and are disposed in the same layer.

13. The array substrate according to claim 4, in, The first electrode structure includes an auxiliary electrode and an electrode portion, the electrode portion is located at a side of the auxiliary electrode away from the substrate, the material of the auxiliary electrode includes a semiconductor material, and the third semiconductor pattern and the auxiliary electrode include the same material and are arranged in the same layer.

14. The array substrate according to claim 13, in, The second electrode structure comprises a third sub-electrode disposed on a side of the third semiconductor pattern away from the substrate, and a fourth sub-electrode disposed on a side of the second semiconductor pattern close to the substrate; The third sub-electrode is arranged opposite to the third semiconductor pattern, and an orthographic projection of the third sub-electrode on the substrate at least partially overlaps with an orthographic projection of the third channel region on the substrate; The fourth sub-electrode is disposed opposite to the second semiconductor pattern, and an orthographic projection of the fourth sub-electrode on the substrate at least partially overlaps with an orthographic projection of the second channel region on the substrate.

15. The array substrate according to claim 14, in, The third sub-electrode and the electrode portion include the same material and are disposed in the same layer.

16. The array substrate according to claim 14 or 15, in, The display area further includes a first signal line, and the first signal line is arranged on a side of the first semiconductor pattern close to the substrate; The first semiconductor pattern includes a first channel region and two first polar regions located at opposite sides of the first channel region, one of the two first polar regions is electrically connected to the connection electrode, and the other is electrically connected to the first signal line; The first signal line and the fourth sub-electrode are made of the same material and are disposed in the same layer.

17. The array substrate according to any one of claims 13 to 16, in, A third insulating layer is included between the auxiliary electrode and the electrode portion; The auxiliary electrode and the electrode portion are electrically connected in the display area; and / or, The auxiliary electrode and the electrode portion are electrically connected in the peripheral region.

18. The array substrate according to claim 17, further comprising: include: A first insulating layer, disposed between the first semiconductor pattern and the first electrode structure; A second insulating layer and a first planar layer are disposed between the first electrode structure and the connecting electrode, and the first planar layer is located farther from the substrate than the second insulating layer; a third via hole, penetrating the first planar layer, the second insulating layer, the third insulating layer and the first insulating layer, and exposing a partial area of ​​the first semiconductor pattern; A second planar layer is disposed between the connecting electrode and the first electrode; The connecting electrode includes a third part and a fourth part, the third part is electrically connected to the first semiconductor pattern through the third via hole, and the fourth part is located on a surface of the first flat layer away from the substrate and is electrically connected to the first electrode; the third part includes a groove portion recessed toward a side close to the substrate, the second flat layer is arranged in the groove portion, and the surface of the second flat layer away from the substrate is roughly flush with the surface of the fourth part away from the substrate.

19. The array substrate according to any one of claims 2 to 18, in, The second semiconductor pattern and the third semiconductor pattern each include a metal oxide semiconductor material; The electron mobility of the second semiconductor pattern is greater than that of the third semiconductor pattern, and the light stability of the third semiconductor pattern is greater than that of the second semiconductor pattern.

20. The array substrate according to claim 19, in, The second semiconductor pattern includes a high-mobility metal oxide semiconductor material; and / or, The third semiconductor pattern includes indium gallium zinc oxide.

21. The array substrate according to any one of claims 1 to 20, further comprising: include: a third transistor, disposed on a side of the first transistor close to the substrate and disposed in the peripheral region; The third transistor comprises a fourth semiconductor pattern and a third electrode structure, wherein the third electrode structure is located at a side of the fourth semiconductor pattern away from the substrate; The fourth semiconductor pattern and the first semiconductor pattern include different semiconductor materials.

22. The array substrate according to claim 21, in, The first transistor is an oxide thin film transistor; and / or, The third transistor is a low temperature polysilicon thin film transistor.

23. The array substrate according to any one of claims 1 to 22, further comprising: include: A first signal line is disposed in the display area and on a side of the first semiconductor pattern close to the substrate; a buffer layer, disposed between the first signal line and the first semiconductor pattern; a fourth via hole, penetrating the buffer layer and exposing a portion of the first signal line; Part of the first semiconductor pattern is located in the fourth via hole and is electrically connected to the first signal line through the fourth via hole.

24. The array substrate according to claim 23, in, The fourth via hole exposes two opposite side walls of the first signal line, and the first semiconductor pattern is The orthographic projection of the fourth via hole on the substrate at least covers 1 / 2 of the orthographic projection of the fourth via hole on the substrate.

25. The array substrate according to claim 23 or 24, in, The buffer layer includes a first sublayer and a second sublayer stacked in a direction away from the substrate; a material of the first sublayer includes silicon nitride, and a material of the second sublayer includes silicon oxide.

26. The array substrate according to claim 25, in, The thickness of the first sublayer is greater than or equal to 50 nm; and / or, The array substrate further includes a first insulating layer, which is disposed between the first semiconductor pattern and the first electrode structure, and has a thickness of 80 nm to 150 nm.

27. The array substrate according to any one of claims 23 to 26, in, In the case that the array substrate includes a third transistor, the third electrode structure and the first signal line include the same material and are disposed in the same layer.

28. The array substrate according to any one of claims 1 to 27, in, The array substrate further includes: a plurality of opening regions, wherein the opening regions are configured to form a light-emitting region of a sub-pixel; A plurality of lens structures are arranged on a side of the first transistor close to the substrate, the lens structures are configured to converge light incident on the lens structures; one of the lens structures covers at least one of the opening areas; A third planar layer, disposed between the lens structure and the first transistor; Wherein, the refractive index of the lens structure is greater than the refractive index of the third flat layer.

29. The array substrate according to claim 28, in, The refractive index of the lens structure is 1.8 to 2.3; and / or, The refractive index of the third flat layer is 1.3-1.

5.

30. The array substrate according to claim 28 or 29, in, The thickness of the lens structure is 800nm ​​to 1500nm; and / or, The thickness of the third planar layer is 1.5 μm to 2.5 μm.

31. The array substrate according to any one of claims 28 to 30, in, One of the lens structures covers one of the opening areas; and / or, The array substrate includes a plurality of pixel units, each of which includes at least two opening areas for emitting different light rays; one lens structure covers the at least two opening areas of one pixel unit.

32. The array substrate according to claim 31, in, The orthographic projection of the lens structure on the substrate at least partially overlaps with the orthographic projection of the first signal line on the substrate.

33. The array substrate according to claim 32, in, Along the first direction, two adjacent lens structures are connected to each other; and / or, Along the second direction, there is a gap between two adjacent lens structures.

Images