BUCK zero-crossing detection circuit with current tracking and false touch prevention

Abstract

The present application relates to a kind of current tracking BUCK zero-crossing detection circuit of false touch prevention, including BUCK power stage module U1, current tracking detection module U2, signal logic module U3, BUCK power stage module U1 by the clock signal VNP of target BUCK power supply circuit and clock signal VN, in conjunction with the control signal of signal logic module U3, select switching high side NMOS power tube HN or low side NMOS power tube LN and drive conduction, again by current tracking detection module U2 to low side NMOS power tube LN current is tracked, corresponding voltage signal output is generated, signal logic module U3 is processed to the voltage signal and generates control signal output to BUCK power stage module U1;Design circuit accurately controls zero-crossing threshold, and the narrow pulse signal of zero-crossing threshold signal and BUCK power supply circuit are synchronized, not only improve the accuracy of zero-crossing detection, but also prevent false triggering, improve the reliability of circuit.

Description

Technical Field

[0001] This invention relates to a BUCK zero-crossing detection circuit for current tracking to prevent accidental touches, belonging to the field of power supply technology in integrated circuits. Background Technology

[0002] BUCK power supply circuits are indispensable modules in various fields such as communications, computers, and consumer electronics. With the continuous improvement of application performance, higher requirements are placed on the high efficiency and high reliability of BUCK chips. However, the inductor current of traditional BUCK power supply circuits drops below zero under light load, resulting in power loss through the low-power transistor. To address this issue, engineers have proposed a zero-crossing detection circuit. The traditional zero-crossing detection circuit uses a comparator to compare the output SW node voltage with the ground potential. This method has a large error, and it is easy to cause misjudgment when SW has LC resonance, which reduces the accuracy and reliability of the circuit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a BUCK zero-crossing detection circuit with current tracking to prevent false triggering. By tracking the LN current of the low-side NMOS power transistor, the zero-crossing threshold is precisely controlled, and the zero-crossing threshold signal is synchronized with the narrow pulse signal of the BUCK power supply circuit. This not only improves the accuracy of zero-crossing detection, but also prevents false triggering and improves the reliability of the circuit.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: The present invention designs a BUCK zero-crossing detection circuit for current tracking and preventing accidental touch, used for zero-crossing detection of a target BUCK power supply circuit, including a BUCK power stage module U1, a current tracking detection module U2, and a signal logic module U3. The BUCK power stage module U1 includes a high-side NMOS power transistor HN and a low-side NMOS power transistor LN, both with built-in freewheeling diodes. The input terminal of the BUCK power stage module U1 is connected to two non-overlapping clock signals VNP and VN in the target BUCK power supply circuit, respectively corresponding to the high-side NMOS power transistor HN and the low-side NMOS power transistor LN. The controlled terminal of the BUCK power stage module U1 is connected to the control terminal of the signal logic module U3. The BUCK power stage module U1 uses the input clock signals VNP and VN, combined with the control signal output from the control terminal of the signal logic module U3, to selectively switch the high-side NMOS power transistor HN or the low-side NMOS power transistor LN for driving and conducting.

[0005] The detection terminal of the current tracking detection module U2 is connected to the detected terminal of the BUCK power stage module U1. When the low-side NMOS power transistor LN in the BUCK power stage module U1 is turned on, the current tracking detection module U2 tracks the current on the low-side NMOS power transistor LN and generates a corresponding voltage signal, which is output from the output terminal. The output terminal of the current tracking detection module U2 is connected to the input terminal of the signal logic module U3. The signal logic module U3 is used to perform logic processing on the voltage signal output by the current tracking detection module U2 and generate a control signal, which is output from the control terminal to the controlled terminal of the BUCK power stage module U1.

[0006] As a preferred embodiment of the present invention: the BUCK power stage module U1 further includes inverters S6, S8, S9, and S10, an AND gate S7, an inductor L, a capacitor C2, and a load resistor R4. The gate terminal of the high-side NMOS power transistor HN constitutes one input terminal of the BUCK power stage module U1, used to connect to the clock signal VNP in the target BUCK power circuit. The output terminal of inverter S10 is connected in series with inverter S6 and then connected to one input terminal of the AND gate S7. The output terminal of the AND gate S7 is connected in series with inverters S8 and S9 and then connected to the gate terminal of the low-side NMOS power transistor LN. The input terminal of inverter S10 constitutes the other input terminal of the BUCK power stage module U1, used to connect to the clock signal VN in the target BUCK power circuit, and corresponds to the low-side NMOS power transistor LN. The input of inverter S6 and the other input of AND gate S7 constitute two controlled terminals of BUCK power stage module U1, which are used to connect to the control terminal of signal logic module U3. The drain of high-side NMOS power transistor HN is connected to the high-voltage power supply terminal VCC in the target BUCK power supply circuit. The source of high-side NMOS power transistor HN, one end of inductor L, and the drain of low-side NMOS power transistor LN are connected together. This connection position is defined as SW node, which constitutes the detected terminal of BUCK power stage module U1, and is used to connect to the detection terminal of current tracking detection module U2. The other end of inductor L, one end of capacitor C2, and one end of load resistor R4 are connected together. This connection position is defined as VOUT node. The source of low-side NMOS power transistor LN, the other end of capacitor C2, and the other end of load resistor R4 are connected together and grounded.

[0007] As a preferred embodiment of the present invention: the signal logic module U3 includes a comparator S1, an operational amplifier S2, an inverter S3, an inverter S4, an RS latch S5, a capacitor C1, a resistor R2, and a resistor R3. The inverting input of comparator S1 is externally connected to a reference voltage Vref. The non-inverting input of comparator S1 constitutes the input of signal logic module U3. The output of comparator S1 is connected in series with capacitor C1 and then connected to the inverting input of operational amplifier S2 and one end of resistor R3. The non-inverting input of operational amplifier S2 is grounded. The output of operational amplifier S2 and resistor R2... One end of resistor R2, the other end of resistor R3, and the input of inverter S3 are connected together. The other end of resistor R2 is connected to power supply VDD. The output of inverter S3 is connected in series with inverter S4 and then connected to the input R of RS latch S5. The input S of RS latch S5 is used to connect the narrow pulse signal CLK, which is synchronized with the narrow pulse signal in the target BUCK power circuit. The enable control terminal EN of comparator S1 and the output Q of RS latch S5 constitute the two control terminals of signal logic module U3, which are connected to the input of inverter S6 and the other input of AND gate S7 in BUCK power stage module U1, respectively.

[0008] As a preferred embodiment of the present invention: the current tracking detection module U2 includes PMOS transistors M1, M2, M3, M6, M9, NMOS transistors M4, M5, M7, and M8, and a resistor R1. The source terminals of PMOS transistors M1, M2, M3, and M6, the gate terminal of NMOS transistor M8, and the source terminal of PMOS transistor M9 are respectively connected to the power supply VDD. The gate terminals of PMOS transistors M1, M2, and M3 are connected together, and this connection point is connected to the positive terminal of the bias current source I. The drain terminal of PMOS transistor M2, the gate terminal of NMOS transistor M3, and the gate terminal of NMOS transistor M9 are connected together. The drain of transistor M4 and the gate of NMOS transistor M7 are connected together. The drain of PMOS transistor M3, the drain of NMOS transistor M5, the gate of NMOS transistor M4, and the gate of NMOS transistor M5 are connected together. The source of NMOS transistor M5, the source of NMOS transistor M7, and the drain of NMOS transistor M8 are connected together. The source of NMOS transistor M8 forms the detection terminal of current tracking detection module U2. The drain of NMOS transistor M7, the drain of PMOS transistor M6, the gate of PMOS transistor M6, and the gate of PMOS transistor M9 are connected together. The drain of PMOS transistor M9 is connected to one end of resistor R1, and this connection position forms the output terminal of current tracking detection module U2. The negative terminal of bias current source I, the source of NMOS transistor M4, and the other end of resistor R1 are connected together and grounded.

[0009] As a preferred embodiment of the present invention, the size ratio of the low-side NMOS power transistor LN to the NMOS transistor M8 is N:1.

[0010] The BUCK zero-crossing detection circuit for current tracking to prevent accidental touches described in this invention has the following technical advantages compared with the prior art:

[0011] This invention presents a BUCK zero-crossing detection circuit with current tracking to prevent accidental triggering. The circuit includes a BUCK power stage module U1, a current tracking detection module U2, and a signal logic module U3. In the BUCK power stage module U1, the clock signals VNP and VN from the target BUCK power circuit, combined with a control signal from the signal logic module U3, selectively switch between driving either the high-side NMOS power transistor HN or the low-side NMOS power transistor LN to conduct. Then, the current tracking detection module U2 tracks the current on the low-side NMOS power transistor LN when it is conducting, generating a corresponding voltage signal output. The signal logic module U3 performs logic processing on this output voltage signal to generate a control signal output to the BUCK power stage module U1. This circuit design precisely controls the zero-crossing threshold and synchronizes the zero-crossing threshold signal with the narrow pulse signal of the BUCK power circuit, improving the accuracy of zero-crossing detection and preventing accidental triggering, thus enhancing the circuit's reliability. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the BUCK zero-crossing detection circuit for current tracking and accidental touch prevention designed in this invention;

[0013] Figure 2 This is a logic waveform diagram of each signal when the BUCK zero-crossing detection circuit for current tracking and accidental touch prevention designed in this invention is working. Detailed Implementation

[0014] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0015] This invention presents a current-tracking, anti-accidental-touch BUCK zero-crossing detection circuit designed for zero-crossing detection of a target BUCK power supply circuit, such as... Figure 1As shown, the design includes a BUCK power stage module U1, a current tracking detection module U2, and a signal logic module U3. The BUCK power stage module U1 includes a high-side NMOS power transistor HN and a low-side NMOS power transistor LN, both with built-in freewheeling diodes. The input of the BUCK power stage module U1 is connected to two non-overlapping clock signals VNP and VN from the target BUCK power circuit, corresponding to the high-side NMOS power transistor HN and the low-side NMOS power transistor LN, respectively. The controlled terminal of the BUCK power stage module U1 is connected to the control terminal of the signal logic module U3. The BUCK power stage module U1 uses the input clock signals VNP and VN, combined with the control signal output from the control terminal of the signal logic module U3, to selectively switch either the high-side NMOS power transistor HN or the low-side NMOS power transistor LN for conduction. The requirement that the clock signals VNP and VN in the target BUCK power circuit are non-overlapping avoids the simultaneous conduction of the high-side NMOS power transistor HN and the low-side NMOS power transistor LN, which could lead to excessive current and overheating.

[0016] The detection terminal of the current tracking detection module U2 is connected to the detected terminal of the BUCK power stage module U1. When the low-side NMOS power transistor LN in the BUCK power stage module U1 is turned on, the current tracking detection module U2 tracks the current on the low-side NMOS power transistor LN and generates a corresponding voltage signal, which is output from the output terminal. The output terminal of the current tracking detection module U2 is connected to the input terminal of the signal logic module U3. The signal logic module U3 is used to perform logic processing on the voltage signal output by the current tracking detection module U2 and generate a control signal, which is output from the control terminal to the controlled terminal of the BUCK power stage module U1.

[0017] In practical applications, the above design involves real-time acquisition of the two non-overlapping clock signals VNP and VN in the target BUCK power supply circuit. These signals are then substituted into the BUCK zero-crossing detection circuit designed in this invention. The BUCK power stage module U1 tracks the current on the low-side NMOS power transistor LN, precisely controls the zero-crossing threshold, and synchronizes the zero-crossing threshold signal with the narrow pulse signal of the BUCK power supply circuit. This not only improves the accuracy of zero-crossing detection but also prevents false triggering and enhances the reliability of the circuit.

[0018] Regarding the above design in specific practical applications, for the BUCK power stage module U1, such as Figure 1As shown, the design includes a high-side NMOS power transistor HN and a low-side NMOS power transistor LN. Further detailed design includes inverters S6, S8, S9, and S10, an AND gate S7, an inductor L, a capacitor C2, and a load resistor R4. The gate of the high-side NMOS power transistor HN forms one input terminal of the BUCK power stage module U1, used to connect to the clock signal VNP in the target BUCK power circuit. The output of inverter S10 is connected in series with inverter S6 and then connected to one input terminal of AND gate S7. The output of AND gate S7 is connected in series with inverters S8 and S9 and then connected to the gate of the low-side NMOS power transistor LN. The input of inverter S10 forms the other input terminal of the BUCK power stage module U1, used to connect to the clock signal VN in the target BUCK power circuit, corresponding to the low-side NMOS power transistor LN. The input terminals of inverter S6 and AND gate S7 form two controlled terminals of BUCK power stage module U1, used to connect to the control terminals of signal logic module U3. The drain terminal of high-side NMOS power transistor HN is connected to the high-voltage supply voltage VCC in the target BUCK power supply circuit, ranging from 8V to 36V. The source terminal of high-side NMOS power transistor HN, one end of inductor L, and the drain terminal of low-side NMOS power transistor LN are connected together. This connection point is defined as the SW node, which forms the detected terminal of BUCK power stage module U1, used to connect to the detection terminal of current tracking detection module U2. The other end of inductor L, one end of capacitor C2, and one end of load resistor R4 are connected together. This connection point is defined as the VOUT node. The source terminal of low-side NMOS power transistor LN, the other end of capacitor C2, and the other end of load resistor R4 are connected together and grounded. In practical applications, the size of inductor L is selected as 2.2uH, and the size of capacitor C2 is selected as 120uF.

[0019] Further targeting the signal logic module U3, such as Figure 1As shown, the specific design includes comparator S1, operational amplifier S2, inverter S3, inverter S4, RS latch S5, capacitor C1, resistor R2, and resistor R3. The inverting input of comparator S1 is connected to an external reference voltage Vref, such as 100mV. The non-inverting input of comparator S1 forms the input of signal logic module U3. The output of comparator S1 is connected in series with capacitor C1 and then connected to the inverting input of operational amplifier S2 and one end of resistor R3. The non-inverting input of operational amplifier S2 is grounded. The output of operational amplifier S2, one end of resistor R2, the other end of resistor R3, and the input of inverter S3 are connected together. The other end of resistor R2 is connected to the power supply VDD. The output of inverter S3 is connected in series with inverter S4. The input R terminal of RS latch S5 is connected to the input S terminal of RS latch S5. The input S terminal of RS latch S5 is used to connect the narrow pulse signal CLK synchronized with the narrow pulse signal in the target BUCK power circuit. The enable control terminal EN of comparator S1 and the output Q terminal of RS latch S5 constitute the two control terminals of signal logic module U3. They are connected to the input terminal of inverter S6 and the other input terminal of AND gate S7 in BUCK power stage module U1, respectively. In practical applications, comparator S1 adopts a traditional five-transistor comparator, RS latch S5 adopts a traditional NOR gate structure, capacitor C1 is 2pF, resistor R2 is 200KΩ, resistor R3 is 100KΩ, and the operational amplifier adopts a traditional five-transistor op-amp and resistors R2, R3, and capacitor C1 to form a differential structure.

[0020] This invention designs a BUCK zero-crossing detection circuit for current tracking to prevent accidental touches. In practical applications, it also designs a current tracking detection module U2, such as... Figure 1As shown, the system specifically includes PMOS transistors M1, M2, M3, M6, M9, NMOS transistors M4, M5, M7, and M8, and resistor R1. The source terminals of PMOS transistors M1, M2, M3, and M6, the gate terminal of NMOS transistor M8, and the source terminal of PMOS transistor M9 are connected to the power supply VDD. The gate terminals and drain terminals of PMOS transistors M1, M2, and M3 are connected together, and this connection point is connected to the positive terminal of the bias current source I (50uA). The drain terminals of PMOS transistors M2 and M4 are connected to the positive terminal of the bias current source I (50uA). The gate terminals of NMOS transistor M7, M3, M5, M4, and M5 are connected together. The source terminals of NMOS transistor M5, M7, and M8 are connected together. The source terminal of NMOS transistor M8 forms the detection terminal of current tracking detection module U2. The drain terminals of NMOS transistor M7, M6, M6, and M9 are connected together. The drain terminal of PMOS transistor M9 is connected to one end of resistor R1, and this connection position forms the output terminal of current tracking detection module U2. The negative terminal of bias current source I, the source terminal of NMOS transistor M4, and the other end of resistor R1 are connected together and grounded.

[0021] In the specific structure of the BUCK zero-crossing detection circuit described above, in practical applications, the size ratio of the low-side NMOS power transistor LN to the NMOS transistor M8 is designed to be N:1. The power supply VDD connected to the current tracking detection module U2 and the signal logic module U3 is a 5V supply voltage. Furthermore, inverters S3, S4, S6, and S10 are small-sized structures, while inverters S8 and S9, as the driver stages for the low-side NMOS power transistor LN, should use large-sized components. With driving capability, the direction of current I1 is defined as from the source terminal of the low-side NMOS power transistor LN to the VOUT node in the direction of inductor L, the direction of current I2 is from the drain terminal of NMOS transistor M8 to the source terminal of the high-side NMOS power transistor HN, current I3 is the current from PMOS transistor M3 to NMOS transistor M5 branch, current I4 is the current from PMOS transistor M6 to NMOS transistor M7 branch, and current I5 is the current from PMOS transistor M9 to resistor R1 branch. Then the ratio of current I1:I4 is N:1.

[0022] The specific structure of the BUCK zero-crossing detection circuit described above, in practical applications, regarding the BUCK power stage module U1, when the narrow pulse width clock signal in the target BUCK power supply circuit arrives at a high level, the clock signal VNP is high and the clock signal VN is low. In the first stage, the high-side NMOS power transistor HN is turned on, and the low-side NMOS power transistor LN is turned off. The voltage at the SW node is the high-voltage supply voltage VCC. At this time, the inductor current flows from the high-voltage supply voltage VCC through the SW node and inductor L to the VOUT node, and the inductor current rises during this stage. When the inductor current rises above the error amplifier threshold in the target BUCK power supply circuit, it enters the second stage. In this stage, the clock signal VNP is low and the clock signal VN is high. The high-side NMOS power transistor HN is turned off, and the low-side NMOS power transistor LN is turned on. During this stage, due to the reverse electromotive force of the energy storage element, the voltage at the SW node is negative. The inductor current then flows from the GND terminal through the freewheeling diode of the low-side NMOS power transistor LN, the SW node, and then to the VOUT node. Figure 1 The current I1 is shown in the diagram. Based on the second stage, when the inductor current drops to zero, the low-side NMOS power transistor LN remains on. The inductor current flows from the VOUT node through the inductor L, the SW node, and the low-side NMOS power transistor LN to the ground terminal. Current loss occurs during this process, which is what the design scheme of this invention needs to avoid.

[0023] This invention designs a current tracking detection module U2. In the first stage, the voltage at node SW is the high-voltage power supply voltage VCC. The branch current formed by PMOS transistor M2 and NMOS transistor M4 is the current of reference current source I, which is 50uA. The branch current I3 formed by PMOS transistor M3 and NMOS transistor M5 is zero, and the current I4 formed by PMOS transistor M6 and NMOS transistor M7 is zero. Since PMOS transistors M6 and M9 form a current mirror structure, the current I5 formed by PMOS transistor M9 and resistor R1 is zero. In this stage, the voltage signal at the drain of PMOS transistor M9 output by the current tracking detection module U2 is zero. Current tracking detection... When the voltage at the SW node in the second stage of module U2 is negative, the branch current I3 formed by PMOS transistor M3 and NMOS transistor M5 is a bias current of 50uA. Since PMOS transistors M6, M7, M4, and M5 form a negative feedback structure, the sum of the currents I4 and I3 in the branch formed by PMOS transistors M6 and M7, divided by the inductor current in this stage, is equal to the width-to-length ratio N:1 of NMOS transistor LN and NMOS transistor M8. Therefore, the branch current I5 formed by PMOS transistor M9 and resistor R1 is equal to the branch current I4, and the drain voltage of PMOS transistor M9 is current I5 × resistor R1. As the SW node voltage gradually rises from negative to zero in the second stage, the inductor current flows from the VOUT node through the SW node to ground, the current I5 gradually decreases, and the drain voltage of PMOS transistor M9 gradually decreases to zero.

[0024] Regarding signal logic module U3, in the first stage, the enable pin EN of comparator S1 is high, disabling the function of comparator S1. During this stage, the output of comparator S1 is high, and the Q value output by capacitor C1, differentiator, and RS latch S5 is also high. When entering the second stage, the enable pin EN of comparator S1 is low, and comparator S1 operates normally. At this time, the current I5 is 1 / N of the inductor current, the voltage at the positive input of the comparator is greater than the voltage reference Vref, and the output of comparator S1 is high. The entire signal logic module U3 remains unchanged from the first stage.

[0025] In the second stage, as the SW node gradually rises from a negative value to zero potential, the inductor current flows from the VOUT node through the SW node to ground. The current of I5 gradually decreases, and the drain voltage of PMOS transistor M9 gradually decreases to below the reference voltage Vref. Comparator S1 outputs a low level, the differentiator composed of operational amplifier S2, resistors R2 and R3, and capacitor C1 outputs a high level, the input R terminal of latch S5 is high, and the output of RS latch S5 to the input terminal of AND gate S7 is low. At this moment, the output of AND gate S7 changes from high to low. The clock signal VN in the target BUCK power supply circuit is low, turning off the low-side NMOS power transistor LN and avoiding energy loss caused by the inductor current flowing back from the VOUT node through the SW node to ground.

[0026] In practical applications, the value of resistor R1 is 1KΩ, meaning the current I5 is set to 100uA as the toggling threshold of comparator S1. At this point, the current I1 is approximately the width-to-length ratio of NMOS transistor LN to NMOS transistor M8, N × 100uA. The circuit can adjust the accuracy by adjusting the value of resistor R1 to set the threshold of current I1.

[0027] like Figure 2 As shown, the X-axis represents time, and the Y-axis represents the high and low levels of each signal. The first stage plus the second stage is defined as one cycle. The second stage is divided into the first half and the second half. The attached figure shows the waveforms of CLK, VNP, VN, VNN, EN, SW, Q, and I5 within one cycle. When the rising edge of the narrow pulse signal synchronized with the target BUCK power circuit and RS latch S5 arrives in the first stage, the clock signal VNP at the gate of the high-side NMOS power transistor HN is high, and the clock signal VN is low. The high-side NMOS power transistor HN is turned on, and the low-side NMOS power transistor LN is turned off. The voltage of the SW node is high in this stage. The current tracking monitoring module U2 does not work in this stage, and the current I5 is zero. However, since the enable terminal EN of comparator S1 is high in this stage, comparator S1 does not work, and the output Q value is high.

[0028] When the second stage arrives, the clock signal VNP connected to the gate of the high-side NMOS power transistor HN is low, and the clock signal VN connected to the gate of the low-side NMOS power transistor LN is high. At this time, the high-side NMOS power transistor HN is off, and the low-side NMOS power transistor LN is on. Due to the reverse electromotive force of the inductor, the SW node will decrease to a negative value, and the inductor current will flow as follows. Figure 1As shown in Figure I1, the current tracking detection module U2 is working, and the current I5 tracks the change of I1. The magnitude of I5 is 1 / N of the magnitude of the current I1. At this time, the drain voltage of PMOS transistor M9 is (I1 / N) × R1. Since the level of the enable terminal EN of comparator S1 is low at this time, comparator S1 starts to work. Since the drain voltage of PMOS transistor M9 is greater than the voltage reference voltage Vref by 100mV at this time, the output of comparator S1 remains high. The output of RS latch S5 remains unchanged. When the reverse electromotive force energy of inductor L gradually... As the pulse weakens, the voltage level at node SW gradually rises to zero. At this time, current I1 gradually decreases. When the drain voltage (I1 / N) × R1 of PMOS transistor M9 is less than the voltage reference voltage Vref100mV, the output of comparator S1 suddenly drops to zero. After passing through the differentiator circuit, the output voltage reaches the input of RS latch S5, causing the output of RS latch S5 to go low. This, along with AND gate S7, changes the clock signal VN from high to low, turning off the low-side NMOS power transistor LN and preventing inductor current from flowing back to ground. This completes one cycle of the circuit's operation. The same process is repeated when the next narrow pulse width cycle arrives.

[0029] In the specific embodiments of the above invention, except that the high signal voltage of the SW node is VCC, and the voltage value can be 8-36V, the high signal of VNP is VCC+VDD, and the low level of the other signals represents the ground voltage, and the high level represents the VDD voltage, with a voltage value of 5V.

[0030] This invention presents a BUCK zero-crossing detection circuit with current tracking to prevent accidental triggering. The circuit includes a BUCK power stage module U1, a current tracking detection module U2, and a signal logic module U3. In the BUCK power stage module U1, the clock signals VNP and VN from the target BUCK power circuit, combined with a control signal from the signal logic module U3, selectively switch between the high-side NMOS power transistor HN and the low-side NMOS power transistor LN for conduction. Then, the current tracking detection module U2 tracks the current on the low-side NMOS power transistor LN while it is conducting, generating a corresponding voltage signal output. The signal logic module U3 processes this output voltage signal to generate a control signal that is output to the BUCK power stage module U1. This circuit design precisely controls the zero-crossing threshold and synchronizes the zero-crossing threshold signal with the narrow pulse signal of the BUCK power circuit, improving the accuracy of zero-crossing detection, preventing accidental triggering, and enhancing the circuit's reliability.

[0031] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A current-tracking, anti-accidental-touch BUCK zero-crossing detection circuit, used for zero-crossing detection of a target BUCK power supply circuit, characterized in that: The system includes a BUCK power stage module U1, a current tracking detection module U2, and a signal logic module U3. The BUCK power stage module U1 includes a high-side NMOS power transistor HN and a low-side NMOS power transistor LN, both with built-in freewheeling diodes. The input terminal of the BUCK power stage module U1 is connected to two non-overlapping clock signals VNP and VN in the target BUCK power circuit, corresponding to the high-side NMOS power transistor HN and the low-side NMOS power transistor LN, respectively. The controlled terminal of the BUCK power stage module U1 is connected to the control terminal of the signal logic module U3. The BUCK power stage module U1 uses the input clock signals VNP and VN, combined with the control signal output from the control terminal of the signal logic module U3, to selectively switch the high-side NMOS power transistor HN or the low-side NMOS power transistor LN for driving and conducting. The detection terminal of the current tracking detection module U2 is connected to the detected terminal of the BUCK power stage module U1. When the low-side NMOS power transistor LN in the BUCK power stage module U1 is turned on, the current tracking detection module U2 tracks the current on the low-side NMOS power transistor LN and generates a corresponding voltage signal, which is output from the output terminal. The output terminal of the current tracking detection module U2 is connected to the input terminal of the signal logic module U3. The signal logic module U3 is used to perform logic processing on the voltage signal output by the current tracking detection module U2 and generate a control signal, which is output from the control terminal to the controlled terminal of the BUCK power stage module U1.

2. The BUCK zero-crossing detection circuit for current tracking to prevent accidental touches according to claim 1, characterized in that: The BUCK power stage module U1 also includes inverters S6, S8, S9, and S10, an AND gate S7, an inductor L, a capacitor C2, and a load resistor R4. The gate of the high-side NMOS power transistor HN forms one input terminal of the BUCK power stage module U1, used to connect to the clock signal VNP in the target BUCK power circuit. The output of inverter S10 is connected in series with inverter S6 and then connected to one input terminal of AND gate S7. The output of AND gate S7 is connected in series with inverters S8 and S9 and then connected to the gate of the low-side NMOS power transistor LN. The input of inverter S10 forms the other input terminal of the BUCK power stage module U1, used to connect to the clock signal VN in the target BUCK power circuit, and corresponds to the low-side NMOS power transistor LN. The inverter S6... The input terminal and the other input terminal of AND gate S7 constitute two controlled terminals of BUCK power stage module U1, which are used to connect to the control terminal of signal logic module U3. The drain terminal of high-side NMOS power transistor HN is connected to the high-voltage power supply terminal VCC in the target BUCK power supply circuit. The source terminal of high-side NMOS power transistor HN, one end of inductor L, and the drain terminal of low-side NMOS power transistor LN are connected together. This connection position is defined as SW node, which constitutes the detected terminal of BUCK power stage module U1, and is used to connect to the detection terminal of current tracking detection module U2. The other end of inductor L, one end of capacitor C2, and one end of load resistor R4 are connected together. This connection position is defined as VOUT node. The source terminal of low-side NMOS power transistor LN, the other end of capacitor C2, and the other end of load resistor R4 are connected together and grounded.

3. The BUCK zero-crossing detection circuit for current tracking to prevent accidental touches according to claim 2, characterized in that: The signal logic module U3 includes a comparator S1, an operational amplifier S2, an inverter S3, an inverter S4, an RS latch S5, a capacitor C1, and resistors R2 and R3. The inverting input of comparator S1 is connected to an external reference voltage Vref. The non-inverting input of comparator S1 forms the input of signal logic module U3. The output of comparator S1 is connected in series with capacitor C1 and then connected to the inverting input of operational amplifier S2 and one end of resistor R3. The non-inverting input of operational amplifier S2 is grounded. The output of operational amplifier S2, one end of resistor R2, and resistor R3 are connected to... The other end of R3 and the input of inverter S3 are connected together. The other end of resistor R2 is connected to power supply VDD. The output of inverter S3 is connected in series with inverter S4 and then connected to the input R of RS latch S5. The input S of RS latch S5 is used to connect the narrow pulse signal CLK that is synchronized with the narrow pulse signal in the target BUCK power circuit. The enable control terminal EN of comparator S1 and the output Q of RS latch S5 constitute the two control terminals of signal logic module U3, which are connected to the input of inverter S6 and the other input of AND gate S7 in BUCK power stage module U1, respectively.

4. The BUCK zero-crossing detection circuit for current tracking to prevent accidental touches according to claim 1, characterized in that: The current tracking detection module U2 includes PMOS transistors M1, M2, M3, M6, M9, NMOS transistors M4, M5, M7, and M8, and resistor R1. The source terminals of PMOS transistors M1, M2, M3, and M6, the gate terminal of NMOS transistor M8, and the source terminal of PMOS transistor M9 are connected to the power supply VDD. The gate terminals of PMOS transistors M1, M2, and M3 are connected together, and this connection point is connected to the positive terminal of the bias current source I. The drain terminals of PMOS transistors M2, M4, and M8, and the NMOS transistor M9 are connected together. The gate terminals of MOSFET M7 are connected together. The drain terminals of PMOS transistor M3, NMOS transistor M5, NMOS transistor M4, and NMOS transistor M5 are connected together. The source terminals of NMOS transistor M5, NMOS transistor M7, and NMOS transistor M8 are connected together. The source terminal of NMOS transistor M8 forms the detection terminal of current tracking detection module U2. The drain terminals of NMOS transistor M7, PMOS transistor M6, PMOS transistor M6, and PMOS transistor M9 are connected together. The drain terminal of PMOS transistor M9 is connected to one end of resistor R1, and this connection position forms the output terminal of current tracking detection module U2. The negative terminal of bias current source I, the source terminal of NMOS transistor M4, and the other end of resistor R1 are connected together and grounded.

5. The BUCK zero-crossing detection circuit for current tracking to prevent accidental touches according to claim 4, characterized in that: The size ratio of the low-side NMOS power transistor LN to the NMOS transistor M8 is N:1.

Images