Timer

Abstract

The embodiment of the invention relates to a timer. A circuit is provided for managing a first clock signal that clocks a timer adapted to be controlled by a processor that is clocked by a second clock signal. When the processor is turned off, the first clock signal is equal to a third clock signal, and the frequency of the third clock signal is lower than that of the second clock signal. When the processor is turned on, the first clock signal equals a fourth signal having a rising edge at each rising edge of the second clock signal immediately following a rising edge of the third clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to French patent application No. FR2309402, filed on September 7, 2023, with the invention name “Compteur de durée”, which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The present disclosure relates generally to electronic devices and circuits. The present disclosure relates to clocking devices and circuits with clock signals, and more particularly, to clocking timer circuits with clock signals. Background Art

[0004] Currently, complex electronic devices use multiple clock signals with different clock frequencies to clock the different circuits that form it. According to one example, a first master clock signal with a first frequency can be used for certain circuits, such as a processor, and a second auxiliary clock signal with a second frequency can be used for specific circuits, such as a timer circuit. The management of multiple clock signals may require the use of signals to re-clock the circuit.

[0005] It would be desirable to be able to at least partially improve certain aspects of the management of clock signals for electronic devices. Summary of the invention

[0006] What is needed is an electronic device that uses multiple clock signals having different clock frequencies to clock different circuits forming it and that does not include a re-clocking circuit.

[0007] What is needed is an electronic device that uses multiple clock signals having different clock frequencies to clock a timer and does not include a re-clocking circuit.

[0008] There is a need for a circuit for managing a clock signal for a circuit of an electronic device.

[0009] A need exists for a circuit for managing a clock signal for a timer of an electronic device.

[0010] One embodiment overcomes all or some of the disadvantages of known management of multiple clock signals within the same electronic device.

[0011] One embodiment overcomes all or some of the disadvantages of known timers.

[0012] One embodiment provides a circuit for managing a clock signal of a timer such that the use of a re-clocking circuit can be avoided.

[0013] One embodiment provides a method for managing a clock signal of a timer such that the use of a re-clocking circuit can be avoided.

[0014] One embodiment provides a timer equipped with such a circuit for managing a clock signal.

[0015] One embodiment provides an electronic device including a processor and a timer provided with such a circuit for managing a clock signal.

[0016] One embodiment provides a circuit for managing a first clock signal that clocks a timer adapted to be controlled by a processor that is clocked by a second clock signal, wherein:

[0017] When the processor is turned off, the first clock signal is equal to a third clock signal, the frequency of the third clock signal being lower than the frequency of the second clock signal; and

[0018] When the processor is turned on, the first clock signal is equal to a fourth signal that exhibits a rising edge at each rising edge of the second clock signal that immediately follows a rising edge of the third clock signal.

[0019] Another embodiment provides a method of managing a first clock signal that clocks a timer that is adapted to be controlled by a processor that is clocked by a second clock signal, the method being implemented by a circuit for managing the first clock signal, wherein:

[0020] When the processor is turned off, the first clock signal is equal to a third clock signal, the frequency of the third clock signal being lower than the frequency of the second clock signal; and

[0021] When the processor is turned on, the first clock signal is equal to a fourth signal that exhibits a rising edge at each rising edge of the second clock signal that immediately follows a rising edge of the third clock signal.

[0022] According to one embodiment, the management circuit comprises a first circuit for generating said fourth signal.

[0023] According to one embodiment, the management circuit comprises a second circuit for generating a fifth signal which exhibits a rising edge at each rising edge of the second clock signal following a falling edge of the third clock signal.

[0024] According to one embodiment, the management circuit comprises circuitry for managing the state of said processor.

[0025] According to one embodiment, said circuit for managing the state of said processor is adapted to deliver a signal for controlling the state of said processor clocked by said fifth signal.

[0026] According to one embodiment, the frequency of the second clock signal is in the range from 60 MHz to 10 GHz.

[0027] According to one embodiment, the frequency of the third clock signal is in the range from 1 kHz to 100 kHz.

[0028] Another embodiment provides a timer provided with the previously described circuit for managing the first clock signal.

[0029] According to an embodiment, the timer comprises a core adapted to be clocked by said first clock signal.

[0030] According to an embodiment, the timer further comprises a register adapted to be clocked by said second clock signal.

[0031] Another embodiment provides an electronic device including the previously described timer.

[0032] According to one embodiment, the electronic device further comprises the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation, with reference to the accompanying drawings, in which:

[0034] Figure 1 An embodiment of an electronic device and a clock management circuit is schematically shown in block form;

[0035] Figure 2 An embodiment of a clock management circuit is schematically shown in block form;

[0036] Figure 3 Shows the description Figure 2 A timing diagram of the operation of an embodiment of the present invention; and

[0037] Figure 4 Shows the description Figure 2 Other timing diagrams of the operation of embodiments of the present invention. DETAILED DESCRIPTION

[0038] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features among the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0039] For clarity, only the steps and elements that are helpful for understanding the described embodiments are described and illustrated in detail.

[0040] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0041] In the following description, when referring to terms that define absolute positions such as terms "side", "back", "top", "bottom", "left", "right", etc., or relative positions such as terms "above", "below", "upper", "lower", etc., or terms that define directions such as terms "horizontal", "vertical", etc., unless otherwise specified, they refer to the orientation of the drawings.

[0042] Unless otherwise indicated, the expressions "approximately", "substantially", and "about" mean plus or minus 10%, preferably plus or minus 5%.

[0043] The embodiments described below relate to managing the use of multiple clock signals with different clock frequencies within the same electronic device. Specifically, these embodiments relate to an electronic device that includes a timer having certain circuits that are clocked by a master clock signal of the device and other circuits that are clocked by a dedicated clock signal that has a clock frequency that is lower than the clock frequency of the master clock signal. In order to allow circuits that are clocked by different clock signals to coexist in the same timer, re-clocking circuits are typically used to adjust the signals exchanged within the timer. These re-clocking circuits have different disadvantages, and the embodiments described herein strive to avoid the use of re-clocking circuits.

[0044] Indeed, re-clocking of circuits and more generally of signals within the same electronic device may cause delays to occur, such as delays in the starting of a timer circuit, or delays during the reading of data supplied by the timer circuit.

[0045] To this end, the embodiments described in detail below relate to a circuit for managing a single clock signal and a method for managing a single clock signal, the clock signal is supplied to a timer, and the state of the clock signal depends on the operating state of the device, in particular, on the operating state of the main circuit (such as a processor) of the electronic device. When the main circuit of the device is in standby or stopped, all circuits of the timer are clock-controlled by a dedicated clock signal. When the main circuit of the device is running, all circuits of the timer are clock-controlled by an isochronous clock signal, which is clock-controlled by both the main clock signal and the dedicated clock signal. The isochronous clock signal will be described in detail below.

[0046] An advantage of the management circuit and the clock signal management method is that it enables the timer to avoid the use of a re-clocking circuit.

[0047] Figure 1 An embodiment of the electronic device 100 is schematically shown in the form of a block diagram.

[0048] The electronic device 100 is a complex electronic device, which is adapted to include a plurality of electronic circuits.

[0049] The electronic device 100 comprises a main circuit 110 (CPU) adapted to control the main functions of the electronic device 100. According to a preferred embodiment, the main circuit 110 (CPU) is a processor of the electronic device 100. Therefore, in the following, the main circuit 110 is referred to as the processor 110. The processor 110 is rated or clocked by at least one main clock signal Main_Clk of the device 100. According to an example, the frequency of the main clock signal Main_Clk is in the range from 60 MHz to 10 GHz.

[0050] According to one embodiment, the electronic device 100 includes multiple operating modes, and in particular, at least two operating modes: a full power operating mode, during which the processor 110 is operating (running), and at least one standby mode, during which the processor 110 is not running, i.e., turned off or in standby.

[0051] The electronic device 100 further comprises a main clock circuit 120 (Main Clk) adapted to generate a main clock signal Main_Clk. The main clock circuit 120 delivers the main clock signal Main_Clk to the processor 110, but also to other circuits described below.

[0052] According to one embodiment, the electronic device 100 further comprises a timer circuit 130 (timer) or timer 130, which is adapted to be controlled by the processor 110. The timer 130 is configured to time a duration based on a clock signal and, for example, send an alarm signal when an expected duration has been counted.

[0053] To this end, the timer 130 includes a core 131 (timer core) implementing the counting functionality, and one or more registers that enable the timer 130 to exchange data with the processor 110 or with any other circuit of the device 100 that wishes to use the functionality of the timer 130.

[0054] According to one embodiment, the core 131 of the timer 130 exchanges data with the registers and implements the functionality of the timer circuit. The core 131 is clocked by a dedicated clock signal Timer_Clk of the device 100. The generation of the dedicated clock signal Timer_Clk will be described below.

[0055] According to one embodiment, the registers of timer 130 are rated by the clock signal used by the circuitry that is desired to implement timer 130. Figure 1 In this case, the register is rated by the main clock signal Main_Clk that controls the processor 110.

[0056] According to an example, the timer 130 includes a first assembled control register 132 (Control Reg), which is suitable for receiving control signals from the processor 110 and, for example, from other circuits of the device 110 that wish to implement the functionality of the timer 130. According to an example, the control signal received by the control register 132 is a start control signal, a stop control signal, a reset control signal, etc.

[0057] According to one example, the timer 130 comprises a second assembled configuration register 133 (Config Reg), which is suitable for receiving configuration data from the processor 110 and, for example, receiving configuration data from other circuits of the device 110 that wish to implement the functionality of the timer 130. According to one example, the configuration data received by the configuration register 133 is data defining a duration to be counted, data defining a counting condition used by the timer 130, etc.

[0058] According to one example, the timer 130 includes a third assembled state register 134 (State Reg), which is suitable for transmitting state data characterizing the state of the timer 130. According to one example, the state data transmitted by the register 134 is, for example, data indicating that a specific duration has been counted, or data indicating that the timer 130 is counting, etc.

[0059] The electronic device 100 further comprises a clock circuit 140 (LFO Clk), which is dedicated to the clock control of the timer 130 and is adapted to generate a clock signal LFO_Clk. According to one embodiment, the clock frequency of the main clock signal is lower than the clock frequency of the main clock signal Main_Clk. According to one example, the clock frequency of the main clock signal is much lower than the clock frequency of the main clock signal Main_Clk. According to one example, the frequency of the clock signal LFO_Clk is in the range from 1kHz to 100kHz.

[0060] According to one embodiment, the electronic device 100 further comprises a circuit 150 for managing (clock management) a clock signal Timer_Clk of the timer 130. More specifically, the management circuit 150 is adapted to deliver the clock signal Timer_Clk based on the main clock signal Main_Clk, the clock signal LFO_Clk, and the operating state of the device 100 (more specifically, the operating state of the processor 110). Figure 2 Detailed examples of management circuits are described.

[0061] The clock signal Timer_Clk is provided by the following conditions. When the processor 110 is turned off, the clock signal Timer_Clk is equal to the clock signal LFO_Clk. When the processor 110 is turned on, the clock signal Timer_Clk is equal to the signal LFO_Clk_Rise, which presents a rising edge at each rising edge of the main clock signal Main_Clk immediately following the rising edge of the clock signal LFO_Clk. The signal LFO_Clk_Rise is combined with Figures 2 to 4 Isochrones described in further detail.

[0062] An advantage of this embodiment is that it makes it possible to avoid the use of re-clocking circuits within the timer 130. In fact, the data received and transmitted by the registers 132 to 134 must be clocked by the clock signal of the circuit that sends and / or receives them, i.e., here the processor 110. By clocking the core 131 of the timer 130 to the signal LFO_Clk_Rise, the data it receives and transmits is clocked by both the main clock signal Main_Clk and the clock signal LFO_Clk, which makes it possible to avoid additional re-clocking circuits.

[0063] Figure 2 The combination is schematically shown in the form of a box Figure 1 A management circuit 200 of the type of management circuit 150 described and its links to processor 110 (CPU), timer 130 (Timer), and circuits 120 (Main Clk) and 140 (LFO_Clk), all in combination Figure 1 to describe.

[0064] The management circuit 200 is a practical example of an implementation of the previously described management circuit 150. Other practical implementation modes of the management circuit 150 are within the capabilities of a person skilled in the art.

[0065] The management circuit 200 comprises a clock signal management circuit 201 (CLKM). The circuit 201 receives a clock signal LFO_Clk on a first input terminal LFO_Clk and a main clock signal Main_Clk on a second input terminal Main_Clk. The circuit 201 is adapted to deliver a signal for enabling the circuit 140 to generate the clock signal LFO_Clk on a first output LFO_EN. It should be noted that the circuit 140 comprises an input enable terminal EN, which is adapted to receive the enable signal LFO_EN. The circuit 201 is also adapted to deliver a clock signal Timer_PClk on a second output PClk, which is sent to the timer 130 to save data in a register of the timer circuit.

[0066] The clock signal Timer_PClk is a clock generated according to the main clock signal Main_Clk so that the two are completely synchronized. For example, when the clock signal Timer_PClk is enabled, the clock signal Timer_PClk can be the same as the main clock signal Main_Clk. The signal Timer_PClk is enabled by the control register of the clock signal management circuit 201. The control register can be controlled by software. When the processor 110 (CPU) uses the timer 130 or receives data from the timer 130 or sends data to the timer 130, the clock signal Timer_PClk is enabled. As described herein, the processor 110 (CPU) can send control data to the control register 132 (Control Reg) of the timer 130, send configuration data to the configuration register 133 (Configuration Reg), and receive status data from the status register 134 (Status Reg) of the timer 130. However, if the processor 110 (CPU) does not use the timer or does not receive data from the timer 130 or send data to the timer 130, the clock signal Timer_PClk can be disabled. Table 1 shows two operating modes and their corresponding operating states.

[0067]

[0068]

[0069] Table 1: Operation modes and operating states

[0070] The management circuit 200 further comprises a circuit 202 for managing the state of the processor 110, i.e. a circuit configured to receive information of the operating state of the processor 110. Thus, the management circuit 202 is adapted to receive, on an input terminal Req, a signal STBY_Req for requesting a switch to a shutdown or standby state of the processor 110. The management circuit 202 is also adapted to deliver, on an output terminal STOP, a signal STOP_Analog for requesting to stop the master clock of the device.

[0071] The management circuit 200 further comprises a circuit 203 for managing the state of the master clock of the device, i.e. a circuit configured to receive a request for turning on or off the master clock (i.e. the master clock of the circuit 120) and to deliver a control signal corresponding to the circuit 120. Thus, the management circuit 203 is adapted to receive a request signal STOP_Analog on an input terminal Req. The management circuit 202 is further adapted to deliver a signal MAIN_EN for enabling the circuit 120 on an output terminal MAIN_EN. It should be noted that the circuit 120 comprises an enable input terminal EN, which is adapted to receive an enable signal MAIN_EN.

[0072] The management circuit 200 also includes a circuit 204 for generating a signal LFO_Clk_Rise. As previously described, the isochronous signal LFO_Clk_Rise is an isochronous clock signal that is clocked by both a rising edge of the main clock signal Main_Clk and a rising edge of the clock signal LFO_Clk. Therefore, the generating circuit 204 includes a first input LFO_Clk adapted to receive the clock signal LFO_Clk, and a second input Main_Clk adapted to receive the main clock signal Main_Clk. The generating circuit 204 is adapted to trigger the rising edge of the signal LFO_Clk_Rise at a moment when the main clock signal Main_Clk presents a rising edge immediately after the rising edge of the clock signal LFO_Clk. In other words, the rising edge of the signal LFO_Clk_Rise is triggered by the first rising edge of the main clock signal Main_Clk after the rising edge of the clock signal LFO_Clk. A diagram of the generation of the signal LFO_Clk_Rise is shown in Figure 3 and Figure 4 is shown in .

[0073] The management circuit 200 also includes a circuit 205 for generating a signal LFO_Clk_Fall. The isochronous signal LFO_Clk_Fall is an isochronous clock signal that is clocked by both a rising edge of the main clock signal Main_Clk and a falling edge of the clock signal LFO_Clk. Therefore, the generating circuit 205 includes a first input LFO_Clk adapted to receive the clock signal LFO_Clk, and a second input Main_Clk adapted to receive the main clock signal Main_Clk. More specifically, the generating circuit 205 is adapted to trigger a rising edge of the signal LFO_Clk_Fall at a moment when the main clock signal Main_Clk presents a rising edge immediately after a falling edge of the clock signal LFO_Clk. In other words, the rising edge of the signal LFO_Clk_Fall is triggered by the first rising edge of the main clock signal Main_Clk after the falling edge of the clock signal LFO_Clk. A diagram of the generation of the signal LFO_Clk_Rise is shown in Figure 3 and Figure 4 is shown in .

[0074] The management circuit 200 further comprises a dual-input selector 206 which receives the clock signal LFO_Clk on a first input 1 and the signal LFO_Clk_Rise on a second input 0. The selector 206 outputs the clock signal Timer_Clk of the timer 130. The selector 206 is controlled by a signal Status_Reg representing the status of the processor 110. Thus, the selector 206 enables the origin of the signal Timer_Clk to be modified depending on the operating status of the processor 110.

[0075] The management circuit 200 further comprises a flip-flop 207 (DFF) comprising a clock control terminal CK receiving the signal LFO_Clk_Fall, an input terminal D receiving the signal STOP_Analog, and an output terminal Q delivering the signal Status_Reg.

[0076] Figure 3 Two sets of timing diagrams 300 and 350 are included, which illustrate the Figure 1 When the processor 110 described above switches from the running state to the shut-down state (OFF), the Figure 2 The operation of management circuit 200 is described.

[0077] Both sets 300 and 350 of timing diagrams include the following timing diagrams:

[0078] Simplified timing diagram of the main clock signal Main_Clk;

[0079] Timing diagram of clock signal LFO_Clk;

[0080] Timing diagram of signal LFO_Clk_Rise;

[0081] Timing diagram of signal LFO_Clk_Fall;

[0082] Timing diagram of request signal STBY_Req;

[0083] a timing diagram of the control signal STOP_Analog; and

[0084] Timing diagram of the clock signal Timer_Clk.

[0085] As mentioned above, the rising edge of the signal LFO_Clk_Rise is triggered by the first rising edge of the clock signal Main_Clk after the rising edge of the clock signal LFO_Clk. Similarly, the rising edge of the signal LFO_Clk_Fall is triggered by the first rising edge of the clock signal Main_Clk after the falling edge of the clock signal LFO_Clk.

[0086] The switching of the processor 110 from the running state to the shutdown state is triggered by a request transmitted by the signal STBY_Req. Such a request corresponds here to the switching of the signal STBY_Req from a low state to a high state. The control signal STOP_Analog transmits the command to the next rising edge of the signal LFO_Clk_Fall, and thus triggers the stopping of the processor 110 and the circuit 120 and the switching of the original signal of the clock signal Timer_Clk.

[0087] Sets 300 and 350 illustrate two specific cases of these implementations.

[0088] Figure 4 Two sets of timing diagrams 400 and 450 are included, which illustrate the Figure 1 When the processor 110 described above switches from the off state (OFF) to the running state, the Figure 2 The operation of management circuit 200 is described.

[0089] Both sets 400 and 450 of timing diagrams include the following timing diagrams:

[0090] Simplified timing diagram of the main clock signal Main_Clk;

[0091] Timing diagram of clock signal LFO_Clk;

[0092] Timing diagram of signal LFO_Clk_Rise;

[0093] Timing diagram of signal LFO_Clk_Fall;

[0094] Timing diagram of request signal STBY_Req;

[0095] a timing diagram of the control signal STOP_Analog; and

[0096] Timing diagram of the clock signal Timer_Clk.

[0097] The switching of the processor 110 from the off state to the running state is triggered by a request transmitted by the signal STBY_Req. Such a request corresponds here to the switching of the signal STBY_Req from a high state to a low state. The control signal STOP_Analog transmits the command to the next rising edge of the signal LFO_Clk_Fall, and thus triggers the switching of the processor 110 and the circuit 120 and the original signal of the clock signal Timer_Clk.

[0098] Sets 400 and 450 illustrate two cases of this implementation.

[0099] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and those skilled in the art will recognize other variations.

[0100] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0101] A circuit (150) for managing a first clock signal (Timer_Clk) that clocks a timer (130) that is adapted to be controlled by a processor (110) that is clocked by a second clock signal (Main_Clk), the circuit (150) being summarized as comprising: when the processor (110) is off, the first clock signal (Timer_Clk) being equal to a third clock signal (LFO_Clk) having a frequency lower than the frequency of the second clock signal (Main_Clk); and when the processor (110) is on, the first clock signal (Timer_Clk) being equal to a fourth signal (LFO_Clk_Rise) that exhibits a rising edge at each rising edge of the second clock signal (Main_Clk) that immediately follows a rising edge of the third clock signal (LFO_Clk).

[0102] A method for managing a first clock signal (Timer_Clk) for clocking a timer (130) adapted to be controlled by a processor (110) which is clocked by a second clock signal (Main_Clk), the method being implemented by a circuit (150) for managing the first clock signal (Timer_Clk), the method being summarized as comprising: when the processor (110) is off, the first clock signal (Timer_Clk) being equal to a third clock signal (LFO_Clk) having a frequency lower than the frequency of the second clock signal (Main_Clk); and when the processor (110) is on, the first clock signal (Timer_Clk) being equal to a fourth signal (LFO_Clk_Rise) which presents a rising edge at each rising edge of the second clock signal (Main_Clk) immediately following a rising edge of the third clock signal (LFO_Clk).

[0103] The management circuit may include a first circuit for generating (204) said fourth signal (LFO_Clk_Rise).

[0104] The management circuit may include a second circuit for generating (205) a fifth signal (LFO_Clk_Fall) exhibiting a rising edge at each rising edge of the second clock signal (Main_Clk) following a falling edge of the third clock signal (LFO_Clk).

[0105] The management circuit may include circuitry (202) for managing the state of the processor (110).

[0106] The circuit (202) for managing the state of the processor (110) may be adapted to deliver a signal (STOP_Analog) for controlling the state of the processor (110) clocked by the fifth signal.

[0107] The frequency of the second clock signal (Main_Clk) may be in the range from 60 MHz to 10 GHz.

[0108] The frequency of the third clock signal (LFO_Clk) may be in the range from 1 kHz to 100 kHz.

[0109] The timer (130) can be summarized as comprising a circuit (150) equipped for managing the first clock signal (Timer_Clk).

[0110] The timer may comprise a core (131) adapted to be clocked by said first clock signal (Timer_Clk).

[0111] The timer may further comprise a register adapted to be clocked by said second clock signal (Main_Clk).

[0112] The electronic device (100) can be summarized as including a timer (130).

[0113] The device may further comprise the processor (110).

[0114] The various embodiments described above can be combined to provide further embodiments.

[0115] These and other changes can be made to the embodiments in light of the above detailed description. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A circuit comprising: an output configured to output a first clock signal, the first clock signal clocking a timer, the timer being configured to be controlled by a processor, the processor being clocked by a second clock signal, wherein: In response to the processor being shut down, the first clock signal is the same as a third clock signal, the third clock signal having a frequency lower than a frequency of the second clock signal; and In response to the processor being turned on, the first clock signal is identical to a fourth signal having a rising edge at each rising edge of the second clock signal immediately following a rising edge of the third clock signal.

2. The circuit according to claim 1, comprising: A first circuit is configured to generate the fourth signal.

3. The circuit according to claim 1, comprising: A second circuit is configured to generate a fifth signal having a rising edge at each rising edge of the second clock signal immediately following a falling edge of the third clock signal.

4. The circuit according to claim 3, comprising: A third circuit is used to manage the state of the processor. 5 . The circuit of claim 4 , wherein the third circuit is configured to output a signal for controlling the state of the processor clocked by the fifth signal. The circuit according to claim 1 , wherein a frequency of the second clock signal is in a range from 60 MHz to 10 GHz. 7 . The circuit according to claim 1 , wherein a frequency of the third clock signal is in a range from 1 kHz to 100 kHz.

8. A timer, comprising: A circuit, the circuit comprising: an output configured to output a first clock signal, the first clock signal clocking a timer, the timer being configured to be controlled by a processor, the processor being clocked by a second clock signal, wherein: In response to the processor being shut down, the first clock signal is the same as a third clock signal, the third clock signal having a frequency lower than a frequency of the second clock signal; and In response to the processor being turned on, the first clock signal is identical to a fourth signal having a rising edge at each rising edge of the second clock signal immediately following a rising edge of the third clock signal.

9. The timer according to claim 8, comprising: A core is configured to be clocked by the first clock signal.

10. The timer according to claim 8, comprising: A register is configured to be clocked by the second clock signal.

11. The timer according to claim 8, comprising: A first circuit is configured to generate the fourth signal.

12. The timer according to claim 8, comprising: A second circuit is configured to generate a fifth signal having a rising edge at each rising edge of the second clock signal immediately following a falling edge of the third clock signal.

13. The timer according to claim 12, comprising: A third circuit is used to manage the state of the processor.

14. The timer of claim 13, wherein the third circuit is configured to output a signal for controlling the state of the processor clocked by the fifth signal.

15. The timer of claim 8, wherein a frequency of the second clock signal is in a range from 60 MHz to 10 GHz.

16. An electronic device comprising the timer according to claim 9.

17. Electronics according to claim 16, comprising said processor.

18. A method comprising: A first clock signal is output by the circuit, the first clock signal clocks a timer, the timer is configured to be controlled by a processor, the processor is clocked by a second clock signal, wherein: In response to the processor being shut down, the first clock signal is the same as a third clock signal, the third clock signal having a frequency lower than a frequency of the second clock signal; and In response to the processor being turned on, the first clock signal is identical to a fourth signal having a rising edge at each rising edge of the second clock signal immediately following a rising edge of the third clock signal.

19. The method according to claim 18, comprising: The fourth signal is generated by the first circuit.

20. The method according to claim 18, comprising: A fifth signal is generated by the second circuit, the fifth signal having a rising edge at each rising edge of the second clock signal immediately following a falling edge of the third clock signal.

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