Dual-mode low dropout linear regulator and chip thereof

Abstract

The invention relates to a dual-mode low dropout linear regulator and a chip thereof in the technical field of electronic circuits. The voltage stabilizer comprises an operational amplifier, N-type transistors Q1, Q2, PMOS (P-channel Metal Oxide Semiconductor) transistors PM1, PM2, current sources Ibias1, Ibias2, switches S1, S2, a switch JUMP, resistors R1, R2 and an output capacitor Co. Heavy-load configuration: controlling the S1 and the switch JUMP to be switched off, and controlling the S2 to be switched on; and light load configuration: controlling the S1 and the switch JUMP to be switched on, and controlling the S2 to be switched off. Therefore, the Q2 is used for heavy load configuration, and the load driving capacity is high. According to light load configuration, Q2 is not used any more, Q1 is selected as a power tube, certain driving capacity is achieved, meanwhile, part of layout area is saved, different working modes are switched according to actual application scenes, and stable output voltage is obtained. Through experimental simulation, the circuit disclosed by the invention can realize switching of two configurations on the premise of not losing performance functionally, and meanwhile, the Q2 with the largest area in the voltage follower can be multiplexed, so that area optimization is realized.

Description

Technical Field

[0001] The present invention relates to a voltage stabilizer and a voltage stabilizer chip in the technical field of electronic circuits, and in particular to a dual-mode low voltage difference linear voltage stabilizer and a voltage stabilizer chip. Background Art

[0002] With the development of semiconductor integrated circuits, the chip manufacturing process is becoming more and more advanced, which requires the chip to have lower power consumption and area. In a complete chip, the power module occupies a large part of the area and power consumption. How to optimize and reduce the area and power consumption of the power module is very meaningful.

[0003] In the BMS power management chip used in the BMS system, the products of major chip companies all have a simple voltage regulator (LDO) that is led out of the chip. This LDO supplies power to some MCUs and functional modules in the board-level circuit. Figure 1 As shown, LDO mainly has three pins: DRIVE, VREG, and GND. DRIVE is the driving end, VREG is the feedback end, and DNG is the ground end. When LDO is running, it needs to be combined with an off-chip circuit, such as a transistor, a 100Ω resistor, a 1μF capacitor, and a 0.1μF capacitor. The base of the transistor is connected to the driving end DRIVE, the emitter of the transistor is not only connected to the feedback end VREG but also to the ground (ground end DNG) via a 1μF capacitor, and the collector of the transistor is not only connected to the battery voltage BAT via a 100Ω resistor but also to the ground via a 0.1μF capacitor. The base of the transistor is controlled by controlling the voltage of the driving end DRIVE, and the feedback end VREG is fed back to the chip by controlling the output of the transistor, thereby achieving a stable output voltage. At the same time, it can drive a large current load, generally up to 30mA. In the low current scenario, the driver end DRIVE can provide a pull current of about 1mA, but the voltage of the driver end DRIVE at this time is different from the output when driving the off-chip transistor, that is, the voltage of the feedback end VREG. In addition, because the small current scenario does not require the expansion of the off-chip transistor DRIVE end voltage, the accuracy will become lower due to the lack of feedback. Summary of the invention

[0004] Based on this, in order to solve the technical problem of instability in output voltage under large and small current scenarios, the present invention provides a dual-mode low voltage difference linear regulator and its chip. The regulator can switch between different working modes according to the actual application scenarios to obtain a stable output voltage, and can achieve switching between the two configurations without losing performance. At the same time, the MOS tube with the largest area in the voltage follower can be reused to achieve area optimization.

[0005] The present invention is implemented by the following technical solution: a dual-mode low voltage drop linear regulator, whose output terminal V0 has two output configurations: a heavy load configuration and a light load configuration for driving large and small current loads respectively; the regulator includes:

[0006] The negative input of the operational amplifier is connected to the output voltage V of the previous bandgap reference circuit. REF ;

[0007] The voltage follower includes PMOS tubes PM1-PM2, N-type transistor Q1, current source I bias1 ~I bias2 , switches S1~S2; the source of PM1 is connected to the power supply voltage V DD , V DD Also through I bias1 The collector of Q1, the gate of PM1 is not only connected to the collector of Q1 but also to the output of the operational amplifier via S1. The emitter of Q1 is connected via I bias2 Ground GND, the base of Q1 is connected to a fixed bias voltage V bias ; The drain of PM1 is connected to the source of PM2, the gate of PM2 is connected to the output of the operational amplifier via S2, and the drain of PM2 is connected to the emitter of Q1;

[0008] The auxiliary circuit includes an N-type transistor Q2, a switch JUMP and an output capacitor C o , the two ends of the switch JUMP are connected to the base and emitter of Q2 respectively, the base of Q2 is connected to the drain of PM1, the emitter of Q2 is grounded to GND via C0, the collector of Q2 is connected to the battery voltage BAT, and the output terminal V0 is drawn from the emitter of Q2;

[0009] The feedback circuit includes resistors R1 and R2; one end of R1 is connected to the emitter of Q2, and the other end of R1 is not only connected to the positive input end of the operational amplifier but also connected to the ground GND via R2;

[0010] Among them, heavy load configuration: control S1, switch JUMP is open, control S2 is closed;

[0011] Light load configuration: control S1, switch JUMP closed, control S2 open.

[0012] As a further improvement of the above solution, Q1 is replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q1, the source of the CMOS tube replaces the emitter of Q1, and the drain of the CMOS tube replaces the collector of Q1.

[0013] As a further improvement of the above solution, Q2 is replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q2, the source of the CMOS tube replaces the emitter of Q2, and the drain of the CMOS tube replaces the collector of Q2.

[0014] As a further improvement of the above scheme, I bias1 ,I bias2 A single-stage MOS tube current mirror circuit is used for biasing.

[0015] As a further improvement of the above scheme, I bias2 Cascode current mirror biasing is used.

[0016] As a further improvement of the above solution, the switch JUMP adopts a jump cap.

[0017] As a further improvement of the above solution, S1, S2 and switch JUMP all adopt electrically controlled switches.

[0018] As a further improvement of the above scheme, the small current is 1mA±0.5 and the large current is up to 30mA.

[0019] As a further improvement of the above solution, the voltage stabilizer is provided with 6 terminals:

[0020] Lead out terminal 1 from the source of PM1 to connect to V DD ;

[0021] Terminal 2 is connected from the base of Q1 to V bias ;

[0022] Lead out terminal 3 from the negative input of the operational amplifier to connect to V REF ;

[0023] Lead out terminal 4 from the grounded end of R2 to connect to GND;

[0024] Terminal 5 is connected from the collector of Q2 to BAT;

[0025] The output terminal V0 is a connection terminal six, which is used to connect the load of the voltage stabilizer.

[0026] Furthermore, the voltage regulator is also provided with three control terminals for respectively controlling S1, S2 and switch JUMP to be opened or closed.

[0027] The present invention also provides a dual-mode low-voltage dropout linear regulator chip, which is encapsulated by the operational amplifier, voltage follower, and feedback circuit in the above-mentioned dual-mode low-voltage dropout linear regulator, and the auxiliary circuit in the above-mentioned dual-mode low-voltage dropout linear regulator is an off-chip circuit of the chip.

[0028] As a further improvement of the above solution, the chip includes 8 pins:

[0029] Lead out pin 1 from the source of PM1 to connect to V DD ;

[0030] Lead pin 2 from the base of Q1 to connect to V bias ;

[0031] Lead out pin 3 from the negative input terminal of the operational amplifier to connect to V REF ;

[0032] Lead out pin 4 from the grounded end of R2 to connect to GND;

[0033] Pin 5 is led out from the drain of PM1 and is used to be defined as the driving end DRIVE of the chip;

[0034] Lead out a pin 6 from the end of R1 away from R2, which is used to be defined as the feedback terminal VREG of the chip;

[0035] Lead out pin 7 from S1 to control the opening or closing of S1;

[0036] Pin eight is led out from S2 to control the opening or closing of S2.

[0037] The present invention also provides another dual-mode low-voltage dropout linear regulator chip, which is packaged using the above-mentioned entire dual-mode low-voltage dropout linear regulator. The chip includes 9 pins:

[0038] Lead out pin 1 from the source of PM1 to connect to V DD ;

[0039] Lead pin 2 from the base of Q1 to connect to V bias ;

[0040] Lead out pin 3 from the negative input terminal of the operational amplifier to connect to V REF ;

[0041] Lead out pin 4 from the grounded end of R2 to connect to GND;

[0042] Lead pin 5 from the collector of Q2 to connect to BAT;

[0043] The output terminal V0 is pin six, which is used to connect the load of the voltage regulator;

[0044] Lead out pin 7 from S1 to control the opening or closing of S1;

[0045] Lead out pin 8 from S2 to control the opening or closing of S2;

[0046] Pin nine is led out from the switch JUMP and is used to control the opening or closing of the switch JUMP.

[0047] Compared with the prior art, the present invention adds a control circuit to the voltage stabilizer, so that when there is an off-chip power tube Q2, the LDO can work in a heavy-load configuration. By inserting a voltage follower between the operational amplifier and the power tube Q2, the LDO can stably output a fixed voltage under a large current load. When there is no off-chip external power tube Q2, by simply switching the control circuit to enter the light-load configuration, the MOS tube Q1 in the on-chip voltage follower can be reused as a power tube, and an LDO with a small driving capability but high precision and stable output can be realized, thereby solving the technical problem of instability of the output voltage in large and small current scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a common voltage stabilizing circuit in BMS system.

[0049] Figure 2 A circuit diagram of a dual-mode low voltage dropout linear regulator provided in a preferred embodiment of the present invention.

[0050] Figure 3 for Figure 2 Circuit diagram of the regulator in heavy load configuration.

[0051] Figure 4 for Figure 2 Circuit diagram of the mid-regulator in light-load configuration.

[0052] Figure 5 for Figure 2 Equivalent circuit diagram of the voltage regulator.

[0053] Figure 6 for Figure 3 Amplitude-frequency characteristic curve of the medium regulator in heavy load configuration. DETAILED DESCRIPTION

[0054] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0057] The dual-mode low-dropout linear regulator of the present invention has two working configurations: a heavy-load configuration and a light-load configuration. The heavy-load configuration uses an external BJT / FET power tube (i.e., Q2) and has a higher load driving capability; the light-load configuration no longer uses the off-chip power tube Q2, and selects to reuse the large-size MOS tube (i.e., Q1) on the chip as the power tube to achieve a certain driving capability, while saving part of the layout area, switching different working modes according to the actual application scenario, and obtaining a stable output voltage. After experimental simulation, the circuit of the present invention can realize the switching of the two configurations without losing performance in terms of function, and can reuse the MOS tube Q1 with the largest area in the voltage follower to achieve area optimization.

[0058] See also Figure 2 , which is a circuit diagram of a dual-mode low-dropout linear regulator provided by Embodiment 1 of the present invention. The dual-mode low-dropout linear regulator includes: an operational amplifier EA, a voltage follower Buffer, a feedback circuit, and an auxiliary circuit.

[0059] The negative input terminal of the operational amplifier is connected to the output voltage V of the previous bandgap reference circuit. REF The voltage follower includes PMOS tubes PM1~PM2, N-type transistor Q1, current source I bias1 ~I bias2 , switches S1~S2. The source of PM1 is connected to the power supply voltage V DD , V DD Also through I bias1 The collector of Q1, the gate of PM1 is not only connected to the collector of Q1 but also to the output of the operational amplifier via S1. The emitter of Q1 is connected via I bias2 Ground GND, the base of Q1 is connected to a fixed bias voltage V bias The drain of PM1 is connected to the source of PM2, and the connection forms a node DRIVE. The gate of PM2 is connected to the output of the operational amplifier via S2, and the drain of PM2 is connected to the emitter of Q1. The auxiliary circuit includes an N-type transistor Q2, a switch JUMP, and an output capacitor C oThe switch JUMP can be a jumper. The two ends of the switch JUMP are connected to the base and emitter of Q2 respectively. The base of Q2 is connected to the drain of PM1, the emitter of Q2 is connected to the ground GND via C0, the collector of Q2 is connected to the battery voltage BAT, and the output terminal V0 is drawn from the emitter of Q2. The feedback circuit includes resistors R1~R2. One end of R1 forms the node VREG and is also connected to the emitter of Q2. The other end of R1 is not only connected to the positive input of the operational amplifier but also to the ground GND via R2.

[0060] Among them, heavy load configuration: control S1, switch JUMP is open, control S2 is closed. Light load configuration: control S1, switch JUMP is closed, control S2 is open.

[0061] Overload configuration: see attached Figure 3 , by controlling the switches S1 and JUMP to be open and S2 to be closed. At this time, the LDO architecture is an op amp + buffer + power tube structure. By introducing the buffer to push up the op amp output pole and the power tube gate pole, the LDO can achieve high precision and stability in a wide load range. When configured with heavy load, the current is large, and the large current can be as high as 30mA.

[0062] Light load configuration: see attached Figure 4 , by controlling the switches S1 and JUMP to close and S2 to open, the LDO architecture is now a classic op amp + power tube structure, which can achieve high precision and stability of LDO under small current load. When configured with light load, the output current is small, and the small current is 1mA±0.5.

[0063] In order to facilitate the switching between heavy-load configuration and light-load configuration, S1, S2, and switch JUMP can all use electronically controlled switches. Mechanical switches are only suitable for manual operation and are not suitable for automatic control. Through the switching control of S1, S2, and switch JUMP, two output configurations of the voltage regulator are realized, so that the LDO of the present invention is designed as a dual-mode low-voltage difference linear regulator: under heavy-load configuration, an external power tube is used to drive a large current load, and under light-load configuration, the on-chip MOS tube is reused as a power tube to realize a low-power circuit while reducing the layout area overhead. Therefore, the voltage regulator of the present invention can be an LDO without external capacitors or an LDO with large external capacitors.

[0064] The current source I in the actual circuit bias1 ,I bias2 It can be biased with a simple single-stage MOS tube current mirror circuit. bias2 It can also be biased with a cascode current mirror. If a cascode current mirror with a higher output impedance is used, the output impedance of the buffer will be reduced by nearly 1 times, further pushing up the pole and improving the LDO phase margin.

[0065] by Figure 2For example, the buffer of the traditional FVF structure needs to adjust the width-to-length ratio of PM1 and PM2 to achieve the optimal output impedance. In the present invention, because the transistor PM1 needs to be reused, more tube area is allocated to PM1. Under the premise of not losing the buffer performance, the area ratio of the reused tube is increased as much as possible to improve the practical value. At the same time, using transistor Q1 to replace the MOS tube in the traditional structure FVF can improve the loop gain, further reduce the output impedance, and improve the phase margin of the LDO. If Q1 is replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q1, the source of the CMOS tube replaces the emitter of Q1, and the drain of the CMOS tube replaces the collector of Q1. Q2 can also be replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q2, the source of the CMOS tube replaces the emitter of Q2, and the drain of the CMOS tube replaces the collector of Q2. Therefore, the voltage follower (buffer) connected between the operational amplifier and the power tube (the power tube can be an N-type tube or a P-type tube) of the present invention is a flip voltage follower (FVF) structure, and a transistor Q1 is connected in series in its feedback loop to increase the loop gain, thereby achieving a lower output impedance than the traditional FVF structure voltage follower and improving the performance of the designed LDO. It should be noted that both transistors Q1 and Q2 can be FET tubes, see Figure 5 .

[0066] See also Figure 6 , which is the amplitude-frequency characteristic curve of the dual-mode LDO heavy-load mode of the present invention. As can be seen from the figure, within the load current range of 100uA to 10mA, the bandwidth of the LDO is a minimum of 15.8kHz and a maximum of 251.2kHz, and the phase margin is a minimum of 52°, which can achieve LDO stability within the full load range. Therefore, the technical solution of the present invention is feasible.

[0067] In this embodiment, the operational amplifier EA operates at any V DD Under power supply, the positive input terminal is connected to the signal VFB; the negative input terminal is connected to the output voltage VREF of the previous bandgap reference circuit; the output terminal is connected to the positive terminal of switch S2. The base of N-type transistor Q1 is connected to the fixed bias voltage V bias ; The emitter is connected to the current source I bias2 The positive terminal of the switch S1; the collector is connected to the negative terminal of the switch S1. The base of the N-type transistor Q2 is connected to the DRIVE signal; the emitter is connected to the output terminal Vo; the collector is connected to the battery voltage BAT. The gate of PM1 is connected to the current source I bias1 Negative terminal; source connected to power supply voltage V DD ; The drain is connected to the DRIVE signal. The gate of PM2 is connected to the negative terminal of switch S2; the source is connected to the DRIVE signal; the drain is connected to the current source I bias2 Positive terminal. Current source I bias1 Positive terminal supply voltage V DD; The negative end is connected to the negative end of switch S1. Current source I bias2 The positive terminal is connected to the drain of PM2; the negative terminal is connected to GND. The positive terminal of switch S1 is connected to the output of op amp EA; the negative terminal is connected to the gate of PM1. The positive terminal of switch S2 is connected to the output of op amp EA; the negative terminal is connected to the gate of PM2. The positive terminal of resistor R1 is connected to VFB; the negative terminal is connected to the LDO output Vo. The positive terminal of resistor R2 is connected to ground GND; the negative terminal is connected to the VFB signal. The positive terminal of output capacitor Co is connected to Vo; the negative terminal is connected to ground. Load resistor R load The positive terminal is connected to Vo, and the negative terminal is grounded. The positive terminal of the jumper cap JUMP is connected to the base of the transistor Q2, and the negative terminal is connected to Vo.

[0068] The present invention can realize that when there is an off-chip power tube, the LDO works in a heavy-load configuration by simply adding a control circuit, and by inserting a voltage follower between the operational amplifier and the power tube, the LDO can stably output a fixed voltage under a large current load. When there is no off-chip external power tube, by simply switching the control circuit to enter the light-load configuration, the MOS tube in the on-chip voltage follower can be reused as a power tube, and an LDO with a small driving capability but high precision and stable output can be realized.

[0069] The dual-mode low-dropout linear regulator of the present invention can be designed as a circuit module when in use, so that the user does not need to use various components to connect the corresponding circuit of the regulator, and can directly use the regulator circuit module. The regulator can be provided with 6 terminals: Terminal 1 is led out from the source of PM1, which is used to connect V DD ; Terminal 2 is connected from the base of Q1 to V bias ; Terminal 3 is connected from the negative input of the operational amplifier to V REF ; Terminal 4 is led out from the grounded end of R2 for connecting to GND; Terminal 5 is led out from the collector of Q2 for connecting to BAT; Output terminal V0 is terminal 6 for connecting to the load of the voltage regulator. In order to facilitate the control of the switch, the voltage regulator can also be provided with three control terminals for controlling S1, S2, and switch JUMP to open or close respectively, and the corresponding switch control instructions are connected through the control terminals.

[0070] The dual-mode low-dropout linear regulator of the present invention can be designed as a chip when in use. There are multiple modes for designing a chip. For example, in the first mode, the operational amplifier, the voltage follower, and the feedback circuit are packaged into a chip, and the auxiliary circuit is an off-chip circuit of the chip. Such a chip can be designed with at least 8 pins: Pin 1 is led out from the source of PM1, and is used to connect V DD ; Pin 2 is connected from the base of Q1 to V bias ; Lead out pin 3 from the negative input of the operational amplifier to connect to V REF; Pin 4 is led out from the grounded end of R2 for connecting to GND; Pin 5 is led out from the drain of PM1 and is defined as the driving end DRIVE of the chip; Pin 6 is led out from the end of R1 away from R2 and is defined as the feedback end VREG of the chip; Pin 7 is led out from S1 and is used to control the opening or closing of S1; Pin 8 is led out from S2 and is used to control the opening or closing of S2.

[0071] For example, in the second method, the entire dual-mode low-dropout linear regulator is packaged into a chip. Such a chip can be designed with at least 9 pins: Pin 1 is led out from the source of PM1 to connect to V DD ; Pin 2 is connected from the base of Q1 to V bias ; Lead out pin 3 from the negative input of the operational amplifier to connect to V REF ; Pin 4 is led out from the grounded end of R2 for connecting to GND; Pin 5 is led out from the collector of Q2 for connecting to BAT; the output end V0 is pin 6 for connecting to the load of the regulator; Pin 7 is led out from S1 for controlling the opening or closing of S1; Pin 8 is led out from S2 for controlling the opening or closing of S2; Pin 9 is led out from the switch JUMP for controlling the opening or closing of the switch JUMP.

[0072] In summary, the LDO of the present invention has two configurations, heavy load and light load. The heavy load configuration uses an external BJT / FET power tube, which has a higher load driving capability; the light load configuration no longer uses an off-chip power tube, and selects to reuse the large-size MOS tube in the chip as the power tube to achieve a certain driving capability, while saving part of the layout area, switching different working modes according to the actual application scenario, and obtaining a stable output voltage. After experimental simulation, the circuit of the present invention can realize the switching of the two configurations without losing performance, and can reuse the MOS tube with the largest area in the voltage follower to achieve area optimization.

[0073] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A dual-mode low-dropout linear regulator, characterized in that: Its output terminal V0 has two output configurations: a heavy load configuration and a light load configuration for driving large and small current loads respectively; the voltage regulator includes: The negative input of the operational amplifier is connected to the output voltage V of the previous bandgap reference circuit. REF ; The voltage follower includes PMOS tubes PM1-PM2, N-type transistor Q1, current source I bias1 ~I bias2 , switches S1~S2; the source of PM1 is connected to the power supply voltage V DD , V DD Also through I bias1 The collector of Q1, the gate of PM1 is not only connected to the collector of Q1 but also to the output of the operational amplifier via S1. The emitter of Q1 is connected via I bias2 Ground GND, the base of Q1 is connected to a fixed bias voltage V bias ; The drain of PM1 is connected to the source of PM2, the gate of PM2 is connected to the output of the operational amplifier via S2, and the drain of PM2 is connected to the emitter of Q1; The auxiliary circuit includes an N-type transistor Q2, a switch JUMP and an output capacitor C o , the two ends of the switch JUMP are connected to the base and emitter of Q2 respectively, the base of Q2 is connected to the drain of PM1, the emitter of Q2 is grounded to GND via C0, the collector of Q2 is connected to the battery voltage BAT, and the output terminal V0 is drawn from the emitter of Q2; The feedback circuit includes resistors R1 and R2; one end of R1 is connected to the emitter of Q2, and the other end of R1 is not only connected to the positive input end of the operational amplifier but also connected to the ground GND via R2; Among them, heavy load configuration: control S1, switch JUMP is open, control S2 is closed; Light load configuration: control S1 and switch JUMP to close, and control S2 to open.

2. The dual-mode low-dropout linear regulator according to claim 1, characterized in that: Q1 is replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q1, the source of the CMOS tube replaces the emitter of Q1, and the drain of the CMOS tube replaces the collector of Q1; And / or, Q2 is replaced by a CMOS tube, the gate of the CMOS tube replaces the base of Q2, the source of the CMOS tube replaces the emitter of Q2, and the drain of the CMOS tube replaces the collector of Q2.

3. The dual-mode low-dropout linear regulator according to claim 1, characterized in that: I bias1 ,I bias2 A single-stage MOS tube current mirror circuit is used for biasing.

4. The dual-mode low-dropout linear regulator according to claim 1, characterized in that: I bias2 Cascode current mirror biasing is used.

5. The dual-mode low-dropout linear regulator according to claim 1, characterized in that: The switch JUMP uses a jumper cap; and / or, S1, S2, and switch JUMP are all electrically controlled switches; And / or, small current is 1mA±0.5, large current is up to 30mA.

6. The dual-mode low-dropout linear regulator according to claim 1, characterized in that: The voltage regulator is provided with 6 terminals: Lead out terminal 1 from the source of PM1 to connect to V DD ; Terminal 2 is connected from the base of Q1 to V bias ; Lead out terminal 3 from the negative input of the operational amplifier to connect to V REF ; Lead out terminal 4 from the grounded end of R2 to connect to GND; Terminal 5 is connected from the collector of Q2 to BAT; The output terminal V0 is a connection terminal six, which is used to connect the load of the voltage stabilizer.

7. The dual-mode low-dropout linear regulator according to claim 6, characterized in that: The voltage stabilizer is also provided with three control terminals for respectively controlling S1, S2 and switch JUMP to be opened or closed.

8. A dual-mode low voltage dropout linear regulator chip, characterized in that: It is encapsulated by the operational amplifier, voltage follower and feedback circuit in the dual-mode low-dropout linear regulator as claimed in claim 1, and the auxiliary circuit in the dual-mode low-dropout linear regulator as claimed in claim 1 is an off-chip circuit of the chip.

9. The dual-mode low-dropout linear regulator chip according to claim 8, characterized in that: The chip includes 8 pins: Lead out pin 1 from the source of PM1 to connect to V DD ; Lead pin 2 from the base of Q1 to connect to V bias ; Lead out pin 3 from the negative input terminal of the operational amplifier to connect to V REF ; Lead out pin 4 from the grounded end of R2 to connect to GND; Pin 5 is led out from the drain of PM1 and is used to be defined as the driving end DRIVE of the chip; Lead out a pin 6 from the end of R1 away from R2, which is used to be defined as the feedback terminal VREG of the chip; Lead out pin 7 from S1 to control the opening or closing of S1; Pin eight is led out from S2 to control the opening or closing of S2.

10. A dual-mode low voltage dropout linear regulator chip, characterized in that: It is packaged using the dual-mode low-dropout linear regulator as claimed in claim 1, and the chip includes 9 pins: Lead out pin 1 from the source of PM1 to connect to V DD ; Lead pin 2 from the base of Q1 to connect to V bias ; Lead out pin 3 from the negative input terminal of the operational amplifier to connect to V REF ; Lead out pin 4 from the grounded end of R2 to connect to GND; Lead pin 5 from the collector of Q2 to connect to BAT; The output terminal V0 is pin six, which is used to connect the load of the voltage regulator; Lead out pin 7 from S1 to control the opening or closing of S1; Lead out pin 8 from S2 to control the opening or closing of S2; Pin nine is led out from the switch JUMP and is used to control the opening or closing of the switch JUMP.

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