Method and apparatus for isa emulation

Abstract

This disclosure relates to a method and apparatus for ISA emulation. The method includes: detecting an illegal instruction exception triggered by an illegal instruction in user mode of the CPU; in response to the illegal instruction exception, invoking a user mode illegal instruction exception handler configured in a first CSR; in response to the execution of the exception handler, obtaining runtime data associated with a thread from a second CSR and obtaining the instruction address of the illegal instruction from a third CSR; performing ISA emulation on one or more instructions in user mode based on the obtained runtime data and the instruction address of the illegal instruction; and, upon completion of ISA emulation on one or more instructions, resuming normal instruction execution flow of the application from the exception handler in response to the execution of a first instruction.

Description

Technical Field

[0001] This disclosure relates to the field of computers, and more specifically, to methods and apparatus for instruction set architecture (ISA) emulation. Background Technology

[0002] Binary translation (BT) is a technology that directly translates executable binary programs. It can translate binary programs on one processor to be executed on another processor, making binary programs between different processors easily portable, thereby expanding the applicability of hardware and software.

[0003] Existing ISA emulation solutions use Bitwise Transmission (BT) technology to emulate unsupported instructions when an illegal instruction exception is triggered. In existing solutions, each exception handling involves at least two context switches between kernel and user space, which introduces significant context switching overhead and greatly impacts BT performance. Summary of the Invention

[0004] According to embodiments of this disclosure, a method for ISA emulation is provided, comprising: detecting an illegal instruction exception triggered by an illegal instruction in user mode of a CPU; in response to detecting the illegal instruction exception, invoking a user mode illegal instruction exception handler configured in a first control status register (CSR); in response to the execution of the user mode illegal instruction exception handler, obtaining runtime data associated with a thread including the illegal instruction from a second CSR and obtaining the instruction address of the illegal instruction from a third CSR; performing ISA emulation on one or more instructions associated with the thread including the illegal instruction in user mode based on the obtained runtime data and the instruction address of the illegal instruction; and, upon completion of the ISA emulation on the one or more instructions, resuming normal instruction execution flow of the application from the user mode illegal instruction exception handler in response to the execution of a first instruction.

[0005] According to embodiments of this disclosure, an apparatus for ISA emulation is provided, wherein the apparatus includes processor circuitry configured to perform the method for ISA emulation described above.

[0006] According to embodiments of the present disclosure, a computer-readable storage medium is provided having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method described above for ISA emulation.

[0007] According to embodiments of this disclosure, a computer program product is provided, including instructions, wherein when executed by a processor, the instructions cause the processor to perform the method described above for ISA emulation.

[0008] This disclosure constructs an optimized user-space exception handling mechanism by introducing support for new CSRs and new instructions. Using this mechanism, the corresponding hardware logic can directly perform BT context switching, thereby eliminating the overhead of context switching between kernel and user space in previous solutions and improving processor performance when handling BT tasks. This mechanism enables application-agnostic and low-overhead ISA translation, provides backward software compatibility for handling obsolete and deprecated instructions, and provides forward software compatibility for supporting new user-mode instructions. Attached Figure Description

[0009] Embodiments of this disclosure will be described by way of example, not limitation, in conjunction with the accompanying drawings, wherein similar reference numerals denote similar elements, and wherein:

[0010] Figure 1 The diagram illustrates a block diagram of an example processor and / or SoC 100, which may have one or more cores and an integrated memory controller.

[0011] Figure 2 A flowchart of a method for ISA simulation according to an embodiment of the present disclosure is shown.

[0012] Figure 3 An example configuration of utvec CSR according to an embodiment of this disclosure is shown.

[0013] Figure 4 An example configuration of the uebp CSR according to an embodiment of this disclosure is shown.

[0014] Figure 5 An example configuration of uepc CSR according to an embodiment of this disclosure is shown.

[0015] Figure 6 A schematic diagram of a workflow for handling illegal instruction exceptions according to an embodiment of the present disclosure is shown.

[0016] Figure 7 A schematic diagram of the per-vCPU context stack and software-simulated registers according to an embodiment of the present disclosure is shown.

[0017] Figure 8 A schematic diagram of the initialization process of uebp CSR according to an embodiment of the present disclosure is shown.

[0018] Figure 9A flowchart of BT context switching in an ISA simulation according to an embodiment of the present disclosure is shown.

[0019] Figure 10 This is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. This application is by no means limited to any specific configuration presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this application. Well-known structures and techniques are not shown in the accompanying drawings and the following description in order to avoid unnecessarily obscuring this application.

[0021] Furthermore, the various operations will be described as multiple discrete operations in a manner most conducive to understanding the illustrative embodiments; however, the order of description should not be construed as implying that these operations must depend on the order. In particular, these operations do not need to be performed in the order presented.

[0022] The phrases “in an embodiment,” “in one embodiment,” and “in some embodiments” are used repeatedly throughout this document. These phrases do not typically refer to the same embodiment; however, they may refer to the same embodiment. Unless the context otherwise specifies, the terms “comprising,” “having,” and “including” are synonyms. The phrases “A or B” and “A / B” mean “(A), (B) or (A and B).”

[0023] Figure 1 A block diagram of an example processor and / or SoC 100 is illustrated, which may have one or more cores and an integrated memory controller. The processor 100 illustrated by solid-line boxes has a single core 102(A), system proxy unit circuitry 110, and a set of one or more interface controller unit circuitry 116, while alternative processors 100 can be illustrated by dashed-line boxes having multiple cores 102(A)-(N), a set of one or more integrated memory control unit circuitry 114 in the system proxy unit circuitry 110, dedicated logic 108, and a set of one or more interface controller unit circuitry 116.

[0024] Different implementations of processor 100 may include: 1) a CPU, where dedicated logic 108 is integrated graphics and / or scientific (throughput) logic (which may include one or more cores, not shown), and cores 102(A)-(N) are one or more general-purpose cores (e.g., general-purpose ordered cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 102(A)-(N) are a large number of dedicated cores primarily for graphics and / or scientific (throughput) purposes; and 3) a coprocessor, where cores 102(A)-(N) are a large number of general-purpose ordered cores. Thus, processor 100 may be a general-purpose processor, a coprocessor, or a dedicated processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (General-Purpose Graphics Processing Unit), a high-throughput integrated many-core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor may be implemented on one or more chips. The processor 100 may be part of one or more substrates and / or may be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0025] The memory hierarchy includes one or more levels of cache cell circuitry 104(A)-(N) within cores 102(A)-(N), a group of one or more shared cache cell circuitry 106, and external memory (not shown) coupled to the group of integrated memory controller cell circuitry 114. The group of one or more shared cache cell circuitry 106 may include one or more intermediate level caches, such as level 2 (L2), level 3 (L3), level 4 (4), or other levels of cache, such as the last-level cache (LLC), and / or combinations thereof. While in some examples interface network circuitry 112 (e.g., a ring interconnect) provides an interface to dedicated logic 108 (e.g., integrated graphics logic), the group of shared cache cell circuitry 106, and system agent cell circuitry 110, alternative examples use any number of known techniques to interface to these units. In some examples, one or more circuits in the shared cache cell circuitry 106 maintain consistency with cores 102(A)-(N). In some examples, the interface controller unit circuit 116 couples these cores to one or more other devices 118, such as one or more I / O devices, storage devices, one or more communication devices (e.g., wireless networks, wired networks, etc.).

[0026] In some examples, one or more of cores 102(A)-(N) have multi-threading capabilities. System agent unit circuitry 110 includes those components that coordinate and operate cores 102(A)-(N). System agent unit circuitry 110 may include, for example, power control unit (PCU) circuitry and / or display unit circuitry (not shown). The PCU may be (or may include) the logic and components required to regulate the power state of cores 102(A)-(N) and / or dedicated logic 108 (e.g., integrated graphics logic). Display unit circuitry is used to drive one or more externally connected displays.

[0027] Core 102(A)-(N) can be homogeneous in terms of instruction set architecture (ISA). Alternatively, core 102(A)-(N) can also be heterogeneous in terms of ISA; that is, a subset of core 102(A)-(N) may be able to execute one ISA, while other cores may be able to execute only a subset of that ISA or be able to execute another ISA. In one embodiment, processor core 102(A)-(N) may employ all or part of the Reduced Instruction Set Computer (RISC-V) instruction set architecture. In another embodiment, processor core 102(A)-(N) may employ various other instruction set architectures, such as x86, ARM, MIPS, etc.

[0028] The high customizability of RISC-V and the rapid evolution of its ISA extensions have led to ISA fragmentation within the RISC-V chip ecosystem, ultimately resulting in significant software compatibility challenges. Software applications that run perfectly on one vendor's chips may fail on another vendor's chips due to illegal instruction exceptions, simply because of a lack of support for certain ISA extensions. Furthermore, for heterogeneous ISA architectures (e.g., the Sophgo platform with small cores supporting vector ISAs and large cores that do not), binary translation (BT) technology is required to migrate threads between big and small core architectures.

[0029] The existing solution uses BitTorrent (BT) technology to emulate unsupported instructions when an illegal instruction exception is triggered. In this solution, each exception handling involves at least two context switches between kernel and user space, introducing significant context switching overhead and greatly impacting BT's performance.

[0030] In light of this, this disclosure constructs an optimized user-space exception handling mechanism by introducing support for a new Control Status Register (CSR) and new instructions. This mechanism allows the corresponding hardware logic to directly perform BT context switching, thereby eliminating the overhead of context switching between kernel and user space in previous solutions and improving processor performance when handling BT tasks. This mechanism enables application-agnostic and low-overhead ISA translation, provides backward software compatibility for handling obsolete and deprecated instructions, and provides forward software compatibility for supporting new user-mode (U-mode) instructions.

[0031] The following discussion uses three CSRs and one new instruction as examples to illustrate the user-space exception handling mechanism disclosed in this application. However, it should be understood that the function of each CSR or instruction disclosed in this application can be implemented using more CSRs or more instructions. This disclosure does not limit the specific number of CSRs and instructions. Rather, this invention aims to cover all possible variations and modifications, as long as they fall within the technical scope claimed by this invention.

[0032] Figure 2 A flowchart of a method for ISA emulation according to an embodiment of the present disclosure is shown. In one embodiment, method 200 may be executed by a RISC-V processor. In another embodiment, method 200 may be executed by a processor based on any other instruction set architecture, such as x86, ARM, MIPS, etc. Method 200 may include steps S202, S204, S206, S208, and S210. However, in some embodiments, method 200 may include more or fewer different steps, which is not limited by the present disclosure.

[0033] In step S202, an illegal instruction exception triggered by an illegal instruction is detected in the CPU's user mode;

[0034] In step S204, in response to the detection of an illegal instruction exception, the user-mode illegal instruction exception handler configured in the first CSR is invoked;

[0035] In step S206, in response to the execution of the user-mode illegal instruction exception handler, runtime data associated with the thread containing the illegal instruction is obtained from the second CSR and the instruction address of the illegal instruction is obtained from the third CSR.

[0036] In step S208, based on the acquired runtime data and the instruction address of the illegal instruction, ISA emulation is performed in user mode on one or more instructions associated with the thread, including the illegal instruction; and

[0037] In step S210, after ISA emulation of one or more instructions has been completed, the normal instruction execution flow of the application is resumed from the user-mode illegal instruction exception handler in response to the execution of the first instruction.

[0038] In embodiments of this disclosure, the CPU's user mode may include a user trap mode, and a user-mode illegal instruction exception handler may run in user trap mode. In one embodiment, if an illegal instruction is detected in user trap mode, an illegal instruction exception is triggered to the corresponding privileged mode.

[0039] In embodiments of this disclosure, the first CSR is a U-mode Trap Vector (utvec) CSR, which is configured to delegate illegal instruction exceptions detected in user mode to a user-mode illegal instruction exception handler configured in the utvec CSR.

[0040] In embodiments of this disclosure, the user-mode illegal instruction exception handler can be registered in the utvec CSR using the operating system kernel's programming interface (API). When an undefined or illegal instruction is detected and an exception is triggered, the CPU can directly call the exception handler of the user-space BT module to perform ISA emulation. When the ISA emulation is complete, the exception handler restores the CPU's register state from the BT's runtime data and executes a first instruction to resume the next instruction pending processing in the application execution flow stored in the third CSR.

[0041] In embodiments of this disclosure, the utvec CSR is used to store an entry pointer to a user-mode illegal instruction exception handler. In one embodiment, the utvec CSR is accessible only in privileged mode, for example, only in supervisory mode (S-mode).

[0042] Figure 3 An example configuration of the utvec CSR according to an embodiment of this disclosure is shown. For example... Figure 3 As shown, the utvec CSR can be a read / write register with a user-mode extended length (UXLEN) bit width, which includes a vector base address (BASE) field and a vector mode (MODE) field. The BASE field can be used to store the user-mode address associated with the user-mode illegal instruction exception handler, and the MODE field can be used to indicate whether the illegal instruction exception delegation function is enabled.

[0043] In one embodiment, the BASE field of the utvec CSR is used to store an entry pointer to the entry point of the user-mode illegal instruction exception handler. In one embodiment, the BASE field is a WARL (Write Any Read Legal) field, for example, including UXLEN-2 bits. In one embodiment, the user-mode address stored in BASE must meet the following alignment constraint: the address must be 4-byte aligned, i.e., the lowest 2 bits must be 0.

[0044] In one embodiment, the MODE field of the utvec CSR may include 2 bits. Table 1 shows the encoding format of the MODE field.

[0045] Table 1

[0046]

[0047] As shown in Table 1, when MODE=0, the illegal instruction exception delegation function is disabled. When MODE=1, if an illegal instruction exception occurs and the current operating mode is user mode, the CPU sets the PC register to the address stored in the BASE field.

[0048] In embodiments of this disclosure, the second CSR is a U-mode ExceptionBase-data Pointer (uebp) CSR, which is configured to store the storage address of per-thread runtime data used by the user-mode exception handler. In one embodiment, the uebp CSR is accessible in both user mode and privileged mode. In another embodiment, the uebp CSR is accessible only in user trap mode and privileged mode.

[0049] In embodiments of this disclosure, when the emulator detects that the uebp CSR is not initialized, it can allocate a dedicated vCPU for the current application thread and keep the vCPU context active throughout the process's lifetime. During context switching between the application and the emulator, the vCPU registers and physical CPU registers can be synchronized to ensure that the application can jump into / out of its code blocks without restriction.

[0050] Figure 4 An example configuration of the uebp CSR according to an embodiment of this disclosure is shown. For example... Figure 4 As shown, the uebp CSR can have a UXLEN bit width. In embodiments of this disclosure, the uebp CSR can be used to store pointers to runtime data of a user ISA emulator that tracks the CPU registers of the corresponding software emulation. In one embodiment, the uebp CSR has a default value upon reset, where all bits are set to 1.

[0051] In the embodiments of this disclosure, the third CSR is a User Exception Program Counter (uepc) CSR. The uepc CSR is used to save the address of the illegal instruction that triggered the exception when an illegal instruction exception is triggered, and to restore the program counter (PC) register after the exception is handled, for example by saving the address of the pending instruction in the corresponding thread after one or more instructions being emulated in the uepc CSR. This ensures that the processor can continue to execute the instructions of the corresponding thread from the correct position after the exception is handled.

[0052] In one embodiment, the uepc CSR is accessible in both user mode and privileged mode. In another embodiment, the uepc CSR is accessible only in user trap mode and privileged mode.

[0053] Figure 5 An example configuration of the uepc CSR according to an embodiment of this disclosure is shown. For example... Figure 5 As shown, the uepc CSR can have a UXLEN bit width. In one embodiment, the uepc CSR is a WARL register, which can be used to store all valid user-mode addresses. Specifically, when an illegal instruction exception occurs in user mode, the uepc CSR is written with the address of the illegal instruction that caused the exception, and after the illegal instruction emulation is complete, the uepc CSR is written with the address of the next instruction to be processed in the corresponding thread. Apart from the automatic writing during exception handling, the uepc CSR is typically not directly written by the processor's hardware implementation, although software can explicitly write to the uepc CSR using specific instructions.

[0054] In embodiments of this disclosure, the first instruction is a U-mode trap return (uret) instruction. In one embodiment, the uret instruction can be used to cause the CPU to return from user trap mode to normal user mode. In one embodiment, the uret instruction is used to set the PC register to the instruction address stored in the uepc CSR (i.e., the address of the next instruction to be processed in the thread) after the simulation ends, so that when the user-mode illegal instruction exception handler completes its task, the processor can return to the normal execution flow of the corresponding thread by executing the uret instruction. By using the uret instruction to directly set the value of the PC register, additional context switching overhead is avoided.

[0055] In one embodiment, the uret instruction can only be executed in user trap mode, and its execution does not result in any change to the privilege level or stack. In another embodiment, if the uret instruction is detected in a privileged mode (such as kernel mode or supervisory mode) or a normal user mode (non-trap mode), an illegal instruction exception is triggered in the corresponding privileged mode.

[0056] Figure 6 A schematic diagram of a workflow for handling illegal instruction exceptions according to an embodiment of this disclosure is shown. Figure 6As shown, user-mode exception management and ISA emulation are divided into two parts running in different CPU modes. The user-mode illegal instruction exception handler is managed by the utvec CSR, which is accessible only in privileged modes (e.g., supervised mode s-mode). When the utvec CSR is correctly configured, illegal instruction exceptions in user space are caught and redirected to the ISA emulation part running in user mode. The ISA emulator can, for example, run only in user mode to prevent the emulated application code from illegally accessing system memory or the memory of other processes. The ISA emulator uses the uebp CSR and uepc CSR to retrieve previously saved BT runtime data and the instructions to be emulated. When the ISA emulation is complete, the exception handler restores the CPU registers from the BT runtime data and executes the uret instruction to restore the next instruction to be processed in the application execution flow stored in the uepc CSR. In embodiments of this disclosure, the emulator's exception handler can be mapped to the same process address space as the application process; that is, the emulator and the application can share the memory address space, much like loading a dynamic library, allowing the emulator to seamlessly access the application's runtime context (e.g., runtime stack, memory space, and CPU registers). When the operating system kernel's thread scheduler performs a thread switch, it saves the data in the current utvec CSR, uebp CSR, and uepc CSR to the CPU context of the thread management metadata corresponding to the current thread in the kernel, and loads the corresponding data from the CPU context of the thread management metadata of the next thread to be run into the utvec CSR, uebp CSR, and uepc CSR, thereby completing the relevant thread context switch.

[0057] In embodiments of this disclosure, when switching CPU context to enter / exit the user-mode illegal instruction exception handler, the per-virtual-CPU (vCPU) context stack (emu_stack) can be used to save / restore the values ​​of the physical CPU registers. At the same time, the context stack can also be used to store the runtime function stack of the ISA emulator itself. Figure 7 A schematic diagram of the per-vCPU context stack and software-simulated registers according to embodiments of the present disclosure is shown. Figure 7As shown, the user-space ISA emulator emulates all the registers that need to be supported (X0-Xn) and maintains a runtime data region (vmarea0-vmareaX) for each vCPU (vCPU0-vCPUx). This runtime data region stores the register values ​​of these software emulations throughout the entire lifecycle of the process. When entering or exiting the emulation code, the corresponding runtime data can be restored from the uebp CSR / a pointer to the corresponding runtime data can be saved to the uebp CSR.

[0058] In the embodiments of this disclosure, obtaining runtime data associated with the corresponding thread from the uebp CSR can first determine the initialization status of the uebp CSR. When the uebp CSR is not initialized, a per-vCPU runtime data region can be allocated for the current application thread to initialize the runtime environment of each vCPU. When the initialization of the uebp CSR is complete, the uebp CSR is set as a pointer to the per-vCPU runtime data region associated with the current thread.

[0059] Figure 8 A schematic diagram illustrating the initialization process of the uebp CSR according to an embodiment of this disclosure is shown. Figure 8 As shown, the initialization process of uebp CSR may include the following steps:

[0060] In step 810, determine whether the uebp CSR has been initialized;

[0061] In step 820, if the uebp CSR is not initialized, a per-vCPU runtime data region associated with the application's current thread is allocated to initialize the runtime environment (e.g., stack and vCPU state) for each vCPU.

[0062] In step 830, after initialization is complete, the uebp CSR is set to a pointer to the runtime data per virtual CPU;

[0063] In step 840, based on the pointer stored in the uebp CSR, the stack is switched to the emu_stack in the corresponding runtime data, that is, the CPU's physical stack pointer register (SP) is set to the top address of the emu_stack; if it is determined at 810 that the uebp CSR has been initialized, steps 820 and 830 are skipped and the process proceeds directly to step 840.

[0064] In step 850, ISA simulation is performed using the corresponding runtime data. When the ISA simulation ends, the simulator can execute the uret instruction to return to the normal instruction execution flow of the application.

[0065] In embodiments of this disclosure, performing ISA emulation of one or more instructions, including the illegal instruction, associated with the thread containing the illegal instruction in user mode based on the acquired runtime data and the instruction address of the illegal instruction may further include: saving data from the physical hardware registers of the CPU associated with the thread to the virtual registers of the vCPU; and setting the value of the vCPU's virtual program counter (vPC) register to the instruction address of the illegal instruction stored in the UEPC CSR. In embodiments of this disclosure, when ISA emulation of one or more instructions has been completed, the data from the vCPU's virtual registers associated with the thread containing the illegal instruction can be saved to the CPU's physical hardware registers, and the value of the vCPU's vPC register can be saved to the UEPC CSR.

[0066] Figure 9 A flowchart illustrating BT context switching in an ISA simulation according to an embodiment of this disclosure is shown. Figure 9 As shown, when an illegal instruction is detected in user mode, an illegal instruction exception is triggered. The simulator is configured to execute the user-mode illegal instruction exception handler specified by the utvec CSR in response to the illegal instruction exception, and perform the following operations:

[0067] In step 910, runtime data of the vCPU is obtained through a pointer stored in the uebp CSR;

[0068] In step 920, the values ​​of the CPU's physical hardware registers are saved to the vCPU's virtual registers;

[0069] In step 930, the value stored in the uepc CSR (i.e., the instruction address of the illegal instruction) is written into the vPC register of the vCPU;

[0070] In step 940, ISA simulation is performed on one or more instructions, including illegal instructions, according to the BT strategy;

[0071] In step 950, after the ISA simulation is completed, the value of the vCPU's virtual register is saved to the CPU's physical hardware register;

[0072] In step 960, the uepc CSR is updated using the value of the vPC register of the vCPU (i.e., the address of the next instruction to be executed in the simulation environment);

[0073] In step 970, the uret instruction is executed to set the PC to the value of uepc CSR, thereby restoring the application execution flow to its state before the simulation.

[0074] In the embodiments of this disclosure, all existing dynamic binary emulation (DBT) techniques can be applied to user-space ISA emulators to reduce repetitive instruction emulation and amortize the overhead of overall BT context switching, such as hotspot code identification, adjustable emulation block size, emulation code caching, etc.

[0075] This disclosure provides a hardware / software co-design aimed at eliminating the overhead of binary emulation context switching between user space and kernel space in ISA emulation solutions. Compared to existing purely software-implemented Soft-ISA emulation solutions, performance profiling data obtained using performance benchmarks shows that in the worst-case scenario of Soft-ISA performance, where each instruction triggers an illegal instruction processing, kernel-user space BT switching accounts for 75% of the context switching overhead, the solution disclosed in this disclosure improves performance by nearly 4 times. According to benchmark results, when the step size is 8 (i.e., the BT module emulates 8 instructions at a time), the performance improvement of BT using the solution disclosed in this disclosure is expected to reach 15%.

[0076] The newly configured utvec CSR, uebp CSR, and uepc CSR, along with the uret instruction, constitute an optimized user-space exception handling mechanism. The corresponding hardware logic can directly execute BT context switching, thereby eliminating the overhead of context switching between kernel and user space in existing solutions and improving processor performance when handling BT tasks. This mechanism enables application-agnostic and low-overhead ISA translation, provides backward software compatibility for handling obsolete and deprecated instructions, and forward software compatibility for supporting new user-mode instructions.

[0077] Figure 10 This is a block diagram illustrating components capable of reading instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium) and performing any one or more of the methods discussed herein, according to some example embodiments. Specifically, Figure 10 A schematic diagram of hardware resource 1000 is shown, which includes one or more processors (or processor cores) 1010, one or more memory / storage devices 1020, and one or more communication resources 1030, wherein each of these processors, memory / storage devices, and communication resources can be communicatively coupled via bus 1040 or other interface circuitry. For embodiments utilizing node virtualization (e.g., Network Functions Virtualization (NFV)), a hypervisor 1002 can be executed to provide an execution environment for one or more network slices / subslices, thereby utilizing hardware resource 1000.

[0078] Processor 1010 may include, for example, processor 1012 and processor 1014. Processor 1010 may be, for example, a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP) such as a baseband processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a radio frequency integrated circuit (RFIC), another processor (including those discussed herein), or any suitable combination thereof.

[0079] The memory / storage device 1020 may include main memory, disk storage devices, or any suitable combination thereof. The memory / storage device 920 may include, but is not limited to, any type of volatile, non-volatile, or semi-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state memory, etc.

[0080] Communication resource 1030 may include interconnect or network interface controllers, components, or other suitable devices for communicating with one or more peripheral devices 1004 or one or more databases 1006 or other network elements via network 1008. For example, communication resource 1030 may include wired communication components (e.g., for coupling via USB, Ethernet, etc.), cellular communication components, near field communication (NFC) components, Bluetooth® (or Bluetooth® Low Energy) components, Wi-Fi® components, and other communication components.

[0081] Instruction 1050 may include software, a program, application program, applet, or other executable code for causing at least any one of the processors 1010 to perform any one or more of the methods discussed herein. Instruction 1050 may reside wholly or partially within processor 1010 (e.g., in the processor's cache), memory / storage device 1020, or any suitable combination thereof. Furthermore, any portion of instruction 1050 may be transferred from any combination of peripheral device 1004 or database 1006 to hardware resource 1000. Therefore, the memory of processor 1010, memory / storage device 1020, peripheral device 1004, and database 1006 are examples of computer-readable and machine-readable media.

[0082] Some examples may be implemented or be implemented as an article of art or at least a computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0083] According to some examples, computer-readable media may include non-transitory storage media to store or maintain instructions that, when executed by a machine, computing device, or system, cause that machine, computing device, or system to perform methods and / or operations according to the described examples. Instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to a predetermined computer language, manner, or syntax to instruct a machine, computing device, or system to perform specific functions. Instructions may be implemented using any suitable high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0084] One or more aspects of at least one example can be implemented by representative instructions representing various logic within a processor, stored on at least one machine-readable medium, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to manufacture logic to perform the techniques described herein. This representation, referred to as an "IP core," can be stored on a tangible machine-readable medium and provided to various customer or manufacturing facilities for loading into the manufacturing machine that actually manufactures the logic or processor.

[0085] The phrase "an example" or "an example" does not necessarily refer to the same example or embodiment. Any aspect described herein may be combined with any other aspect or similar aspect described herein, whether or not these aspects are described with reference to the same drawings or elements. The division, omission, or inclusion of block functions depicted in the drawings does not imply that hardware components, circuits, software, and / or elements used to implement these functions will necessarily be divided, omitted, or included in the embodiments.

[0086] Examples can be described using the terms “coupling” and “connection” and their derivatives. These terms are not necessarily intended to be synonyms. For example, a description using the terms “connection” and / or “coupling” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupling” may also refer to two or more elements that are not in direct contact with each other but still cooperate or interact with each other.

[0087] The terms “first,” “second,” and the like are not used herein to indicate any order, quantity, or importance, but rather to distinguish one element from another. The term “a” herein does not imply a limitation on quantity, but rather indicates the presence of at least one mentioned item. The term “assertion” as used herein when referring to a signal refers to a state in which the signal is valid and can be achieved by applying any logic level (whether logic 0 or logic 1) to the signal. The terms “subsequently” or “afterward” can mean immediately following or following one or more other events. According to alternative embodiments, other sequences of steps may also be performed. Furthermore, depending on the specific application, additional steps may be added or removed. Any combination of variations can be used, and many variations, modifications, and alternative embodiments will be understood by those skilled in the art who benefit from this disclosure.

[0088] Unless otherwise specifically stated, disjunctive language such as the phrase "at least one of X, Y, or Z" is understood in context to generally state that an item, term, etc., can be X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Thus, such disjunctive language is generally not intended, nor should it imply, that certain embodiments require the presence of each of at least one X, at least one Y, or at least one Z. Furthermore, unless otherwise specifically stated, connective language such as the phrase "at least one of X, Y, and Z" should also be understood to refer to X, Y, Z, or any combination thereof, including "X, Y, and / or Z".

Claims

1. A method for ISA simulation, comprising: Detect illegal instruction exceptions triggered by illegal instructions in the CPU's user mode; In response to the detection of the illegal instruction exception, the user-mode illegal instruction exception handler configured in the first control status register (CSR) is invoked, wherein the user-mode illegal instruction exception handler runs in the user mode of the CPU. In response to the execution of the user-mode illegal instruction exception handler, runtime data associated with the thread including the illegal instruction is obtained from a second CSR and the instruction address of the illegal instruction is obtained from a third CSR, wherein the second CSR is accessible in both user mode and privileged mode; Based on the acquired runtime data and the instruction address of the illegal instruction, perform ISA emulation in user mode on one or more instructions associated with the thread, including the illegal instruction; and Once the ISA emulation of the one or more instructions has been completed, the normal instruction execution flow of the application resumes from the user-mode illegal instruction exception handler in response to the execution of the first instruction.

2. The method according to claim 1, wherein, The first control status register (CSR) is used to store an entry pointer that points to the entry point of the user-mode illegal instruction exception handler.

3. The method according to claim 1, wherein, When the ISA emulation of the one or more instructions has been completed, the recovery from the user-mode illegal instruction exception handler to the normal instruction execution flow of the application in response to the execution of the first instruction includes: Update the value of the third CSR to the instruction address of the next instruction to be processed after the one or more instructions; and In response to the execution of the first instruction, the value of the program counter is set to the updated value in the third CSR.

4. The method according to any one of claims 1-3, wherein, In response to the execution of the user-mode illegal instruction exception handler, runtime data associated with the thread including the illegal instruction is obtained from the second CSR, including: Determine whether the second CSR has been initialized; In response to the second CSR not being initialized, a per-vCPU runtime data region associated with the thread is allocated to initialize the per-vCPU runtime environment; and In response to the completion of the initialization of the second CSR, the second CSR is set to a pointer to the per-virtual CPU runtime data region associated with the thread.

5. The method according to any one of claims 1-3, wherein, Based on the acquired runtime data and the instruction address of the illegal instruction, ISA emulation is performed in user mode on one or more instructions associated with the thread, including the illegal instruction, including: Save the data in the physical hardware registers of the CPU associated with the thread to the virtual registers of the vCPU. Set the CPU's physical stack pointer register to the dedicated stack address in the acquired runtime data area; Set the value of the vCPU's virtual program counter register to the address of the illegal instruction stored in the third CSR; and The user-mode ISA emulator uses vCPU virtual register data to simulate the execution of one or more instructions associated with the thread, including the illegal instruction.

6. The method according to claim 5, further comprising: Once the ISA emulation of the one or more instructions has been completed, the data in the vCPU virtual register associated with the thread is saved to the CPU's physical hardware registers; and Save the value of the vCPU's virtual program counter register to the third CSR.

7. The method according to any one of claims 1-3, further comprising: Using the operating system kernel's programming interface, the user-mode illegal instruction exception handler is registered to the first control status register (CSR).

8. The method according to any one of claims 1-3, wherein, The first control status register (CSR) is only accessible in privileged mode.

9. The method according to any one of claims 1-3, wherein, The third CSR can be accessed in both user mode and privileged mode.

10. The method according to any one of claims 1-3, wherein, The second and third CSRs are only accessible in user trap mode and privileged mode.

11. The method according to any one of claims 1-3, wherein, The first control status register (CSR) includes a vector base address field and a vector mode field. The vector base address field is used to store the user-mode address associated with the user-mode illegal instruction exception handler, and the mode field is used to indicate whether the illegal instruction exception delegation function is enabled.

12. The method of claim 11, further comprising: In response to the illegal instruction exception delegation function being enabled in the mode field of the first CSR, if the illegal instruction exception is detected and the current running mode is user mode, the program counter register is set to the address in the vector base address field.

13. The method according to any one of claims 1-3, wherein, The CPU's user mode includes a user trap mode, in which the user mode illegal instruction exception handler runs.

14. The method of claim 13, wherein if an illegal instruction is detected in user trap mode, an illegal instruction exception is triggered to the corresponding privileged mode.

15. The method according to any one of claims 1-3, wherein, The ISA simulation is a RISC-V ISA simulation, x86 ISA simulation, ARM ISA simulation, or MIPS ISA simulation.

16. An apparatus for ISA simulation, wherein, The apparatus includes a processor circuit configured to perform the method of any one of claims 1-15.

17. A computer-readable storage medium having instructions stored thereon, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-15.

18. A computer program product comprising instructions, wherein the instructions, when executed by a processor, cause the processor to perform the method according to any one of claims 1-15.

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