A method and device for data transmission between GPU chips, electronic equipment and storage medium

Abstract

The present disclosure relates to a method and apparatus, electronic device, and storage medium for data transmission between GPU chips. The method is applied to a local GPU chip, which is the GPU chip that performs data transmission with a remote GPU chip. The method includes: determining the address of the video memory space of the remote GPU chip in response to a cross-chip data transmission instruction; determining at least two transmission links for transmitting data based on the address and a mapping relationship established between the address and the transmission link; and performing data transmission with the remote GPU chip in parallel based on the at least two transmission links. Embodiments of the present disclosure can improve the efficiency of data transmission between GPU chips.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a method and device for data transmission between GPU chips, an electronic device, and a storage medium. Background Art

[0002] In high-performance computer systems, multiple graphics processing units (GPUs) may be installed on the same host or on different hosts and connected via a high-speed network. These GPUs work together to process large amounts of data in parallel or perform complex computing tasks.

[0003] For example, in deep learning training environments, multi-GPU systems are very common. Because deep learning models typically have a large number of parameters and a large amount of computation, a single GPU may not be able to meet the training requirements. Therefore, multiple GPUs are often used to accelerate the training process. These GPUs can be connected together through high-speed interconnect technology to form a multi-GPU training platform. Through parallel computing and data parallel processing, multi-GPU systems can significantly shorten training time and improve model training efficiency and performance.

[0004] However, in the prior art, data transmission efficiency between GPUs is low. Summary of the Invention

[0005] This disclosure proposes a technical solution for data transmission between GPU chips.

[0006] According to one aspect of the present disclosure, a method for data transmission between GPU chips is provided, which is applied to a local GPU chip, where the local GPU chip is a GPU chip that performs data transmission with a remote GPU chip. The method includes:

[0007] In response to the cross-chip data transfer instruction, determining the address of the video memory space of the remote GPU chip;

[0008] Determining, according to the address, at least two transmission links for transmitting data based on a constructed mapping relationship between the address and the transmission link;

[0009] Based on the at least two transmission links, data is transmitted in parallel with the remote GPU chip.

[0010] In one possible implementation, the mapping relationship includes: taking the video memory page of the GPU chip as the granularity, dividing the video memory space into multiple video memory pages according to the logical addresses in the video memory space, and alternately mapping the video memory pages to different transmission links according to the arrangement order of the logical addresses of the multiple video memory pages.

[0011] In a possible implementation, the process of constructing the mapping relationship includes:

[0012] Determining a mapping ratio according to a bandwidth ratio of the at least two transmission links, where the mapping ratio is a ratio of addresses mapped to the respective transmission links;

[0013] The video memory space is divided into a plurality of video memory pages according to the logical addresses in the video memory space, and the video memory pages are alternately mapped to different transmission links according to the mapping ratio according to the arrangement order of the logical addresses of the plurality of video memory pages.

[0014] In a possible implementation, determining the mapping ratio according to the bandwidth ratio of the at least two transmission links includes:

[0015] determining a bandwidth utilization rate of each of the transmission links when data transmission is performed according to the bandwidth ratio;

[0016] Based on the bandwidth utilization, load balancing is performed on each of the transmission links to obtain the mapping ratio.

[0017] In a possible implementation, the method further includes:

[0018] In response to the mapping ratio received from the user, the established mapping relationship is deleted, and the video memory pages are alternately mapped to different transmission links in accordance with the new mapping ratio in the order of the logical addresses of the video memory pages to obtain a new mapping relationship.

[0019] In one possible implementation, transmitting data in parallel with a remote GPU chip based on the at least two transmission links includes:

[0020] Based on at least two processing units, data is transmitted in parallel with a remote GPU chip through different transmission links respectively, wherein the transmission links used by the same processing unit are the same.

[0021] In a possible implementation, after transmitting data in parallel with the remote GPU chip based on the at least two transmission links, the method further includes:

[0022] The data in the at least two processing units are fused and subsequently processed.

[0023] In a possible implementation, the method further includes:

[0024] Determine the bandwidth and latency of each transmission link;

[0025] Based on the bandwidth and latency requirements of GPU-processed business scenarios and the determined bandwidth and latency of each transmission link, the mapping ratio of addresses mapped to each transmission link is dynamically adjusted.

[0026] In one possible implementation, the transmission link includes a first transmission link and a second transmission link, the latency of the first transmission link is less than the latency of the second transmission link, the bandwidth and latency requirements of the GPU-based processing business scenario, and the determined bandwidth and latency of each transmission link are dynamically adjusted, including:

[0027] In the case where the business scenario is a real-time rendering scenario, the mapping ratio of the addresses of the transmission links used to transmit real-time rendering data is determined as follows: the ratio of the first transmission link is greater than the ratio of the second transmission link.

[0028] In one possible implementation, the GPU-based processing-based business scenario's bandwidth and latency requirements, as well as the determined bandwidth and latency of each transmission link, dynamically adjusts the mapping ratio of addresses mapped to each transmission link, including:

[0029] When the business scenario is a machine learning scenario, the bandwidth ratio of each transmission link is used as the mapping ratio of the addresses of each transmission link used to transmit training data.

[0030] According to one aspect of the present disclosure, a data transmission device between GPU chips is provided, which is applied to a local GPU chip, where the local GPU chip is a GPU chip that performs data transmission with a remote GPU chip. The device includes:

[0031] An address determination module, configured to determine the address of the video memory space of the remote GPU chip in response to a cross-chip data transfer instruction;

[0032] An address mapping module, configured to determine at least two transmission links for transmitting data based on the mapping relationship between the addresses and the transmission links;

[0033] The data transmission module is used to transmit data with the remote GPU chip in parallel based on the at least two transmission links.

[0034] In one possible implementation, the mapping relationship includes: taking the video memory page of the GPU chip as the granularity, dividing the video memory space into multiple video memory pages according to the logical addresses in the video memory space, and alternately mapping the video memory pages to different transmission links according to the arrangement order of the logical addresses of the multiple video memory pages.

[0035] In a possible implementation, the apparatus includes a mapping relationship building module, configured to:

[0036] Determining a mapping ratio according to a bandwidth ratio of the at least two transmission links, where the mapping ratio is a ratio of addresses mapped to the respective transmission links;

[0037] The video memory space is divided into a plurality of video memory pages according to the logical addresses in the video memory space, and the video memory pages are alternately mapped to different transmission links according to the mapping ratio according to the arrangement order of the logical addresses of the plurality of video memory pages.

[0038] In a possible implementation, the mapping relationship building module is used to:

[0039] determining a bandwidth utilization rate of each of the transmission links when data transmission is performed according to the bandwidth ratio;

[0040] Based on the bandwidth utilization, load balancing is performed on each of the transmission links to obtain the mapping ratio.

[0041] In a possible implementation, the apparatus further includes:

[0042] The mapping relationship update module is used to delete the established mapping relationship in response to the mapping ratio received from the user, and map the video memory pages to different transmission links in turn according to the new mapping ratio in the order of the logical addresses of the video memory pages to obtain a new mapping relationship.

[0043] In a possible implementation, the data transmission module is configured to transmit data in parallel with a remote GPU chip based on at least two processing units, respectively, through different transmission links, wherein the transmission links used by the same processing unit are the same.

[0044] In a possible implementation, the apparatus further includes:

[0045] The fusion unit is used to fuse the data in the at least two processing units and perform subsequent processing on the fused data.

[0046] In a possible implementation, the apparatus further includes:

[0047] A physical characteristics determination module, used to determine the bandwidth and delay of each transmission link;

[0048] The dynamic adjustment module is used to dynamically adjust the mapping ratio of addresses mapped to each transmission link based on the bandwidth and latency requirements of the GPU-processed business scenario and the determined bandwidth and latency of each transmission link.

[0049] In one possible implementation, the transmission link includes a first transmission link and a second transmission link, the delay of the first transmission link is less than the delay of the second transmission link, and the dynamic adjustment module is used to determine the mapping ratio of the addresses of each transmission link used to transmit real-time rendering data when the business scenario is a real-time rendering scenario: the ratio of the first transmission link is greater than the ratio of the second transmission link.

[0050] In one possible implementation, the dynamic adjustment module is configured to use the bandwidth ratio of each transmission link as a mapping ratio of the addresses of each transmission link used to transmit training data when the business scenario is a machine learning scenario.

[0051] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0052] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0053] In an embodiment of the present disclosure, the local GPU chip, in response to a cross-chip data transfer instruction, determines the address of the video memory space of the remote GPU chip. Then, based on the address and a mapping relationship between the established addresses and transmission links, it determines at least two transmission links for transmitting data. Data is then transmitted in parallel with the remote GPU chip based on the at least two transmission links. Thus, by selecting two transmission links based on the determined video memory space address and transmitting data in parallel with the remote GPU chip, hardware resources are fully utilized, the bandwidth for data transmission between GPU chips is maximized, and the efficiency of data transmission between GPU chips is improved compared to transmitting data via a single transmission link.

[0054] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0056] Figure 1 A flowchart of a method for transmitting data between GPU chips according to an embodiment of the present disclosure is shown.

[0057] Figure 2 A schematic diagram of a multi-GPU architecture according to an embodiment of the present disclosure is shown.

[0058] Figure 3 A schematic diagram showing a mapping relationship according to an embodiment of the present disclosure.

[0059] Figure 4 A schematic diagram illustrating a process of a parallel transmission method according to an embodiment of the present disclosure is shown.

[0060] Figure 5 A block diagram of a data transmission device between GPU chips according to an embodiment of the present disclosure is shown.

[0061] Figure 6 A block diagram of an electronic device 1900 according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0062] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0063] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0064] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0065] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0066] Figure 1 A flowchart of a method for data transmission between GPU chips according to an embodiment of the present disclosure is shown. The method is applied to a local GPU chip, which is a GPU chip that performs data transmission with a remote GPU chip. Figure 1 As shown, the method includes:

[0067] In step S11, in response to the cross-chip data transfer instruction, the address of the video memory space of the remote GPU chip is determined;

[0068] The present disclosure is applied to a multi-GPU architecture, which includes multiple GPU chips, for example, different GPU chips configured in different slots of the same computer, or GPU chips on different computers. Figure 2 A schematic diagram of a multi-GPU architecture according to an embodiment of the present disclosure is shown as follows: Figure 2 As shown in FIG, the architecture includes four GPU chips, namely chip 0, chip 1, chip 2, and chip 3. Each GPU chip includes an image processing unit (GPU) and a video random access memory (DRAM). The transmission links between different GPU chips include: a direct link constructed between direct connection modules 0 to 3 (link0 to link3), and a transmission link constructed based on the high-speed serial computer expansion bus standard PCIe. The PCIe link is linked through a PCIe switch (PCIE SWITCH).

[0069] For ease of description, for two GPU chips that need to transmit data, the chip that initiates the data transmission is described as the local GPU chip, and the GPU chip on the other end that receives the data is called the remote GPU chip. The two may be located in different slots of the same computer or in different computers, which is not limited in this disclosure. For example, see Figure 2 Assume that chip 0 needs to transfer part of the data to chip 2. Then chip 0 is the chip that initiates the data transmission, and chip 2 is the chip that receives the data. Therefore, chip 0 is the local GPU chip, and chip 2 is the remote GPU chip.

[0070] The address in the video memory space can be a number or identifier that indicates a specific location (such as a byte or bit) in the video memory space. It is used to indicate the location of the data requested to be obtained or the location of the data requested to be written in the video memory space.

[0071] The GPU chip executes instructions sent by the upper layer. When the executed instruction is a cross-chip data transfer instruction, the instruction will contain the address of the remote GPU chip's video memory space. This instruction can be sent by the upper-layer application. The upper-layer software can obtain the address of the GPU chip's video memory space in advance. Each GPU chip is usually assigned a specific address space range to ensure that they can independently and securely access their own video memory. For example, there are a total of four GPU chips (chip0, chip1, chip2, chip3), and the size of the video memory space of each chip is 128G. Among them, chip0 is assigned an address range of 0-128G; chip1 is assigned an address range of 128G-256G; chip2 is assigned an address range of 256G-384G; chip3 is assigned an address range of 384G-512G.

[0072] When accessing the video memory space of a remote GPU chip is needed, the upper-level software needs to determine the remote GPU chip's number and send a request to the Memory Management Unit (MMU) to allocate memory within the address space accessible on the remote GPU chip. The Memory Management Unit checks whether there is any available memory in the remote GPU chip's address space and decides whether to allocate it. If available memory exists, the MMU selects one or more contiguous address ranges and returns these addresses to the upper-level software. The upper-level software then writes the address into a cross-chip data transfer instruction and sends it to the local GPU chip for execution.

[0073] In step S12, according to the address, at least two transmission links for transmitting data are determined based on the constructed mapping relationship between the address and the transmission link;

[0074] After determining the address of the video memory space, the transmission link to be selected for data transmission can be determined based on the pre-built mapping relationship between the address and the transmission link. The mapping relationship can be built based on the physical connection of the hardware, the bandwidth of the link, the delay and other characteristics.

[0075] The at least two transmission links include: a direct link between GPU chips; and a transmission link based on the high-speed serial computer expansion bus standard PCIe. For ease of description, the direct link between GPU chips is referred to as a direct link, and the transmission link based on the high-speed serial computer expansion bus standard PCIe is referred to as a PCIe link.

[0076] The direct link is a high-speed, low-latency communication link between GPUs based on multi-link aggregation and high-speed serial interface technology. It improves the data transmission efficiency between GPU chips by directly connecting each GPU chip without transferring data through the host.

[0077] The mapping relationship between the video memory space address and the transmission link can be pre-established. The specific construction method can be referred to the possible implementation methods provided in this disclosure and will not be described in detail here. This mapping relationship clearly defines the transmission link corresponding to each address. In this implementation, at least two transmission links will be selected to facilitate parallel data transmission.

[0078] In step S13, data is transmitted in parallel with the remote GPU chip based on the at least two transmission links.

[0079] After the transmission link is determined, the local GPU chip will begin to transmit data in parallel with the remote GPU chip. During this process, the data to be transmitted will be divided into multiple parts and then transmitted through different transmission links. Due to the use of parallel transmission, the overall data transmission speed will be greatly improved.

[0080] In addition, during data transmission, mechanisms such as data verification and retransmission can be used to ensure data integrity and accuracy. Data verification ensures the integrity of transmitted data, while retransmission ensures that data that fails to transmit reaches the remote GPU chip in a timely manner.

[0081] In an embodiment of the present disclosure, the local GPU chip, in response to a cross-chip data transfer instruction, determines the address of the video memory space of the remote GPU chip. Then, based on the address and a mapping relationship between the established addresses and transmission links, it determines at least two transmission links for transmitting data. Data is then transmitted in parallel with the remote GPU chip based on the at least two transmission links. Thus, by selecting two transmission links based on the determined video memory space address and transmitting data in parallel with the remote GPU chip, hardware resources are fully utilized, the bandwidth for data transmission between GPU chips is maximized, and the efficiency of data transmission between GPU chips is improved compared to transmitting data via a single transmission link.

[0082] In one possible implementation, the mapping relationship includes: the mapping relationship includes: taking the video memory page of the GPU chip as the granularity, dividing the video memory space into multiple video memory pages according to the logical addresses in the video memory space, and mapping the video memory pages alternately to different transmission links according to the arrangement order of the logical addresses of the multiple video memory pages.

[0083] In the mapping relationship, the granularity of mapping is the GPU chip's video memory page. A video memory page is the basic unit of memory management in the operating system, and its size is generally determined by both the hardware and the operating system. In GPUs, video memory pages often have a specific size, such as 4KB, 8KB, or even larger.

[0084] For example, assuming that the video memory space is divided into 4 pages and the size of each page is 4KB, the logical addresses of these 4 pages can be as follows: the logical address range of the first video memory page is 0x00000000-0x00000FFF, the logical address range of the second video memory page is 0x00001000-0x00001FFF, and so on.

[0085] A logical address is the address used by a program or application when accessing memory. In the GPU's memory space, a logical address represents a specific location or range within the GPU's memory space. For a specific range of logical addresses representing a block of memory space, the memory space can be divided into multiple memory pages at the memory page granularity. Each memory page corresponds to a logical address, and these logical addresses can be arranged in a specific order. According to this order, the memory pages are sequentially assigned to different transmission links. In one example, assume there are two transmission links A and B, and GPU memory pages are arranged in the order of their logical addresses: P1, P2, P3, ... . The mapping relationship can be that the logical address of the first memory page P1 is mapped to transmission link A; the logical address of the second memory page P2 is mapped to transmission link B; the logical address of the third memory page P3 is again mapped to transmission link A (alternating). And so on, with subsequent pages being mapped alternately to transmission links A and B.

[0086] In another example, the user may preset a mapping ratio, and based on the user-preset mapping ratio, the video memory pages are alternately mapped to different transmission links in sequence.

[0087] See also Figure 3 , Figure 3 A schematic diagram illustrating a mapping relationship according to an embodiment of the present disclosure is provided. In this example, there are a total of L memory pages, with a mapping ratio of M:N. Memory pages 1-M are mapped to transmission link A, and memory pages (M+1)-(M+N) are mapped to link B, and so on, until all memory pages are mapped. When the number of remaining memory pages mapped is less than M, all remaining memory pages are mapped to link B. L, M, and N are all positive integers.

[0088] For example, link A is a PCIe link and link B is a direct link. Then, the addresses given to PCIE and link are alternating. For example, if the mapping ratio is 4:1, the addresses are based on the memory page ratio, with page 0-3 given to PCIE, page 4 given to Link, page 4-7 given to PCIE, and page 8 given to Link, and so on, alternating until all addresses are mapped.

[0089] In this implementation, mapping at the granularity of video memory pages can simplify memory management because the operating system or driver can more easily track which pages are mapped to which links, thereby improving the efficiency of data transmission between GPU chips.

[0090] In one possible implementation, the process of constructing the mapping relationship includes: determining a mapping ratio based on the bandwidth ratio of the at least two transmission links, where the mapping ratio is the ratio of the addresses mapped to each transmission link; dividing the video memory space into multiple video memory pages based on the logical addresses in the video memory space, and mapping the video memory pages alternately to different transmission links according to the mapping ratio in the order of arrangement of the logical addresses of the multiple video memory pages.

[0091] The bandwidth ratio of a transmission link can be calculated based on the bandwidth of the transmission link. This bandwidth can be obtained through actual measurement or by querying system parameters. After obtaining the bandwidth value, the bandwidth ratio of various transmission links can be calculated. For example, if the bandwidth ratio of PCIE to Link is 2:3, then ideally, to achieve optimal transmission efficiency, PCIE and Link should each handle memory access requests that match their bandwidth ratio.

[0092] Therefore, based on the bandwidth ratio, the mapping ratio can be determined, that is, the ratio of addresses mapped to each transmission link. Continuing with the previous example, the mapping ratio is the same as the bandwidth ratio, which is also 2:3. For example, for every 5 consecutive video memory pages, 2 pages should be mapped to PCIE transmission links, and the remaining 3 pages should be mapped to link transmission links.

[0093] According to the determined mapping ratio, a specific mapping relationship can be constructed to alternately map video memory pages to different transmission links. Continuing with the previous example, starting with pages 1 and 2 in the video memory, they will be mapped to the PCIE transmission link; then, pages 3, 4, and 5 will be mapped to the Link transmission link; and so on, in a 2:3 ratio, the subsequent pages will be alternately mapped to PCIE and Link until all memory pages are mapped to the corresponding transmission links. When the number of remaining video memory pages mapped to the last page is less than 2, all remaining video memory pages will be mapped to the PCIE transmission link.

[0094] In the disclosed embodiment, by determining a mapping ratio based on the bandwidth ratio of the at least two transmission links and alternately mapping the video memory pages to different transmission links according to the mapping ratio, the data transmission volume can be matched with the transmission link bandwidth, thereby reducing bandwidth waste or shortage, and thus improving the overall efficiency of data transmission between GPU chips.

[0095] In a possible implementation, determining the mapping ratio according to the bandwidth ratio of the at least two transmission links includes: determining a bandwidth utilization rate of each of the transmission links when data is transmitted according to the bandwidth ratio;

[0096] Based on the bandwidth utilization, load balancing is performed on each of the transmission links to obtain the mapping ratio.

[0097] In this implementation, external factors in the actual transmission process, such as transmission loss, latency, and link characteristics, are taken into account when determining the mapping ratio of video memory addresses to different transmission links. This allows for further optimization of the mapping relationship obtained based on a simple bandwidth ratio (e.g., 2:3) to improve bandwidth utilization.

[0098] After determining the bandwidth ratio, we can measure or estimate the bandwidth utilization of each transmission link during actual transmission, when data is transmitted at a given bandwidth ratio (e.g., 2:3). Bandwidth utilization can be calculated as the ratio of the actual amount of data transmitted per unit time to the theoretical bandwidth of the link, thereby determining the actual usage of each transmission link under the current mapping ratio.

[0099] In addition, external factors that affect transmission performance, such as transmission loss, delay, link quality, etc., can be analyzed to obtain analysis results. These factors may cause some transmission links to be overloaded or idle even if mapping is performed according to the theoretical bandwidth ratio.

[0100] Based on the analysis of bandwidth utilization and external factors, a load balancing algorithm is applied to adjust the mapping ratio. The goal of the load balancing algorithm is to maintain the best possible balance in bandwidth utilization across transmission links while meeting transmission requirements. The algorithm dynamically adjusts the mapping ratio based on the real-time status of the transmission links (such as bandwidth utilization, transmission speed, and response time).

[0101] The load balancing algorithm calculates a new mapping ratio. This ratio may no longer be a simple 2:3, but is dynamically adjusted based on the current system status and link characteristics. After adjusting the mapping ratio, the mapping of memory addresses to different transmission links can be re-performed.

[0102] Since the system status and link characteristics may change at any time, in actual applications, the bandwidth utilization and performance indicators of each transmission link can be continuously monitored and adjusted as needed so that the system always runs in the best state and achieves efficient data transmission.

[0103] For example, suppose that initially, bandwidth mapping is performed at a 2:3 ratio, but during actual transmission, it is found that the bandwidth utilization of the Link is much lower than that of the PCIE link. In this case, the load balancing algorithm can be used to appropriately increase the Link mapping ratio (for example, to 3:4 or 4:5) to improve its bandwidth utilization. At the same time, it is also necessary to ensure that the bandwidth utilization of the PCIE link is not too high to maintain the overall balance and stability of the system.

[0104] In the embodiment of the present disclosure, by determining the bandwidth utilization of each transmission link when data is transmitted according to the bandwidth ratio, load balancing is performed on each transmission link, so that the bandwidth of each link can be utilized more efficiently, which helps to reduce bandwidth waste and improve the overall data transmission efficiency between GPU chips.

[0105] In one possible implementation, the method further includes: in response to a mapping ratio received from a user input, deleting the established mapping relationship, and mapping the video memory pages alternately to different transmission links in accordance with the new mapping ratio in the order of arrangement of the logical addresses of the video memory pages to obtain a new mapping relationship.

[0106] In this implementation, users are allowed to dynamically adjust the mapping ratio of video memory addresses to different transmission links based on actual needs or system status. For example, a system administrator or user can enter a new mapping ratio of video memory addresses to transmission links through a specific interface or interface.

[0107] The upper layer software can receive a new mapping ratio input by the user through a user interface or a dedicated interface. The input can be a recommended value based on the current transmission status or a value set by the user according to specific needs.

[0108] After receiving the new mapping ratio, the upper-layer software will notify the GPU to delete the previously established mapping relationship to avoid the influence of the old mapping relationship on the new mapping relationship.

[0109] After deleting the old mapping relationship, the memory pages can be alternately mapped to different transmission links in accordance with the new mapping ratio according to the arrangement order of the logical addresses of the memory pages, that is, a mapping relationship with the corresponding transmission link is established for each logical address.

[0110] After the new mapping relationship is established, the local GPU chip can initiate a data transmission request. At this time, data transmission can be carried out according to the new mapping relationship.

[0111] In the disclosed embodiment, users can adjust the mapping ratio at any time according to actual needs or system status. This dynamic controllability makes data transmission more flexible and can adapt to application needs in different scenarios.

[0112] In one possible implementation, the performing of data transmission with the remote GPU chip in parallel based on the at least two transmission links includes: performing data transmission with the remote GPU chip in parallel based on at least two processing units through different transmission links, respectively, wherein the transmission links used by the same processing unit are the same.

[0113] A GPU typically contains a large number of processing units (PUs), which can perform computing tasks in parallel. When transferring data between GPU chips, these PUs can send data to the remote GPU chip in parallel through different transmission links.

[0114] Based on the mapping relationship, the address of the video memory space of the remote GPU chip when the same processing unit performs data transmission is determined to ensure that the transmission link used by the same processing unit is the same. For the address of the video memory space, if the mapping relationship between the address and the transmission link is known, the addresses mapped to the same transmission link can be assigned to the same processing unit for processing. Assuming that there are two transmission links, for example, PCIE and Link, according to the mapping relationship, the address mapped to the PCIE link can be assigned to the same processing unit, and the address mapped to the Link link can be assigned to the same processing unit, ensuring that each processing unit uses the same transmission link for data transmission.

[0115] In another example, the addresses of the video memory space of the remote GPU chip can be allocated to different processing units for processing according to the allocation method of allocating video memory space to different transmission links. For example, assuming that the mapping ratio is M:N, the pages in the VRAM space can be allocated to the processing units using different transmission links according to the ratio of M:N. First, the total number of pages in the video memory space is determined; then, according to the mapping ratio M:N, the first M pages are allocated to the processing units using the PCIE transmission link, and the next N pages are allocated to the processing units using the Link transmission link, until all pages are allocated.

[0116] These processing units can perform data transfer operations in parallel, with each processing unit performing data transfers in the video memory page it is responsible for.

[0117] See also Figure 4 , Figure 4 A schematic diagram showing a process of a parallel transmission method according to an embodiment of the present disclosure is shown. In this example, Figure 3The video memory pages shown are the same, with a total of L video memory pages. The user sets the mapping ratio to M:N, so the 1st to Mth video memory pages are mapped to transmission link A, the (M+1)th to (M+N)th video memory pages are mapped to link B, and so on, until all video memory pages are mapped. When the number of mapped to the last remaining video memory pages is less than M, all the remaining video memory pages are actually mapped to link B. The local GPU chip includes processing unit 1 and processing unit 2, wherein processing unit 1 is responsible for performing data transmission operations on the PCIe link, and processing unit 2 is responsible for performing data transmission operations on the direct link. The address mapping module determines the transmission link corresponding to the address when processing unit 1 and processing unit 2 perform data transmission based on the mapping relationship between the constructed address and the transmission link, and then instructs processing unit 1 to perform data transmission operations with the remote GPU chip based on the PCIe switch, and processing unit 2 to perform data transmission operations with the remote GPU chip based on the direct connection module.

[0118] In this implementation, by transmitting data in parallel with a remote GPU chip through different transmission links based on at least two processing units, data can be transmitted in parallel with the remote GPU chip, thereby greatly improving the efficiency of data transmission.

[0119] In a possible implementation, after transmitting data in parallel with a remote GPU chip based on the at least two transmission links, the method further includes: fusing the data in the at least two processing units and performing subsequent processing on the fused data.

[0120] In the case where data transmission is to read data from a remote GPU chip, after the data transmitted by the remote GPU chip is received in parallel through at least two transmission links, the data from different processing units can be further fused and subsequently processed to ensure the integrity and consistency of the data, and provide the necessary data foundation for subsequent graphics rendering, calculation or other GPU tasks.

[0121] Because data is transmitted in parallel through different processing units and transmission links, it may be scattered and fragmented when it arrives. Through data fusion processing, this data can be reassembled into a complete and coherent data set.

[0122] Specifically, since the addresses of the data in the video memory space of the remote GPU chip are continuous, the data can be sorted and organized based on the order of the addresses in the video memory space of the remote GPU chip, and then the sorted data can be spliced ​​and integrated to obtain fused data.

[0123] After the data fusion is completed, the fused data can be verified to ensure the integrity and accuracy of the data. For example, a checksum, hash function or other data integrity check method can be used to verify the integrity of the data.

[0124] After data fusion is complete, the fused data can be processed. The specific operations of this processing depend on the application requirements and the purpose of the GPU. For example, in graphics rendering, this processing may include steps such as texture mapping, lighting calculation, and pixel shading. In computing tasks, this processing may include computationally intensive tasks such as data analysis and machine learning inference.

[0125] In the embodiment of the present disclosure, since data is transmitted in parallel through different processing units, the data is synchronized and integrated to ensure the integrity and consistency of the data, so as to facilitate subsequent data processing operations.

[0126] In one possible implementation, the method further includes: determining the bandwidth and latency of each transmission link; dynamically adjusting the mapping ratio of the addresses mapped to each transmission link based on the bandwidth and latency requirements of the business scenarios processed by the GPU and the determined bandwidth and latency of each transmission link.

[0127] Bandwidth is the amount of data that a transmission link can transmit per unit time, while latency is the time required for data to be transmitted from the sender to the receiver. When determining the mapping ratio, the bandwidth and latency of each transmission link can be determined first. Specifically, the bandwidth and latency of each transmission link can be determined by measurement or estimation. For example, the bandwidth and latency of each transmission link can be determined by actual measurement, or the bandwidth and latency of each transmission link can be directly obtained by pre-setting them. This application does not limit the specific method for determining the bandwidth and latency.

[0128] For example, when the data transmission link between GPU chips includes a PCIe link and a direct link, the bandwidth and latency of these two links can be measured separately so that the mapping ratio can be dynamically adjusted according to business needs.

[0129] GPU processing business scenarios (such as real-time rendering, machine learning, etc.) have different requirements for data transmission bandwidth and latency. For example, real-time rendering scenarios pay more attention to low latency to ensure the smoothness of the picture; while machine learning scenarios pay more attention to high bandwidth to speed up the transmission of training data. Specifically, in real-time rendering scenarios, if the latency is too high, it may cause the picture to freeze or be delayed, affecting the user experience. Therefore, in this case, more data transmission tasks can be assigned to transmission links with smaller latency. Machine learning scenarios transmit a large amount of training data and pay more attention to high bandwidth. Therefore, more data transmission tasks can be assigned to transmission links with high bandwidth to achieve rapid transmission of large amounts of data.

[0130] Based on the bandwidth and latency information obtained for each transmission link, as well as the bandwidth and latency requirements of the GPU processing business scenario, the mapping ratio of video memory pages to each transmission link can be dynamically adjusted. Dynamically adjusting the mapping ratio maximizes the bandwidth utilization of the transmission link while meeting the latency requirements of the business scenario. By adjusting the mapping ratio, the data transmission volume can be matched to the link bandwidth, reducing bandwidth waste or shortage.

[0131] In one possible implementation, the transmission link includes a first transmission link and a second transmission link, the latency of the first transmission link is less than the latency of the second transmission link, the bandwidth and latency requirements of the GPU-based processing business scenario, and the determined bandwidth and latency of each transmission link, dynamically adjust the mapping ratio of the addresses mapped to each transmission link, including: when the business scenario is a real-time rendering scenario, determining the mapping ratio of the addresses of each transmission link used to transmit real-time rendering data as: the ratio of the first transmission link is greater than the ratio of the second transmission link.

[0132] In computer graphics, real-time rendering is the process of generating and updating images through real-time calculations, allowing for smooth animations and interactive performance. Real-time rendering scenarios include a variety of application scenarios that require real-time interaction and dynamic visual effects. For example, in gaming scenarios, real-time rendering is used to present the game screen to gamers, who can interact with the game screen through devices such as keyboards, mice, or game controllers. Real-time rendering technology ensures the smoothness and interactivity of the game screen. In virtual reality (VR) and augmented reality (AR) scenarios, real-time rendering technology is used to generate virtual scenes and objects, allowing users to immerse themselves in the virtual environment or interact with virtual objects. In applications such as live broadcasts and video calls, real-time rendering technology is used to generate and transmit video streams, ensuring that users can see each other's images and sounds in real time.

[0133] In this implementation, the first transmission link has a lower latency and is suitable for transmitting time-sensitive data, such as real-time rendering data; while the second transmission link has a relatively high latency and is suitable for transmitting data with less stringent time requirements, or for assisting the first transmission link in transmission, or for transmitting data when the first transmission link is saturated.

[0134] Since real-time rendering scenarios have high requirements for the timeliness of data transmission, data needs to be transmitted quickly between GPU chips to achieve rapid data processing and real-time rendering. Therefore, the first transmission link with lower latency can be used to transmit real-time rendering data. Therefore, the mapping ratio of the first transmission link will be set to be greater than the mapping ratio of the second transmission link.

[0135] For example, the first transmission link may be a Link link, and the second transmission link may be a PCIe link. Then, the mapping ratio of the Link link may be set to be greater than that of the PCIe link.

[0136] For example, in a real-time online game, player actions require immediate feedback on the screen to ensure smooth and interactive gameplay. If the scene is identified as real-time rendering, the mapping ratio of game data between the Link link and the PCIe link can be automatically adjusted. Because the Link link has low latency, more game data can be transmitted through the Link link, ensuring timely data arrival and smooth game operation.

[0137] In the embodiment of the present disclosure, in a real-time rendering scenario, by dynamically adjusting the mapping ratio to ensure that the first transmission link (with lower latency) undertakes more real-time rendering data transmission tasks, the waiting time in the rendering process can be reduced, making the rendering results smoother and more timely, thereby improving rendering efficiency.

[0138] In one possible implementation, the GPU-based processing-based business scenario has requirements for bandwidth and latency, as well as the determined bandwidth and latency of each transmission link, and dynamically adjusts the mapping ratio of the addresses mapped to each transmission link, including: when the business scenario is a machine learning scenario, using the bandwidth ratio of each transmission link as the mapping ratio of the addresses of each transmission link used to transmit training data.

[0139] In machine learning scenarios, since training data is typically large, the latency requirement for data transmission is relatively low, but the bandwidth requirement is high. Therefore, in this scenario, the mapping ratio of addresses mapped to each transmission link can be dynamically adjusted based on the bandwidth ratio of each transmission link.

[0140] Specifically, the bandwidth ratio of each transmission link can be directly used as the mapping ratio of the addresses of each transmission link used to transmit training data, thereby maximizing the utilization of the bandwidth resources of each transmission link and improving data transmission efficiency. For example, if the bandwidth of the PCIE link is twice that of the Link link, then when transmitting training data, the number of addresses mapped to the PCIE link will be twice the number of addresses mapped to the Link link.

[0141] For example, consider a machine learning training task that requires transferring a large amount of data. By obtaining pre-stored bandwidth information, it can be determined that the bandwidth of the PCIE link is 100GB / s, while the bandwidth of the Link link is 50GB / s. Therefore, the mapping ratio can be set to PCIE:Link = 2:1. In other words, two pages are mapped to the PCIE link, then one page is mapped to the Link link, then two pages are mapped to the PCIE link, then one page is mapped to the Link link, and so on, alternating mapping until all pages are mapped.

[0142] The following describes an application scenario of an embodiment of the present disclosure. In this application scenario, a write access process needs to be performed from chip0 to chip1, involving a data transfer capacity of 4G, where each video memory page has a PageSize of 4KB. The detailed steps of the implementation process include:

[0143] Step 1: On chip0, first apply for access to the target card chip1's address. Chip1's accessible address range is 128GB to 256GB. After applying, 4GB of address space is obtained, specifically from 128GB to 132GB.

[0144] Step 2: Alternate Address Mapping: To optimize data transmission efficiency, the alternate address mapping technology provided in this disclosure is employed. Considering the unidirectional PCIE bandwidth of 56 GB / s and the unidirectional Link bandwidth of 112 GB / s, the optimal mapping ratio between PCIE and MT-Link is set at 1:2. In other words, the first page is transmitted via PCIE, the next two pages via Link, and so on. A total of 1024 pages need to be transmitted, with the final page also transmitted via PCIE.

[0145] The following are examples of mapped addresses:

[0146] The address of the first page is 0x802000000000;

[0147] The address of the second Page is 0x2000001000;

[0148] The address of the third Page is 0x2000002000;

[0149] The address of the fourth Page is 0x802000003000;

[0150] The address of the fifth Page is 0x2000004000;

[0151] The address of the sixth Page is 0x2000005000;

[0152] ...(and so on)

[0153] Step 3: Initiate a write operation: On chip 0, initiate a write operation to the memory space in chip 1. This operation accesses the memory page granularity. For each memory space, data is sent to chip 1 in parallel via the corresponding link based on its mapped transmission method (PCIE or Link). When using Link, if there are multiple links, hardware load balancing technology will be used to determine which links to use for data transmission. Ultimately, this data transmission method can achieve a theoretical bandwidth of 168GB / s, greatly improving data transmission efficiency.

[0154] In one possible implementation, the memory fault detection method can be executed by electronic devices such as terminal devices and servers. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc. The method can be implemented by a processor calling computer-readable instructions stored in a memory.

[0155] In addition, the present disclosure also provides a data transmission device, electronic device, computer-readable storage medium, and program between GPU chips, all of which can be used to implement any of the data transmission methods between GPU chips provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method section and will not be repeated here.

[0156] Figure 5 A block diagram of a data transmission device between GPU chips according to an embodiment of the present disclosure is shown. The device is applied to a local GPU chip, which is a GPU chip that performs data transmission with a remote GPU chip, such as Figure 5 As shown, the device 20 includes:

[0157] An address determination module 21 is configured to determine the address of the video memory space of the remote GPU chip in response to a cross-chip data transfer instruction;

[0158] An address mapping module 22, configured to determine at least two transmission links for transmitting data based on the constructed mapping relationship between addresses and transmission links;

[0159] The data transmission module 23 is configured to perform data transmission with the remote GPU chip in parallel based on the at least two transmission links.

[0160] In one possible implementation, the mapping relationship includes: taking the video memory page of the GPU chip as the granularity, dividing the video memory space into multiple video memory pages according to the logical addresses in the video memory space, and alternately mapping the video memory pages to different transmission links according to the arrangement order of the logical addresses of the multiple video memory pages.

[0161] In a possible implementation, the apparatus includes a mapping relationship building module, configured to:

[0162] Determining a mapping ratio according to a bandwidth ratio of the at least two transmission links, where the mapping ratio is a ratio of addresses mapped to the respective transmission links;

[0163] The video memory space is divided into a plurality of video memory pages according to the logical addresses in the video memory space, and the video memory pages are alternately mapped to different transmission links according to the mapping ratio according to the arrangement order of the logical addresses of the plurality of video memory pages.

[0164] In a possible implementation, the mapping relationship building module is used to:

[0165] determining a bandwidth utilization rate of each of the transmission links when data transmission is performed according to the bandwidth ratio;

[0166] Based on the bandwidth utilization, load balancing is performed on each of the transmission links to obtain the mapping ratio.

[0167] In a possible implementation, the apparatus further includes:

[0168] The mapping relationship update module is used to delete the established mapping relationship in response to the mapping ratio received from the user, and map the video memory pages to different transmission links in turn according to the new mapping ratio in the order of the logical addresses of the video memory pages to obtain a new mapping relationship.

[0169] In a possible implementation, the data transmission module is configured to transmit data in parallel with a remote GPU chip based on at least two processing units, respectively, through different transmission links, wherein the transmission links used by the same processing unit are the same.

[0170] In a possible implementation, the apparatus further includes:

[0171] The fusion unit is used to fuse the data in the at least two processing units and perform subsequent processing on the fused data.

[0172] In a possible implementation, the apparatus further includes:

[0173] A physical characteristics determination module, used to determine the bandwidth and delay of each transmission link;

[0174] The dynamic adjustment module is used to dynamically adjust the mapping ratio of addresses mapped to each transmission link based on the bandwidth and latency requirements of the GPU-processed business scenario and the determined bandwidth and latency of each transmission link.

[0175] In one possible implementation, the transmission link includes a first transmission link and a second transmission link, the delay of the first transmission link is less than the delay of the second transmission link, and the dynamic adjustment module is used to determine the mapping ratio of the addresses of each transmission link used to transmit real-time rendering data when the business scenario is a real-time rendering scenario: the ratio of the first transmission link is greater than the ratio of the second transmission link.

[0176] In one possible implementation, the dynamic adjustment module is configured to use the bandwidth ratio of each transmission link as a mapping ratio of the addresses of each transmission link used to transmit training data when the business scenario is a machine learning scenario.

[0177] This method has a specific technical connection with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware computing efficiency or execution effect (including reducing the amount of data storage, reducing the amount of data transmission, increasing the hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the laws of nature.

[0178] In some embodiments, the functions or modules included in the method provided by the embodiments of the present disclosure can be used to execute the method described in the above method embodiments. The specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0179] The present disclosure also provides a computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above method when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0180] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0181] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0182] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0183] Figure 6 FIG1 shows a block diagram of an electronic device 1900 according to an embodiment of the present disclosure. For example, the electronic device 1900 can be provided as a server or a terminal device. Figure 6 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0184] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OSX TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0185] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0186] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0187] Computer-readable storage media can be a tangible device that can hold and store the instructions used by the instruction execution device. Computer-readable storage media can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. Computer-readable storage media used herein is not interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagated by waveguides or other transmission media (for example, light pulses by fiber optic cables), or electrical signals transmitted by wires.

[0188] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0189] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0190] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0191] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0192] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0193] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0194] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0195] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0196] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0197] If the technical solution of this application involves personal information, the product that applies the technical solution of this application has clearly informed the personal information processing rules and obtained the individual's voluntary consent before processing personal information. If the technical solution of this application involves sensitive personal information, the product that applies the technical solution of this application has obtained the individual's separate consent before processing sensitive personal information, and at the same time meets the "explicit consent" requirement. For example, on personal information collection devices such as cameras, a clear and prominent sign is set to inform that the personal information collection scope has been entered and personal information will be collected. If the individual voluntarily enters the collection scope, it is deemed that they agree to the collection of their personal information; or on the personal information processing device, when the personal information processing rules are notified by obvious signs / information, the individual's authorization is obtained through pop-up information or by asking the individual to upload their personal information; among which, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the type of personal information processed.

[0198] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for data transmission between GPU chips, characterized in that: Applied to a local GPU chip, where the local GPU chip is a GPU chip that performs data transmission with a remote GPU chip, the method includes: In response to the cross-chip data transfer instruction, determining the address of the video memory space of the remote GPU chip; Determining, according to the address, at least two transmission links for transmitting data based on a constructed mapping relationship between the address and the transmission link; Based on the at least two transmission links, transmit data to the remote GPU chip in parallel; The process of constructing the mapping relationship includes: Determining bandwidth utilization of each transmission link when performing data transmission according to the bandwidth ratio; Based on the bandwidth utilization, load balancing is performed on each transmission link to obtain a mapping ratio, where the mapping ratio is a ratio of addresses mapped to each transmission link; The video memory space is divided into a plurality of video memory pages according to the logical addresses in the video memory space, and the video memory pages are alternately mapped to different transmission links according to the mapping ratio according to the arrangement order of the logical addresses of the plurality of video memory pages.

2. The method according to claim 1, characterized in that The mapping relationship includes: taking the memory page of the GPU chip as the granularity, dividing the memory space into multiple memory pages according to the logical addresses in the memory space, and alternately mapping the memory pages to different transmission links according to the arrangement order of the logical addresses of the multiple memory pages.

3. The method according to claim 1, characterized in that The method further comprises: In response to the mapping ratio received from the user, the established mapping relationship is deleted, and the video memory pages are alternately mapped to different transmission links in accordance with the new mapping ratio in the order of the logical addresses of the video memory pages to obtain a new mapping relationship.

4. The method according to claim 1, wherein The performing data transmission with the remote GPU chip in parallel based on the at least two transmission links includes: Based on at least two processing units, data is transmitted in parallel with a remote GPU chip through different transmission links respectively, wherein the transmission links used by the same processing unit are the same.

5. The method according to claim 4, characterized in that After performing data transmission with the remote GPU chip in parallel based on the at least two transmission links, the method further includes: The data in the at least two processing units are fused and subsequently processed.

6. The method according to claim 1, characterized in that The method further comprises: Determine the bandwidth and latency of each transmission link; Based on the bandwidth and latency requirements of GPU-processed business scenarios and the determined bandwidth and latency of each transmission link, the mapping ratio of addresses mapped to each transmission link is dynamically adjusted.

7. The method according to claim 6, characterized in that The transmission link includes a first transmission link and a second transmission link, the latency of the first transmission link is less than the latency of the second transmission link, the bandwidth and latency requirements of the GPU-based business scenario, and the determined bandwidth and latency of each transmission link, and dynamically adjusting the mapping ratio of addresses mapped to each transmission link, including: In the case where the business scenario is a real-time rendering scenario, the mapping ratio of the addresses of the transmission links used to transmit real-time rendering data is determined as follows: the ratio of the first transmission link is greater than the ratio of the second transmission link.

8. The method according to claim 6, characterized in that The GPU-based business scenario's bandwidth and latency requirements, as well as the bandwidth and latency of each transmission link, dynamically adjust the mapping ratio of addresses mapped to each transmission link, including: When the business scenario is a machine learning scenario, the bandwidth ratio of each transmission link is used as the mapping ratio of the addresses of each transmission link used to transmit training data.

9. A data transmission device between GPU chips, characterized in that: Applied to a local GPU chip, where the local GPU chip is a GPU chip that performs data transmission with a remote GPU chip, the device includes: An address determination module, configured to determine the address of the video memory space of the remote GPU chip in response to a cross-chip data transfer instruction; An address mapping module, configured to determine at least two transmission links for transmitting data based on the mapping relationship between the addresses and the transmission links; a data transmission module, configured to transmit data in parallel with a remote GPU chip based on the at least two transmission links; The device includes a mapping relationship building module, which is used to: Determining bandwidth utilization of each transmission link when performing data transmission according to the bandwidth ratio; Based on the bandwidth utilization, load balancing is performed on each transmission link to obtain a mapping ratio, where the mapping ratio is a ratio of addresses mapped to each transmission link; The video memory space is divided into a plurality of video memory pages according to the logical addresses in the video memory space, and the video memory pages are alternately mapped to different transmission links according to the mapping ratio according to the arrangement order of the logical addresses of the plurality of video memory pages.

10. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to implement the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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