Attack detection circuit and attack detection method

Abstract

The invention provides an attack detection circuit and an attack detection method, and the attack detection circuit in an integrated circuit comprises a main detector and a pulse detection circuit. The main detector is configured to detect an abnormal bit of a power supply input voltage of the integrated circuit upon startup. The pulse detection circuit is configured to detect a transition of the power supply input voltage and transmit a start-up indication to the main detector in response to the detected transition.

Description

Technical Field

[0001] The present disclosure relates to the security of integrated circuits, and more particularly to an apparatus and method for detecting power side-channel attacks. Background Art

[0002] Side-channel attacks, including power supply attacks, are used to obtain secrets from integrated circuits (ICs). ICs sometimes include methods for monitoring the power input as a means of protection.

[0003] In "Power supply glitch attacks: Design and evaluation of detection circuits" (K. Gomina et.al., 2014 IEEE International Symposium on Hardware-Oriented Security and Trust) (DOI: 10.1109 / HST.2014.6855584), the authors analyze the mechanisms involved in these attacks and show that the timing characteristics of logic gates are very sensitive to power failures and can be used to insert faults. Among them, new methods for verifying power failure detection circuits are presented, allowing the process of evaluating these detection circuits to be standardized as a digital design flow.

[0004] In "Detecting Power Attacks on Reconfigurable Hardware" (Le Masle & Luk, 22nd International Conference on Field Programmable Logic and Application (FPL), August 29-31, 2012) (DOI: 10.1109 / FPL.2012.6339235), the authors present an architecture implemented on reconfigurable hardware for detecting power attacks on crypto systems. The authors demonstrate how to monitor the supply voltage of a device using an on-chip power monitor based on a ring oscillator. A power attack detection measure is developed that takes into account abnormal supply voltage and power line impedance values ​​in order to detect the insertion of power measurement circuits on the power line of the device. The above measures are integrated into an on-chip attack detector. The results applied to the Advanced Encryption Standard (AES) and RSA encryption systems show that with proper operational settings, the above attack detection framework can achieve a false-positive rate and false-negative rate equivalent to 0% in all test cases.

[0005] Finally, “How a voltage glitch attack could cripple your SoC or MCU” (INVIA application note, version 1.0, June 30, 2020) shows that voltage glitch is a simple and low-cost method to create error insertion vulnerabilities on any accessible device, and argues that defenses against this attack technique require layered security protections, including fast and reliable detection of voltage transient events at the power supply end of the target device, and hardware and software that are resilient to the attack. The application note goes on to describe a voltage glitch detection circuit. Summary of the invention

[0006] An embodiment herein describes an attack detection circuit in an integrated circuit. The attack detection circuit includes a main detector and a pulse detection circuit. The main detector is configured to detect an abnormal position of a power supply input voltage of the integrated circuit at startup. The pulse detection circuit is configured to detect a transition of the power supply input voltage and transmit an activation indication to the main detector in response to the detected transition.

[0007] In some embodiments, the master detector is configured to switch between a low power mode of operation and a high speed mode of operation in response to the start-up indication, wherein the low power mode of operation is used to detect slower power bit drops and the high speed mode of operation is used to detect fast errors, and the high speed mode of operation has a higher bit detection speed and higher power consumption. In one embodiment, the master detector is configured to switch between a disabled mode of operation and an enabled mode of operation in response to the start-up indication. In one disclosed embodiment, the master detector is configured to switch between a limited function mode of operation (detecting slower power bit drops) and a full function mode of operation in response to the start-up indication.

[0008] In some embodiments, the activation indication includes an increased supply current. In an example of an embodiment, the power supply of the attack detection circuit includes a rectifier power supply. In another embodiment, the attack detection circuit further includes a rectifier power supply with a low voltage drop, configured to supply a stable voltage to the main detector based on an input source of a reference voltage. The attack detection circuit may further include a bandgap reference voltage source, configured to generate a reference voltage. In one embodiment, the pulse detection circuit is configured to detect multiple transitions of the power supply input voltage above a predetermined threshold.

[0009] According to an embodiment described herein, an attack detection method in an integrated circuit is additionally provided. When a master detector is activated, the master detector is used to detect an abnormal position of a power supply input voltage of the integrated circuit. A pulse detection circuit is used to detect a transition of the power supply input voltage, and an activation indication is sent to the master detector in response to the transition.

[0010] In order to more fully understand the present invention, a detailed description of the embodiments will be provided with reference to the following drawings, wherein: BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram of an integrated circuit (IC) with power supply attack resilience according to an embodiment of the present invention;

[0012] Figure 2 A flow chart of a power supply attack detection method for an IC according to an embodiment of the present invention;

[0013] Figure 3 A block diagram of an attack detection circuit according to an embodiment of the present invention;

[0014] Figure 4 A block diagram of a pulse detection circuit according to an embodiment of the present invention;

[0015] Figure 5A timing diagram according to an embodiment of the present invention is shown, showing the timing of the attack detection circuit responding to a power supply (Vcc) pulse of -0.6V;

[0016] Figure 6 FIG. 1 is a timing diagram according to an embodiment of the present invention, showing the timing of the attack detection circuit responding to a plurality of pulses of the power supply input voltage Vcc below a predetermined threshold.

[0017] Explanation of symbols

[0018] 100: Integrated Circuit (IC)

[0019] 102,300: Attack detection circuit (A-DET)

[0020] 104,302,400: Pulse detection circuit

[0021] 106,304: Main detector

[0022] 200: Flowchart

[0023] 202: Pulse detection operation

[0024] 204: Vcc attack detection operation

[0025] 301:Low Dropout (LDO) Rectifier

[0026] 306,308,410,420:PMOS

[0027] 310,312,332,334,336,412,422:NMOS

[0028] 314,402,415,426,Sence:Node

[0029] 316,318,320,322,404,406:Resistance

[0030] 324: Reverse

[0031] 328,428: Latch

[0032] 330,430: Delay circuit

[0033] 414,424: Enable NMOS

[0034] 416: Capacitor

[0035] 432: Logic Gates

[0036] 500,600: Timing diagram

[0037] 502,504,506,510,512,602,606,608,610: Waveform

[0038] 508: Amplification Enable Waveform

[0039] 511,513:Charts

[0040] 604: Detection Threshold

[0041] Vcc: power supply input voltage

[0042] Vref: preset voltage

[0043] Vldo: rectified voltage

[0044] Isink: Constant current

[0045] Nbias: bias

[0046] V1, V2: voltage

[0047] EN: Enable signal DETAILED DESCRIPTION

[0048] Side-channel attacks are used to obtain secrets, such as encryption or authentication keys, from an integrated circuit (IC), and are usually performed through the power supply input voltage (herein referred to as Vcc). Common side-channel attack techniques involve supplying voltages that exceed the operating requirements of the IC, which causes the IC to operate abnormally and may allow secrets stored on the IC to be obtained. ICs sometimes include some means of monitoring the power supply input voltage and detecting voltage irregularities; however, because the attack can include providing very short pulses to the power supply input voltage, the detection circuit must be very fast and therefore requires a lot of power. Furthermore, the detection circuit needs to have accuracy so that normal fluctuations in the power supply input voltage Vcc are not judged as security attacks.

[0049] The embodiments of the present invention disclosed herein provide an attack detection circuit and method with good accuracy and low average power consumption.

[0050] In some embodiments, the IC has an attack detection circuit (A-DET) including a fast spike detection circuit for detecting and signaling a transition of a power supply input voltage Vcc as a power supply input voltage and a main detector for accurately comparing the bit of the power supply input voltage Vcc with a predetermined limit value to indicate whether the bit of the power supply input voltage Vcc exceeds the limit value. In some embodiments, the main detector is not activated until the spike detection circuit indicates a transition (i.e., a "spike") of the power supply input voltage Vcc. In other embodiments, the main detector is in a low power consumption "standby" mode (e.g., having low power consumption) and thus performs the comparison at a slower speed; in response to a spike detection indication, the active detector enters a fast operation mode for a short period of time.

[0051] In one embodiment, the pulse detection circuit includes a comparator having a capacitive feed-forward path for responding to fast pulses. In some embodiments, the pulse detection circuit includes matched transistors for better accuracy.

[0052] Finally, in some embodiments, the A-DET includes a rectified voltage (also referred to as a stable voltage) Vldo of a power supply controlled by a band-gap-reference (BGREF) with a low dropout (LDO) to filter pulses of the power supply input voltage Vcc and provide a stable power supply operating voltage for the sensitive A-DET.

[0053] System Description

[0054] Figure 1 A block diagram of an integrated circuit (IC) 100 with power supply attack resilience according to an embodiment of the present invention is shown. For example, IC 100 may include a secure processor or a memory device, or any other type of IC that needs to be protected from power supply side-channel attacks. To detect power supply attacks, we define a range of power supply voltages for "normal" operating bits and check whether the power supply is outside the normal range (voltage bits outside the "normal" range are called "abnormal voltage bits").

[0055] IC 100 includes an attack detection circuit (A-DET) 102, which is configured to detect an abnormal voltage level of a power supply input voltage Vcc of IC 100 (Vdd is usually used to represent the supply input voltage in metal oxide semiconductor (MOS) based ICs, but Vcc is used here).

[0056] For example, if an abnormal voltage level is detected, A-DET 102 is configured to transmit an attack detection indication to a reset circuit (not shown) in IC 100, or in another example, to multiple gates that disable all IC outputs. Thus, a power supply attack on IC 100 can force IC 100 to reset, or alternatively, block all outputs to protect any confidential data stored in IC 100.

[0057] In various embodiments, A-DET 102 is very fast and can detect a brief drop in power supply input voltage Vcc. At the same time, because A-DET 102 is typically enabled when IC 100 is enabled (to provide continuous protection), the power consumption of A-DET 102 is relatively low.

[0058] In order to meet the above conflicting requirements, the A-DET 102 has a low-power pulse detection circuit 104 and a high-power main detector 106, wherein the pulse detection circuit 104 is configured to detect and indicate the bit transition of the power supply input voltage Vcc, and the main detector 106 is used to accurately compare the bit of the power supply input voltage Vcc with the bit of a preset voltage (also referred to as a reference voltage) Vref. In response to the transition of the power supply input voltage Vcc, the pulse detection circuit 104 transmits an activation indication to the main detector 106. In one embodiment, the default state of the main detector 106 is a disabled state, but when the pulse detection circuit 104 indicates a transition of the power supply input voltage Vcc (i.e., transmits an activation indication), the main detector 106 is switched to an activated state. In another embodiment, the default state of the main detector 106 is a low-power (and therefore slow-speed operation) operation mode (also referred to as a limited-function operation mode), and switches to a full-function high-speed (but therefore high-power) operation mode (also referred to as a full-function operation mode) in response to the activation indication.

[0059] In actual applications, the indication of detected pulses does not always indicate an attack on the power supply input voltage Vcc; the main detector with accurate voltage level comparison circuits may ignore some indications of detected pulses. Such false indications may cause the main detector to require power for a short period of time, but on average, the power consumption of A-DET 102 is relatively low. It should be noted that the pulse detector makes false indications rare and filters out normal noise of the power supply voltage (wherein the structure of the pulse detector according to various embodiments will be described below with reference to Figure 4 for explanation).

[0060] In one embodiment, the activation indication sent by the pulse detection circuit is an amplified current (or an amplified supply current) applied to a lower current consumed by the main detector operating in a low power consumption mode. In some embodiments, the power consumption of the pulse detector is very low (e.g., 2 μA vs. 72 μA).

[0061] like Figure 1 The configurations of IC 100 and A-DET 102 shown and described as examples above are by way of example only. Other configurations may be used in alternative embodiments. For example, in some embodiments, pulse detection circuit 104 is configured to detect transitions in power supply input voltage Vcc that exceed a predetermined rate of change.

[0062] Figure 2 A flowchart 200 is shown for describing a method for detecting a power supply attack in an IC according to an embodiment of the present invention. The flowchart 200 is executed by the pulse detection circuit 104 and the main detector 106 .

[0063] Flowchart 200 begins with a pulse detection operation 202, where the main detector 106 is in a standby / slow detection mode and the pulse detection circuit 104 is looking for a transition (also referred to as a pulse) in the power supply input voltage Vcc. At this point, the power consumption of the main detector 106 is low or zero (in some embodiments, the power of the main detector 106 is above zero to allow for high-speed startup). Flowchart 200 will remain in the pulse detection operation 202 until a transition in the power supply input voltage Vcc is detected.

[0064] When the pulse detection circuit 104 detects a transition of the power supply input voltage Vcc, the flowchart 200 enters a power supply input voltage (Vcc) attack detection operation 204, where (i) the pulse detection circuit transmits an amplified current to the main detector to set the main detector to the high-speed detection mode (also known as the startup operation mode), (ii) the main detector compares the power supply input voltage Vcc with a preset voltage Vref, and (iii) a timer confirms whether the time length of the flowchart 200 in the Vcc attack detection operation 204 exceeds a preset limit. As long as the preset time limit is not exceeded and Vcc ≥ Vref, the flowchart 200 remains in the Vcc attack detection operation 204.

[0065] If the time limit has been exceeded (this event is called timeout), the flowchart 200 re-enters the pulse detection operation 202 to reduce power consumption and look for subsequent transitions of the power supply input voltage Vcc. If in the Vcc attack detection operation 204, the main detector detects that Vcc < Vref, the main detector transmits an attack detection indication signal representing the detected attack to initiate protection measures (such as resetting the device or blocking all output terminals) to maintain the security of confidential information.

[0066] For the purpose of simplicity, Figure 2 the flowchart 200 shown and described above is only an example. Other flowcharts can be used in alternative embodiments. For example, in some embodiments, frequent detection of Vcc < Vref may result in a reset, while signal detection only blocks the read operation. In multiple embodiments, the main detector can deactivate the operation mode instead of the low-power operation mode.

[0067] Next, the detailed design of the circuits of the pulse detection circuit and the main detector will be described according to an embodiment.

[0068] Figure 3 FIG. is a block diagram of an A-DET 300 described according to an embodiment of the present invention. The A-DET 300 includes an LDO rectifier (or rectified power supply) 301 of a low dropout regulator (LDO). The voltage output by the LDO rectifier 301 (also known as the rectified voltage Vldo) is controlled by a bandgap reference voltage (BGREF). In multiple embodiments, the supply input voltage is typically 3.3V, and the rectified voltage Vldo is typically 1.8V. The LDO rectifier 301 isolates, or at least attenuates, the voltage variation of the rectified voltage Vldo from the voltage variation of the power supply input voltage Vcc (including fast pulses), so that the rectified voltage Vldo can be used as a stable and accurate power supply in the power supply input voltage Vcc with a wide range of values.

[0069] According to Figure 3In the example of the embodiment shown, the rectified voltage Vldo is used as the power supply for other A-DETs, so that attacks on the power supply input voltage Vcc can be safely detected (if the power supply input voltage Vcc drops to zero, or drops to a low level where the rectified voltage Vldo becomes unstable, other circuits of IC 100 will stop operating to maintain the security of all stored secrets).

[0070] The A-DET 300 further includes a pulse detection circuit 302 and a main detector 304. The pulse detection circuit 302 is configured to detect the transition of the power supply input voltage Vcc, and the main detector 304 is configured to accurately compare the power supply input voltage Vcc with the preset voltage Vref.

[0071] In order to shorten the notation length, an N-channel metal-oxide-silicon transistor will be referred to as an NMOS transistor (or NMOS), and a P-channel metal-oxide-silicon transistor will be referred to as a PMOS transistor (or PMOS) hereinafter.

[0072] The main detector 304 includes a PMOS 306, a PMOS 308, an NMOS 310, and an NMOS 312. The pair of PMOS 306, NMOS 310 and the matching pair of PMOS 308, NMOS 312 are connected between the rectified voltage Vldo and a node 314. When a current source from the node 314 converges a constant current Isink, the PMOS 306, 308 and the NMOS 310, 312 compare the gate voltage of the NMOS 310 with the gate voltage of the NMOS 312. According to the constant current Isink, the above comparison can be slow (e.g., 10ns) or fast (e.g., 2ns). The gate voltages of the NMOS 310 and 312 are determined by a resistor 316, a resistor 318, a resistor 320, and a resistor 322:

[0073] V g310 =Vcc×R 318 / (R 318 +R 316 )

[0074] V g312 =Vldo×R 322 / (R 322 +R 320 )

[0075] Where R 318 , R 316 , R 322 and R 320represents the impedance values ​​of the corresponding resistors 318, 316, 322 and 320, and V g310 and V g312 represents the gate voltage of the corresponding NMOS 310 and 312 .

[0076] Therefore, by selecting appropriate resistor values, the power supply input voltage Vcc can be compared to a preset threshold value, and the node labeled "Sense" can assume a low voltage when the power supply input voltage Vcc is below the threshold value. The low voltage can be inverted to a high voltage by an inverter 324 to set a latch 328 to output an attack detection indication. A delay circuit 330 resets the latch 328 after a preset delay (e.g., 50ns) so that the attack detection indication will form a pulse long enough for the digital response to proceed. Subsequent attacks will be detected after the pulse is reset.

[0077] according to Figure 3 In the example of the embodiment shown, when no pulse is detected, an NMOS 332 sinks current from node 314 according to a preset bias voltage Nbias and the width-to-length ratio of the NMOS 332. In response to a pulse of the power supply input voltage Vcc detected, the pulse detection circuit 302 sets the gate of an NMOS 334 for enabling amplification to a high voltage level. Then, an NMOS 336 applies additional amplification current to the constant current Isink.

[0078] Like the gate of NMOS 332, the gate of NMOS 336 is also connected to the bias voltage Nbias, but in one embodiment, the width-to-length ratio of NMOS 336 is very large relative to that of NMOS 332 (e.g., four times the width-to-length ratio of NMOS 332), so that the main detector 304 can compare the power supply input voltage Vcc and the preset voltage Vref more quickly.

[0079] Refer to the following Figure 4 As mentioned above, the bias voltage Nbias is also input to the pulse detection circuit 302 .

[0080] like Figure 3 As shown, and as described above, the configuration of A-DET 300 is by way of example only. Other configurations may be used in alternative embodiments. For example, in some embodiments, main detector 304 remains disabled until a pulse is detected by the pulse detection circuit; thus, NMOS 332 is not required. In one embodiment, attack detection resets the IC, and thus delay circuit 330 is not required (because delay circuit 330 stops the attack detection indication after a predetermined delay).

[0081] Figure 4FIG. 4 is a block diagram of a pulse detection circuit 400 according to an embodiment of the present invention.

[0082] A node 402 is set to a voltage V1 according to a fixed rectified voltage Vldo, a variable (and possibly attacked) power supply input voltage Vcc, and a ratio of a resistor 404 to a resistor 406. A first conductive path includes a PMOS 410 and an NMOS 412, and is connected in series with an enable NMOS 414 (the gate of which can receive an enable signal EN), wherein the first conductive path sets a voltage (labeled as V2) at a node 415 according to the voltage V1, the bias voltage Nbias, and the characteristics of the PMOS 410, the NMOS 412, and the enable NMOS 414.

[0083] A second conductive path includes a PMOS 420 and an NMOS 422 connected in series with an enabling NMOS 424, wherein the input terminals of the PMOS 420 and the NMOS 422 are connected to the voltage V1 output by the first conductive path. In one embodiment, the PMOS 420 and the PMOS 410 have the same layout and therefore have approximately matched threshold voltages to compensate for any process / temperature variations.

[0084] The resistors 404 and 406 are appropriately selected so that under direct current (DC) conditions, the voltage V1 is higher than the rectified voltage Vldo, and thus the voltage V2 is close to the position of the rectified voltage Vldo and away from the tripoint voltage; therefore, the voltage at a node 426 is a low voltage. In order to achieve a fast response to a pulse of the power supply input voltage Vcc, the pulse detection circuit 400 further includes a capacitor 416 to provide a capacitive coupling between the power supply input voltage Vcc and the voltage V2. A negative transition of the power supply input voltage Vcc sets the voltage V2 to a low voltage, and thus sets the node 426 to a high voltage. A latch 428 then turns high, and an amplifier enable signal increases the main detector 304 ( Figure 3 ) bias current. After a preset delay (e.g., 5ns), a delay circuit 430 disables latch 428 to prepare for a subsequent power supply input voltage Vcc error. A logic gate 432 is configured to reset latch 428 when pulse (or error) detection circuit 400 is not enabled.

[0085] In some embodiments, voltage V1 becomes higher than rectified voltage Vldo, while voltage V2 is approximately equal to V1-Vtp (where Vtp is the threshold voltage of PMOS). Voltage V1 maintains voltage V2 (≈V1-Vtp) slightly lower than rectified voltage Vldo to maintain node 426 at a low voltage, while allowing voltage V2 to still "drop" below the threshold during an error process; voltage V2 will not be too low below rectified voltage Vldo to avoid triggering a false alarm.

[0086] It should be noted that voltage V1 is related to the standard level of power supply input voltage Vcc; if an attacker sets the power supply input voltage Vcc to 2.8V before inserting an error (to reduce the depth of the error to avoid detection), the steady-state level of voltage V1 will be reduced, and voltage V2 will also be reduced to match the depth of the error; if the power supply input voltage Vcc is set to 2.8V, the attacker needs an error of about -400mV to reach 2.4V; at this time, since voltage V2 has been reduced and is closer to the threshold of PMOS 420, this -400mV error will be easily detected.

[0087] If an attacker uses a high voltage power supply input voltage Vcc (e.g., 3.6V) to attack, both voltages V1 and V2 will become higher (wherein voltage V2 may be slightly higher than the rectified voltage Vldo and away from the threshold of PMOS 420); however, the error required to reach 2.4V is -1.2V at this time and can be easily detected.

[0088] The voltage V2 and the detection threshold (threshold of PMOS 420) are both related to the threshold voltage Vtp of the PMOS, thus ensuring that the pulse detector is coupled to all process / voltage / temperature (PVT) variations.

[0089] Simulation Results

[0090] like Figure 4 A circuit is configured to be simulated with the following parameters:

[0091] Process node: TSMC 40nm

[0092] Simulation corner: TYP

[0093] transistor:

[0094] transistor type W(width)(nm) L(length)(nm) 410 PMOS 4000 270 412 NMOS 500 1200 414 NMOS 3000 550 420 PMOS 1000 270 422 NMOS 1000 270 424 NMOS 2000 600

[0095] resistance:

[0096] resistance Resistance(Ohm) 406 200k 404 170k

[0097] capacitance:

[0098] capacitance Capacitance(fF) 416 600

[0099] Voltage of the error (or attack) detection circuit:

[0100] Node (or voltage) Steady-state voltage Small error (0.25V) Big Error (0.6V) Vcc 3V 2.75V 2.4V V1 2.2V ～2.2V ～2.2V V2 1.75V 1.5V 1.2V Latch N / A N / A Vldo's Pulse

[0101] Figure 5 A timing diagram 500 is shown in accordance with an embodiment of the present invention, showing the process of A-DET 300 responding to a -0.6V power supply (Vcc) pulse. All waveforms share the same time axis. A waveform 502 depicts the voltage of the power supply input voltage Vcc, which drops from 3.0V to 2.4V at a time of 1ns. A waveform 504 depicts the voltage V1 (i.e., Figure 4 The voltage of the node 402 in FIG. 5 is a voltage at the node 402 in FIG. 5 , which drops from 2.19V in the initial state to 1.75V in response to the voltage drop of the power supply input voltage Vcc. A waveform 506 describes the voltage V2 (i.e., Figure 4 Since node 415 is capacitively coupled to the power supply input voltage Vcc, voltage V2 drops significantly (from 1.74V to 1.14V) in response to the voltage drop of the power supply input voltage Vcc. The rapid drop in waveform 506 is reversed (i.e., Figure 4 , but not shown in the figure). An amplifier enable waveform 508 describes an amplifier enable signal (given by Figure 4 The voltage of the latch 428 output in is triggered by a high voltage bit on node 426.

[0102] A waveform 510 describes the constant current Isink (given by Figure 3 In the initial state, the constant current Isink is a low current (in absolute value) of approximately -16.6 μA. In response to a high voltage level of the amplifier enable waveform 508, the sink current increases (in absolute value) to -72 μA, thereby increasing the speed of the main detector 304 (the overshoot in the waveform is typically less than 0.1 ns and is caused by the sharing of current between internal nodes by the capacitive charge when a new branch is added). Referring to a graph 511 describing the constant current Isink when the pulse detector (or pulse detection circuit) is not enabled (e.g., an embodiment including only one main detector), the current value is maintained at a constant -16.6 μA.

[0103] A waveform 512 depicts the attack detection indication output by the A-DET 300. As shown, although the main detector draws only 20 μA of current in the absence of a pulse, the delay between an error in the power supply input voltage Vcc and the attack detection indication is only 3.0 ns. For comparison, a graph 513 depicts the attack detection response when the pulse detector (or pulse detection circuit) is not enabled (e.g., an embodiment including only the main detector), and it should be noted that the attack is detected much later (approximately 11 ns) relative to when the pulse detector is enabled.

[0104] Figure 6 A timing diagram 600 is described in accordance with an embodiment of the present invention, showing the response of the A-DET 300 to a pulse of the power supply input voltage Vcc below a preset threshold. All waveforms share a common time axis. A waveform 602 depicts the voltage of the power supply input voltage Vcc, where until the pulse is inserted (at approximately 22ns), the voltage of the power supply input voltage Vcc is 3.0V. However, during the time period when all pulses occur, the power supply input voltage Vcc is above a detection threshold 604 (2.73V). It should be noted that this represents a strong resistance to false alarms. Figure 6 In the example of the described embodiment, pulses below 250 mV are ignored; in alternative embodiments, other maximum pulse levels may be set by adjusting circuit parameters (eg, voltages V1 and V2).

[0105] As shown in a waveform 606, in response to a pulse of the power supply input voltage Vcc, Figure 4 The voltage V2 of the node 415 is slightly reduced, but the reduction is too small to be temporarily stored in the latch 428, and as shown in a waveform 608, the outputted amplification enable signal only rises slightly, but is still smaller than the NMOS 334 ( Figure 3 A waveform 610 describes the bias current of A-DET, which oscillates slightly at -16 μA.

[0106] like Figures 1 to 4As shown and described above, the configuration of the attack detection circuit (A-DET) 300 includes an error (or pulse) detection circuit 400, a main detector 304, a (BGREF's) LDO rectifier 301, and a flowchart 200, wherein the above configuration and flowchart are shown only as examples and are shown only for the purpose of clearly presenting the concepts herein. Any suitable system configuration and flowchart may be used for alternative embodiments. The various components of the A-DET 300 may be implemented in an integrated circuit, for example, an application specific integrated circuit (ASIC) or a field-programmable gate-array (FPGA).

[0107] Although the embodiments described herein are primarily directed to the detection of supply voltage side-channel attacks, the methods and systems described herein may also be used in other applications, such as design for testability (DFT) for power supply noise monitoring, and systems for monitoring power supply modes.

[0108] It should be understood that the embodiments described above are only examples, and the present invention is not limited to the contents described and shown above. On the contrary, the scope of the present invention includes the combination of the features described above or a subset of the combination, as well as the evolution and derivative of the above features discovered by those skilled in the art after reading the foregoing description and finding the contents not disclosed in the prior art. The documents incorporated into this patent application by reference should be considered as part of the present case, but when any term appears in these incorporated documents that conflicts with the explicit or implicit definition in this specification, only the definition in this specification should be considered.

Claims

1. An attack detection circuit, characterized in that: Located in an integrated circuit, the above-mentioned attack detection circuit includes: a main detector configured to detect an abnormal level of a power supply input voltage of the integrated circuit at startup; and A pulse detection circuit is configured to detect a transition of the power supply input voltage and transmit an activation indication to the main detector in response to the detected transition.

2. The attack detection circuit according to claim 1, characterized in that: The master detector is configured to switch between a low power operation mode and a high speed operation mode in response to the activation indication, wherein the high speed operation mode has a faster bit detection speed and higher power consumption relative to the low power operation mode.

3. The attack detection circuit according to claim 1, characterized in that: The master detector is configured to switch between a deactivated mode of operation and an activated mode of operation in response to the activation indication.

4. The attack detection circuit according to claim 1, characterized in that: The master detector is configured to switch between a limited function operating mode and a full function operating mode in response to the activation indication.

5. The attack detection circuit according to claim 1, characterized in that: The activation instruction includes an increased supply current.

6. The attack detection circuit according to claim 1, characterized in that: The power supply of the attack detection circuit includes a rectifier power supply.

7. The attack detection circuit according to claim 1, characterized in that: The invention further comprises a rectifier power supply with low voltage drop, wherein the rectifier power supply is configured to provide a stable voltage to the main detector according to an input source of a reference voltage.

8. The attack detection circuit according to claim 7, characterized in that: The invention further comprises a bandgap reference voltage source, which is configured to generate the reference voltage.

9. The attack detection circuit according to claim 1, characterized in that: The pulse detection circuit is configured to detect multiple transitions of the power supply input voltage that are greater than a predetermined threshold.

10. An attack detection method, characterized in that: For an integrated circuit, the method comprises: When a main detector is in an activated state, using the main detector to detect an abnormal position of a power supply input voltage of the integrated circuit; and A pulse detection circuit is used to detect a transition of the power supply input voltage, and an activation indication is transmitted to the main detector in response to the detected transition.

11. The attack detection method according to claim 10, characterized in that: The operation of transmitting the activation indication includes switching the main detector between a low power operation mode and a high speed operation mode, wherein the high speed operation mode has a faster bit detection speed but a higher power consumption than the low power operation mode.

12. The attack detection method according to claim 10, characterized in that: The operation of transmitting the above-mentioned activation indication includes switching the above-mentioned main detector between a disabled operating mode and an activated operating mode.

13. The attack detection method according to claim 10, characterized in that: The operation of transmitting the above-mentioned activation indication includes switching the above-mentioned main detector between a limited function operating mode and a full function operating mode.

14. The attack detection method according to claim 10, characterized in that: The operation of transmitting the activation instruction includes transmitting an increased supply current.

15. The attack detection method according to claim 10, characterized in that: The invention further comprises an input source according to a reference voltage to supply a stable voltage to the main detector.

16. The attack detection method according to claim 15, characterized in that: The invention further comprises utilizing a bandgap reference voltage source to generate the reference voltage.

17. The attack detection method according to claim 10, characterized in that: The operation of detecting the transitions includes detecting a plurality of transitions of the power supply input voltage above a predetermined threshold.

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