State machine control method, electronic device, and chip for integrating event security

Abstract

The embodiments of the present application provide a state machine control method, electronic device, and chip that integrate event safety, and relate to the technical field of the technical field of electronic digital data processing. The method steps include: providing one or more safety matrix modules to output a safety regression condition signal; obtaining a chip system output signal, a chip system enable signal, and a state machine event execution result signal, and causing the safety matrix module to output a corresponding safety regression condition signal according to the result of the logical operation; in response to the safety regression condition signal, causing the state machine to jump or the chip system to enter a safe state. The embodiments of the present application can meet the requirements of the current highest safety level ASIL D certification, realize the design of a safety state machine with a smaller chip area, and integrate the safety of the state machine itself with the safety of the event execution result to generate feedback for calculation and control, thereby enhancing the close relationship between the state machine and event execution.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic digital data processing, and in particular to a state machine control method, electronic device, and chip for integrating event security. Background Art

[0002] With the increasing prevalence of autonomous driving and the improvement of its safety level, system complexity is increasing exponentially, and chip design costs are also rising. Therefore, optimizing design complexity, reducing resources, and optimizing costs while meeting safety levels will be a major technical challenge in the future. State machine design methods often rely on heaping resources and increasing chip area, resulting in a near 1:1 ratio between functional safety measures and functional safety area. This cost is particularly pronounced in complex ASIL D designs.

[0003] A state machine is a mathematical model used to represent a finite number of states and the transitions between them. Related art designs for secure state machines typically modify only the state definition. For example, the bit width of the state definition is doubled, using a Hamming distance = 2 design scheme. However, this simple increase in the state machine bit width introduces issues like common cause failures. If all 6 bits are hit in a given scenario, execution errors will still occur, limiting the improvement in security performance. Related art also employs a shadow state machine as a backup for the main state machine. This isolates the state machine bit width and addresses the common cause failure issue, but it increases resources, especially when the state machine is complex.

[0004] There is currently no effective technical solution to problems such as increasing chip area and resources, which can no longer meet people's requirements and urgently needs to be improved. Summary of the Invention

[0005] The main purpose of the embodiments of the present application is to provide a state machine control method, electronic device, and chip that integrate event security, so as to solve the problem of designing a secure state machine in related technologies by relying solely on stack resources, increasing chip area, and other methods.

[0006] According to one aspect of an embodiment of the present application, a state machine control method for integrating event security is provided, which is applied to chip system detection, including:

[0007] Providing one or more security matrix modules, wherein the security matrix modules are configured to output a security regression condition signal for representing a security state of the chip system;

[0008] Obtaining a chip system output signal, a chip system enable signal, and a state machine event execution result signal, performing a logic operation, and causing the safety matrix module to output a corresponding safety regression condition signal according to the result of the logic operation;

[0009] In response to the safety return condition signal, the state machine jumps from the current state to the next state, or: the chip system enters the safe state and executes corresponding safety measures.

[0010] According to at least one specific embodiment of the embodiments of the present application, the provision of one or more security matrix modules further includes: the security matrix module obtains the chip system output signal, chip system enable signal and state machine event execution result signal through the state machine function module, and the chip system enable signal includes a chip system configuration enable signal, a chip system scan enable signal and a chip system output enable signal.

[0011] According to at least one specific implementation of the embodiments of the present application, when the chip system enable signal is a chip system configuration enable signal, if the chip system output signal and the chip system configuration enable signal are both high levels, the safe return condition signal outputs a high level.

[0012] According to at least one specific implementation of the embodiments of the present application, when the chip system enable signal is a chip system scan enable signal, if the chip system output signal and the chip system scan enable signal are both high level, the safety return condition signal outputs a high level.

[0013] According to at least one specific implementation of the embodiments of the present application, when the state machine event execution result signal is a chip system configuration function completion signal, if the chip system output signal is a high level and the chip system configuration function completion signal is a low level, then the safety return condition signal outputs a high level.

[0014] According to at least one specific implementation of the embodiments of the present application, when the state machine event execution result signal is a chip system configuration function completion signal and a chip system scan function completion signal, if the chip system output signal is a high level and the chip system configuration function completion signal is a low level, then the safety return condition signal outputs a high level, or:

[0015] If the chip system output signal is at a high level, the chip system scan function completion signal is at a low level, and the safety return condition signal outputs a high level.

[0016] According to at least one specific implementation of the embodiments of the present application, the chip system enters a safe state and executes corresponding safety measures, specifically: the chip system enters a safe state, turns off the output, and restarts the configuration of the system cycle state machine.

[0017] A state machine control system for fusion event security, used to implement the state machine control method for fusion event security, comprising:

[0018] A safety matrix module setting unit, configured to provide one or more safety matrix modules, wherein the safety matrix modules are configured to output a safety regression condition signal for representing a safety state of the chip system;

[0019] a signal logic operation unit, configured to obtain a chip system output signal, a chip system enable signal, and a state machine event execution result signal, perform logic operations, and enable the safety matrix module to output a corresponding safety regression condition signal according to the result of the logic operations;

[0020] The safety return condition signal response unit responds to the safety return condition signal to make the state machine jump from the current state to the next state, or: the chip system enters a safe state and executes corresponding safety measures.

[0021] A chip is provided, wherein the state machine control system for fusion event safety is integrated into the chip.

[0022] An electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor executes the state machine control method for fusion event safety.

[0023] The beneficial technical effects of the embodiments of the present application are:

[0024] The embodiments of the present application propose a state machine control method, electronic device, and chip that integrate event safety, which can meet the requirements of the current highest safety level ASIL D certification, implement the design of a safe state machine with a smaller chip area, and integrate the security of the state machine itself with the security of the event execution results to form a highly secure overall solution. The event execution results are used as a feedback quantity of the state machine for calculation and control, thereby enhancing the close relationship between the state machine and event execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the embodiments of the present application or the technical solutions in related technologies, the following will briefly introduce the drawings required for use in the specific implementation methods or related technical descriptions. Obviously, the drawings described below are only some implementation methods of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 It is a principle block diagram of a state machine in the related art;

[0027] Figure 2 State machine principle block diagram for the design of a safety state machine that meets ASIL D requirements;

[0028] Figure 3 This is a flowchart of a state machine control method for integrating event security according to an embodiment of the present application;

[0029] Figure 4 This is an architectural diagram of a state machine control system integrating event security in an embodiment of the present application;

[0030] Figure 5 This is the implementation method of the embodiment of the present application in a specific application scenario;

[0031] Figure 6 It is a structural diagram of an electronic device in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the embodiments of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present application described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] like Figure 1 The principle block diagram of the state machine in the related art is shown. The state machine design method in the related art is mostly implemented by stacking resources and increasing the chip area. The ratio of functional safety measures to functional safety area is close to 1:1, and the cost is particularly prominent in the more complex ASIL D design.

[0035] accomplish Figure 1 The code and description of the state machine of the related technology are as follows:

[0036] always @(posedge clk or negedge rst_n) begin

[0037] if(rst_n == 1'b0) begin

[0038] current_state<=IDLE;

[0039] end

[0040] else begin

[0041] current_state<= next_state;

[0042] end

[0043] end

[0044] The above code describes the state update logic of the state machine. At each rising edge of the clock or falling edge of the reset signal, the state machine updates its current state. If the reset signal is valid (rst_n==1'b0), the state machine sets the current state to IDLE. Otherwise, the state machine updates the current state to the next state.

[0045] State transition code:

[0046] Assuming that Gray coding is not considered, the following five states can be simplified:

[0047] IDLE = 3'b000;

[0048] FUN_A =3'b001;

[0049] FUN_B =3'b010;

[0050] FUN_C =3'b011;

[0051] FUN_SAFE = 3'b100;

[0052] FUN_A performs chip configuration, FUN_B performs chip test scans, FUN_C performs chip outputs, and FUN_SAFE is the safe state, entered when a system error occurs. The states are described as follows: IDLE initialization state, FUN_A performs chip configuration, FUN_B performs chip test scans, and FUN_C performs chip outputs. Testing or configuring the chip while outputs are active can damage the chip. FUN_SAFE is the safe state, entered when a chip system error occurs, such as overtemperature, output error, or configuration error, and all chip functions are disabled.

[0053] Define the following variables:

[0054] current_state current state

[0055] next_state next state

[0056] fun_a_en chip system configuration enable signal

[0057] fun_b_en chip system scan enable signal

[0058] fun_c_en chip system output enable signal

[0059] fun_a_done Chip system configuration function completion signal

[0060] fun_b_done Chip system scan function completion signal

[0061] sys_out chip system output signal

[0062] sys_err system fault signal

[0063] Code example:

[0064] always @(*) begin

[0065] case (current_state)

[0066] IDLE: begin

[0067] next_state = FUN_A;

[0068] end

[0069] FUN_A:

[0070] if(fun_a_done)

[0071] next_state = FUN_B;

[0072] else

[0073] next_state = FUN_A;

[0074] FUN_B:

[0075] if(fun_b_done)

[0076] next_state = FUN_C;

[0077] else

[0078] next_state = FUN_B;

[0079] FUN_C:

[0080] if(sys_err)

[0081] next_state = FUN_SAFE;

[0082] else

[0083] next_state = FUN_C;

[0084] FUN_SAFE:

[0085] if(sys_err)

[0086] next_state = FUN_SAFE;

[0087] else

[0088] next_state = FUN_A;

[0089] default:

[0090] next_state = FUN_SAFE;

[0091] endcase

[0092] end

[0093] The state transitions involved in the above code are described as follows: After entering the system, the chip system is configured. After configuration is complete, the chip is scanned. After the scan is complete, the system starts and begins normal output. If an error occurs, the system enters a safe state, shuts down the output, and restarts the system configuration cycle. The above code describes the state machine's state transition logic. Based on the current state and input conditions, the state machine determines the next state. For example, the IDLE state jumps directly to the FUN_A state, and from the FUN_A state, after configuration is complete, it jumps to the FUN_B state, and so on.

[0094] like Figure 2 As shown, there is another design scheme in the related art that meets the ASIL B safety state machine. This design scheme only changes the state definition part, and other parts such as Figure 1 The state machine design shown in Figure 2 In the safety state machine shown, the bit width of the state definition is doubled. Using the design scheme with Hamming distance = 2, the state machine of this alternative design scheme can be redefined as:

[0095] IDLE = 6'b000000;

[0096] FUN_A =6'b000011;

[0097] FUN_B =6'b001100;

[0098] FUN_C =6'b001111;

[0099] FUN_SAFE = 6'b110000;

[0100] Simply put, this approach increases the state machine bit width, requiring two bits to fail in order to reach the existing state and execute the incorrect behavior. However, this simple increase in the state machine bit width poses common cause failures (CFFs). Even if all six bits are hit in a given scenario, the incorrect behavior can still occur. Therefore, this approach is considered a medium-to-high safety state machine design method, resolving approximately 90% of errors caused by traditional state machine erroneous jumps. ASIL D designs require resolving approximately 99% of errors caused by traditional state machine erroneous jumps. Increasing the bit width offers limited safety improvements and falls short of these requirements.

[0101] In this technical solution, the State_err signal is described as outputting an error signal when a state comparison error occurs. When an error occurs, the state is placed in a safe state. The code is briefly described as follows:

[0102] always @(posedge clk or negedge rst_n) begin

[0103] if(rst_n == 1'b0) begin

[0104] current_state<=IDLE;

[0105] end

[0106] else begin

[0107] if(State_err)

[0108] current_state<= FUN_SAFE;

[0109] else

[0110] current_state<= next_state;

[0111] end

[0112] end

[0113] This state machine design uses a shadow state machine to back up the main state machine. The main state machine can be designed using an ASIL B design, while the shadow state machine can be designed using traditional state machine methods. This solution further isolates the state machine bit width, addressing common cause failures. It can be considered to address approximately 99% of errors caused by erroneous jumps in traditional state machines, meeting ASIL D requirements. However, due to the backup state machine, this solution increases resources by more than half of those of an ASIL B-compliant state machine (0.5 state machine bit width resources + combinational logic resources). This significant resource increase is significant when the state machine is complex, and still cannot meet user requirements.

[0114] like Figure 3 As shown, the embodiment of the present application discloses a state machine control method for integrating event security, including the following steps:

[0115] Step S1 provides one or more safety matrix modules, Safe_matrix, configured to output a safe return condition signal representing the safe state of the chip system. Step S1 differs from related art in that one or more safety matrix modules are added to the state machine control process. The safety matrix module Safe_matrix can output a safe return condition signal, which is used to map the chip system's state error jump to the safe return condition signal.

[0116] Step S2: Obtain the chip system output signal, the chip system enable signal, and the state machine event execution result signal, perform a logical operation, and, based on the result of the logical operation, cause the safety matrix module Safe_matrix to output a corresponding safety return condition signal. In step S2, the corresponding safety return condition signal is generated by performing a logical operation on the chip system output signal, the chip system enable signal, and the state machine event execution result signal. The event result feedback of the state machine execution is used as the input condition of the state machine. The state machine control, execution result, and key system identification signals (such as various all-purpose signals) are all used as input quantities for logical judgment in the safety matrix module Safe_matrix. The state machine security and event security are considered as one, and the event execution result is used as feedback to the state machine. This enhances the close relationship between the state machine and event execution, and integrates the security of the state machine itself with the results of the execution event.

[0117] In step S3, in response to the safety return condition signal, the state machine jumps from the current state to the next state, or the chip system enters a safe state and executes corresponding safety measures. For example, the safety measures in step S3 may include entering the safe state, shutting down the output, and reconfiguring the system cycle state machine.

[0118] The technical solution provided by steps S1 to S3 links the security control of the state machine with the event execution results by introducing the safety matrix module Safe_matrix, forming a closed-loop safety control system, ensuring that each part of the system is under the control of a safe state, improving the reliability and stability of the system, and the closed-loop safety control system and method can quickly implement safety measures when a chip system fails, reducing the damage and maintenance costs caused by the chip system due to failure problems. The safety matrix module Safe_matrix can perform logical operations based on the output signal, enable signal and state machine event execution result signal of the chip system, output a safety return condition signal, and safely jump the state machine from the current state to the next state, or make the chip system enter a safe state and execute corresponding safety measures. Compared with the states in which state machine security and event security are usually handled separately in the related art, the embodiment of the present application combines the two into one, simplifies the design logic, reduces the number of safety mechanisms that need to be handled separately, thereby reducing the design complexity, achieving an optimized design, reducing the required hardware resources, and thus reducing the chip area. When the state machine is relatively complex, the increase in resources is far less than that of the related art.

[0119] Preferably, one or more safety matrix modules Safe_matrix are provided in step S1, and the safety matrix module obtains the chip system output signal sys_out, the chip system enable signal and the state machine event execution result signal through the state machine function module.

[0120] Preferably, in step S2, the chip system enable signal includes a chip system configuration enable signal fun_a_en, a chip system scan enable signal fun_b_en, and a chip system output enable signal fun_c_en; the state machine event execution result signal includes a chip system configuration function completion signal fun_a_done and a chip system scan function completion signal fun_b_done. By performing logical operations on the above configuration enable signals and function complete signals, a corresponding safe return condition signal safe_return can be generated. For example:

[0121] Step S21: When the chip system enable signal is the chip system configuration enable signal fun_a_en, if the chip system output signal sys_out and the chip system configuration enable signal fun_a_en are both high, then the safe return condition signal Safe_return outputs a high level, or:

[0122] Step S22: When the chip system enable signal is the chip system scan enable signal fun_b_en, if the chip system output signal sys_out and the chip system scan enable signal fun_b_en are both high, then the safe return condition signal Safe_return outputs a high level, or:

[0123] Step S23: When the state machine event execution result signal is the chip system configuration function completion signal fun_a_done, if the chip system output signal sys_out is high and the chip system configuration function completion signal fun_a_done is low, then the safe return condition signal Safe_return outputs a high level, or:

[0124] Step S24: When the state machine event execution result signal is the chip system configuration function completion signal fun_a_done and the chip system scan function completion signal fun_b_done, if the chip system output signal sys_out is high and the chip system configuration function completion signal fun_a_done is low, then the safe return condition signal Safe_return outputs a high level, or:

[0125] Step S25 , if the chip system output signal sys_out is at a high level, the chip system scan function completion signal fun_b_done is at a low level, and the safety return condition signal Safe_return outputs a high level.

[0126] The optimization technical solution provided in steps S21 to S25 can perform logical operations based on the chip system configuration enable signal fun_a_en, the chip system scan enable signal fun_b_en, the chip system output enable signal fun_c_en, the chip system configuration function completion signal fun_a_done, and the chip system scan function completion signal fun_b_done to obtain the corresponding safety return condition signal Safe_return, map the chip system status error jump to the safety return condition signal Safe_return, and also feed back the event execution results ignored by the related technology as the input quantity of the state machine.

[0127] For the method steps disclosed in the above embodiments, for the purpose of simple description, the method steps are expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present application are not limited to the order of the actions described, and some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present application.

[0128] Any process or method description described in a flowchart or other manner can be understood as: a module, fragment or part of a code that includes one or more executable instructions for implementing a specific logical function or process step, and the scope of the preferred implementation of the embodiments of the present application includes alternative implementations, which may not be in the order shown or discussed, including executing and implementing functions in a substantially simultaneous manner or in the opposite order according to the functions involved, or executing computer instructions and implementing corresponding functions according to program structures such as loops and branches, which can naturally be understood by those skilled in the art when implementing the embodiments of the present application.

[0129] like Figure 4 As shown, the embodiment of the present application further provides a state machine control system integrating event security, which is used to implement the specific implementation of any one of the embodiments of the present application, including:

[0130] A safety matrix module setting unit, configured to provide one or more safety matrix modules, wherein the safety matrix modules are configured to output a safety regression condition signal for representing a safety state of the chip system;

[0131] a signal logic operation unit, configured to obtain a chip system output signal, a chip system enable signal, and a state machine event execution result signal, perform logic operations, and enable the safety matrix module to output a corresponding safety regression condition signal according to the result of the logic operations;

[0132] The safety return condition signal response unit responds to the safety return condition signal to make the state machine jump from the current state to the next state, or: the chip system enters a safe state and executes corresponding safety measures.

[0133] The embodiments of the system described above are merely illustrative. For example, the various functional modules, units, or subsystems in the system may or may not be physically separate, or may or may not be physical units, that is, they may be located in the same place or distributed across multiple different systems and their subsystems or modules. Those skilled in the art may select some or all of the functional modules, units, or subsystems according to actual needs to achieve the purpose of the embodiments of the present application. For the above-mentioned situations, those of ordinary skill in the art can understand and implement them without inventive work.

[0134] like Figure 5 As shown, Figure 5 The figure shows the implementation of the embodiment of the present application in a specific application scenario, including: IDLE initialization state, FUN_A executing chip configuration function, FUN_B executing chip test scan function, FUN_C executing chip external output function, safe state FUN_SAFE, state machine function module Function, based on the relevant technology, one or more safety matrix modules Safe_matrix are added, and the logical description function of the safety matrix module Safe_matrix is ​​as follows:

[0135] When the detection chip system output signal sys_out is equal to 1 and the chip system configuration enable signal fun_a_en is 1, the output safety return condition signal Safe_return=1.

[0136] When the detection chip system output signal sys_out is equal to 1 and the chip system scan enable signal fun_b_en is 1, the safe return condition signal Safe_return=1 is output.

[0137] When the chip system scan enable signal fun_b_en is equal to 1 and the chip system configuration function completion signal fun_a_done is 0, the safe return condition signal Safe_return=1 is output.

[0138] When the chip system output signal sys_out is equal to 1 and the chip system configuration function completion signal fun_a_done or the chip system scan function completion signal fun_b_done is 0, the safety return condition signal Safe_return=1 is output.

[0139] The use of the output safety return condition signal Safe_return can refer to the following code. When it is equal to 1, the state is set to a safe state:

[0140] always @(posedge clk or negedge rst_n) begin

[0141] if(rst_n == 1'b0) begin

[0142] current_state<=IDLE;

[0143] end

[0144] else begin

[0145] if(Safe_return)

[0146] current_state<= FUN_SAFE;

[0147] else

[0148] current_state<= next_state;

[0149] end

[0150] end

[0151] In this specific implementation, the state machine control method for integrating event safety treats the state machine function module as a white box, fully utilizing the dependencies between the events of the state machine function module to map state error jumps to Safe_return (safe return condition signal). The logic is relatively simple and does not require judgment on all states. It only requires judgment on some states that are dependent or mutually exclusive. The safety portion of the state machine control method for integrating event safety includes not only the state machine control itself, but also the safety of the state machine execution results, achieving closed-loop control of the chip system output signal, chip system enable signal, state machine event execution result signal, and safe return condition signal. When the state machine is complex, its resource increase is far less than half of the resources of (state machine that meets ASIL B).

[0152] The specific implementation method described here can be applied to the field of automotive functional safety (ASIL D level). The state machine function module is responsible for handling specific functions in the state machine. In the state machine, dependencies may exist between different events, meaning that the occurrence of one event may affect whether or how another event occurs. By providing feedback on these trust relationships and event execution results as input, the design of the state machine can be simplified, unnecessary state judgments can be reduced, and the safety of the chip system can be ensured through the safety return condition signal Safe_return. This forms a closed-loop control, monitors the output results of the state machine, and adjusts the input parameters based on the difference between the actual output and the expected output. This not only focuses on the state transition itself, but also considers the safety of the execution results, forming a complete control loop. Therefore, even if the state machine becomes complex, the required hardware resources increase is far less than half of the resources required by traditional state machines that meet the ASIL B standard, achieving more efficient resource utilization while maintaining high performance. To sum up, the specific implementation method provided in the embodiments of the present application provides an efficient and secure state machine design method, which is suitable for application in the functional safety field of the automotive industry. By treating the state machine functional module as a white box, making full use of the dependencies between events, and introducing safe regression conditions, the chip system complexity and resource consumption can be effectively reduced, while ensuring that the entire process forms a closed-loop control, thereby improving the reliability and safety of the system.

[0153] like Figure 6 As shown, the embodiment of the present application provides a state machine control method and system for integrating event security, and also provides corresponding chips and electronic devices:

[0154] A chip integrates a state machine control system for fusion event security, and is used to implement a state machine control method for fusion event security.

[0155] An electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to cause the at least one processor to perform the state machine control method for fusion event safety described in any specific embodiment of the present application. The electronic device includes one or more processors 51 and a memory 52. Figure 6 A processor 51 is taken as an example.

[0156] The controller may further include an input device 53 and an output device 54 .

[0157] The processor 51, the memory 52, the input device 53 and the output device 54 may be connected via a bus or other means. Figure 6The bus connection is taken as an example.

[0158] The processor 51 may be a central processing unit (CPU), or other general-purpose processors, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above chips. The general-purpose processor may be a microprocessor or any conventional processor.

[0159] Memory 52, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as the program instructions / modules corresponding to the control method in the embodiments of the present application. Processor 51 executes the non-transitory software programs, instructions, and modules stored in memory 52 to execute various server functional applications and data processing, thereby implementing the aforementioned state machine control method for fusion event security.

[0160] The memory 52 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the processing device operated by the server, etc. In addition, the memory 52 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 52 may optionally include a memory remotely located relative to the processor 51, and these remote memories may be connected to a network connection device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0161] The input device 53 can receive input digital or character information and generate key signal input related to user settings and function control of the processing device of the server. The output device 54 can include a display device such as a display screen.

[0162] One or more modules are stored in the memory 52 , and when executed by one or more processors 51 , perform the state machine control method for fusion event safety.

[0163] Those skilled in the art will appreciate that all or part of the processes in the above method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes in the above method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (FM), a hard disk drive (HDD), or a solid-state drive (SSD). The storage medium can also include a combination of the above types of memory.

[0164] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art in the technical field to which the embodiments of the present application belong. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless specifically defined, will not be interpreted in an idealized or overly formal sense.

[0165] It should be noted that certain terms are used in the description and claims of the embodiments of this application to refer to specific components. Those skilled in the art will understand that different manufacturers and suppliers may use different terms to refer to the same component. The description and claims do not distinguish components based on differences in terms, but rather on differences in their functions.

[0166] Furthermore, those skilled in the art will appreciate that although some embodiments described herein include certain features that are included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, any one of the embodiments claimed in the claims may be used in any combination in the embodiments of this application.

[0167] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0168] In addition, the technical solutions between the various specific implementation methods of the embodiments of the present application can be combined with each other, but they must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0169] Although the implementation methods of the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the embodiments of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A state machine control method integrating event security, applied to chip system detection, characterized in that: include: One or more safety matrix modules are provided, each configured to output a safety regression condition signal for representing the safety state of the chip system, and to map a state error jump of the chip system to the safety regression condition signal. Specifically, the safety matrix module maps the state error jump to the safety regression condition signal by utilizing the dependency relationship between events of the state machine function module; monitors the output result of the state machine through the safety regression condition signal, and adjusts the input parameters according to the difference between the actual output and the expected output; Obtaining a chip system output signal, a chip system enable signal, and a state machine event execution result signal, performing a logic operation, and causing the safety matrix module to output a corresponding safety regression condition signal according to the result of the logic operation, further comprising: the safety matrix module obtaining the chip system output signal, the chip system enable signal, and the state machine event execution result signal through a state machine function module, wherein the chip system enable signal includes a chip system configuration enable signal, a chip system scan enable signal, and a chip system output enable signal; By performing logical operations on the chip system output signal, the chip system enable signal, and the state machine event execution result signal, a corresponding safety regression condition signal is generated, and the event result feedback of the state machine execution is used as the input condition of the state machine; In response to the safety return condition signal, the state machine jumps from the current state to the next state, or: the chip system enters the safe state and executes corresponding safety measures, specifically: the chip system enters the safe state, turns off the output, and restarts the configuration system cycle state machine.

2. The state machine control method for fusion event security according to claim 1, characterized in that: When the chip system enable signal is a chip system configuration enable signal, if the chip system output signal and the chip system configuration enable signal are both high level, the safety return condition signal outputs a high level.

3. The state machine control method for fusion event security according to claim 1, characterized in that: When the chip system enable signal is a chip system scan enable signal, if the chip system output signal and the chip system scan enable signal are both high level, the safety return condition signal outputs a high level.

4. The state machine control method for fusion event security according to claim 1, characterized in that: When the state machine event execution result signal is a chip system configuration function completion signal, if the chip system output signal is high and the chip system configuration function completion signal is low, the safety return condition signal outputs a high level.

5. The state machine control method for fusion event security according to claim 1, characterized in that: When the state machine event execution result signal is a chip system configuration function completion signal and a chip system scan function completion signal, if the chip system output signal is high and the chip system configuration function completion signal is low, then the safety return condition signal outputs a high level, or: If the chip system output signal is at a high level, the chip system scan function completion signal is at a low level, and the safety return condition signal outputs a high level.

6. A state machine control system for fusion event safety, used to implement the state machine control method for fusion event safety according to any one of claims 1 to 5, characterized in that: include: A safety matrix module setting unit is configured to provide one or more safety matrix modules, wherein the safety matrix modules are configured to output a safety regression condition signal for representing the safety state of the chip system, and to map the state error jump of the chip system to the safety regression condition signal, specifically by: utilizing the dependency relationship between the events of the state machine function module to map the state error jump to the safety regression condition signal; monitoring the output result of the state machine through the safety regression condition signal, and adjusting the input parameters according to the difference between the actual output and the expected output; A signal logic operation unit is used to obtain a chip system output signal, a chip system enable signal, and a state machine event execution result signal, perform a logic operation, and enable the safety matrix module to output a corresponding safety regression condition signal according to the result of the logic operation, further comprising: the safety matrix module obtains the chip system output signal, the chip system enable signal, and the state machine event execution result signal through the state machine function module, the chip system enable signal including a chip system configuration enable signal, a chip system scan enable signal, and a chip system output enable signal; By performing logical operations on the chip system output signal, the chip system enable signal, and the state machine event execution result signal, a corresponding safety regression condition signal is generated, and the event result feedback of the state machine execution is used as the input condition of the state machine; The safety regression condition signal response unit responds to the safety regression condition signal to make the state machine jump from the current state to the next state, or: the chip system enters the safe state and executes corresponding safety measures, specifically: the chip system enters the safe state, turns off the output, and restarts the configuration of the system cycle state machine.

7. A chip, characterized in that: The chip integrates the state machine control system for fusion event safety according to claim 6.

8. An electronic device, characterized in that: The electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor executes the state machine control method for fusion event safety described in any one of claims 1 to 5.

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