Cache verification platform and method and related equipment

Abstract

The embodiment of the invention provides a cache verification platform, a cache verification method and related equipment, the cache verification platform is used for verifying cache design, the cache design comprises data storage logic, core control logic and routing logic which are mutually independent, and the data storage logic, the core control logic and the routing logic are mutually independent. The cache verification platform is used for associating association logic of the data storage logic, the core control logic and the routing logic, and comprises a storage logic verification module used for verifying the data storage logic in the cache design; the core control verification module is used for verifying core control logic in the cache design; the routing verification module is used for verifying the core control logic in the cache design and the routing logic of the upstream module or the downstream module; and the cache verification module is used for verifying a cache design obtained after the association logic is associated with the data storage logic, the core control logic and the routing logic. The cache verification scheme enables sufficient verification of the cache.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuit design and manufacturing, and specifically to a cache verification platform, method and related equipment. Background Art

[0002] The cache is a temporary storage component set up inside the CPU (central processing unit). It is used to temporarily store memory data that the processor core needs to read / write, and to save memory data that is frequently read by the processor core as much as possible to reduce data access delays and improve the overall performance of the system.

[0003] In the cache, multiple mechanisms are usually configured to implement the cache function and improve data processing efficiency. For example, a data consistency mechanism is configured to ensure that the data in the cache is consistent with the data in the memory; a data replacement mechanism is configured to ensure that the data frequently used by the processor core is retained in the cache under the premise of limited cache capacity, and the data that is not frequently used by the processor core is removed.

[0004] As cache capacity increases and the corresponding configuration mechanism becomes more and more complex, the cache structure becomes more and more complex. Accordingly, it is becoming increasingly difficult to fully verify the cache during the chip design phase. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a cache verification platform, method and related devices, wherein the cache verification scheme can achieve full verification of the cache.

[0006] An embodiment of the present invention provides a cache verification platform for verifying a cache design, wherein the cache design includes mutually independent data storage logic, core control logic, and routing logic, and association logic for associating the data storage logic, core control logic, and routing logic, and the cache verification platform includes:

[0007] A storage logic verification module, used to verify the data storage logic in the cache design;

[0008] A core control verification module, used to verify the core control logic in the cache design;

[0009] A routing verification module, used to verify the routing logic of the core control logic and the upstream module or the downstream module in the cache design;

[0010] The cache verification module is used to verify the cache design obtained after the association logic is associated with the data storage logic, the core control logic and the routing logic.

[0011] Optionally, the cache verification platform further includes:

[0012] The preloading module is used to preload initial data for the data storage logic, wherein the initial data is preset data or random data, and the location where the initial data is loaded in the data storage logic is a preset location or a random location.

[0013] Optionally, the preloading module is also used to load error points, and / or, the preloading module is also used to fix the potential of preset points in the data storage logic to simulate a test scenario in which a device bad point exists in the data storage logic.

[0014] Optionally, the storage logic verification module includes a memory access function verification module and a logic control verification module, the memory access function verification module is used to verify the memory access function of the data storage logic, and the logic control verification module is used to verify the logic control function in the data storage logic;

[0015] The data storage logic includes a plurality of data storage units, and the memory access function verification module is used to verify the data storage units.

[0016] Optionally, the storage logic verification module further includes a storage logic driving module, and the storage logic driving module is used to drive a test stimulus for verifying the data storage logic, so that the data storage logic executes corresponding logic based on the test stimulus.

[0017] Optionally, the storage logic verification module also includes a first monitoring module for monitoring the data storage logic, the first monitoring module including a first monitor, and a first scoreboard and a first coverage calculation unit connected to the first monitor, the first monitor being used to monitor first result information output by the data storage logic based on a test stimulus, the first scoreboard being used to determine a verification result based on the first result information, and the first coverage calculation unit being used to calculate the coverage of the verification run on the data storage logic based on the first result information.

[0018] Optionally, the routing verification module includes a data transmission verification module and an arbitration mechanism verification module, the data transmission verification module is used to verify the data transmission function of the routing logic; the arbitration mechanism verification module is used to verify the arbitration mechanism of the routing logic.

[0019] Optionally, the routing verification module includes a second monitoring module for monitoring the routing logic, the second monitoring module includes a second monitor, and a second scoreboard and a second coverage calculation unit connected to the second monitor, the second monitor is used to monitor second result information output by the routing logic based on a test stimulus, the second scoreboard is used to determine a verification result based on the second result information, and the second coverage calculation unit is used to calculate the coverage of the verification running on the routing logic based on the second result information.

[0020] Optionally, the core control verification module includes a pipeline verification module and a data consistency verification module, wherein the pipeline verification module is used to verify the pipeline processing flow in the core control logic; the data consistency verification module is used to verify the data consistency mechanism in the core control logic;

[0021] Among them, the pipeline verification module is used to verify the pipeline processing flow in the core control logic, specifically, based on the control of the clock cycle, running the test case used to generate the conflict event; the conflict event is one or more of the index conflict, address conflict and resource conflict; the test case takes the first preset number of clock cycles as a cycle, and periodically generates the second preset number of conflict events, and the first preset number and the second preset number are both integers greater than or equal to 1.

[0022] Optionally, the pipeline verification module also monitors RTL information of the cache design in the pipeline verification process.

[0023] Optionally, a cache simulation model and a consistency monitor are pre-built in the data consistency verification module;

[0024] The cache simulation model receives the same access request synchronously with the core control logic, and updates the data based on the access request; the consistency monitor is used to determine whether the updated data in the cache design is accurate based on the data in the cache simulation model;

[0025] The data consistency verification module is also used to obtain an access request sent by the output end of the core control logic to the downstream module, and determine whether the access request complies with the data consistency mechanism.

[0026] Optionally, the cache verification module includes a cache verification association module and the storage logic verification module, the core control verification module and the routing verification module embedded in the cache verification association module;

[0027] The core control verification module reuses the first monitoring module in the storage logic verification module and the second monitoring module in the routing verification module.

[0028] The embodiment of the present invention also provides a cache verification method, including:

[0029] Splitting the cache design into mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic;

[0030] Verifying the data storage logic, core control logic and routing logic respectively;

[0031] After the data storage logic, core control logic and routing logic are verified, the cache design is verified.

[0032] Optionally, before respectively verifying the data storage logic, the core control logic, and the routing logic, the method further includes:

[0033] Preload initial data for the data storage logic, the initial data is preset data or random data, and the location where the initial data is loaded by the data storage logic is a preset location or a random location.

[0034] Optionally, in the step of preloading initial data for the data storage logic, error points are also loaded for the data storage logic, and / or the potentials of preset points in the data storage logic are fixed to simulate a test scenario in which device bad points exist in the data storage logic.

[0035] Optionally, the verification of the core control logic includes:

[0036] Verify the pipeline processing flow in the core control logic; and verify the data consistency mechanism in the core control logic;

[0037] Among them, the pipeline processing flow in the core control logic is verified, specifically, based on the control of the clock cycle, running a test case for generating a conflict event; the conflict event is one or more of an index conflict and an address conflict; the test case takes a first preset number of clock cycles as a cycle, and periodically generates a second preset number of conflict events, and the first preset number and the second preset number are both integers greater than or equal to 1.

[0038] An embodiment of the present invention provides an electronic device, which is configured as a cache verification platform as described in the embodiment of the present invention.

[0039] An embodiment of the present invention provides a storage medium, wherein the storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the cache verification method according to the embodiment of the present invention is implemented.

[0040] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0041] An embodiment of the present invention provides a cache verification platform, method and related equipment, wherein the cache design includes mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic, and the cache verification platform includes: a storage logic verification module, used to verify the data storage logic in the cache design; a core control verification module, used to verify the core control logic in the cache design; a routing verification module, used to verify the routing logic between the core control logic in the cache design and an upstream module or a downstream module; a cache verification module, used to verify the cache design obtained after the association logic associates the data storage logic, core control logic and routing logic.

[0042] It can be seen that the cache verification scheme described in the embodiment of the present invention aims at the independent data storage logic, core control logic and routing logic in the cache, verifies each functional logic based on different verification modules respectively, and then verifies the cache design as a whole, thereby achieving full verification of the cache design. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0044] Figure 1 A schematic diagram of an optional structure of a cache verification platform provided by an embodiment of the present invention;

[0045] Figure 2 A schematic diagram of an optional structure of a storage logic verification module provided by an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of another optional structure of the cache verification platform provided by an embodiment of the present invention;

[0047] Figure 4 A schematic diagram of an optional structure of a routing verification module provided in an embodiment of the present invention;

[0048] Figure 5 An optional structural diagram of a core control verification module provided by an embodiment of the present invention;

[0049] Figure 6 A schematic diagram of an optional structure of a cache verification module provided in an embodiment of the present invention;

[0050] Figure 7A schematic diagram of another optional structure of the cache verification module provided in an embodiment of the present invention;

[0051] Figure 8 A schematic diagram of an optional flow chart of a cache verification method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] As described in the background art, as the cache capacity increases and the corresponding configuration mechanism becomes more and more complex, the cache structure becomes more and more complex. Accordingly, it becomes increasingly difficult to fully verify the cache during the chip design phase.

[0054] The inventors noticed that in the existing cache verification methods, the conventional idea is to verify the cache as a whole, that is, to verify the overall logic in the cache to confirm its processing effect on the data. The inventors believe that this method is difficult to achieve sufficient verification of the cache. After analysis, the inventors believe that based on the processing logic of the cache itself, the corresponding functions in the cache are affected by its own logic, which leads to the limitation of its corresponding verification. For example, when verifying the storage function of the cache, the cache’s own data error correction mechanism may affect the verification of its storage function. In other words, when verifying whether the stored data is accurate, even if the result is that the data is accurate, it cannot be determined whether the corresponding result is generated by the correct storage of the cache’s own data, or is generated after error correction based on the data error correction mechanism.

[0055] In view of this, an embodiment of the present invention provides a cache verification scheme, in which the independent data storage logic, core control logic and routing logic in the cache design are verified by verifying each functional logic based on different verification modules respectively, and then the cache design is verified as a whole, thereby achieving full verification of the cache design.

[0056] In order to better understand the solution provided by the embodiment of the present invention, the specific content of the cache verification solution provided by the embodiment of the present invention is further explained below.

[0057] In an embodiment of the present invention, a cache verification platform is provided, which is used to verify cache design, wherein the cache design includes mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic.

[0058] It can be understood that the cache can be divided into a first-level cache, a second-level cache, and a third-level cache, etc. In an embodiment of the present invention, the cache design can be a cache at any level, for example, it can be a last-level cache (LLC, Last Level Cache, that is, the bottom-level cache. When there is a second-level cache, the last-level cache can be a second-level cache, and when there is a third-level cache, the last-level cache can be a third-level cache). The function based on the last-level cache is more complex than that of other levels of cache. Therefore, the verification platform that adapts to the last-level cache can also be applicable to other levels of cache.

[0059] refer to Figure 1 An optional structural diagram of a cache verification platform is shown, including: a storage logic verification module 110, a core control verification module 120, a routing verification module 130 and a cache verification module 140. The storage logic verification module 110 is used to verify the data storage logic in the cache design; the core control verification module 120 is used to verify the core control logic in the cache design; the routing verification module 130 is used to verify the routing logic of the core control logic and the upstream module or downstream module in the cache design; the cache verification module 140 is used to verify the cache design obtained after the association logic associates the data storage logic, the core control logic and the routing logic.

[0060] The storage logic verification module 110 is used to verify the data storage logic in the cache design.

[0061] In the optional example, refer to Figure 2 An optional structural diagram of a storage logic verification module is shown, and the storage logic verification module may include a memory access function verification module 111 and a logic control verification module 112, wherein the memory access function verification module 111 is used to verify the memory access function of the data storage logic, and the logic control verification module 112 is used to verify the logic control function in the data storage logic.

[0062] It can be understood that the basic functions of the data storage logic can be verified through the memory access function verification module 111 and the logic control verification module 112.

[0063] Among them, in some optional examples, the data storage logic includes multiple data storage units, for example, the SRAM (Static Random-Access Memory) storage logic may include multiple SRAMMacro storage units, and the memory access function verification module 111 is used to verify the data storage unit, for example, verifying the storage function of the data storage unit one by one, performing random read and write verification on the data storage unit, and repeatedly reading and writing verification on a specific data storage unit.

[0064] In a further example, the storage logic verification module further includes a storage logic driving module 113, and the storage logic driving module 113 is used to drive a test stimulus for verifying the data storage logic, so that the data storage logic executes corresponding logic based on the test stimulus.

[0065] It should be noted that in the scenario of performing overall verification on the cache in a conventional manner, the overall verification can only be performed after the core control logic is driven, and the core control logic generates corresponding test stimuli. However, based on the constraints in the core control logic, the test stimuli generated by it can only be a subset of the data storage constraints, and it cannot provide comprehensive and sufficient test stimuli. In comparison, the embodiment of the present invention drives the test stimuli of the data storage logic based on an independent storage logic driver module, and can provide the data storage logic with test stimuli that are not constrained by the core control logic and are only fully verified for the data storage logic, so that random stimuli can be given without driving constraints to verify the read and write correctness of the data storage logic.

[0066] In a further example, the storage logic verification module may also include a first monitoring module 114 for monitoring the data storage logic, the first monitoring module 114 including a first monitor, and a first scoreboard and a first coverage calculation unit connected to the first monitor, the first monitor being used to monitor first result information output by the data storage logic based on a test stimulus, the first scoreboard being used to determine a verification result based on the first result information, and the first coverage calculation unit being used to calculate the coverage of the verification run on the data storage logic based on the first result information.

[0067] It should be further explained that the embodiment of the present invention provides a cache verification platform, which can implement separate verification of data storage logic based on a storage logic verification module, thereby specifically discovering defects (such as bugs) that may occur in the data storage logic.

[0068] In a further alternative example, reference Figure 3Another optional structural diagram of the cache verification platform is shown. The cache verification platform of the embodiment of the present invention may further include a preloading module 150 for preloading initial data for the data storage logic.

[0069] During the cache verification process, the initial data is preloaded through the preloading module to simulate the test scenario of the data storage logic when the initial data exists. It is understandable that the initial data is different based on different test scenarios. In the scenario where the cache is verified as a whole in the conventional way, it is necessary to drive the core control logic to load the initial data. Under the premise that the core control logic has not been verified to accurately implement its preset function, whether the corresponding initial data is loaded and whether it is accurately loaded obviously carries great uncertainty. In comparison, the preloading module of the embodiment of the present invention can realize the accurate loading of the initial data, eliminating the uncertainty of the conventional method.

[0070] Among them, the initial data preloaded by the preloading module described in the embodiment of the present invention for the data storage logic can be preset data or random data, and the location where the initial data is loaded in the data storage logic can be a preset location or a random location.

[0071] It is understandable that in the scenario of performing overall verification on the cache in a conventional manner, it is necessary to drive the core control logic to load the initial data, so that the corresponding initial data also needs to meet the constraints in the core control logic. Obviously, the initial data preloaded by the preloading module described in the embodiment of the present invention may not be constrained by the core control logic, so that the preloading of preset data or random data can be achieved; or, the loading of preset locations or random locations can be achieved, for example, the verification environment randomly selects the initial data, or the verification environment randomly selects the write location, etc.

[0072] At the same time, in an embodiment of the present invention, the preloading module can also preload error points (i.e., error bit points) to simulate the test scenario of data storage logic when there are device bad points (such as error points) (for example, illegal data can be randomly injected).

[0073] It is understandable that in the conventional scenario of overall verification of the cache, it is necessary to drive the core control logic to load the initial data, and the core control logic is usually configured with an automatic error correction function, which makes it difficult to implement verification testing in scenarios where error points exist. In contrast, the preloading module of the embodiment of the present invention can load the error points and fully verify the data storage logic in the cache.

[0074] Meanwhile, in the embodiment of the present invention, the preloading module may also fix the potential of a preset point (ie, bit point) in the data storage logic to simulate a test scenario in which the data storage logic has a device defect.

[0075] It can be understood that the potential of the preset point (i.e., bit point) in the fixed data storage logic is used to ensure that the preset point in the data storage logic is always at the preset point, which is expressed as a fixed value at the data level. In the scenario where the cache is verified as a whole in a conventional manner, the scenario simulation of a device bad point is obviously difficult to achieve. The embodiment of the present invention can achieve the simulation of such a scenario by preloading (such a scenario is also called brute force verification).

[0076] In a specific example, the preloading module can write initial data to the data storage logic through a backdoor method.

[0077] The preloading module in the embodiment of the present invention can realize flexible loading of initial data, thereby greatly shortening the verification time and enriching the verification scenarios.

[0078] Continue to refer Figure 1 The routing verification module 130 is used to verify the routing logic between the core control logic and the upstream module or the downstream module in the cache design.

[0079] In the cache design, the routing logic is used to transmit requests sent to or from the core control logic and determine the order in which the requests are sent based on a preset arbitration mechanism.

[0080] Specifically, the routing logic sends the request sent by the upstream module to the core control logic, and further sends the request issued by the core control logic to the downstream module. The routing logic includes an input port and an output port, the input port is used to input the request sent by the upstream module or the request issued by the core control logic, and the output port is used to output the request sent by the upstream module to the core control logic or output the request issued by the core control logic to the corresponding interface of the downstream module.

[0081] Accordingly, in the embodiments of the present invention, reference is made to Figure 4The optional structural diagram of the routing verification module shown in the figure may include a data transmission verification module 131 for verifying the data transmission function of the routing logic. In the optional example, the data accuracy of the request transmitted by the routing logic can be verified, that is, whether the data transmitted from the input port to the output port is accurate; the data transmission efficiency and transmission quality of the routing logic can also be verified, that is, the number of data transmissions transmitted from the input port to the output port in a preset time period, and whether there is packet loss or multiple packets; the delay of the routing logic can also be verified, that is, the amount of data delay transmitted from the input port to the output port is determined.

[0082] In a further example, the routing verification module may also include an arbitration mechanism verification module 132 for verifying the arbitration mechanism configured in the routing logic, such as whether the transmission order of data satisfies the preset arbitration mechanism when multiple data are transmitted from the input port to the output port.

[0083] In a further optional example, the routing verification module may further include a routing driving module 133 for driving a test stimulus for verifying the routing logic, so that the routing logic executes corresponding logic based on the test stimulus.

[0084] In a further example, the routing verification module may also include a second monitoring module 134 for monitoring the routing logic, the second monitoring module including a second monitor, and a second scoreboard and a second coverage calculation unit connected to the second monitor, the second monitor being used to monitor second result information output by the routing logic based on a test stimulus, the second scoreboard being used to determine a verification result based on the second result information, and the second coverage calculation unit being used to calculate the coverage of the verification running on the routing logic based on the second result information.

[0085] It is understandable that by independently verifying the routing logic based on the embodiment of the present invention, sufficient verification from various angles can be achieved without being affected by the overall logical constraints of the cache.

[0086] Continue to refer Figure 1 The core control verification module 120 is used to verify the core control logic in the cache design.

[0087] In the cache design, the core control logic is used to process the requests received at the input end in a pipeline-based manner to access the memory data corresponding to the request and maintain the data consistency in the cache and in the memory to ensure that the modified data is not lost.

[0088] Accordingly, reference Figure 5The optional structural diagram of the core control verification module shown in FIG. 1 , the core control verification module may include a pipeline verification module 121 and a data consistency verification module 122, wherein the pipeline verification module 121 is used to verify the pipeline processing flow in the core control logic; the data consistency verification module 122 is used to verify the data consistency mechanism in the core control logic;

[0089] Through the pipeline verification module and data consistency verification module, the basic functions of the core control logic can be verified.

[0090] In the cache, pipeline flow control is one of the basic functions of the core control logic in the cache. In an optional example, the pipeline process is executed based on a preset data replacement mechanism. The pipeline verification module can verify the pipeline flow control of the core control logic based on the conflict detection method. Specifically, based on the control of the clock cycle, a test case for generating a conflict event can be run to verify the pipeline operation process, wherein the conflict event can be, for example, one or more of an index conflict, an address conflict, and a resource conflict. In a further example, a test case that periodically generates a conflict event can also be run. For example, the test case takes a first preset number of clock cycles as a cycle, and periodically generates a second preset number of conflict events. The first preset number and the second preset number are both integers greater than or equal to 1, so that one or more conflict events can be generated within a cycle, thereby verifying the pipeline process of the cache.

[0091] Obviously, in the embodiment of the present invention, based on the control of the clock cycle, running the test cases for generating conflict events can improve the coverage of the test cases and improve the efficiency of debugging.

[0092] When the pipeline verification module verifies the pipeline processing flow, it can also monitor the RTL information of the cache design in the pipeline verification flow, so that the accuracy of the RTL (Register Transfer Level) of the cache design can be verified based on the pipeline verification flow, such as whether conflict information corresponding to the conflict event is generated, if there is other erroneous conflict information, whether the corresponding error information delays the operation process of the pipeline, and the specific delay amount, etc. It can be understood that the basic functions that may exist in the RTL level (such as automatic error correction, etc.) usually affect the verification results, and based on the conflict detection process, verifying the accuracy of the RTL (Register Transfer Level) of the cache design can directly and effectively determine the error.

[0093] It is understandable that in the conventional scenario of overall verification of the cache, it is necessary to drive the core control logic to run the corresponding test cases and perform test analysis based on the running results, which makes it difficult to achieve sufficient and effective verification in this way, and it is difficult to find hidden defects in the cache design at the RTL level. In contrast, the pipeline verification module of the embodiment of the present invention can achieve sufficient and effective verification of the pipeline processing flow, as well as verification of hidden defects in the RTL.

[0094] In the cache, the data consistency mechanism is one of the basic functions of the core control logic in the cache. The data consistency mechanism is used to ensure the consistency of the data stored in the cache with the data stored in the memory. In the data consistency verification module, a cache simulation model can be pre-built, and the cache simulation model receives the same access request synchronously with the core control logic, and updates the data based on the access request. When performing data consistency verification, based on the data in the cache simulation model, it is determined whether the updated data in the cache design is accurate.

[0095] In a further example, a consistency checker may be configured for the data consistency verification module, so that a comparison between the data in the cache simulation model and the data in the cache design may be performed based on the consistency checker, thereby determining whether the updated data in the cache design is accurate based on the data in the cache simulation model.

[0096] Furthermore, considering that the data consistency mechanism also includes data modification of downstream devices, the data consistency verification module is also used to obtain the access request issued by the output end of the core control logic to the downstream module, and determine whether the access request complies with the data consistency mechanism, thereby achieving full verification of the data consistency mechanism.

[0097] In a further optional example, the core control verification module may also include a core control driving module 123 for driving a test stimulus for verifying the core control logic, so that the core control logic executes corresponding logic based on the test stimulus.

[0098] In a further example, a driving stimulus for driving the data storage logic may also be generated in the verification process of the core control logic. In an embodiment of the present invention, the core control verification module may also reuse the first monitoring module to obtain the driving stimulus based on the first monitor in the storage logic verification module, and then determine whether the driving stimulus complies with the constraints of the core control logic based on the first scoreboard.

[0099] In a further example, the verification process of the core control logic will also generate an interaction request with the upstream module or the downstream module. In an embodiment of the present invention, the core control verification module can also reuse the second monitoring module to obtain the interaction request between the core control logic and the upstream module or the downstream module based on the second monitor in the routing logic verification module, and then determine whether the interaction request complies with the constraints of the core control logic based on the second scoreboard.

[0100] It should be further explained that the embodiments of the present invention provide a cache verification platform, which can implement separate verification of data storage logic based on a storage logic verification module, implement separate verification of core control logic based on a core control verification module, and implement separate verification of routing logic based on a routing verification module, thereby specifically discovering defects (bugs) that may occur in the data storage logic.

[0101] Moreover, in some optional scenarios, the cache verification platform can also adapt to cache designs that have not yet been completed, that is, as the cache design is completed, the completed logic can be verified in real time. For example, a separate verification of the data storage logic is performed when the data storage logic is completed, a separate verification of the core control logic is performed when the core control logic is completed, and a separate verification of the routing logic is performed when the routing logic is completed, thereby improving the flexibility of chip verification and accelerating cache verification iterations.

[0102] In a further example, the cache verification platform further includes a cache verification module, referring to Figure 6 The optional structural diagram of the cache verification module is shown. Specifically, the cache verification module includes: a cache verification association module 141 and the storage logic verification module 110, the core control verification module 120 and the routing verification module 130 embedded in the cache verification association module.

[0103] Among them, the cache verification module is composed of the cache verification association module and the storage logic verification module, the core control verification module and the routing verification module embedded in the cache verification association module, which is used to perform overall verification on the cache design obtained after the association logic associates the data storage logic, core control logic and routing logic, thereby realizing overall verification of the cache design.

[0104] It is understandable that the overall verification of the cache design is achieved by embedding the cache verification association module based on the existing module, which can avoid the corresponding debugging process (such as data debugging, parameter matching, etc.), thereby reducing the time consumption of the verification process and shortening the verification cycle.

[0105] In an optional example, the core control verification module in the cache verification module reuses the first monitoring module and the second monitoring module at the same time, referring to Figure 7 Another optional structural diagram of the cache verification module is shown. Wherein, for the data storage logic, the storage logic verification module 110 performs verification, and monitors and calculates the verification result based on the first monitoring module; for the routing logic, the routing verification module 130 performs verification, and monitors and calculates the verification result based on the second monitoring module; for the core control logic, the core control verification module 120 performs verification, wherein the core control verification module reuses the first monitoring module and the second monitoring module at the same time, wherein the first monitoring module is used to monitor the verification process of the core control logic and also generates a driving stimulus for driving the data storage logic, and the second monitoring module is used to monitor the interaction request between the core control logic and the upstream module or the downstream module.

[0106] It can be understood that the cache verification platform performs separate verification on the data storage logic, core control logic and routing logic respectively, and further performs comprehensive verification on the overall cache design, thereby achieving comprehensive and sufficient verification of the cache design.

[0107] Based on the above cache verification platform, in an embodiment of the present invention, a cache verification method is further provided, which can be executed based on the above cache verification platform or on other verification platforms with equivalent processes. Figure 8 An optional flow chart of a cache verification method is shown, the method comprising:

[0108] Step S100: splitting the cache design into mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic;

[0109] The cache design is an object to be verified. The cache design may be a design scheme in the chip design stage. Accordingly, the embodiment of the present application is a verification scheme for the corresponding cache design. The cache may be understood as a design in software form, or a design in hardware form, or a combination of software and hardware.

[0110] It can be understood that the cache can be divided into a first-level cache, a second-level cache, and a third-level cache, etc. In an embodiment of the present invention, the cache design can be a cache at any level, for example, it can be a last-level cache (LLC, Last Level Cache, that is, the bottom-level cache. When there is a second-level cache, the last-level cache can be a second-level cache. When storing a third-level cache, the last-level cache can be a third-level cache). Among them, the functions based on the last-level cache are more complex than those of other levels of cache. Therefore, the verification platform that adapts to the last-level cache can also be applicable to caches at other levels.

[0111] In an embodiment of the present invention, the cache design is split into mutually independent data storage logic, core control logic and routing logic, as well as an association logic for associating the data storage logic, core control logic and routing logic, so as to perform separate verifications based on the independent data storage logic, core control logic and routing logic, thereby achieving full verification of the cache design.

[0112] Step S110: verifying the data storage logic, core control logic and routing logic respectively;

[0113] The verification of the data storage logic may include verifying the memory access function of the data storage logic and verifying the logic control function in the data storage logic.

[0114] In some optional examples, the data storage logic includes multiple data storage units, for example, the SRAM storage logic may include multiple SRAM Macro storage units, and the memory access function of the verification data storage logic may specifically be to verify the data storage units one by one.

[0115] In a further example, the embodiment of the present invention may also provide a driving signal for the data storage logic, thereby driving a test stimulus for verifying the data storage logic, so that the data storage logic executes corresponding logic based on the test stimulus.

[0116] In an optional example, this step can further monitor the first result information output by the data storage logic based on the test stimulus, determine the verification result based on the first result information, and calculate the coverage of the verification running on the data storage logic based on the first result information.

[0117] The verification of the routing logic specifically includes verifying the routing logic between the core control logic and the upstream module or the downstream module in the cache design.

[0118] Accordingly, verification of the routing logic may include verification of the data transmission function of the routing logic and verification of the arbitration mechanism configured to the routing logic.

[0119] Among them, verifying the data transmission function of the routing logic, for example, may include verifying the data accuracy of the request transmitted by the routing logic, that is, determining whether the data transmitted from the input port of the routing logic to the output port of the routing logic is accurate; it may also include verifying the data transmission efficiency of the routing logic, that is, the amount of data transmission from the input port to the output port in a preset time period, and determining whether there is packet loss or multiple packets; it may also include verifying the delay of the routing logic, that is, determining the amount of data delay transmitted from the input port to the output port.

[0120] The arbitration mechanism configured in the routing logic is verified, specifically, when multiple data are transmitted from an input port to an output port, whether the transmission order of the data satisfies a preset arbitration mechanism.

[0121] In a further example, the embodiment of the present invention may also provide a driving signal for the routing logic, thereby driving a test stimulus for verifying the routing logic, so that the routing logic executes corresponding logic based on the test stimulus.

[0122] In an optional example, this step can further monitor the second result information output by the routing logic based on the test stimulus, determine the verification result based on the second result information, and calculate the coverage of the verification running on the routing logic based on the second result information.

[0123] The verification of the core control logic may include verifying the pipeline processing flow in the core control logic and verifying the data consistency mechanism in the core control logic.

[0124] In a specific example, verifying the pipeline processing flow in the core control logic can be implemented based on conflict detection. Specifically, based on the control of the clock cycle, a test case for generating a conflict event can be run to verify the pipeline operation process, wherein the conflict event can be, for example, one or more of an index conflict, an address conflict, etc. In a further example, a test case that periodically generates a conflict event can also be run. For example, the test case takes a first preset number of clock cycles as a cycle, and periodically generates a second preset number of conflict events. Both the first preset number and the second preset number are integers greater than or equal to 1, so that one or more conflict events can be generated within one cycle, thereby verifying the cached pipeline process.

[0125] In an optional example, during the verification of the pipeline processing flow, the RTL information of the cache design in the pipeline verification flow can also be monitored, so that the accuracy of the RTL (Register Transfer Level) of the cache design can be verified based on the pipeline verification flow, such as whether conflict information corresponding to the conflict event is generated, if there is other erroneous conflict information, whether the corresponding error information delays the operation process of the pipeline, and the specific delay amount, etc. It can be understood that the basic functions that may exist in the RTL level (such as automatic error correction, etc.) usually affect the verification results, and based on the conflict detection process, verifying the accuracy of the RTL (Register Transfer Level) of the cache design can directly and effectively determine the error.

[0126] In the process of verifying the data consistency mechanism in the core control logic, a cache simulation model can be pre-built, and the cache simulation model receives the same access request synchronously with the core control logic, and updates the data based on the access request. When performing data consistency verification, based on the data in the cache simulation model, it is determined whether the updated data in the cache design is accurate.

[0127] In a further example, a consistency checker may be configured to compare data in a cache simulation model with data in a cache design based on the consistency checker, thereby determining whether updated data in the cache design is accurate based on the data in the cache simulation model.

[0128] Considering that the data consistency mechanism also includes data modification of downstream devices, the verification process of the data consistency mechanism also includes obtaining the access request issued by the output end of the core control logic to the downstream module, and determining whether the access request complies with the data consistency mechanism, thereby achieving full verification of the data consistency mechanism.

[0129] In a further example, the embodiment of the present invention may also provide a driving signal for the core control logic, thereby driving a test stimulus for verifying the core control logic, so that the core control logic executes corresponding logic based on the test stimulus.

[0130] Step S120: After the data storage logic, core control logic and routing logic are verified, verify the cache design.

[0131] It can be understood that the cache verification method performs separate verification on the data storage logic, core control logic and routing logic respectively, and further performs comprehensive verification on the overall cache design, thereby achieving comprehensive and sufficient verification of the cache design.

[0132] In an optional example, before step S110, the following may also be included:

[0133] Step S200: preloading initial data for data storage logic;

[0134] The initial data is preset data or random data, and the location where the initial data is loaded in the data storage logic is a preset location or a random location.

[0135] In the step of preloading initial data for the data storage logic, error points are also loaded for the data storage logic, and / or the potentials of preset points in the data storage logic are fixed to simulate a test scenario in which device bad points exist in the data storage logic.

[0136] In a specific example, initial data may also be written to the data storage logic through a backdoor method.

[0137] The cache verification method in the embodiment of the present invention can realize flexible loading of initial data, thereby greatly shortening the verification time and enriching the verification scenarios.

[0138] An embodiment of the present invention further provides an electronic device, which is configured as a cache verification platform as provided in the above embodiment.

[0139] An embodiment of the present invention further provides a storage medium, wherein the storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the cache verification method in the embodiment of the present invention is implemented.

[0140] The above describes multiple implementation schemes provided by the embodiments of the present invention. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present invention.

[0141] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A cache verification platform, characterized in that: Used to verify cache design, wherein the cache design includes mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic, the cache verification platform includes: A storage logic verification module, used to verify the data storage logic in the cache design; A core control verification module, used to verify the core control logic in the cache design; A routing verification module, used to verify the routing logic of the core control logic and the upstream module or the downstream module in the cache design; The cache verification module is used to verify the cache design obtained after the association logic is associated with the data storage logic, the core control logic and the routing logic.

2. The cache verification platform according to claim 1, characterized in that: Also includes: The preloading module is used to preload initial data for the data storage logic, wherein the initial data is preset data or random data, and the location where the initial data is loaded in the data storage logic is a preset location or a random location.

3. The cache verification platform according to claim 2, characterized in that: The preloading module is further used to load error points, and / or the preloading module is further used to fix the potential of preset points in the data storage logic to simulate a test scenario in which a device bad point exists in the data storage logic.

4. The cache verification platform according to claim 1, characterized in that: The storage logic verification module includes a memory access function verification module and a logic control verification module, wherein the memory access function verification module is used to verify the memory access function of the data storage logic, and the logic control verification module is used to verify the logic control function in the data storage logic; The data storage logic includes a plurality of data storage units, and the memory access function verification module is used to verify the data storage units.

5. The cache verification platform according to claim 4, characterized in that: The storage logic verification module also includes a storage logic driving module, which is used to drive a test stimulus for verifying the data storage logic, so that the data storage logic executes corresponding logic based on the test stimulus.

6. The cache verification platform according to claim 4, characterized in that: The storage logic verification module also includes a first monitoring module for monitoring the data storage logic, the first monitoring module includes a first monitor, and a first scoreboard and a first coverage calculation unit connected to the first monitor, the first monitor is used to monitor the first result information output by the data storage logic based on the test stimulus, the first scoreboard is used to determine the verification result based on the first result information, and the first coverage calculation unit is used to calculate the coverage of the verification run on the data storage logic based on the first result information.

7. The cache verification platform according to claim 1, characterized in that: The routing verification module includes a data transmission verification module and an arbitration mechanism verification module. The data transmission verification module is used to verify the data transmission function of the routing logic; the arbitration mechanism verification module is used to verify the arbitration mechanism of the routing logic.

8. The cache verification platform according to claim 7, characterized in that: The routing verification module also includes a second monitoring module for monitoring the routing logic, the second monitoring module includes a second monitor, and a second scoreboard and a second coverage calculation unit connected to the second monitor, the second monitor is used to monitor second result information output by the routing logic based on test stimulus, the second scoreboard is used to determine the verification result based on the second result information, and the second coverage calculation unit is used to calculate the coverage of the verification running on the routing logic based on the second result information.

9. The cache verification platform according to claim 1, characterized in that: The core control verification module includes a pipeline verification module and a data consistency verification module, wherein the pipeline verification module is used to verify the pipeline processing flow in the core control logic; the data consistency verification module is used to verify the data consistency mechanism in the core control logic; Among them, the pipeline verification module is used to verify the pipeline processing flow in the core control logic, specifically, based on the control of the clock cycle, running the test case used to generate the conflict event; the conflict event is one or more of the index conflict, address conflict and resource conflict; the test case takes the first preset number of clock cycles as a cycle, and periodically generates the second preset number of conflict events, and the first preset number and the second preset number are both integers greater than or equal to 1.

10. The cache verification platform according to claim 9, characterized in that: The pipeline verification module also monitors the RTL information of the cache design in the pipeline verification process.

11. The cache verification platform according to claim 9, characterized in that: The data consistency verification module is pre-built with a cache simulation model and a consistency monitor; The cache simulation model receives the same access request synchronously with the core control logic, and updates the data based on the access request; the consistency monitor is used to determine whether the updated data in the cache design is accurate based on the data in the cache simulation model; The data consistency verification module is also used to obtain an access request sent by the output end of the core control logic to a downstream module, and determine whether the access request complies with the data consistency mechanism.

12. The cache verification platform according to claim 1, characterized in that: The cache verification module includes a cache verification association module and the storage logic verification module, the core control verification module and the routing verification module embedded in the cache verification association module; The core control verification module reuses the first monitoring module in the storage logic verification module and the second monitoring module in the routing verification module.

13. A cache verification method, characterized in that: include: Splitting the cache design into mutually independent data storage logic, core control logic and routing logic, and association logic for associating the data storage logic, core control logic and routing logic; Verifying the data storage logic, core control logic and routing logic respectively; After the data storage logic, core control logic and routing logic are verified, the cache design is verified.

14. The cache verification method according to claim 13, characterized in that: Before respectively verifying the data storage logic, the core control logic and the routing logic, the method further includes: Preload initial data for the data storage logic, the initial data is preset data or random data, and the location where the initial data is loaded by the data storage logic is a preset location or a random location.

15. The cache verification method according to claim 14, characterized in that: In the step of preloading initial data for the data storage logic, error points are also loaded for the data storage logic, and / or the potentials of preset points in the data storage logic are fixed to simulate a test scenario in which a device defect exists in the data storage logic.

16. The cache verification method according to claim 13, characterized in that: The verification of the core control logic includes: Verify the pipeline processing flow in the core control logic; and verify the data consistency mechanism in the core control logic; Among them, the pipeline processing flow in the core control logic is verified, specifically, based on the control of the clock cycle, running a test case for generating a conflict event; the conflict event is one or more of an index conflict and an address conflict; the test case takes a first preset number of clock cycles as a cycle, and periodically generates a second preset number of conflict events, and the first preset number and the second preset number are both integers greater than or equal to 1.

17. An electronic device, characterized in that: The electronic device is configured as a cache verification platform as claimed in any one of claims 1 to 12.

18. A storage medium, characterized in that: The storage medium stores one or more computer executable instructions, and when the one or more computer executable instructions are executed, the cache verification method according to any one of claims 13 to 16 is implemented.

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