Automatic layout method of circuit board, automatic layout device and computer storage medium

Abstract

The present application proposes an automatic layout method, an automatic layout device, and a computer storage medium for a circuit board. The automatic layout method includes: obtaining the graph structure data of the circuit board; generating a layout strategy based on the layout rules of the devices in the circuit board in the current layout stage; automatically laying out the graph structure data according to the layout strategy to obtain an automatic layout solution; optimizing the rule parameters in the layout strategy using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is ended and the current automatic layout solution is output. Through the above-mentioned automatic layout method, the layout strategy is continuously optimized according to the advantages and disadvantages of the layout solutions in different layout stages to obtain the optimal layout strategy to automatically generate the optimal layout solution, improve the practicality of the layout strategy and layout mode, and improve the efficiency of automatic layout.

Description

Technical Field

[0001] The present application relates to the field of PCB automation technology, and in particular to an automatic layout method, an automatic layout device and a computer storage medium for a circuit board. Background Art

[0002] PCB (Printed Circuit Board) automatic layout is a key research direction in the field of EDA (Electronic design automation). In the field of algorithms, it is a classic combinatorial optimization problem that cannot be solved under polynomial time complexity and is a typical NP-hard problem. The current mainstream solution is to use various optimization algorithms to find the best possible solution in the shortest possible time. The PCB layout problem is a non-convex problem with complex rule constraints. Common optimization algorithms such as particle swarm and genetic algorithms cannot meet the needs of actual engineering design in terms of optimization performance and solution quality under complex constraints.

[0003] The current layout strategy is single and fixed, and can only be laid out through simple manual experience program templates. The program template is single and fixed, and the devices are prioritized in the order of crystal oscillator, capacitor, inductor, and resistor, and are laid out in the order of device volume from large to small, which cannot cope with the complex device relationships in actual engineering design. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes an automatic layout method, an automatic layout device and a computer storage medium for a circuit board.

[0005] In order to solve the above technical problems, the present application proposes an automatic layout method for a circuit board, the automatic layout method comprising:

[0006] Acquire graph structure data of the circuit board;

[0007] In the current layout stage, a layout strategy is generated based on the layout rules of the components in the circuit board;

[0008] Automatically layout the graph structure data according to the layout strategy to obtain an automatic layout solution;

[0009] The evaluation feedback of the automatic layout solution is used to optimize the rule parameters in the layout strategy to generate a new layout strategy, until the current layout stage is ended and the current automatic layout solution is output.

[0010] In order to solve the above technical problems, the present application also proposes an automatic layout device for a circuit board, the automatic layout device comprising: a data module, a strategy module, a solution module, and an optimization module; wherein:

[0011] The data module is used to obtain the graphic structure data of the circuit board;

[0012] The strategy module is used to generate a layout strategy based on the layout rules of the components in the circuit board in the current layout stage;

[0013] The solution module is used to automatically layout the graph structure data according to the layout strategy and obtain an automatic layout solution;

[0014] The optimization module is used to optimize the rule parameters in the layout strategy by using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is ended and the current automatic layout solution is output.

[0015] In order to solve the above technical problems, the present application also proposes an automatic layout device for a circuit board, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the automatic layout method as described above.

[0016] In order to solve the above technical problems, the present application also proposes a computer storage medium, wherein the computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the above automatic layout method.

[0017] Compared with the prior art, the beneficial effects of the present application are: the automatic layout device obtains the graph structure data of the circuit board; in the current layout stage, a layout strategy is generated based on the layout rules of the devices in the circuit board; the graph structure data is automatically laid out according to the layout strategy to obtain an automatic layout solution; the rule parameters in the layout strategy are optimized using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is ended and the current automatic layout solution is output. Through the above-mentioned automatic layout method, the layout strategy is continuously optimized according to the advantages and disadvantages of the layout solutions in different layout stages to obtain the optimal layout strategy to automatically generate the optimal layout solution, improve the practicality of the layout strategy and layout mode, and improve the efficiency of automatic layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0019] Figure 1It is a flowchart of an embodiment of an automatic layout method provided by the present application;

[0020] Figure 2 It is a schematic diagram of the overall process of the automatic layout method provided by this application;

[0021] Figure 3 It is a schematic diagram of an embodiment of graph structure data provided by the present application;

[0022] Figure 4 It is a comparative schematic diagram of the functional module diagram structure before and after segmentation provided by the present application;

[0023] Figure 5 It is a workflow diagram of the hierarchical layout state machine provided by this application;

[0024] Figure 6 It is a schematic diagram of the framework of the rule manager provided by this application;

[0025] Figure 7 It is a schematic diagram of the PCB layout infrastructure provided by this application;

[0026] Figure 8 yes Figure 1 The specific flow chart of step S12 of the automatic layout method is shown;

[0027] Fig. 9 yes Figure 1 The specific flow chart of step S14 of the automatic layout method is shown;

[0028] Fig.10 is a flow chart of another embodiment of the automatic layout method provided by the present application;

[0029] Fig.11 is a schematic diagram of the Monte Carlo tree search process provided by this application;

[0030] Fig.12 It is a structural schematic diagram of an embodiment of an automatic layout device for a circuit board provided by the present application;

[0031] Fig.13 It is a structural schematic diagram of an embodiment of an automatic layout device for a circuit board provided by the present application;

[0032] Fig.14 It is a structural diagram of an embodiment of a computer storage medium provided by the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0034] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] PCB layout planning is to place electronic components within the board frame according to functions and rules. The layout quality directly determines the product function and performance, and is an important part of PCB layout design. As a carrier of electronic components, PCB has long relied heavily on the ability and experience of engineers due to its complexity. At the same time, with the development of electronic technology, the number of devices in PCB has increased rapidly with Moore's Law. PCB is developing towards miniaturization and density, and layout design is becoming more and more difficult. Engineers urgently need automatic layout technology to assist layout.

[0036] Therefore, the present application provides a dynamic decision-making PCB automatic layout method, which generates a graph data structure by re-encoding the schematic diagram, generates a multi-scale circuit module by automatic module aggregation; performs phased layout through a state machine; converts complex layout rules into strategic actions to guide layout through a rule manager, a heuristic strategy generation algorithm, and a search decision planning algorithm, makes layout decisions in a simulated exploration manner, and dynamically adjusts the execution strategy in combination with a real-time feedback verification mechanism to achieve efficient and high-quality automatic layout.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 is a flow chart of an embodiment of an automatic layout method provided by the present application, Figure 2 It is a schematic diagram of the overall process of the automatic layout method provided by this application.

[0038] The automatic layout method of the present application is applied to an automatic layout device, wherein the automatic layout device of the present application can be a server, a terminal device, or a system in which a server and a terminal device cooperate with each other. Accordingly, the various parts included in the automatic layout device, such as various units, sub-units, modules, and sub-modules, can all be set in the server, can all be set in the terminal device, or can be set in the server and the terminal device respectively.

[0039] Furthermore, the above-mentioned server can be hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or it can be implemented as a single server. When the server is software, it can be implemented as multiple software or software modules, such as software or software modules used to provide distributed servers, or it can be implemented as a single software or software module, which is not specifically limited here.

[0040] like Figure 1 As shown, the specific steps are as follows:

[0041] Step S11: Acquire the graphic structure data of the circuit board.

[0042] In the embodiments of the present application, Figure 2 As shown, the automatic layout pre-processing steps include schematic information reading, board frame information reading, device modeling and circuit modularization, etc.

[0043] Among them, the netlist reading process converts the graphical schematic file into structured data that can be processed programmatically, including device information, connection relationships, network information, etc. Device modeling is the recoding of the circuit to build an efficient data structure that can be processed by the layout algorithm. This application uses a graph data structure to represent the connection relationship and attribute information of the device. Some device attributes such as geometric information and signal rate come from the component library and protocol library. Circuit modularization is a key step in PCB layout. The division and clustering of the minimum functional modules are completed before layout to facilitate subsequent layout planning. Here, relevant experience is used to perform automated module division.

[0044] Specifically, the main contents of the automatic layout pre-processing of the present application are the encoding of schematic diagram information and the modularization of circuits.

[0045] This application uses netlist files and DXF (Drawing Exchange Format, vector data format) files as input files. Netlist files are circuit descriptive text files that schematic software imports information into PCB design tools, containing detailed information about the circuit, such as device attributes, device pin types, device connection relationships, etc. DXF files are general CAD (Computer Aided Design) files, and this application stores structural information such as board frame shape, height restriction area, heat dissipation sheet metal area, and device placement restriction area.

[0046] Among them, the descriptive text information of the netlist file is not suitable for algorithm program processing. This application adopts a graph structure As the basic data structure for describing a circuit, V is a set of graph nodes, which represent devices in this application, and E is a set of graph edges, which are connection lines between devices here, to simplify the data structure.

[0047] The graph structure data of this application adopts an undirected graph, and the direction of the edge is not considered. The graph structure used to describe the circuit here is different from the common undirected graph structure. The topological characteristics of the circuit determine that there may be multiple connection lines between devices, such as Figure 3 Show, node Indicates device, edge Indicates the device and The first The graph structure naturally has the ability to represent connection relationships. In order to restore the circuit characteristics in detail, the structured parameter data of devices and networks are bound to nodes and edges in the form of key-value pairs, which fully improves the information density of the graph structure. Figure 3 It is a schematic diagram of an embodiment of graph structure data provided by this application.

[0048] like Figure 3 As shown, after the present application abstracts the circuit into a data structure that can be efficiently processed by the program, the system has the data foundation for programmatic modeling. According to the existing node and edge information from the schematic diagram, the corresponding device and signal parameters are matched in the external component library, protocol library and other databases to further enrich the attribute information, such as the outer contour shape, height, rated power consumption, thermal resistance, network line length limit, etc. After the basic data structure is constructed, a real layout environment is constructed in the form of visual graphics or program virtualization. This environment has detailed structural constraints, and all devices have two-dimensional geometric shapes and height attributes. Subsequent algorithms will perform automatic layout in this environment.

[0049] Specifically, the present application also provides a method for rapid and automatic modularization of complex circuits. In actual engineering design, modular layout is an important way to simplify layout difficulty and improve layout quality. The circuit itself imported from the schematic diagram to the PCB is scattered components. The system-level schematic circuit may contain thousands of devices and networks. Engineers need to divide the functional modules according to the circuit function and design experience. The most common method is to cluster peripheral related devices around core devices such as chips or connectors, complete the layout of small functional modules, and use this module as a layout unit, that is, as a larger component, and perform a higher-level layout until the layout of the entire PCB is completed.

[0050] Referring to the layout process of engineers, the core of modularization lies in the precise division and clustering of modules. The previous step has built a fully functional diagram structure of the schematic diagram, identified the chip and connector device nodes through device attribute information, marked such device nodes as module core nodes, and recursively searched with this node as the starting point in a depth-first or breadth-first search manner, traversing the associated devices through the network connection relationship, and traversing the current link terminates when traversing to a device that meets the following conditions:

[0051] a. This device is the core device of other modules.

[0052] b. The other pin networks of the device are all power or ground networks covered by the entire board.

[0053] c. The device is not on the same page as the module core device in the schematic diagram.

[0054] d. The coordinate position of this device in the schematic diagram page is closer to the core devices of other modules.

[0055] The automatic layout device repeats the above steps until all modules are divided and clustered. The complex system-level graph structure will be divided into several functional module graph structures, such as Figure 4 As shown, each functional module is relatively independent but the modules still maintain the original connection relationship, reducing the complexity without losing the original information. Figure 4 It is a comparative schematic diagram of the functional module diagram structure before and after segmentation provided by this application.

[0056] Step S12: In the current layout stage, a layout strategy is generated based on the layout rules of the components in the circuit board.

[0057] In the embodiments of the present application, Figure 2As shown, the hierarchical layout state machine in the automatic layout device provided by the present application controls the layout stage. Among them, the state machine is used to manage and apply rules at different stages. Drawing on the layout experience of engineers, the basic rules are preferentially satisfied according to the rule hierarchy to form a preliminary layout, and the advanced rules are subsequently applied to optimize the performance. The minimum functional module layout is completed according to the layout stage, and a larger scale layout is subsequently performed in modules. The state machine guides the generation of application strategies according to the current layout state to ensure the efficiency and flexibility of the layout process. Therefore, the current layout stage can be a module layout stage, or a global layout stage.

[0058] This application proposes to add a state machine to the automatic layout process to achieve multi-stage and multi-rule level layout optimization, further decomposing and simplifying complex problems.

[0059] Among them, the automatic layout scheme can be divided into two stages according to the scale, namely module layout and global layout. In each stage, the applicable rules are divided into two levels: basic rules and advanced rules. The simplified flow chart of the state machine is as follows: Figure 5 As shown, Figure 5 It is a workflow diagram of the hierarchical layout state machine provided in this application.

[0060] like Figure 5 As shown, the state machine is the top-level control engine of the automatic layout algorithm, which guides the layout algorithm to apply the most appropriate layout strategy according to the current layout state.

[0061] During the module layout stage, the algorithm focuses on the layout of scattered devices within small functional modules, mainly using short connecting lines. Therefore, it focuses more on basic rules, with the basic goal of making modules compact, devices neat and without physical interference. On this basis, a small number of advanced rules are used to fine-tune the devices.

[0062] In the global layout stage, there are also two levels of rules: basic and advanced. Since the board is composed of modular components with a small number of components, the basic rules are easier to meet, and the algorithm focuses more on advanced rules that improve PCB performance and optimizes layout quality as much as possible. Phased and hierarchical layout can effectively improve the effectiveness of the algorithm and make it easier to achieve the best layout efficiency and quality.

[0063] It should be noted that if divided into module layout stage and global layout stage, the automatic layout solution can be divided into Figure 5 The process shown first performs the module layout stage, that is, the devices in the structural data of each functional module diagram are laid out within the module range; then all functional modules are input into the global layout stage, that is, the layout results of all functional modules are automatically laid out according to the module dimensions.

[0064] After determining the current stage through the hierarchical layout state machine, the automatic layout device further implements a closed-loop automatic layout logic through a rule manager, a policy generator, and a layout module.

[0065] Specifically, the rule manager plays the role of constraining and guiding the automatic layout algorithm in this application. Its core includes two parts: the rule container and the verifier. Its simplified architecture diagram is as follows: Figure 6 As shown. The rule container stores rules and outputs them to the verifier and strategy generation module in a standard format; the layout verifier connects the rule container, the layout feedback terminal and the strategy generation manager to perform layout quality evaluation. Figure 6 It is a schematic diagram of the framework of the rule manager provided by this application.

[0066] In PCB design, rules can be divided into two categories: normative and empirical. Normative rules are defined based on fixed standards, design specifications, process technology and other factors. They are mainly based on constraints and usually have clear conditions and values. Their purpose is to ensure the basic functions and reliability of the design. Empirical rules are mostly based on engineers' actual experience and industry best practices. They aim to optimize the performance and reliability of the layout. Such rules are highly flexible, relatively abstract in description, and difficult to define.

[0067] In order to effectively describe and manage rules, especially empirical rules, and optimize the flexibility and adaptability of automatic layout, this application proposes an object-oriented general rule description structure. The basic structure of rule description is as follows:

[0068]

[0069] Among them, the unique identifier is used to distinguish rules for easy management and calling.

[0070] Description is a brief explanation of the rule, which helps to quickly understand the purpose and scope of application of the rule.

[0071] The rule type is enumerated to refer to the normative and empirical rules respectively, which is convenient for correct calling of the algorithm. When the device contains multiple rules, the normative rules are generally given priority.

[0072] The weight indicates the importance of this rule in the evaluation. Modifying the weight can greatly affect the layout effect.

[0073] The condition list contains one or more conditions. Each condition contains the condition type and specific parameters. The type is also expressed in enumeration form. The parameters are described in dictionary form, providing the necessary parameter information for the algorithm. The evaluation function provides a layout scoring equation. The algorithm scores the layout quality based on the feedback combined with this function equation.

[0074] Object-oriented means that rules, devices, networks and other elements are regarded as objects. They are encapsulated and called through classes, which can realize the binding of rules with devices and networks. It can also realize the inheritance and combination of multiple simple rules to form complex rules, so that the automatic layout algorithm can realize complex multi-condition constraints and provide maximum flexibility and convenience.

[0075] like Figure 2 As shown, the present application further inputs the layout rules and rule parameters provided by the rule manager into the strategy generator to realize dynamic heuristic strategy generation and optimization through the startup strategy generation layout guidance algorithm.

[0076] The existing common solutions generally use heuristic optimization algorithms (genetic algorithms, particle swarm algorithms, etc.) to directly apply to automatic layout for device combination optimization. By comparing the indicators or constraints set in advance, the device adjustment direction is changed, and the algorithm is gradually iterated to the best combination result considered by the algorithm. The automatic layout algorithm under the existing heuristic algorithm framework generally takes the position (coordinates) of the device in the canvas as the optimization object or parameter, but the PCB layout is carried out under a large number of constraints. Even if only the basic condition that the device does not physically interfere is considered, the automatic layout will become a complex non-convex problem, and there is a huge solution space. If conditions such as signal integrity are added to improve the layout quality, the challenges to the algorithm convergence speed and solution quality will be further increased. Even if improvements are made through adaptive evaluation function adjustment, canvas grid division, multi-algorithm fusion and other methods to improve the solution (search) speed and reduce the solution space, because the direction of device layout optimization or search is not specified in the algorithm, the algorithm focuses on constraints and neglects guidance, and can only screen possible optimal solutions through evaluation indicators in the iteration of approximate random traversal.

[0077] Therefore, this application proposes a PCB layout execution process under a dynamic strategy, applies a heuristic optimization algorithm to the strategy generation stage, uses a Monte Carlo search algorithm to perform efficient PCB layout search and real-time feedback in the layout stage, and combines a rule manager to implement a dynamic optimization layout strategy. This fusion algorithm can quickly make decisions to generate a PCB layout that meets the design purpose. The basic architecture is as follows Figure 7 As shown, it includes three modules: rule analysis, strategy optimization, layout execution and feedback. Figure 7 It is a schematic diagram of the PCB layout infrastructure provided by this application.

[0078] Please continue reading Figure 8 , Figure 8 yes Figure 1 A specific flow chart of step S12 of the automatic layout method is shown.

[0079] like Figure 8 As shown, the specific steps are as follows:

[0080] Step S121: converting the layout rules of the components in the circuit board into execution actions.

[0081] In the embodiment of the present application, the input of the rule parsing module comes from the rule manager, which converts the descriptive language of the constraint rules into a logical execution formula that can be processed by the layout algorithm. For example, if device A has a minimum spacing rule , which is a normative rule, the purpose is that the distance between the device and the nearby device or the specific device is greater than the set value. The data structure of the constraint condition is as follows:

[0082]

[0083]

[0084]

[0085]

[0086]

[0087] For the above rules, the automatic layout device converts and executes actions through the rule parsing module. For example, device A is placed at a position greater than the minimum spacing from other devices:

[0088] For example, device A also contains alignment rules , which is an empirical rule, the purpose is to align nearby devices or specific devices, the data structure is as follows:

[0089]

[0090]

[0091]

[0092]

[0093]

[0094] For the above rules, the automatic layout device converts the execution action through the rule parsing module, that is, the X-direction coordinate or the Y-direction coordinate of device A and device B are equal:

[0095]

[0096] In this application, both devices and rules are object-oriented data structures, and rules can be accurately added to devices. Through the rule parsing module, the constraint rules assigned to the device are converted into specific execution actions to guide automatic layout. The algorithm execution goal is clear and will not fail to converge due to overly complex constraints.

[0097] Step S122: Generate a layout strategy based on the execution actions of the components in the circuit board.

[0098] In the embodiments of the present application, Figure 7 As shown, the rule parsing module converts the execution action obtained in step S121 into an execution strategy, that is, a layout strategy.

[0099] Step S13: Automatically layout the graph structure data according to the layout strategy to obtain an automatic layout solution.

[0100] In the embodiment of the present application, the automatic layout device will Figure 7 The layout strategy generated by the strategy is input into the layout execution, or the layout module automatically layouts the graph structure data.

[0101] Among them, the strategy generator, rule manager and layout module are the core components of this application, which are used for the generation, optimization and execution of layout algorithms.

[0102] The rule manager contains underlying basic rules and advanced optimization rules. The basic rules involve basic physical constraints and design requirements, such as device spacing, boundary restrictions, height restrictions, etc. Advanced optimization rules are divided into power module rules, connector module rules, etc. according to application scenarios; they can be divided into heat dissipation, EMC (Electromagnetic Compatibility), alignment, compact layout rules, etc. according to different focuses. The rule manager provides layout constraints and evaluations, and does not directly participate in the automatic layout of devices. It converts complex design constraints and difficult-to-program empirical rules into layout strategy actions.

[0103] This application proposes a dynamic heuristic algorithm-based strategy generator that adaptively adjusts applicable rules and weights based on scenarios and layout feedback to generate a layout solution that meets design requirements.

[0104] The layout execution or layout module uses the Monte Carlo search tree as a framework, treats the layout state as a tree node, explores the potential optimal layout through fast layout simulation, and completes the PCB layout in the search iteration.

[0105] Step S14: optimizing the rule parameters in the layout strategy using the evaluation feedback of the automatic layout solution to generate a new layout strategy, until the current layout stage is terminated and the current automatic layout solution is output.

[0106] In the embodiment of the present application, a layout verifier is set to evaluate the layout effect. The verifier accepts the layout diagram fed back from the layout algorithm, and at the same time accepts the rule parameters used to implement this layout from the strategy generation module. The layout quality is scored according to the rule evaluation function, and the result is fed back to the strategy generation module to optimize the implementation strategy and improve the layout quality. The layout verifier that is independent of the layout algorithm and the optimization algorithm is more flexible. Because the devices, networks, and rules are all constructed in an object manner, the verifier can only process the local layout diagram in a targeted manner, thereby improving the efficiency of the layout cycle optimization.

[0107] like Figure 7 The heuristic strategy optimization module shown is based on the framework of heuristic algorithms. The algorithms can use particle swarm, genetic algorithm, simulated annealing, etc. The purpose is to adjust the strategy execution priority and rule weight in the strategy generation stage. Compared with directly applying the heuristic algorithm to adjust the device layout, the optimization strategy at this stage can more significantly affect the automatic layout process. At the same time, the process complexity of the optimization strategy is lower, which is more suitable for the application of such algorithms.

[0108] Please refer to Fig. 9 , Fig. 9 yes Figure 1 A specific flow chart of step S14 of the automatic layout method is shown.

[0109] like Fig. 9 As shown, the specific steps are as follows:

[0110] Step S141: Obtain the satisfaction degree of each layout rule and the rule weight of each layout rule under the layout strategy.

[0111] In the embodiment of the present application, the heuristic algorithm includes several key processes such as initialization, evaluation, and loop optimization. In the present application, the algorithm performs parameter initialization according to the above initial strategy, and allocates the initial order and priority according to the high and low levels of the rules, which are expressed as follows:

[0112]

[0113] in, Indicates the strategy implemented by a device or connection line. It is a collection of all policies. This list is just a container without priority distinction.

[0114]

[0115] in , Indicates the rules contained in this policy. is the weight, and the list order indicates the execution priority.

[0116] During initialization, the algorithm has not yet performed the first layout, so the subsequent optimization process is skipped and the layout phase is entered.

[0117] Step S142: using the satisfaction degree and the rule weight, obtaining the fitness value of the automatic layout solution.

[0118] In the embodiment of the present application, after executing the layout process in the layout module, the algorithm receives the feedback rule deviation value, and the algorithm evaluates it through the fitness function. The fitness function is configured based on the rule compliance and weight, and the goal is to be as large as possible. The formula is as follows:

[0119]

[0120] in, Indicates strategy, Representation strategy No. Implementation rules, express Strategy The degree of satisfaction of the rules, The weight corresponding to this rule.

[0121] Step S143: optimizing the rule configuration data, rule weight, and / or rule priority in the rule parameters based on the fitness value to generate a new layout strategy.

[0122] In the embodiment of the present application, the automatic layout device can adjust the three parameters of rule configuration data, rule weight, and rule priority through a fitness function algorithm. Adjusting the rules will generate new ones, and this process is repeated for iterative optimization until the stopping condition is met.

[0123] Finally, the automatic layout device obtains the optimal layout strategy and uses it to automatically layout the graph structure data to obtain the optimal layout execution solution.

[0124] In the automatic layout method of the present application, evaluation and feedback are the key to the gradual optimization of the layout strategy. The layout algorithm evaluates the degree of compliance of the current layout status with the rules in real time, and feeds back the deviation to the strategy manager in real time. The manager responds to the feedback and optimizes and adjusts the relevant strategies to correct the deviation until the rules are met or further optimization is impossible. The layout will enter the next stage or end the layout.

[0125] In the present application, the automatic layout device obtains the graph structure data of the circuit board; in the current layout stage, generates a layout strategy based on the layout rules of the devices in the circuit board; automatically layouts the graph structure data according to the layout strategy to obtain an automatic layout solution; optimizes the rule parameters in the layout strategy using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is ended and the current automatic layout solution is output. Through the above-mentioned automatic layout method, the layout strategy is continuously optimized according to the advantages and disadvantages of the layout solutions in different layout stages to obtain the optimal layout strategy to automatically generate the optimal layout solution, improve the practicality of the layout strategy and layout mode, and improve the efficiency of automatic layout.

[0126] Furthermore, this application uses the Monte Carlo Tree Search algorithm (MCTS) as the algorithm framework for executing the automatic layout process, and executes the layout process in a dynamic optimization method. Whenever a device is laid out, the algorithm will explore the layout space for simulation and try to find the subsequent optimal layout. Based on the algorithm principle, the key steps are divided into selection, expansion, simulation and backtracking, integrating the real-time feedback evaluation mechanism and strategy dynamic optimization to realize PCB layout under complex constraints.

[0127] PCB layout is a combination of limited devices in a limited space. In theory, all layout methods can be exhaustively enumerated, but the actual computing power and time determine that the exhaustive method is not feasible. Heuristic algorithms are better at solving such combinatorial optimization problems, but in the face of a huge solution space, the solution speed, quality, and stability of weak constraint algorithms that lack a clear search direction are difficult to meet the requirements of engineering applications.

[0128] PCB layout can be regarded as a Markov decision process, that is, the possible layout in the future will affect the current decision, similar to a chess game problem. Under the current layout state node, which device to choose next and where to place it, the current situation and the subsequent devices to be laid out will affect the final layout effect. To achieve the above process, it is necessary to predict and simulate the subsequent state after the action is executed, and adjust the current decision action based on this to achieve the optimal final result. However, it is unrealistic to exhaustively enumerate without a goal. This application uses the MCTS algorithm to perform this search and decision-making process. Its core is to focus on the direction that is most worth exploring, combining the generality of random search and the accuracy of tree search, avoiding invalid searches in a huge solution space, and finding the global optimal solution at a lower cost of time and computing power.

[0129] Please continue to read Fig.10 , Fig.10 It is a flowchart of another embodiment of the automatic layout method provided by the present application.

[0130] The Monte Carlo tree search used in this application is optimized for PCB layout characteristics and dynamic strategy solutions. MCTS searches in the form of a tree, with a node representing a layout state, and the expansion of the tree represents the layout process of gradually adding devices. For the combination of MCTS and the dynamic strategy optimization proposed in this application, each node will provide real-time layout feedback to the rule manager to evaluate the current layout, but the dynamic optimization of the strategy is only for the child nodes expanded from the current state node, such as Fig.11 Node B1, Node B2, Node B3 under Node A. Among them, Fig.11 It is a schematic diagram of the Monte Carlo tree search process provided by this application.

[0131] like Fig.10 As shown, the specific steps are as follows:

[0132] Step S21: Select an initialization node from the graph structure data.

[0133] In the embodiment of the present application, there is no selectable layout state in the algorithm initialization stage, so the automatic layout device selects the module center device as the initial root node, that is, the initialization node. Fig.11 Node A in the module includes only one circuit device, the module center device.

[0134] Step S22: executing the layout process with the initialization node as the layout starting point, and determining the first target child node.

[0135] In the embodiment of the present application, the automatic layout device performs an expansion action based on the root node A, selects a device connected to the device in the A layout and adds it to the A layout, such as Fig.11 There are three devices connected to A, forming three possible layout states: B1, B2, and B3. The expanded nodes contain construction parameters x / y, where x represents the evaluation score of the node, obtained by weighted average of the expanded child nodes, and y represents the number of times the node has been explored. At this time, each of the B1 node, the B2 node, and the B3 node includes the layout states of the two devices determined by the current layout strategy.

[0136] After the automatic layout device expands the child nodes, it will perform a selection operation. The selection operation of the MCTS algorithm follows the "greedy principle" and selects a child node that is most worth exploring each time. Whether the node is worth exploring needs to use the upper confidence limit (UCB) formula:

[0137]

[0138] in, Evaluate the layout score for this node. is the total number of times the child nodes under its parent node are explored, is the number of times the node has been explored, is a real number parameter.

[0139] in the formula It can be regarded as the winning rate in the game problem. In this application, it is the evaluation of the current layout state, indicating the degree of exploration. Using this formula can well balance the optimal strategy and unknown exploration. The algorithm will execute along the current optimal strategy, while paying more attention to nodes that are less explored, ensuring the search breadth to avoid missing potential optimal solutions.

[0140] Fig.11 The three child nodes in the extended part of b are all 0 / 0, so one of the nodes B1 is randomly selected initially. After B1 performs the expansion action, C1 and C2 nodes are obtained. After evaluating the layout, the relationship parameter is 3 / 2. At this time, the UCB values ​​of all child nodes are calculated. Since B2 and B3 have not been explored, the UCB values ​​are positive infinity, so exploration will be performed on the B2 or B3 node in the future.

[0141] The layout algorithm of the present application will recursively search step by step according to the above selection and expansion rules, and feed back the search results to the root node. This process is the simulation and backtracking in the algorithm.

[0142] This application adjusts and transforms the simulation and backtracking operations of the algorithm, evaluates the current layout status with real-time feedback, and optimizes the layout using dynamic strategies, where the real-time feedback evaluation mechanism applies to all nodes, while the dynamic strategy layout optimization is only for the first-level child nodes under the root node.

[0143] Fig.11 In the simulation and backtracking part of d, it is assumed that the simulation and backtracking operations are performed on the B1 branch, and the dynamic strategy layout will be applied to the B1 node. The first-level child node under the root node will determine the next device to be laid out. Its layout quality must be guaranteed to be optimal, and the iteration of dynamic strategy adjustment is a relatively time-consuming process. During the search process, this node is guaranteed to be optimal. In the subsequent expansion, a fast search strategy is adopted to quickly perform layout simulation to achieve a balance between quality and efficiency. After the backtracking operation makes a layout evaluation for the child node, the parameters are recursively fed back to the parent node and the node UCB formula parameters are updated.

[0144] Fig.11 The e-iteration part is an iterative search process. The PCB layout problem is different from the game problem in terms of results. It cannot be judged whether it is over by winning or losing. Therefore, this application uses the addition of all devices to the layout scene as the end of the iteration mark.

[0145] In the current iteration phase, the automatic layout device will search for the node B3 with the highest score at the end of the iteration as the current execution action. At this time, the node B3 is the first target child node.

[0146] Step S23: continue to execute the layout process with the first target sub-node as the layout starting point, determine the second target sub-node, until the layout status of all devices is determined, and generate an automatic layout solution.

[0147] In the embodiment of the present application, the automatic layout device continues to repeatedly execute the layout process shown in step S22 on the basis that node B3 is the first target child node until the layout of all devices is completed.

[0148] The automatic layout method of this application has higher solution efficiency. Compared with the traditional heuristic algorithm that directly performs combinatorial optimization of the layout graph, the heuristic dynamic strategy + MCTS algorithm is applied to the strategy action generation and layout search links respectively, which effectively narrows the solution space and reduces the difficulty of solution. Real-time feedback evaluation and dynamic strategy help the algorithm converge quickly. The staged and scaled layout scheme further reduces the complexity of the layout problem and is more in line with the design experience of human engineers.

[0149] The automatic layout method of the present application has better layout quality and stability. Real-time feedback and adjustment are performed during the layout process to ensure that the layout is performed within the constraints of the rules. In the present application, the rules are not only constraints, but also become clear actions to guide the execution of the layout after being converted into strategies, which improves the effectiveness of the automatic layout and makes it easier for the layout results to meet the design specifications. Compared with the automatic layout of heuristic algorithms and deep learning solutions, the layout quality of the present application is more stable, because the execution strategies converted from similar rules are similar, and the layout results of similar circuits have a higher consistency, avoiding the situation where the layout results of similar circuits are very different.

[0150] The automatic layout method of this application can more flexibly adapt to various complex layout problems. Object-oriented rule design allows the algorithm to accurately match the applicable rules of devices or networks. The algorithm can combine rich rules and strategies to deal with complex constrained circuits. At the same time, dynamic real-time adjustment can quickly respond to changes in layout status. The algorithm has high adaptability and engineering practicality.

[0151] The automatic layout method of this application is easier to expand layout scenarios. The algorithm-independent rule manager is loosely coupled with the main automatic layout algorithm. When faced with new layout scenarios or new rules, engineers can quickly add them to the library. The object-oriented design facilitates the derivation of rules, and the rule application and management are flexible, making it easier to expand the applicable scenarios of this automatic layout solution.

[0152] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0153] In order to realize the above automatic layout method, the present application also proposes an automatic layout device for a circuit board. Fig.12 , Fig.12 It is a structural schematic diagram of an embodiment of an automatic layout device for a circuit board provided in the present application.

[0154] The automatic layout device 500 of this embodiment includes: a data module 51 , a strategy module 52 , a solution module 53 , and an optimization module 54 .

[0155] Wherein, the data module 51 is used to obtain the graphic structure data of the circuit board.

[0156] The strategy module 52 is used to generate a layout strategy based on the layout rules of the components in the circuit board in the current layout stage.

[0157] The solution module 53 is used to automatically layout the graph structure data according to the layout strategy and obtain an automatic layout solution.

[0158] The optimization module 54 is used to optimize the rule parameters in the layout strategy by using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is terminated and the current automatic layout solution is output.

[0159] In order to realize the above automatic layout method, the present application also proposes an automatic layout device for a circuit board, for details, please refer to Fig.13 , Fig.13 It is a structural schematic diagram of an embodiment of an automatic layout device for a circuit board provided in the present application.

[0160] The automatic layout device 400 of this embodiment includes a processor 41 , a memory 42 , an input / output device 43 , and a bus 44 .

[0161] The processor 41 , the memory 42 , and the input / output device 43 are respectively connected to the bus 44 . The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the automatic layout method described in the above embodiment.

[0162] In the embodiment of the present application, the processor 41 may also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip having the ability to process signals. The processor 41 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or the processor 41 may also be any conventional processor, etc.

[0163] This application also provides a computer storage medium, please continue to refer to Fig.14 , Fig.14 It is a structural diagram of an embodiment of a computer storage medium provided in the present application. The computer storage medium 600 stores a computer program 61. When the computer program 61 is executed by a processor, it is used to implement the automatic layout method of the above embodiment.

[0164] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program code.

[0165] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for automatic layout of a circuit board, characterized in that: The automatic layout method comprises: Acquire graph structure data of the circuit board; In the current layout stage, a layout strategy is generated based on the layout rules of the components in the circuit board; Automatically layout the graph structure data according to the layout strategy to obtain an automatic layout solution; Optimizing the rule parameters in the layout strategy using the evaluation feedback of the automatic layout solution to generate a new layout strategy, until the current layout stage is terminated and the current automatic layout solution is output; The optimizing the rule parameters in the layout strategy by using the evaluation feedback of the automatic layout solution to generate a new layout strategy includes: Obtaining the satisfaction degree of each layout rule and the rule weight of each layout rule under the layout strategy; Using the satisfaction degree and the rule weight, obtaining a fitness value of the automatic layout solution; The rule configuration data, rule weight, and / or rule priority in the rule parameters are optimized based on the fitness value to generate a new layout strategy.

2. The automatic layout method according to claim 1, characterized in that: The step of obtaining the graph structure data of the circuit board includes: Obtaining schematic information and board frame information of the circuit board; Based on the schematic diagram information and the board frame information, generating original diagram structure data; The chip and connector device nodes in the original graph structure data are used as module core nodes to perform a recursive search, traverse all associated devices, and obtain the functional module graph structure data.

3. The automatic layout method according to claim 1, characterized in that: The current layout stage is a module layout stage or a global layout stage; The output of the current automatic layout solution includes: In response to the current layout stage being the module layout stage, generating a global layout strategy using the layout rules of the devices in the current automatic layout scheme of each functional module; Automatically layout the graph structure data according to the global layout strategy to obtain a global layout solution; The evaluation feedback of the global layout solution is used to optimize the rule parameters in the global layout strategy to generate a new global layout strategy, until the global layout stage is ended and a final automatic layout solution is output.

4. The automatic layout method according to claim 1, characterized in that: The layout rules include basic layout rules and advanced layout rules, wherein the basic layout rules are physical constraints of the device, and the advanced layout rules are module rules of the device.

5. The automatic layout method according to claim 1 or 4, It is characterized in that Wherein, the layout rule is a normative rule and / or an empirical rule; The generating of the layout strategy based on the layout rules of the devices in the circuit board comprises: Converting layout rules of devices in the circuit board into execution actions; A layout strategy is generated based on the execution actions of the components in the circuit board.

6. The automatic layout method according to claim 1, characterized in that: The automatically laying out the graph structure data according to the layout strategy to obtain an automatic layout solution includes: Selecting an initialization node from the graph structure data; Execute the layout process with the initialization node as the layout starting point to determine the first target child node; Continue to execute the layout process with the first target sub-node as the layout starting point, determine the second target sub-node, until the layout status of all devices is determined, and generate the automatic layout solution; The layout process includes: according to the layout strategy and the initialization node, selecting a device connected to a device in the initialization node to expand a first child node; Get the upper limit of the confidence interval of each first child node; Search other child nodes according to the first child node of the upper limit of the maximum confidence interval until all devices are traversed; The confidence interval upper limit of each first sub-node is re-acquired, and the first sub-node with the maximum confidence interval upper limit is determined as the first target sub-node.

7. An automatic layout device for a circuit board, characterized in that: The automatic layout device includes: a data module, a strategy module, a solution module, and an optimization module; wherein, The data module is used to obtain the graphic structure data of the circuit board; The strategy module is used to generate a layout strategy based on the layout rules of the components in the circuit board in the current layout stage; The solution module is used to automatically layout the graph structure data according to the layout strategy and obtain an automatic layout solution; The optimization module is used to optimize the rule parameters in the layout strategy by using the evaluation feedback of the automatic layout solution to generate a new layout strategy until the current layout stage is ended and the current automatic layout solution is output; The optimization module is further used to obtain the satisfaction degree of each layout rule and the rule weight of each layout rule under the layout strategy; obtain the fitness value of the automatic layout scheme using the satisfaction degree and the rule weight; and optimize the rule configuration data, rule weight, and / or rule priority in the rule parameters based on the fitness value to generate a new layout strategy.

8. An automatic layout device for a circuit board, characterized in that: The automatic layout device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the automatic layout method as described in any one of claims 1 to 6.

9. A computer storage medium, characterized in that The computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the automatic layout method according to any one of claims 1 to 6.

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