Local search term updating method and circuit of global interconnection Isin architecture computing system based on DRAM (Dynamic Random Access Memory)
By designing a local search term update method and circuit for the global interconnection Isin architecture computing system based on DRAM, and using components such as addition modules and sensitive amplifiers, the problem of lack of DRAM in the existing technology to realize global interconnection system is solved, and efficient local search term update and synchronization is achieved, which is suitable for modern high-density DRAM design.
Patent Information
- Application Number
- CN202410861072.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-03-07
AI Technical Summary
The prior art lacks the structural design of the global interconnected Isin architecture computing system based on DRAM, which makes it difficult to implement a large-scale spin system, and the overhead of local search circuits is relatively large, making it difficult to apply to the addition tree to implement on DRAM.
A local search term update method and circuit for a globally interconnected Isin architecture computing system based on DRAM is designed. Using circuit components such as addition module, NOT row, data bypass and sensitive amplifier, rapid local search term update and synchronization are achieved through addition operations and carry propagation.
It realizes the local search term update method and circuit with low cost, high interconnection and efficient solution speed, reduces circuit area consumption, quickly calculates and synchronizes local search terms, saves annealing time, and meets the design requirements of implementing global interconnection Isin architecture computing system based on DRAM.
Smart Images
Figure CN119578577A_ABST
Abstract
Description
Technical Field
[0001] The present invention mainly relates to the field of computer technology, and in particular to a local search item updating method and circuit of a DRAM-based global interconnected Ising architecture computing system. Background Art
[0002] In order to solve combinatorial optimization problems with higher complexity and larger problem scale, it is necessary to realize a larger-scale CMOS Ising architecture computing system. The current Ising architecture computing system has a small number of spins, especially the number of spins of the Ising architecture computing system that realizes global interconnection. The Ising architecture computing system that realizes global interconnection has a small number of spins, which makes it difficult to solve large-scale combinatorial optimization problems. However, the mapping and solution of most combinatorial optimization problems require a globally connected Ising architecture. Although current researchers have made innovations in structures such as spin updaters and reduced some overhead, they still mainly expand the CMOS Ising architecture computing system by increasing the storage capacity of SRAM.
[0003] Since most chips rely on SRAM storage, the increase in spin scale is bound to increase the capacity of SRAM, and the increase in SRAM capacity will bring non-negligible power consumption and area overhead. Therefore, it is still difficult for the current Ising chip to realize a large-scale spin system. The capacity of the spin system built based on SRAM is limited, and the scale of the problem that can be solved is often small, and its practicality is limited. In order to realize a highly integrated Ising architecture computing system, it is necessary to implement the Ising architecture computing system on DRAM. However, there is a lack of research on Ising architecture computing systems based on DRAM in the academic community, especially the local search item update circuit that is closely related to spin updates. Most systems are still based on adder trees to implement spin updates. This results in the local search circuit overhead accounting for too large a proportion, and it is not suitable to use adder trees to implement local search circuits on DRAM.
[0004] DRAM has the characteristics of high integration density, mature production and low cost, making it more suitable for realizing globally interconnected Ising architecture computing systems than SRAM. Ising architecture computing systems need to update spin states when solving combinatorial optimization problems. Updating spin states includes two key steps: local search and probability flipping. The local search items of each spin are related to the spin state of the connection. When the spin state of the connection changes, its own local search items need to be performed. To realize a globally interconnected Ising architecture computing system on DRAM, it is necessary to design a local search item update circuit that matches the characteristics of DRAM to perform local search. However, on the one hand, the existing technology has not yet realized a global interconnection system on DRAM, and on the other hand, it also lacks a local search item update circuit based on DRAM.
[0005] In summary, the prior art lacks the structural design of a globally interconnected Ising architecture computing system based on DRAM. Due to the speed difference caused by the inherent properties of DRAM storage and SRAM storage, the access time of DRAM is usually longer than that of SRAM. Therefore, finding a fast spin update and a method for synchronizing local search items is very important for accelerating annealing calculations. The basic unit of DRAM is a capacitor and a switching transistor, which have relatively small area and power consumption. This feature requires that the design of the local search item update circuit needs to minimize the area and power consumption. In addition, DRAM is a traditional storage element, and the production process is already very mature, so the changes to DRAM must be small and must be compatible with the DRAM memory structure. Summary of the invention
[0006] The technical problem to be solved by the present invention is to provide a local search item updating method and circuit for a DRAM-based globally interconnected Ising architecture computing system with low cost, high interconnection degree and high solving speed in view of the deficiencies in the prior art.
[0007] In order to solve the above technical problems, the present invention adopts the following technical solutions: A local search term updating method of a DRAM-based global interconnected Ising architecture computing system, comprising: Step S1: Use the addition module to complete the addition operation; Based on the basic logic operation and circuit of the bit line, a transistor is provided at one end connected to and storage cell capacitors to form a NOT row to implement NOT operations; a data bypass and a sensitive amplifier are set between the two bit lines to complete the carry calculation by controlling the corresponding transistors; the SHF row is set for carry propagation of the look-ahead carry; the sensitive amplifier is shared by the two sub-arrays, bitline and It is relative, and the mirror function is realized through the sensitive amplifier and four transistors; when a carry occurs, only when P=1 will the adjacent bit line turn on the transmission transistor for data transmission; Step S2, performing negation operation and addition calculation; Step S3: After calculating the local search term, synchronize the new local search term. As a further improvement of the method of the present invention, in step S1, one end of the switching transistor of the SHF16 row is connected to the capacitor of the source storage unit, and the other end is connected to the storage unit bit line of the same corresponding bit of the other 15 local search items, and the corresponding 32 SHF16 transistors of the same local search item are switched by the same control signal. As a further improvement of the method of the present invention, in step S1, the addition calculation includes three stages. The first stage is to generate G and P using basic logical operations. The second stage is to generate carry signals for each bit inside the improved sensitive amplifier and in the added circuit. The third stage is to calculate P and The XOR of is used to obtain the final calculation result. The specific implementation formula is as follows: (Formula 1). As a further improvement of the method of the present invention, in step S2, the addition is based on the basic logic operation and circuit of the bit line, and a transistor is added to connect one end of the bit line to the and storage unit capacitors to form a NOT row, thereby realizing a NOT operation. As a further improvement of the method of the present invention, in step S3, the process of calculating the local search item is divided into three stages. The first stage and the third stage use large-scale logic operations on bit lines to respectively calculate the corresponding G and P and the final addition result. The second stage uses the added logic circuit to calculate the carry C. As a further improvement of the method of the present invention, when the local search item is calculated, the corresponding 0th local search item needs to be synchronized to other local search items, that is, open After that, turn on the sensitive amplifier and turn off the sensitive amplifier after the data is stable. , and finally turn on the word line to write the bit line data into the memory cell. The present invention further provides a local search item update circuit of a DRAM-based globally interconnected Ising architecture computing system, wherein one end of a switch transistor of a SHF16 row is connected to a capacitor of a source storage unit, and the other end is connected to a storage unit bit line of the same corresponding bit of other 15 local search items, and the corresponding 32 SHF16 transistors of the same local search item are switched and controlled by the same control signal.
[0008] As a further improvement of the circuit of the present invention, whether the local search item is valid is related to the number of the selected spin, that is, the position of the interaction coefficient corresponding to the selected spin; if the selected spin number is 0, the calculation of the 0th local search item is valid; when the local search item is calculated, the corresponding 0th local search item is synchronized to other local search items, that is, open After that, turn on the sensitive amplifier and turn off the sensitive amplifier after the data is stable. , and finally turn on the word line to write the bit line data into the memory cell.
[0009] As a further improvement of the circuit of the present invention, after precharging, the word line of the SHF16 row is turned on, the voltage of the storage cell mb0 connected to one end of the SHF drops significantly, and the voltage of all the bit lines of the target cell increases. After turning on the sensitive amplifier, the voltage of the source storage cell mb0 and the bit line of the target storage cell can rise to VDD, which indicates that the data can be transmitted correctly and the data itself remains unchanged, which is in line with expectations. Subsequently, the word line and the sensitive amplifier of the local search item LC row are turned on to store the data on the bit line into the cell, thus completing the synchronous local search item.
[0010] As a further improvement of the circuit of the present invention, based on the basic logic operation and circuit of the bit line, a transistor is provided with one end connected to and storage cell capacitors to form a NOT row to implement NOT operations; a data bypass and a sensitive amplifier are set between the two bit lines to complete the carry calculation by controlling the corresponding transistors; the SHF row is set for carry propagation of the look-ahead carry; the sensitive amplifier is shared by the two sub-arrays, bitline and It is relative, and the mirror function is realized through the sensitive amplifier and four transistors; when a carry occurs, only when P=1 will the adjacent bit line turn on the transmission transistor for data transmission; Compared with the prior art, the advantages of the present invention are: 1. The local search item updating method and circuit of the DRAM-based globally interconnected Ising architecture computing system of the present invention have low cost, high interconnection degree, and efficient solution speed. The circuit designed by the present invention consumes little area, can quickly calculate and synchronize local search items, can save annealing time, and can meet the design requirements of the DRAM-based globally interconnected Ising architecture computing system.
[0011] 2. The local search item update method and circuit of the DRAM-based global interconnected Ising architecture computing system of the present invention implements the negation operation and addition calculation of the global interconnected CMOS Ising architecture computing system, which is mainly based on a DRAM-based carry-lookahead adder method and is improved to make it applicable to modern high-density DRAM design. At the same time, this paper modifies some transistors in the addition module to make it transmit data more accurately. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 The figure is a schematic diagram of a specific circuit principle of a global interconnection system subarray in a specific embodiment of the present invention.
[0013] Figure 2 A schematic diagram of LTspice simulation results for generating carry for local search calculation in a specific embodiment of the present invention.
[0014] Figure 3Schematic diagram of the SHF16 row circuit for synchronizing local search items in a specific embodiment of the present invention.
[0015] Figure 4 Schematic diagram of LTspice simulation results of SHF16 row in a specific embodiment of the present invention. DETAILED DESCRIPTION
[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0017] The present invention designs a local search term update method and circuit for a DRAM-based global interconnected Ising architecture computing system. In the global interconnected system, if the selected spin changes its spin state, all other spins need to recalculate their local search terms. The local search term calculation needs to be calculated according to the following formula (1.1), because The value of has only two cases, "+1" and "-1", so the calculation of the local search term can be simplified to the negation operation and the addition operation.
[0018]
[0019] (1.1) The invention realizes the negation operation and addition operation of the global interconnected CMOS Ising architecture computing system, which is mainly based on a method of DRAM-based carry-lookahead adder and is improved to be applicable to modern high-density DRAM design. At the same time, the invention modifies some transistors in the addition module to make it transmit data more accurately.
[0020] In the technical solution of the present invention, the first stage of addition calculation is to generate G and P using basic logic operations, the second stage is to generate carry signals of each bit inside the improved sensitive amplifier and the added circuit, and the third stage is to calculate P and The XOR of is used to obtain the final calculation result. The specific implementation formula is as follows:
[0021] In the system of the present invention, two sub-arrays reuse half-row sensitive amplifiers, and the specific circuits modified by the sub-arrays are as follows: Figure 1 This addition is based on the basic logic operation of the bit line and the circuit, adding a transistor at one end to connect The NOT row is composed of the storage cell capacitors and the storage cell capacitors to realize the NOT operation. A data bypass is added between the two bit lines and the sensitive amplifier is modified to complete the carry calculation by controlling the corresponding transistors. The added SHF row is mainly used for carry propagation of carry lookahead. The sensitive amplifier is shared by two sub-arrays, bitline and It is relative, for example, the bitline of subarray1 is also the bitline of subarray0. Therefore, this part adds four transistors to the sensitive amplifier to realize the mirror function. When a carry occurs, only when P=1 will the adjacent bit line turn on the transmission transistor for data transmission. In order to more accurately transmit the "1" data to turn on the transistor connecting the two bit lines, the present invention changes the T4 transistor in the figure to PMOS.
[0022] In the technical solution of the present invention, the specific process of calculating the local search term can be roughly divided into three stages, wherein the first and third stages use bit line bulk logic operations to respectively calculate the corresponding G and P and the final addition result, and the second stage uses the added logic circuit to calculate the carry C. Figure 2 The simulation results of the second-stage addition module of LTspice simulation for the generation of carry are shown, where the 0th bit G0 = 1, P0 = 0, and the 1st bit G1 = 0, P1 = 1. In this case, since P1 = 1, a transmission channel is formed between the 0th bit and the 1st bit SA, and since G0 = 1, the 0th bit will transmit data 1 to the 1st bit, that is, C1 is 1.
[0023] like Figure 2 , first activate the spin of the row where G is located, and then turn on the sense enable to read G to the bit line. When the sense enable is turned on for the first time, the bit line bitline0-0 where the 0th bit is located is 1, and the bit line bitline0-1 where the 1st bit is located is 0. After PEN0 is enabled and PCB is enabled, a carry begins to occur, and the bit line inverted bieline1-1 of the 1st bit drops to the same 0 potential as the bit line inverted bitline1-0 of the 0th bit. After the sense enable is turned on again, the bit lines of the 0th and 1st bits are both at the expected potential, that is, both are 1. After a carry is generated on the bit line, the value on the bit line is written to the SHF row, and the carry is shifted left to the high bit, and then the third stage of operation is started, and the result of addition is finally obtained.
[0024] For a 512*512 size subarray, the storage capacity of each row is sufficient to store 16 32-bit wide local search items. During a spin update, only one of the local search items is effectively calculated. Therefore, after the calculation is completed, the new local search item needs to be synchronized to the other local search items in the row.
[0025] Furthermore, the present invention designs a SHF16 row, that is, a row of transistors is added on the basis of a DRAM storage row. This design solves the synchronization problem and ensures that all local search items can be updated promptly and accurately after each spin update.
[0026] The specific circuit of the present invention is as follows Figure 3As shown, one end of the switch transistor of the SHF16 row is connected to the capacitor of the source storage unit, and the other end is connected to the storage unit bit line of the same corresponding bit of the other 15 local search items. The corresponding 32 SHF16 transistors of the same local search item are switched by the same control signal. For example, the 32 SHF16 transistors of the 0th local search item are controlled by the same control signal. Control, similarly, the ath local search item is controlled by Control. Whether the local search item is valid depends on the number of the selected spin, that is, the position of the interaction coefficient corresponding to the selected spin. If the selected spin number is 0, the calculation of the 0th local search item is valid. When the local search item is calculated, the corresponding 0th local search item needs to be synchronized to other local search items, that is, open After that, turn on the sensitive amplifier and turn off the sensitive amplifier after the data is stable. , and finally turn on the word line to write the bit line data into the memory cell.
[0027] After calculating the local search term, the new local search term needs to be synchronized. Figure 4 The LTspice simulation results of the SHF16 row circuit are presented, indicating that the SHF16 is able to transfer local search item data to the other 15 storage locations without affecting the correctness of its own stored data.
[0028] After precharging, the word line of SHF16 is turned on, and the voltage of the storage cell mb0 connected to one end of SHF drops significantly, while the voltage of all bit lines of the target cell (only bitline0-1 and bitline0-15 are shown) rises. After turning on the sensitive amplifier, the voltage of the source storage cell mb0 and the bit line of the target storage cell can rise to VDD, which indicates that the data can be transmitted correctly and the data itself remains unchanged, which is in line with expectations. Then, the word line and sensitive amplifier of the local search item LC row are turned on to store the data on the bit line into the cell, completing the synchronous local search item.
[0029] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.
Claims
1. A local search term update method for a DRAM-based global interconnected Ising architecture computing system, characterized in that: include: Step S1: using the addition module to complete the addition operation; Based on the basic logic operation and circuit of bit line, a transistor is connected at one end and storage cell capacitors to form a NOT row to implement NOT operations; a data bypass and a sensitive amplifier are set between the two bit lines to complete the carry calculation by controlling the corresponding transistors; the SHF row is set for carry propagation of the look-ahead carry; the sensitive amplifier is shared by the two sub-arrays, bitline and It is relative, and the mirror function is realized through the sensitive amplifier and four transistors; when a carry occurs, only when P=1 will the adjacent bit line turn on the transmission transistor for data transmission; Step S2, performing negation operation and addition calculation; Step S3: After calculating the local search term, synchronize the new local search term.
2. The local search term updating method of the DRAM-based global interconnected Ising architecture computing system according to claim 1, characterized in that: In step S1, one end of the switch transistor of the SHF16 row is connected to the capacitor of the source storage unit, and the other end is connected to the storage unit bit line of the same corresponding bit of the other 15 local search items. The corresponding 32 SHF16 transistors of the same local search item are switched by the same control signal.
3. The local search term updating method of the DRAM-based global interconnected Ising architecture computing system according to claim 1, characterized in that: In step S1, the addition calculation includes: Step S101: Generate G and P using basic logic operations; Step S102: generating a carry signal of each bit inside the sensitive amplifier and in the added circuit; Step S103: Calculate the XOR of P and $C_{in}$ to obtain the final calculation result, as follows: 。 4. The local search term updating method of the DRAM-based global interconnected Ising architecture computing system according to claim 3, characterized in that: In step S2, the addition is based on the basic logic operation and circuit of the bit line, and a transistor is added to connect one end of the transistor to the and storage unit capacitors to form a NOT row for implementing a NOT operation.
5. The local search term updating method of the DRAM-based global interconnected Ising architecture computing system according to claim 4, characterized in that: In step S3, the process of calculating the local search term includes three stages, wherein the first and third stages use bit line bulk logic operations to respectively calculate the corresponding G and P and the final addition result, and the second stage uses the added logic circuit to calculate the carry C.
6. The local search term updating method of the DRAM-based global interconnected Ising architecture computing system according to claim 5, characterized in that: When the local search item is calculated, the corresponding 0th local search item needs to be synchronized to other local search items, that is, open After that, turn on the sensitive amplifier and turn off the sensitive amplifier after the data is stable. , and finally turn on the word line to write the bit line data into the memory cell.
7. A local search term update circuit for a DRAM-based global interconnected Ising architecture computing system, characterized in that: One end of the switch transistor of the SHF16 row is connected to the capacitor of the source storage unit, and the other end is connected to the storage unit bit line of the same corresponding bit of the other 15 local search items. The corresponding 32 SHF16 transistors of the same local search item are switched by the same control signal.
8. The local search term update circuit of the DRAM-based global interconnected Ising architecture computing system according to claim 7, characterized in that: Whether the local search item is valid depends on the number of the selected spin, that is, the position of the interaction coefficient corresponding to the selected spin; if the selected spin number is 0, the calculation of the 0th local search item is valid; when the local search item is calculated, the corresponding 0th local search item is synchronized to other local search items, that is, open After that, turn on the sensitive amplifier and turn off the sensitive amplifier after the data is stable. , and finally turn on the word line to write the bit line data into the memory cell.
9. The local search term update circuit of the DRAM-based global interconnected Ising architecture computing system according to claim 7, characterized in that: After precharging, the word line of the SHF16 row is turned on, and the voltage of the storage cell mb0 connected to one end of the SHF drops significantly, while the voltage of all the bit lines of the target cell increases. After turning on the sensitive amplifier, the voltage of the source storage cell mb0 and the bit line of the target storage cell can rise to VDD, which indicates that the data can be transmitted correctly and the data itself remains unchanged, which is in line with expectations. Subsequently, the word line and sensitive amplifier of the local search item LC row are turned on to store the data on the bit line into the cell, thus completing the synchronous local search item.
10. The local search term update circuit of the DRAM-based global interconnected Ising architecture computing system according to claim 7, characterized in that: Based on the basic logic operation and circuit of bit line, a transistor is connected at one end and storage cell capacitors to form a NOT row to implement NOT operations; a data bypass and a sensitive amplifier are set between the two bit lines to complete the carry calculation by controlling the corresponding transistors; the SHF row is set for carry propagation of the look-ahead carry; the sensitive amplifier is shared by the two sub-arrays, bitline and It is relative, and the mirror function is realized through a sensitive amplifier and four transistors; when a carry occurs, only when P=1 will the adjacent bit line turn on the transfer transistor for data transmission.