Driving circuit, display panel and driving method

Abstract

The invention provides a driving circuit, a display panel and a driving method.The driving circuit comprises a controller, a plurality of first scanning lines and a plurality of second scanning lines, the first scanning lines and the second scanning lines extend in the second direction, the controller is electrically connected with the second scanning lines, and the controller is configured as follows: in any two adjacent rows of first row pixel units and M rows of second row pixel units between the two adjacent rows of first row pixel units, M is a positive integer; under the condition that any first scanning line transmits a first scanning signal to start the corresponding first row of pixel units to display a first gray-scale value N1, the controller is further used for inputting a second scanning signal to the second scanning line, and the second scanning signal is used for starting the second row of pixel units to display a second gray-scale value N2; n2 = i * N1 / (M + 1). In the application, the interpolation gray-scale value based on the gray-scale value of the first row of pixel units is allocated to the second row of pixel units, so that smoother image transition can be realized, and particularly, when a high-contrast image is displayed, zigzag edges are reduced, and the image quality in an HSR display mode is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit, a display panel and a driving method. Background Art

[0002] The display industry is now pursuing higher and higher refresh rates, and it is becoming more and more common to use frequency doubling technology to increase the refresh rate of TV displays, such as HSR (Hardware Super Resolution) technology.

[0003] HSR is a technology that uses low refresh to drive high refresh displays. For example, a 4K×2K UHD 60Hz display can be displayed as a 4K×1K UHD 120Hz display by adjusting the timing. A 4K×2K UHD 120Hz display can be displayed as a 4K×1K UHD240Hz display by adjusting the timing. Because the total amount of data displayed is the same, the specifications of the driving components are the same. The refresh rate can be doubled only by adjusting the timing, but some resolution is also sacrificed.

[0004] At present, in order to improve the display clarity under HSR technology, the long-brightness display screen adjusts the Gn (scanning data) phase to charge the even-numbered row pixels with a portion of the grayscale voltage of the previous odd-numbered row pixels, and then charges a portion of the grayscale voltage of the next odd-numbered row pixels. After neutralization, the grayscale displayed by the even-numbered row pixels is roughly realized, so as to blur the boundary position with large contrast difference, making the image boundary smoother. However, in the direct display screen with PWM (Pulse-Width Modulation) dimming, there is no charging process, and the grayscale is realized by controlling the length of the bright and dark time, and the display data cannot be increased. Therefore, the middle value when the two adjacent odd-numbered row pixels display different grayscales by adjusting the Gn phase to realize the display of even-numbered row pixels is not applicable to the direct display screen with PWM dimming. That is, when the direct display screen with PWM dimming realizes HSR, jagged edges are prone to appear at the boundary position with large contrast difference during display, which reduces the overall quality of the image. Summary of the invention

[0005] The present application provides a driving circuit, a display panel and a driving method that are beneficial to improving image quality under HSR technology.

[0006] In a first aspect, an embodiment of the present application provides a driving circuit, which is applied to a display panel, wherein the display panel includes a plurality of pixel units arranged in a periodic array along a first direction and a second direction, wherein in the second direction, a plurality of rows of pixel units include a first row of pixel units and a second row of pixel units, and M rows of the second row of pixel units are arranged between each two adjacent first row of pixel units; the driving circuit includes:

[0007] a plurality of first scan lines and second scan lines extending along a second direction, each row of the first row of pixel units being connected to a corresponding first scan line, and each row of the second row of pixel units being connected to a corresponding second scan line;

[0008] a controller, the controller being electrically connected to the second scan line, the controller being configured to: in any two adjacent rows of the first row pixel units and the M rows of the second row pixel units therebetween, when any of the first scan lines transmits a first scan signal to start the corresponding first row pixel unit to display a first grayscale value N1, the controller is further used to input a second scan signal to the second scan line, the second scan signal being used to start the second row pixel unit to display a second grayscale value N2, N2=i*N1 / (M+1);

[0009] Wherein, M is a positive integer, i is the serial number of the second row of pixel units, and the serial numbers of the second row of pixel units increase along the direction approaching the activated first row of pixel units, and i is a positive integer.

[0010] According to the first aspect, in a possible implementation manner, the first scan lines and the second scan lines are alternately arranged, the first row of pixel units are odd-numbered row of pixel units, and the second row of pixel units are even-numbered row of pixel units.

[0011] According to the first aspect, in a possible implementation, the controller includes multiple control units, each second scan line is electrically connected to a corresponding one of the control units, the control unit includes a first switching transistor and a second switching transistor arranged in parallel, the input ends of the first switching transistor and the second switching transistor are electrically connected to the third scan line, and the output ends of the first switching transistor and the second switching transistor are electrically connected to the corresponding second scan line; the control end of the first switching transistor is electrically connected to one of the first scan lines adjacent to the second scan line, and the control end of the second switching transistor is electrically connected to another of the first scan lines adjacent to the second scan line.

[0012] According to the first aspect, in a possible implementation, the driving circuit further includes a switching unit, the first scan line and the second scan line are both electrically connected to a scan driver, and the switching unit is configured to control the driving circuit to switch between a first mode and a second mode; when the driving circuit is in the first mode, the scan driver transmits a first scan signal to the first scan line row by row to start the odd-row pixel unit and the two even-row pixel units adjacent to the odd-row pixel unit; when the driving circuit is in the second mode, the scan driver transmits a third scan signal to the first scan line and the second scan line row by row to start the pixel units row by row.

[0013] According to the first aspect, in a possible implementation, a third switching transistor is provided on the second scanning signal, the third switching transistor is located between the connection point between the scanning driver and the control unit, and the control end of the third switching transistor is electrically connected to the switching unit.

[0014] According to the first aspect, in a possible implementation, a fourth switch transistor is provided on the control unit, the fourth switch transistor is located between the input end of the first switch transistor and the third scan line, and the control end of the fourth switch transistor is electrically connected to the switching unit.

[0015] According to the first aspect, in a possible implementation, the switching unit includes a first control line and a second control line, each of the third switching transistors is connected to the first control line, and each of the fourth switching transistors is connected to the second control line; the first control line is used to output a low level, and the second control line is used to output a high level to control the drive circuit to switch to a first mode; the first control line is used to output a high level, and the second control line is used to output a low level to control the drive circuit to switch to a second mode.

[0016] In a second aspect, an embodiment of the present application further provides a display panel, which includes a plurality of pixel units distributed in an array and the driving circuit described in the first aspect, wherein pixel units in the same row are connected to the same scan line.

[0017] In a third aspect, an embodiment of the present application further provides a driving method, which is applied to the driving circuit described in the first aspect, and the driving method includes:

[0018] Acquire first image data corresponding to the first row of pixel units according to the original image data, where the first image data includes timing information and a target grayscale value N;

[0019] When the display mode of the display panel is HSR, according to the timing information, a first scanning signal is input to the first scanning line in a preset time period to start the corresponding first row of pixel units to display a first grayscale value N1;

[0020] In any two adjacent rows of the first row of pixel units and the M rows of the second row of pixel units therebetween, when any of the first row of pixel units displays the first grayscale value N1, a second scanning signal is input to the second scanning line to enable the second row of pixel units to display the second grayscale value N2, where N2=i*N1 / (M+1);

[0021] Wherein, M is a positive integer, i is the serial number of the second row of pixel units, and the serial numbers of the second row of pixel units increase along the direction approaching the activated first row of pixel units, and i is a positive integer.

[0022] According to the third aspect, in a possible implementation manner, the driving method further includes:

[0023] Dividing the original image data into odd-numbered frame image data and even-numbered frame image data;

[0024] In a first frame display period, starting a first row of pixel units with the odd-numbered frame image data as first image data;

[0025] In a second frame display period, starting the first row of pixel units with the even-numbered frame image data as the first image data;

[0026] The first frame display period and the second frame display period are two adjacent frame display periods.

[0027] The driving circuit, display panel and driving method provided by the present application can achieve smoother image transition, especially when displaying high-contrast images, by assigning interpolated grayscale values ​​based on the grayscale values ​​of the first row of pixel units to the second row of pixel units. This not only improves the fineness of the image, but also improves the image quality in the HSR display mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 is a circuit diagram of a driving circuit and a pixel unit in an embodiment of the present application;

[0030] Figure 2 is a circuit diagram of a driving circuit and a pixel unit in another embodiment of the present application;

[0031] Figure 3 yes Figure 2 The signal timing diagram in the embodiment shown;

[0032] Figure 4 It is a flowchart of a driving method in an embodiment of the present application.

[0033] Reference numerals:

[0034] 10-pixel unit; 10a-first row pixel unit; 10b-second row pixel unit; 20-control unit; 30-switching unit; 40-scan driver; X1-first control line; X2-second control line; V+-third scan line; T1-first switch transistor; T2-second switch transistor; T3-third switch transistor; T4-fourth switch transistor; G1-first scan line; G2-second scan line; OE-enable signal. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0036] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there can be a central component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there can be a central component at the same time.

[0037] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this application and in the specification are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this application includes any and all combinations of one or more of the related listed items.

[0038] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0039] The present application provides a display panel, such as Figure 1 As shown, the display panel includes a plurality of pixel units 10 distributed in an array and a driving circuit of the first aspect, and the pixel units 10 in the same row are connected to the same scan line. The driving circuit has a first mode and a second mode. When the driving circuit is in the first mode, the pixel units 10 in adjacent rows can work together through a specific signal processing algorithm and circuit design to jointly improve the refresh rate of the display panel, so that the display panel realizes the HSR display mode. When the driving circuit is in the second mode, the display panel will work in a traditional row-by-row scanning mode. In this mode, the pixel units 10 in each row will be activated in turn, and the picture will be displayed row by row in a top-to-bottom or left-to-right order.

[0040] A plurality of pixel units 10 are arranged in an array on the display panel, and these pixel units 10 are responsible for generating and displaying images. Each pixel unit 10 usually contains three sub-pixels of red (R), green (G), and blue (B) or other color combinations to present rich colors. The pixel units 10 in the same row are connected by the same scan line, which enables the driving circuit to control all pixel units 10 in a row at the same time. The function of the scan line is to sequentially activate each row of pixel units during the display process so as to form a complete image on the screen.

[0041] In one embodiment, the pixel units 10 are arranged in a periodic array along a first direction and a second direction to form a standard display matrix. In the second direction, the pixel units 10 are divided into two types of rows: first-row pixel units 10a and second-row pixel units 10b. M rows of second-row pixel units 10b are inserted between each two adjacent first-row pixel units 10a, where M is a positive integer. By controlling the grayscale of the first-row pixel units 10a and the second-row pixel units 10b, a smoother image transition can be achieved. The first direction is the row direction, and the second direction is the column direction.

[0042] The driving circuit includes a controller and a plurality of first scan lines G1 and second scan lines G2 extending along the second direction.

[0043] The number of the first scan lines G1 is consistent with the number of the first-row pixel units 10a. Each row of the first-row pixel units 10a is connected to a corresponding first scan line, and each row of the first-row pixel units 10a receives a scan signal through an independent first scan line G1.

[0044] The number of the second scan lines G2 is consistent with the number of the second-row pixel units 10b. Each row of the second-row pixel units 10b is connected to a corresponding second scan line, and each row of the second-row pixel units 10b receives a scan signal through an independent second scan line G2.

[0045] Each second scan line G2 is electrically connected to a control unit 20. The control units 20 send corresponding scan signals to the corresponding second scan lines G2 according to the signal state of the first scan lines G1.

[0046] For the convenience of illustration, in this application, two adjacent rows of first-row pixel units 10a and M rows of second-row pixel units 10b between them are taken as a display unit. In the case of the second mode, in a display unit, when any first scan line G1 transmits a first scan signal to start the corresponding first-row pixel unit 10a to display the first grayscale value N1, the controller in the adjacent M rows of second-row pixel units 10b will receive a trigger signal in some form, which can be a signal directly from the first scan line G1 or a signal generated by other logic circuits. The controller calculates the second grayscale value N2 to be displayed according to the number i of the started second-row pixel unit 10b. The calculation formula is N2=i*N1 / (M+1). The number i of the second-row pixel unit 10b increases along the direction close to the started first-row pixel unit 10a, and i is a positive integer; M is the number of rows of the inserted second-row pixel unit 10b. The control unit 20 then sends a second scan signal to the second scan line G2 to start the second-row pixel unit 10b to display the calculated grayscale value N2. Therefore, when displaying a high-contrast image, the aliasing effect can be reduced and the fineness of the image can be improved by adjusting the grayscale value of the second row of pixel units 10 b.

[0047] For example, two adjacent first-row pixel units 10a may be provided with three second-row pixel units 10b, forming a unit group consisting of five rows of pixel units; represented by 2n+1 to 2n+5 rows, where n is a natural number representing the position of the unit group in the overall pixel array. In the second mode, when any first scan line G1, for example, the first scan line G1 connected to the 2n+1 row of pixel units transmits a first scan signal to start the 2n+1 row of pixel units to display the first grayscale value N1, the controller receives a trigger signal and inputs a second scan signal to the second scan lines G2 corresponding to the 2n+2 row of pixel units, the 2n+3 row of pixel units, and the 2n+4 row of pixel units.

[0048] When the first grayscale value N1 is displayed in row 2n+1, taking row 2n+1 as the reference, the grayscale value N21=3*N1 / 4 displayed by row 2n+2, the grayscale value N22=N1 / 2 displayed by row 2n+3, and the grayscale value N23=N1 / 4 displayed by row 2n+4.

[0049] When the 2n+5th row displays the first grayscale value N1', taking the 2n+5th row of pixel units as a reference, the grayscale value displayed by the 2n+2th row of pixel units is N21'=N1' / 4, the grayscale value displayed by the 2n+3th row of pixel units is N22'=N1' / 2, and the grayscale value displayed by the 2n+4th row of pixel units is N23'=3*N1' / 4.

[0050] In one display cycle, the 2n+1 row displays the first grayscale value N1, the 2n+2 row of pixel units displays the grayscale value N2=N21+N21'=3N1 / 4+N1' / 4, the 2n+3 row of pixel units displays the grayscale value N3=N22+N22'=N1 / 2+N1' / 2, the 2n+4 row of pixel units displays the grayscale value N4=N23+N23'=N1 / 4+3*N1' / 4, and the 2n+5 row displays the first grayscale value N1'.

[0051] The 2n+5 row of pixel units also serves as the start of the next display unit, that is, when any first row of pixel units 10a is started, the multiple second pixel units 10 adjacent to it on both sides are all started. Thus, the three adjacent second row of pixel units 10b, that is, 2n+2 row of pixel units, 2n+3 row of pixel units, and 2n+4 row of pixel units realize a gradual transition from 2n+1 row of pixel units to 2n+5 row of pixel units. By assigning the interpolated grayscale value based on the grayscale value of the first row of pixel units 10a to the second row of pixel units 10b, a smoother image transition can be achieved, especially when displaying high-contrast images. This not only improves the fineness of the image, but also improves the image quality in the HSR display mode.

[0052] In other embodiments, the number of the second row of pixel units 10b inserted between two adjacent first row of pixel units 10a may be 1 row, 2 rows, 4 rows, 5 rows or even more, which is not limited in the present application.

[0053] In the above embodiment 1 example, Figure 2 and Figure 3 As shown, the first scanning line G1 and the second scanning line G2 are alternately arranged, the first row of pixel units 10a are odd-numbered pixel units, and the second row of pixel units 10b are even-numbered pixel units. That is, the first scanning line G1 scans the odd-numbered pixel units, and the second scanning line G2 scans the even-numbered pixel units. In order to reduce the aliasing in the high-contrast image, as shown in FIG. Figure 2As shown, in the five consecutive rows of pixel units (2n+1 rows of pixel units to 2n+5 rows of pixel units), the corresponding scan lines are represented by G2n+1 to G2n+5. When the 2n+3 row (odd row) of pixel units 10 displays the grayscale value N1, its adjacent even row of pixel units (2n+2 rows of pixel units and 2n+4 rows of pixel units) can respectively display a certain interpolation result of N1, such as N1 / 2. Thus, in a display unit, from the 2n+1 row of pixel units to the 2n+3 row of pixel units, when the 2n+1 row of pixel units is started, the 2n+2 row of pixel units is started, and the timing is consistent, and the brightness of the 2n+2 row of pixel units is half of the brightness of the 2n+1 row of pixel units; when the 2n+3 row of pixel units is started, the 2n+2 row of pixel units is started, and the timing is consistent, and the brightness of the 2n+2 row of pixel units is half of the brightness of the 2n+3 row of pixel units; the grayscale value is the integral of the brightness and time, that is, the grayscale value of the 2n+1 row of pixel units is N1, the grayscale value of the 2n+3 row of pixel units is N1', and the grayscale value of the 2n+2 row of pixel units is (N1+N1') / 2. It can be understood that the 2n+3 row of pixel units also serves as the starting point of the next display unit, that is, the grayscale value of the 2n+4 row of pixel units is the intermediate grayscale value of the grayscale values ​​of the 2n+3 row of pixel units and the 2n+5 row of pixel units. In this way, for any two adjacent odd-numbered row of pixel units and the even-numbered row of pixel units between them, the even-numbered row of pixel units can display the intermediate grayscale value of the two odd-numbered row of pixel units.

[0054] in, Figure 3 OE is an enable signal, which is usually transmitted to the driver chip of the display panel together with the data signal and the control signal. When the enable signal OE is at a high level, the driver chip receives and processes the data signal to control whether the pixel unit 10 on the display panel is lit.

[0055] Therefore, in the PWM dimming direct display screen, the voltage of the scanning signal Gn and the driving signal Sn is constant, and different grayscales are achieved by adjusting the length of the bright and dark time. It is constant in brightness when it is bright and black when it is dark. In this application, Sn does not change at all. By adjusting the scanning signal voltage corresponding to the second row of pixel units 10b, the display panel achieves smoother image transition in the HSR display mode and improves the picture quality.

[0056] In one embodiment, the controller includes a plurality of control units 20, and each second scan line G2 is electrically connected to a corresponding control unit 20. The control unit 20 includes a first switch transistor T1 and a second switch transistor T2 arranged in parallel, the input terminals of the first switch transistor T1 and the second switch transistor T2 are electrically connected to the third scan line V+, and the output terminals of the first switch transistor T1 and the second switch transistor T2 are electrically connected to the corresponding second scan line G2; the control terminal of the first switch transistor T1 is electrically connected to a first scan line G1 adjacent to the second scan line G2, and the control terminal of the second switch transistor T2 is electrically connected to another first scan line G1 adjacent to the second scan line G2. The output terminals of the first switch transistor T1 and the second switch transistor T2 are both electrically connected to the corresponding second scan line G2. Since the two switch transistors are connected in parallel, namely the first switch transistor T1 and the second switch transistor T2, when any one of the switch transistors is turned on, the second scan line G2 is connected to the third scan line V+ to receive the second scan signal.

[0057] The control end of the first switch transistor T1 is electrically connected to the previous first scan line G1, while the control end of the second switch transistor T2 is electrically connected to the next first scan line G1. Thus, when the previous first scan line G1 outputs the first scan signal to the first row of pixel units 10a, the first switch transistor T1 is turned on, and when the next first scan line G1 outputs the first scan signal to the first row of pixel units 10a, the second switch transistor T2 is turned on. This design allows the two switch transistors to independently control the activation of the second scan line G2 according to different signals of the first scan line G1.

[0058] And the third scan line V+ can input a constant voltage, and the specific voltage value is determined according to the grayscale value to be displayed. Since the first scan signal is a square wave signal, the two switch transistors are turned on when the level is high and turned off when the level is low, so that the timing of the second scan signal is consistent with the timing of the first scan signal.

[0059] The driving circuit further includes a switching unit 30, the first scanning line G1 and the second scanning line G2 are both electrically connected to the scanning driver 40, and the switching unit 30 is configured to control the driving circuit to switch between the first mode and the second mode;

[0060] When the driving circuit is in the first mode, the scan driver 40 transmits the first scan signal to the first scan line G1 row by row to start the odd-numbered pixel unit and the two even-numbered pixel units adjacent to the odd-numbered pixel unit; the display panel implements the HSR display mode by simultaneously activating the adjacent odd-numbered and even-numbered pixel units and using interpolation or other techniques to smooth the transition, thereby reducing the jagged feeling in the high-contrast picture and improving the display effect.

[0061] When the driving circuit is in the second mode, the scan driver 40 transmits the third scan signal to the first scan line G1 and the second scan line G2 row by row to activate the pixel unit 10 row by row. The second mode is suitable for standard display requirements, and all pixel units 10 are activated row by row directly through independent scan lines (the first scan line G1 and the second scan line G2), such as daily video playback, text display, etc., in which row-by-row scanning is sufficient to meet the display quality requirements.

[0062] One end of the first scan line G1 and the second scan line G2 can be connected to the scan driver 40, and the scan driver 40 starts the first scan line G1 and the second scan line G2 line by line, thereby realizing the second mode. The switching unit 30 can conduct the second scan line G2 with the control unit 20, thereby realizing the first mode. The switching unit 30 allows flexible switching between the two modes according to the current display requirements or optimization goals. This increases the flexibility and adaptability of the driving circuit, enabling it to cope with different application scenarios and display requirements.

[0063] The third switch transistor T3 is provided on the second scan signal, and the third switch transistor T3 is located between the connection point of the scan driver 40 and the control unit 20, and the control end of the third switch transistor T3 is electrically connected to the switching unit 30. The switching unit 30 can directly control the switching state of the third switch transistor T3. When the driving circuit needs to switch to a different working mode (such as the first mode or the second mode), the switching unit 30 will send a control signal to the third switch transistor T3. If the third switch transistor T3 is turned off (i.e., not conducting), the scan driver 40 cannot send the third scan signal to the control unit 20; if the third switch transistor T3 is turned on (i.e., conducting), the scan driver 40 can normally send the third scan signal to the control unit 20, thereby allowing the second row of pixel units 10b to be activated by the third scan signal.

[0064] The control unit 20 is provided with a fourth switch transistor T4, which is located between the input end of the first switch transistor T1 and the third scan line V+, and the control end of the fourth switch transistor T4 is electrically connected to the switching unit 30. The switching unit 30 can also control the switching state of the fourth switch transistor T4. When the driving circuit is in a mode where the control unit 20 is not required to work (such as the second mode), the switching unit 30 can turn off the fourth switch transistor T4, thereby blocking the third scan line V+ from transmitting the scan signal to the second scan line G2. In a mode where the control unit 20 is required to work (such as the first mode), the switching unit 30 will turn on the fourth switch transistor T4, allowing the signal of the third scan line V+ to be normally transmitted to the input ends of the first switch transistor T1 and the second switch transistor T2.

[0065] In other embodiments, the fourth switch transistor T4 may also be disposed between the control terminals of the first switch transistor T1 and the second switch transistor T2 and the first scan line G1, so that the signal flow on the first scan line G1 can be more directly controlled. This helps to reduce signal interference and false triggering, and improve the stability and reliability of the circuit. This application does not limit this.

[0066] The switching unit 30 includes a first control line X1 and a second control line X2 , each third switch transistor T3 is connected to the first control line X1 , and each fourth switch transistor T4 is connected to the second control line X2 .

[0067] Specifically, the first control line X1 outputs a high level and the second control line X2 outputs a low level to control the drive circuit to switch to the first mode; since the first control line X1 outputs a high level, the third switch transistor T3 is activated (conducted). This means that the second scan line G2 is conductively connected to the scan driver 40, allowing the scan driver 40 to send a third scan signal to the second scan line G2. Since the second control line X2 outputs a low level, the fourth switch transistor T4 is turned off (not conductive). This disconnects the input terminals of the first switch transistor T1 and the second switch transistor T2 from the third scan signal. This enables the scan driver 40 to scan all pixel units 10 row by row in the first mode.

[0068] The first control line X1 outputs a low level, and the second control line X2 outputs a high level to control the drive circuit to switch to the second mode. Since the first control line X1 outputs a low level, the third switch transistor T3 is turned off (not conducting). The circuit path related to the second scan line G2 from the scan driver 40 is blocked, preventing the scan driver 40 from sending the third scan signal to the second scan line G2. Since the second control line X2 outputs a high level, the fourth switch transistor T4 is activated (conducting). The input ends of the first switch transistor T1 and the second switch transistor T2 are connected to the third scan signal, which allows the on and off of the first switch transistor T1 and the second switch transistor T2 to be controlled by the signal flow of the first scan line G1. Thus, in the second mode, the scan driver 40 outputs the first scan signal to the first scan line G1, thereby controlling the odd-numbered row pixel units to start row by row. When any row of odd-numbered row pixel units is started, the third scan line V+ outputs the second scan signal to the second scan line G2, thereby controlling the two even-numbered row pixel units adjacent to the started odd-numbered row pixel units.

[0069] In addition, the present application also provides a driving method, which is applied to the driving circuit described above. Figure 4 As shown, the driving method includes:

[0070] Step S10, acquiring first image data corresponding to the first row of pixel units according to the original image data, wherein the first image data includes timing information and a target grayscale value N;

[0071] In this step, the system first extracts the first image data related to the first row of pixel units based on the original image data. These data include timing information and target grayscale value N. The timing information is used to determine when to send a scan signal to the scan line, while the target grayscale value N specifies the brightness level that the pixel unit should display.

[0072] Step S20, when the display mode of the display panel is HSR, according to the timing information, inputting a first scan signal to the first scan line in a preset time period to enable the corresponding first row of pixel units to display a first grayscale value N1;

[0073] When the display panel is in the HSR display mode, the system inputs a first scan signal to the first scan line within a preset time period according to the timing information obtained in step S10. This signal is used to start the corresponding first row of pixel units and make them display the first grayscale value N1. It should be noted that although there may be errors in actual applications, the first grayscale value N1 displayed by the first row of pixel units remains consistent with the target grayscale value N.

[0074] Step S30, in any two adjacent rows of the first row of pixel units and the M rows of the second row of pixel units therebetween, when any of the first row of pixel units displays the first grayscale value N1, the control unit inputs a second scanning signal to the second scanning line to enable the second row of pixel units to display the second grayscale value N2;

[0075] Wherein, M is a positive integer, N2=i*N1 / (M+1); i is the number of the second row of pixel units, and the numbers of the second row of pixel units increase along the direction approaching the activated first row of pixel units, and i is a positive integer.

[0076] According to the given formula N2=i*N1 / (M+1), the grayscale value that each second-row pixel unit should display can be calculated. Take the example that two adjacent first-row pixel units can be provided with three second-row pixel units, forming a unit group consisting of five rows of pixel units (represented by 2n+1 to 2n+5 rows, where n is a natural number, representing the position of the unit group in the overall pixel array). In the second mode (corresponding to the HSR display mode of the display panel), when any first scan line (for example, the one connecting the first-row pixel unit of the 2n+1th row) transmits a first scan signal to start the corresponding first-row pixel unit to display the first grayscale value N1, the control unit in the adjacent three rows of second-row pixel units (2n+2 rows, 2n+3 rows, 2n+4 rows) will receive a trigger signal.

[0077] When the first grayscale value N1 is displayed in row 2n+1, taking row 2n+1 as the reference, the grayscale value N21=3*N1 / 4 displayed by row 2n+2, the grayscale value N22=N1 / 2 displayed by row 2n+3, and the grayscale value N23=N1 / 4 displayed by row 2n+4.

[0078] When the 2n+5th row displays the first grayscale value N1', taking the 2n+5th row of pixel units as a reference, the grayscale value displayed by the 2n+2th row of pixel units is N21'=N1' / 4, the grayscale value displayed by the 2n+3th row of pixel units is N22'=N1' / 2, and the grayscale value displayed by the 2n+4th row of pixel units is N23'=3*N1' / 4.

[0079] In one display cycle, the 2n+1 row displays the first grayscale value N1, the 2n+2 row pixel units display a grayscale value N2=N21+N21'=3N1 / 4+N1' / 4, the 2n+3 row pixel units display a grayscale value N3=N22+N22'=N1 / 2+N1' / 2, the 2n+4 row pixel units display a grayscale value N4=N23+N23'=N1 / 4+3*N1' / 4, and the 2n+5 row displays the first grayscale value N1'.

[0080] The 2n+5 row of pixel units also serves as the start of the next display unit, that is, when any first row of pixel units is started, multiple second pixel units adjacent to it on both sides are also started. As a result, the three adjacent second row pixel units (2n+2 row, 2n+3 row, 2n+4 row) realize a gradual transition from the 2n+1 row of pixel units to the 2n+5 row of pixel units, that is, by assigning the second row of pixel units an interpolated grayscale value based on the grayscale value of the first row of pixel units, a smoother image transition can be achieved, especially when displaying high-contrast images. This not only improves the fineness of the image, but also improves the image quality in the HSR display mode.

[0081] An example is given for description in which the first row of pixel units is an odd-numbered row of pixel units and the second row of pixel units is an even-numbered row of pixel units.

[0082] The driving method includes: dividing the original image data into odd-numbered frame image data and even-numbered frame image data; in a first frame display cycle, starting a first row of pixel units with the odd-numbered frame image data as the first image data; in a second frame display cycle, starting a first row of pixel units with the even-numbered frame image data as the first image data; wherein the first frame display cycle and the second frame display cycle are two adjacent frame display cycles.

[0083] The timing information and the target grayscale value N related to the first row of pixel units are extracted from the original image data. The data are divided into odd frames and even frames in chronological order, and each frame contains a portion of image data. Specifically, the image data corresponding to the odd rows of pixel units are odd frame image data, and the image data corresponding to the even rows of pixel units are even frame image data.

[0084] In the first frame display cycle, the first scan signal is input to the first scan line according to the odd frame image data to start the first row of pixel units to display the first grayscale value N1. In the second frame display cycle, the above process is repeated using the even frame image data to update or maintain the display state of the first row of pixel units.

[0085] By dividing the original image data into odd frames and even frames, the refresh rate of the display panel is improved without increasing the amount of additional data.

[0086] In the description of the embodiments of the present application, it should be noted that the orientation or positional relationship of terms such as "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" are based on the orientation or positional relationship described in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0087] What is disclosed above is only a preferred embodiment of the present application, and it certainly cannot be used to limit the scope of rights of the present application. Ordinary technicians in this field can understand that all or part of the processes of implementing the above embodiment and equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A driving circuit, applied to a display panel, characterized in that: The display panel includes a plurality of pixel units arranged in a periodic array along a first direction and a second direction. In the second direction, the plurality of rows of pixel units include a first row of pixel units and a second row of pixel units, and M rows of the second row of pixel units are arranged between each two adjacent first row of pixel units. The driving circuit includes: a plurality of first scan lines and second scan lines extending along a second direction, each row of the first row of pixel units being connected to a corresponding first scan line, and each row of the second row of pixel units being connected to a corresponding second scan line; a controller, the controller being electrically connected to the second scan line, the controller being configured to: in any two adjacent rows of the first row pixel units and the M rows of the second row pixel units therebetween, when any of the first scan lines transmits a first scan signal to start the corresponding first row pixel unit to display a first grayscale value N1, the controller is further used to input a second scan signal to the second scan line, the second scan signal being used to start the second row pixel unit to display a second grayscale value N2, N2=i*N1 / (M+1); Wherein, M is a positive integer, i is the serial number of the second row of pixel units, and the serial numbers of the second row of pixel units increase in a direction approaching the activated first row of pixel units, and i is a positive integer.

2. The driving circuit according to claim 1, characterized in that: The first scanning lines and the second scanning lines are alternately arranged, the first row of pixel units are odd-numbered row of pixel units, and the second row of pixel units are even-numbered row of pixel units.

3. The driving circuit according to claim 2, characterized in that: The controller includes a plurality of control units, each second scan line is electrically connected to a corresponding one of the control units, the control unit includes a first switch transistor and a second switch transistor arranged in parallel, the input ends of the first switch transistor and the second switch transistor are electrically connected to the third scan line, and the output ends of the first switch transistor and the second switch transistor are electrically connected to the corresponding second scan line; The control end of the first switch transistor is electrically connected to one of the first scan lines adjacent to the second scan line, and the control end of the second switch transistor is electrically connected to another of the first scan lines adjacent to the second scan line.

4. The driving circuit according to claim 3, characterized in that: The driving circuit further includes a switching unit, the first scanning line and the second scanning line are both electrically connected to the scanning driver, and the switching unit is configured to control the driving circuit to switch between the first mode and the second mode; When the driving circuit is in the first mode, the scan driver transmits a first scan signal to the first scan line row by row to start the odd-numbered pixel unit and two even-numbered pixel units adjacent to the odd-numbered pixel unit; When the driving circuit is in the second mode, the scan driver transmits a third scan signal to the first scan lines and the second scan lines row by row to activate the pixel units row by row.

5. The driving circuit according to claim 4, characterized in that: A third switch transistor is provided on the second scan signal, the third switch transistor is located between the connection point between the scan driver and the control unit, and the control end of the third switch transistor is electrically connected to the switching unit.

6. The driving circuit according to claim 5, characterized in that: The control unit is provided with a fourth switch transistor, the fourth switch transistor is located between the input end of the first switch transistor and the third scan line, and the control end of the fourth switch transistor is electrically connected to the switching unit.

7. The driving circuit according to claim 6, characterized in that: The switching unit comprises a first control line and a second control line, each of the third switch transistors is connected to the first control line, and each of the fourth switch transistors is connected to the second control line; The first control line is used to output a low level, and the second control line is used to output a high level to control the drive circuit to switch to a first mode; the first control line is used to output a high level, and the second control line is used to output a low level to control the drive circuit to switch to a second mode.

8. A display panel, characterized in that: The display panel comprises a plurality of pixel units distributed in an array and a driving circuit as claimed in any one of claims 1 to 7, and the pixel units in the same row are connected to the same scan line.

9. A driving method, characterized in that: Applied to the driving circuit according to any one of claims 1 to 7, the driving method comprises: Acquire first image data corresponding to the first row of pixel units according to the original image data, where the first image data includes timing information and a target grayscale value N; When the display mode of the display panel is HSR, according to the timing information, a first scanning signal is input to the first scanning line in a preset time period to start the corresponding first row of pixel units to display a first grayscale value N1; In any two adjacent rows of the first row of pixel units and the M rows of the second row of pixel units therebetween, when any of the first row of pixel units displays the first grayscale value N1, a second scanning signal is input to the second scanning line to enable the second row of pixel units to display the second grayscale value N2, where N2=i*N1 / (M+1); Wherein, M is a positive integer, i is the serial number of the second row of pixel units, and the serial numbers of the second row of pixel units increase along the direction approaching the activated first row of pixel units, and i is a positive integer.

10. The driving method according to claim 9, characterized in that: The driving method further includes: Dividing the original image data into odd-numbered frame image data and even-numbered frame image data; In a first frame display period, starting a first row of pixel units with the odd-numbered frame image data as first image data; In a second frame display period, starting the first row of pixel units with the even-numbered frame image data as the first image data; The first frame display period and the second frame display period are two adjacent frame display periods.

Images