Gate driver

Abstract

The present application is a kind of gate driver. The gate driver is electrically connected to a timing controller, and the gate driver includes N-stage gate drive circuits. The nth-stage gate drive circuit includes an output signal setting module electrically connected to the timing controller and an intermediate terminal. During a full gate synchronization period, the output signal setting module sets an nth-stage pixel gate signal according to a full gate synchronization enable signal transmitted by the timing controller. During an nth-stage single-stage scanning period in a round-robin scanning period, the output signal setting module selectively sets an nth-stage column scanning state signal and the nth-stage pixel gate signal in response to a voltage of the intermediate terminal. The round-robin scanning period includes N-stage single-stage scanning periods corresponding to the N-stage gate drive circuits, respectively.

Description

Technical Field

[0001] This invention relates to a gate driver, and more particularly to a gate driver compatible with gate-in-circuit technology. Background Technology

[0002] Please see Figure 1 This is a schematic diagram of a display device. The display device 10 includes a timing controller 103, a source driver 105, a gate driver 107, and a display panel 101. The type of display panel 101 is not limited; for example, the display panel can be a cholesteric liquid crystal display panel or a general liquid crystal panel. The timing controller 103 is electrically connected to the source driver 105 and the gate driver 107, and both the source driver 105 and the gate driver 107 are electrically connected to the display panel 101.

[0003] In this paper, the uppercase variable M represents the total number of rows of the pixel array on the display panel, the uppercase variable N represents the total number of columns of the pixel array on the display panel, and the lowercase variable n represents one column of the pixel array. Variables n, N, and M are all positive integers, and n ≤ N. In addition, for the sake of simplicity, the same symbols are used to represent signal lines and signals transmitted on signal lines. For example, after the timing controller 103 generates a gate driver control signal to the gate driver 107, the gate driver 107 will generate N-level pixel gate signals G[1] to G[N]. And the N-level pixel gate signals G[1] to G[N] are transmitted to the display panel 101 through the pixel gate signal lines G[1] to G[N] respectively.

[0004] The pixel gate signal line G[n] is simultaneously connected to the M pixels in the nth column of the pixel array. When the gate driver 107 controls the pixel gate signal G[n] to generate a pulse, the M pixels in the nth column on the display panel 101 will be synchronously enabled. Therefore, the pixel gate signal G[n] is visible and is the signal used to enable the M pixel transistors PXL(1,n) to PXL(M,n) in the nth column of the pixel array.

[0005] The connection method and signal control relationship between the timing controller 103, the source driver 105, the gate driver 107, and the display panel 101 will not be described in detail here. This article only focuses on the way the gate driver 107 generates N-level pixel gate signals G[1] to G[N].

[0006] Please see Figure 2This is a schematic diagram of a gate driver. The gate driver 107 includes N gate driving circuits gtCKT[1] to gtCKT[N]. The gate driving circuits gtCKT[1] to gtCKT[N] are used to generate N levels of pixel gate signals G[1] to G[N]. The gate driver control signals received by the gate driving circuits gtCKT[1] to gtCKT[N] from the timing controller 103 can be divided into two categories: one category is the timing control signals provided for each level of the N different gate driving circuits gtCKT[1] to gtCKT[N]; the other category is the synchronous timing control signals provided to the gate driving circuits gtCKT[1] to gtCKT[N]. In addition, the gate driving circuits gtCKT[1] to gtCKT[N] also simultaneously receive multiple constant voltages with different voltage values ​​(e.g., supply voltage, ground voltage, etc.).

[0007] The pixel array is controlled periodically over the Tframe period. See also... Figure 3 It is a waveform diagram of the N-level pixel gate signals G[1]~G[N] generated by the gate driver during the frame period Tframe when used with a cholesterol liquid crystal panel. Figure 3 The horizontal axis represents time, and the vertical axis represents the change of the N-level pixel gate signal G[1]~G[N]. The frame period Tframe is between time points t1 and t10. The frame period Tframe includes: the positive reset period Reset+ between time points t1 and t2, the negative reset period Reset- between time points t2 and t3, the wait period Wait between time points t3 and t4, the common swing duration ComSwing1 between time points t4 and t5, the positive scan period Scan+ between time points t5 and t6, the common swing period ComSwing2 between time points t6 and t7, the negative scan period Scan- between time points t7 and t8, the positive end period End+ between time points t8 and t9, and the negative end period End- between time points t9 and t10.

[0008] Depend on Figure 3 It can be seen that within the same frame period Tframe, some periods are the periods during which the N-level pixel gate signals G[1]~G[N] need to synchronously generate pulses. For example, the positive reset period Reset+, the negative reset period Reset-, the wait period Wait, the common swing period Com swing, the positive end period End+, and the negative end period End-. This paper refers to the periods during which the N-level pixel gate signals G[1]~G[N] need to synchronously generate pulses as the duration of all gate one (DURall-sync).

[0009] On the other hand, within the same frame period Tframe, there is a period during which the pixel gate signals G[1] to G[N] need to generate pulses sequentially according to the column order n=1 to N. For example, the positive scan period Scan+. This paper refers to the period during which the N-level pixel gate signals G[1] to G[N] need to generate pulses sequentially as the DURall-scan period.

[0010] When the gate driver generates N-level pixel gate signals G[1]~G[N] for use in a general liquid crystal panel, the timing relationship is slightly different from that of a cholesteric liquid crystal panel. When the general liquid crystal panel is in normal operation mode, the gate driver needs to control the pixel gate signals G[1]~G[N] to generate pulses sequentially according to the column order n=1~N during the frame period Tframe; and, before the general liquid crystal panel is about to be turned off, the gate driver needs to control the N-level pixel gate signals G[1]~G[N] to generate pulses synchronously.

[0011] Although the gate driver does not generate pulses and scan continuously during the Tframe period when driving a general LCD panel, the overall operation process can still be divided into two requirements: synchronous pulse generation and reception and continuous scanning.

[0012] To provide users with a better visual experience, display devices are moving towards narrow bezel technology. To this end, display device manufacturers have begun to integrate the gate driver directly into the thin-film transistor array. That is, the pixel array and the gate driver 107 are simultaneously set on the display panel. This technology of setting the gate driver 107 on the display panel to save the area occupied by the screen bezel is called Gate Driver on Array (GoA). In display devices using GoA technology, because the N-level pixel gate signals G[1] to G[N] are designed on the side of the display panel, the display device manufacturers cannot continue the past practice of directly receiving the N-level pixel gate signals G[1] to G[N] generated by the timing controller 103.

[0013] Currently, display devices using GoA technology can only generate pulses sequentially on the N-level pixel gate signal lines G[1] to G[N] during the sequential scanning period. However, current display devices using GoA technology are still unable to synchronously generate the pulses of the N-level pixel gate signals G[1] to G[N] during the full gate synchronization period. Therefore, the functionality of display devices using GoA technology at present is still not perfect. Summary of the Invention

[0014] This invention relates to a gate driver compatible with GOA technology. Both embodiments disclosed herein can control the N-level pixel gate signals G[1] to G[N] to generate pulses in a synchronous or sequential manner to meet the requirements of DURall-sync during full gate synchronization and DURall-scan during sequential scanning.

[0015] According to one aspect of the present invention, a gate driver electrically connected to a timing controller is provided. The gate driver includes an N-stage gate driving circuit. The nth-stage gate driving circuit in the N-stage gate driving circuit includes an output signal setting module. The output signal setting module is electrically connected to the timing controller and an intermediate terminal. During full gate synchronization, the N-stage gate driving circuit synchronously sets the N-stage pixel gate signal according to a full gate synchronization enable signal transmitted by the timing controller. During a single-stage scan of the nth stage in a sequential scan, the output signal setting module selectively sets the nth-stage column scan state signal and the nth-stage pixel gate signal in the N-stage pixel gate signal according to the voltage of the intermediate terminal. The sequential scan includes N-stage single-stage scan periods corresponding to the N-stage gate driving circuits. n and N are positive integers, and n is less than or equal to N.

[0016] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figure 1 It is a schematic diagram of the display device;

[0018] Figure 2 This is a schematic diagram of a gate driver;

[0019] Figure 3 It is a waveform diagram of the N-level pixel gate signals G[1]~G[N] generated by the gate driver during a frame period Tframe when used with a cholesterol liquid crystal panel;

[0020] Figure 4 This is a schematic diagram of various signals related to a first embodiment of the nth-stage gate drive circuit gtCKT[n] of the present disclosure concept;

[0021] Figure 5 This is a block diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] of the present invention;

[0022] Figure 6 This is a circuit diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure.

[0023] Figure 7It is a waveform diagram of the signal associated with the nth-level gate drive circuit gtCKT[n] according to the first embodiment of the present disclosure, used to generate the nth-level pixel gate signal G[n].

[0024] Figures 8A-8C This is a schematic diagram of the state of DURall-sync at different stages during full gate synchronization, according to a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the present disclosure.

[0025] Figures 9A-9D This is a schematic diagram of the state of DURscan[n] at different stages during the nth stage single-stage scan, according to a first embodiment of the nth stage gate drive circuit gtCKT[n] based on the present disclosure.

[0026] Figure 10 This is a schematic diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, combined with a method to reduce leakage current.

[0027] Figure 11 This is a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, with a schematic diagram of two sets of voltage regulation circuits;

[0028] Figure 12 It is a schematic diagram of various signals related to the second embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure;

[0029] Figure 13 This is a block diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] of the present invention.

[0030] Figure 14 This is a circuit diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure.

[0031] Figure 15 It is a waveform diagram of a signal related to the nth-level pixel gate signal G[n] in a second embodiment of the nth-level gate drive circuit gtCKT[n] according to the present disclosure.

[0032] Figures 16A-16C This is a schematic diagram of the state of DURall-sync at different stages during full gate synchronization, according to a second embodiment of the nth-stage gate drive circuit gtCKT[n] based on the present disclosure.

[0033] Figures 17A-17CThis is a schematic diagram of the state of DURscan[n] at different stages during the nth stage single-stage scan, according to a second embodiment of the nth stage gate drive circuit gtCKT[n] based on the present disclosure.

[0034] Figure 18 This is a schematic diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, combined with a method to reduce leakage current.

[0035] Figure 19 This is a second embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, with a schematic diagram of two sets of voltage regulator circuits; and

[0036] Figure 20 It is a schematic diagram of the nth-stage gate drive circuit gtCKT[n] proposed according to this disclosure.

[0037] In the attached figures, the following labels are used:

[0038] 10: Display device

[0039] 103: Timing Controller

[0040] 107: Gate Driver

[0041] 105: Source Driver

[0042] 101: Display Panel

[0043] G[1],G[n],G[N],G[n-1],G[n+1]: Pixel gate signals (lines)

[0044] gtCKT[1],gtCKT[n],gtCKT[N],gtCKT[np],gtCKT[nq],gtCKT[n+p],gtCKT[n+q]: Gate drive circuit

[0045] Tframe: During the frame

[0046] Reset+: During positive reset

[0047] Reset-: During negative polarity reset

[0048] Wait: During the waiting period

[0049] ComSwing1, ComSwing2: Shared swing period

[0050] Scan+: During positive electrode scanning

[0051] Scan-: During negative electrode scanning

[0052] End+: Positive electrode termination period

[0053] End-: Negative electrode termination period

[0054] t1~t10: Time points

[0055] ST[np]: The (np)th level column scan status signal (line)

[0056] ST[n]: The nth level column scan status signal (line)

[0057] ST[n+q]: The (n+q)th level column scan status signal (line)

[0058] HC[k]: Select signal (line) column by column

[0059] XON_C: Signal (line) during full-gate synchronization

[0060] XON_S: All-gate synchronization enable signal (line)

[0061] rstST: Intermediate endpoint reset signal (line)

[0062] LC, LC-a, LC-b: Voltage supplied to the regulated terminals (signal lines)

[0063] VSSQ: Intermediate Terminal Ground Voltage (Signal Line)

[0064] VSSG: Pixel gate ground voltage (signal line)

[0065] VGHD: Gate supply voltage (signal line)

[0066] H: Positive voltage value

[0067] L-: Minimum negative voltage value

[0068] L: Second lowest negative voltage value

[0069] ST[n-1]: The (n-1)th level column scan status signal (line)

[0070] ST[n+1]: The (n+1)th level column scan status signal (line)

[0071] C[n]: Capacitance

[0072] NDmd[n]: Median endpoint

[0073] NDstb[n]: Regulated voltage endpoint

[0074] nmuCKT[n]: Pull-up circuit at intermediate endpoint

[0075] ssCKT[n]: Status signal setting circuit

[0076] gsCKT[n]: Gate signal setting circuit

[0077] stbMDL[n], stbMDL-a[n], stbMDL-b[n]: Voltage regulator module

[0078] stbsCKT[n]: Voltage regulator terminal setting circuit

[0079] stbCKT[n]: Voltage regulator circuit

[0080] nmdCKT[n]: Intermediate endpoint pull-down circuit

[0081] Tnmu[n]: Pull-up transistor at intermediate endpoint

[0082] Tss[n]: Status signal setting transistor

[0083] Tgs1[n], Tgs2[n]: Gate signal setting transistors

[0084] Tf1[n],Tf2[n],Tf3[n],Tf4[n],Tf5[n],Tf6[n]: Zener transistors; Tnmstb[n],Tgstb[n],Tsstb[n]: Zener transistors

[0085] Tnmd_nxt[n], Tnmd_xon[n]: Middle terminal pull-down transistor

[0086] Tnmd_rst[n]: Intermediate endpoint reset transistor

[0087] FM1, FM2, FM3, FM4: Dashed box selection area

[0088] DURall-sync: During full-gate synchronization

[0089] DURscan[n]: During the nth level single-level scan

[0090] STG-a1, STG-a2, STG-a3: Synchronization Phase

[0091] STG-s1[n], STG-s2[n], STG-s3[n], STG-s4[n]: Scanning phase

[0092] ΔVc[n]: Capacitive voltage difference

[0093] NDints[n]: Voltage regulation setting endpoint

[0094] lkgCNT_1a,lkgCNT_1b,lkgCNT_2a,lkgCNT_2b: line segment

[0095] L1a, L1b, L1c, L2a, L2b: Dashed line segments Detailed Implementation

[0096] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the present invention.

[0097] This disclosure addresses the shortcomings of existing technologies using GoA, which cannot simultaneously provide DURall-sync during full-gate synchronization and DURall-scan waveforms during sequential scan. The following embodiments can be divided into two types; for the first embodiment, please refer to [link to first embodiment]. Figures 4-10 The description is as follows; for the second embodiment, please refer to the following. Figures 11-1 7. This paper describes the circuit composition of the nth-stage gate drive circuit gtCKT[n] in both embodiments, and illustrates the circuit behavior of the nth-stage gate drive circuit gtCKT[n] with waveform diagrams. Both embodiments disclosed herein can be used with GoA technology, and can generate pulses in the Nth-stage pixel gate signals G[1] to G[N] in a synchronous or alternating manner according to the requirements of DURall-sync during full gate synchronization and DURall-scan during sequential scanning.

[0098] As previously mentioned, the gate driver 107 includes N gate drive circuits gtCKT[1] to gtCKT[N]. Since the internal composition of the gate drive circuits [1] to gtCKT[N] is similar, the following description will take the nth gate drive circuit gtCKT[n] as an example. For ease of explanation, if the circuit elements or signals provided or generated individually for each column n=1 to N are individually set, the corresponding gate level will be distinguished by "[n]". If the circuit elements or signals are simultaneously set for each column n=1 to N, [n] will not be additionally indicated.

[0099] According to the concept disclosed herein, the circuit behavior of the nth-stage gate drive circuit gtCKT[n] is related to the gate drive circuits before and after it. In the following embodiments, variables (np) and (nq) are used to represent the preceding gate drive circuits (i.e., gate drive circuits gtCKT[np] and gtCKT[nq]) related to the nth-stage gate drive circuit gtCKT[n]; and variables (n+p) and (n+q) are used to represent the following gate drive circuits (i.e., gate drive circuits gtCKT[n+p] and gtCKT[n+q]) related to the nth-stage gate drive circuit gtCKT[n]. Here, n, p, and q are all positive integers, n ≤ N, and p and q may be equal or unequal.

[0100] For ease of illustration, the following examples assume (n+q)≤N, (n+p)≤N, 1≤(np), and 1≤(nq). In practical applications, if (n+q)>N, (n+p)>N, 1>(np), and 1>(nq), a timing controller is required to generate the corresponding analog control signals. This application-specific variation will not be detailed in this article.

[0101] Firstly Figures 4-11 This disclosure describes a first embodiment of how to design the nth-stage gate drive circuit gtCKT[n]. Figure 4 Explain the signals associated with the nth-stage gate drive circuit gtCKT[n]; Figure 5 Explain the internal circuitry of the n-stage gate drive circuit gtCKT[n]; Figure 6 Explain the circuit elements and connections of the nth-stage gate drive circuit gtCKT[n]; Figure 7 The waveform diagram illustrates how the signals associated with the nth stage gate drive circuit gtCKT[n] change in response to DURall-sync during full gate synchronization and DURscan[n] during the nth stage single-stage scan. Figures 8A-8C illustrate Figure 5 The nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a1, STG-a2, STG-a3 during the full gate synchronization period DURall-sync; Figures 9A-9D illustrate Figure 5 The nth stage gate drive circuit gtCKT[n] is in the scanning phase STG-s1[n], STG-s2[n], STG-s3[n], STG-s4[n] during the nth stage single-stage scan in DURscan[n]; Figure 10 Explain how to Figure 6 The nth-stage gate drive circuit gtCKT[n] improves leakage current. Figure 11 This explains how, for the purpose of extending transistor lifespan, two sets of voltage regulator circuits are set in the nth stage gate drive circuit gtCKT[n] of the first embodiment.

[0102] Please see Figure 4 This is a schematic diagram of various signals related to a first embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. Figure 4 In the diagram, different types of signals are indicated by arrow directions. Depending on the signal direction, the signals associated with the nth-stage gate drive circuit gtCKT[n] can be distinguished as: input signals received from other circuits; and output signals transmitted to other circuits.

[0103] exist Figure 4In the diagram, the input signals received by the gate drive circuit gtCKT[n] from the external circuit are located to the left of the gate drive circuit gtCKT[n], and the arrows of these input signals point towards the gate drive circuit gtCKT[n]. The following is a brief introduction to each input signal and its purpose:

[0104] The (np)th level column scan state signal ST[np] is the input signal received by the nth level gate drive circuit gtCKT[n] from the (np)th level gate drive circuit gtCKT[np]; the (n+q)th level column scan state signal ST[n+q] is the input signal received by the nth level gate drive circuit gtCKT[n] from the (n+q)th level gate drive circuit gtCKT[n+q]; and the column-by-column selection signal (high level control signal) HC[k] received from the timing controller. The column-by-column selection signals HC[1]~HC[K] are control signals generated in turn by the timing controller after grouping the N columns of pixel units (assuming they are divided into K=2, 4, 6, ... groups) according to the different groups (the kth group, k=1~K). The variables k and K are positive integers, N is a multiple of K, and k≤K. For example, K=2, 4, 6...

[0105] Assuming K=4, the timing controller will sequentially set the column selection signals HC[1]~HC[4] to positive voltage values ​​H. For example, if the timing controller sets the column selection signal HC[1] to positive voltage value H (HC[1]=H), then the column selection signals HC[2]~HC[4] will be set to the lowest negative voltage value L- (HC[2]=HC[3]=HC[4]=L); if the timing controller sets the column selection signal HC[2] to positive voltage value H (HC[2]=H), then the column selection signals HC[1], HC[3], and HC[4] will be set to the lowest negative voltage value L (HC[1]=HC[3]=HC[4]=L), and so on.

[0106] The timing controller transmits the k=1th column-by-column selection signal HC[1] to the gate drive circuits gtCKT[1], gtCKT[1+K*1], gtCKT[1+K*2], etc. of the k=1st group; transmits the k=2nd column-by-column selection signal HC[2] to the gate drive circuits gtCKT[2], gtCKT[2+K*1], gtCKT[2+K*2], etc. of the k=2nd group; transmits the k=3rd column-by-column selection signal HC[3] to the gate drive circuits gtCKT[3], gtCKT[3+K*1], gtCKT[3+K*2], etc. of the k=3rd group; and transmits the k=4th column-by-column selection signal HC[4] to the gate drive circuits gtCKT[4], gtCKT[4+K*1], gtCKT[4+K*2], etc. of the k=4th group.

[0107] According to the concept disclosed herein, when the intermediate endpoint NDmd[n] is a positive voltage value H (NDmd[n] = H), the voltages of the nth-level pixel gate signal G[n] and the nth-level column scan state signal ST[n] are determined based on the column-by-column selection signal HC[k]. Furthermore, during the scan phase STG-s2[n] of DURscan[n] in the nth-level single-level scan, the timing controller sets the column-by-column selection signal HC[k] to a positive voltage value H (HC[k] = H). Accordingly, the timing controller only needs to provide K column-by-column selection signals HC[1] to HC[K] as scan pulses to generate the nth-level pixel gate signal G[n]. By generating pulses in a cyclic manner, the number of input signals required by the timing controller to set the scan pulses for the nth-level pixel gate signal G[n] can be reduced.

[0108] The variations in the XON_C and XON_S signals during full gate synchronization will be explained below. Also note that the intermediate endpoint reset signal rstST is used when the display panel performs frame switching. That is, the intermediate endpoint reset signal rstST maintains a minimum negative voltage value L- (e.g., -12V) during the frame period Tframe, and is a positive voltage value H only during the transition between two consecutive frame periods. Therefore, the intermediate endpoint reset signal rstST does not affect the circuit behavior of the gate drive circuit gtCKT[n] during full gate synchronization (DURall-sync) and during sequential scanning (DURall-scan).

[0109] The regulated terminal supply voltage LC, intermediate terminal ground voltage VSSQ, pixel gate ground voltage VSSG, and gate supply voltage VGHD received from the voltage source or timing controller have constant voltage values. In this paper, H represents a positive voltage value, L- represents the lowest negative voltage value (e.g., -12V), and L represents the second lowest negative voltage value (e.g., -9V). Among them, H>L>L-. In the third type of input signal received by the nth stage gate drive circuit gtCKT[n], the regulated terminal supply voltage LC is equal to the positive voltage value (LC=H), the intermediate terminal ground voltage VSSQ is equal to the lowest negative voltage value L- (VSSQ=L-), the pixel gate ground voltage VSSG is equal to the second lowest negative voltage value L (VSSG=L), and the gate supply voltage VGHD is equal to the positive voltage value H (VGHD=H).

[0110] The input signals received by the nth-stage gate drive circuit gtCKT[n] can be classified according to their application, characteristics, or whether they change with the nth stage (n=1 to N). Table 1 summarizes the different ways of classifying input signals.

[0111] Table 1

[0112]

[0113]

[0114] According to their application, the input signal area can be roughly divided into two categories: First, input signals used to control whether transistors are turned on or off (including: the (np)th level column scan state signal ST[np], the (n+q)th level column scan state signal ST[n+q], the full-gate synchronization period signal XON_C, and the intermediate endpoint reset signal rstST); second, input signals that change the voltage of internal endpoints or output signals as transistors are turned on (including: column-by-column select signal HC[k], the full-gate synchronization enable signal XON_S, the intermediate endpoint ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD). Note that the regulated endpoint supply voltage LC can be used to control whether transistors are turned on or off, and also to change the internal endpoints. Therefore, the regulated endpoint supply voltage LC belongs to both types.

[0115] According to signal characteristics, input signals can be divided into two categories: the first is input signals with non-constant voltage (logic level will change) (including: the (np)th level column scan state signal ST[np], the (n+q)th level column scan state signal ST[n+q], the full gate synchronization period signal XON_C, and the intermediate endpoint reset signal rstST, the column-by-column select signal HC[k], and the full gate synchronization enable signal XON_S); the second is input signals with constant voltage (including: the regulated endpoint supply voltage LC, the intermediate endpoint ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD).

[0116] When classifying input signals according to whether they change with different levels n=1 to N, they can be divided into two categories: the first is input signals that change with different levels n=1 to N (including: the column scan state signal ST[np] of level (np), the column scan state signal ST[n+q] of level (n+q), and the column-by-column selection signal HC[k]); the second is input signals that do not change with different levels n=1 to N (including: the full gate synchronization signal XON_C, the intermediate endpoint reset signal rstST, the full gate synchronization enable signal XON_S, the regulated endpoint supply voltage LC, the intermediate endpoint ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD).

[0117] exist Figure 4In the diagram, the output signal transmitted from the gate drive circuit gtCKT[n] to the external circuit is located to the right of the gate drive circuit gtCKT[n], and the arrow direction of the output signal originates from the gate drive circuit gtCKT[n]. The output signal generated by the nth-level gate drive circuit gtCKT[n] includes: the nth-level column scan state signal ST[n] and the nth-level pixel gate signal G[n].

[0118] Specifically, the nth-level gate drive circuit gtCKT[n] transmits the nth-level column scan status signal ST[n] to the (nq)th-level gate drive circuit gtCKT[nq] and the (n+p)th-level gate drive circuit gtCKT[n+p]. Furthermore, the nth-level gate drive circuit gtCKT[n] transmits the nth-level pixel gate signal G[n] to the M pixel transistors PXL(1,n) to PXL(M,n) located in the nth column of the pixel array.

[0119] Please see Figure 5 This is a block diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] of the disclosed concept. Figure 5 It can be seen that the nth stage gate drive circuit gtCKT[n] includes: output signal setting module outSetMDL[n], intermediate endpoint setting module nmSetMDL[n], and voltage regulation module stbMDL[n].

[0120] The output signal setting module outSetMDL[n] further includes: a status signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The intermediate endpoint setting module nmSetMDL[n] further includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n], and an intermediate endpoint pull-down circuit nmdCKT[n]. The voltage regulator module stbMDL[n] further includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] that are electrically connected to each other.

[0121] The circuit elements in the output signal setting module outSetMDL[n] are all related to the voltage of the output signal (the nth level pixel gate signal G[n] and / or the nth level column scan state signal ST[n]). The circuit elements in the intermediate endpoint setting module nmSetMDL[n] are all related to the voltage of the intermediate endpoint NDmd[n]. The circuit elements in the voltage regulator module stbMDL[n] are all related to the voltage of the voltage regulator endpoint NDstb[n].

[0122] Please also see Figure 4 , 5 .Apart from Figure 4 In addition to the input and output signals related to other circuit elements, the diagram shows... Figure 5 The endpoints are also located inside the nth-stage gate drive circuit gtCKT[n]. For example, the intermediate endpoint NDmd[n] and the regulated endpoint NDstb[n].

[0123] In the intermediate endpoint setting module nmSetMDL[n], one end of capacitor C[n] is electrically connected to the intermediate endpoint NDmd[n], and the other end is electrically connected to the nth pixel gate signal line G[n]. The intermediate endpoint pull-up circuit nmuCKT[n] receives the gate supply voltage VGHD and the (np)th column scan state signal ST[np], and the intermediate endpoint pull-up circuit nmuCKT[n] is electrically connected to the intermediate endpoint NDmd[n].

[0124] In the output signal setting module outSetMDL[n], the status signal setting circuit ssCKT[n] receives the column-by-column selection signal HC[k], and the status signal setting circuit ssCKT[n] is electrically connected to the intermediate endpoint NDmd[n] and the nth-level column scan status signal line ST[n]. The gate signal setting circuit gsCKT[n] receives the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C, and the gate signal setting circuit gsCKT[n] is electrically connected to the intermediate endpoint NDmd[n] and the nth-level pixel gate signal line G[n].

[0125] In the voltage regulator module stbMDL[n], the voltage regulator endpoint setting circuit stbsCKT[n] receives the voltage regulator endpoint supply voltage LC, the intermediate endpoint ground voltage signal line VSSQ, and the full gate synchronization period signal XON_C. The voltage regulator endpoint setting circuit stbsCKT[n] is electrically connected to the intermediate endpoint NDmd[n] and the voltage regulator endpoint NDstb[n]. On the other hand, the voltage regulator circuit stbCKT[n] receives the intermediate endpoint ground voltage VSSQ and the pixel gate ground voltage VSSG. The voltage regulator circuit stbCKT[n] is electrically connected to the voltage regulator endpoint NDstb[n], the intermediate endpoint NDmd[n], the nth level column scan state signal line ST[n], and the nth level pixel gate signal line G[n]. In addition, the intermediate endpoint pull-down circuit nmdCKT[n] receives the (n+q)th level column scan status signal ST[n+q], the intermediate endpoint ground voltage signal line VSSQ, the full gate synchronization period signal XON_C, and the intermediate endpoint reset signal line rstST, and the intermediate endpoint pull-down circuit nmdCKT[n] is electrically connected to the intermediate endpoint NDmd[n].

[0126] Please see Figure 6 This is a circuit diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. Please also refer to... Figure 5 , 6For ease of explanation, in Figure 6 In the above, assume p = 1 and q = 1.

[0127] Based on this assumption, the nth-level gate drive circuit gtCKT[n] receives the column scan status signal ST[np] = ST[n-1] from the (np) = (n-1)th-level gate drive circuit gtCKT[np] = gtCKT[n-1]; and receives the column scan status signal ST[n+q] = ST[n+1] from the (n+q) = (n+1)th-level gate drive circuit gtCKT[n+q] = gtCKT[n+1]. Furthermore, the nth-level gate drive circuit gtCKT[n] transmits the nth-level column scan status signal ST[n] to the (nq) = (n-1)th-level gate drive circuit gtCKT[nq] = gtCKT[n-1]; and transmits the nth-level column scan status signal ST[n] to the (n+p) = (n+1)th-level gate drive circuit gtCKT[n+p] = gtCKT[n+1].

[0128] The following section will first explain the composition of the circuit elements in the intermediate endpoint setting module nmSetMDL[n], the output signal setting module outSetMDL[n], and the voltage regulation module stbMDL[n]. Next, the circuit elements related to each signal will be explained according to the different signal types.

[0129] The intermediate endpoint setting module nmSetMDL[n] includes: capacitor C[n], intermediate endpoint pull-up circuit nmuCKT[n], and intermediate endpoint pull-down circuit nmdCKT[n]. The intermediate endpoint pull-up circuit nmuCKT[n] includes: intermediate endpoint pull-up transistor Tnmu[n]; and the intermediate endpoint pull-down circuit nmdCKT[n] includes: intermediate endpoint pull-down transistors Tnmd_nxt[n], Tnmd_xon[n], and intermediate endpoint reset transistor Tnmd_rst[n]. The following describes the connection method of the transistors in the intermediate endpoint pull-up circuit nmuCKT[n] and the intermediate endpoint pull-down circuit nmdCKT[n].

[0130] In the intermediate terminal pull-up circuit nmuCKT[n], the drain terminal of the intermediate terminal pull-up transistor Tnmu[n] receives the gate supply voltage VGHD, the control terminal receives the (n-1)th stage column scan state signal ST[n-1], and the source terminal is electrically connected to the intermediate terminal NDmd[n]. Accordingly, the on / off state of the intermediate terminal pull-up transistor Tnmu[n] depends on the voltage of the (n-1)th stage column scan state signal ST[n-1]. When the intermediate terminal pull-up transistor Tnmu[n] is on, it conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n].

[0131] In the intermediate endpoint pull-down circuit nmdCKT[n], the drain of the intermediate endpoint pull-down transistor Tnmd_nxt[n] is connected to the intermediate endpoint NDmd[n], the control terminal receives the (n+1)th column scan status signal ST[n+1], and the source terminal is connected to the intermediate endpoint ground voltage signal line VSSQ. The drain of the intermediate endpoint pull-down transistor Tnmd_xon[n] is connected to the intermediate endpoint NDmd[n], the control terminal receives the all-gate synchronization period signal XON_C, and the source terminal is connected to the intermediate endpoint ground voltage signal line VSSQ. The drain of the intermediate endpoint reset transistor Tnmd_rst[n] is connected to the intermediate endpoint NDmd[n], the control terminal receives the intermediate endpoint reset signal rstST, and the source terminal is connected to the intermediate endpoint ground voltage signal line VSSQ.

[0132] Accordingly, the on / off state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th stage column scan state signal ST[n+1]. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0133] Furthermore, the on / off state of the intermediate terminal pull-down transistor Tnmd_xon[n] depends on the signal XON_C during full-gate synchronization. When the intermediate terminal pull-down transistor Tnmd_xon[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0134] Furthermore, the on / off state of the intermediate endpoint reset transistor Tnmd_rst[n] depends on the intermediate endpoint reset signal rstST. When the intermediate endpoint reset transistor Tnmd_rst[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ to the intermediate endpoint NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0135] Please also note that because the intermediate endpoint reset signal rstST issued by the timing controller has the lowest negative voltage value L- (rstST = L-) during both full-gate synchronization (DURall-sync) and polling (DURall-scan), the intermediate endpoint reset transistor Tnmd_rst[n] remains off during both full-gate synchronization (DURall-sync) and polling (DURall-scan). Therefore, the intermediate endpoint reset transistor Tnmd_rst[n] will not be drawn again when explaining the circuit behavior later.

[0136] The output signal setting module outSetMDL[n] includes: a status signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The status signal setting circuit ssCKT[n] includes: a status signal setting transistor Tss[n]; and the gate signal setting circuit gsCKT[n] includes: gate signal setting transistors Tgs1[n] and Tgs2[n].

[0137] In the state signal setting circuit ssCKT[n], the drain terminal of the state signal setting transistor Tss[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the nth column scan state signal line ST[n]. Therefore, the on / off state of the state signal setting transistor Tss[n] depends on the voltage of the intermediate terminal NDmd[n]. When the state signal setting transistor Tss[n] is on, it conducts the voltage of the column-by-column selection signal HC[k] to the nth column scan state signal ST[n]. That is, ST[n] = HC[k].

[0138] In the gate signal setting circuit gsCKT[n], the drain terminal of the gate signal setting transistor Tgs1[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the nth pixel gate signal line G[n]. The drain terminal of the gate signal setting transistor Tgs2[n] receives the full gate synchronization enable signal XON_S, the control terminal receives the full gate synchronization period signal XON_C, and the source terminal is electrically connected to the nth pixel gate signal line G[n].

[0139] Accordingly, the on / off state of the gate signal setting transistor Tgs1[n] depends on the voltage of the intermediate terminal NDmd[n]. When the gate signal setting transistor Tgs1[n] is on, the voltage of the column-by-column selection signal HC[k] is conducted to the nth pixel gate signal line G[n]. That is, G[n] = HC[k]. On the other hand, the on / off state of the gate signal setting transistor Tgs2[n] depends on the voltage of the signal XON_C during full gate synchronization. When the gate signal setting transistor Tgs2[n] is on, the voltage of the full gate synchronization enable signal XON_S is conducted to the nth pixel gate signal line G[n]. That is, G[n] = XON_S.

[0140] The voltage regulator module stbMDL[n] includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] that are electrically connected to each other. The voltage regulator endpoint setting circuit stbsCKT[n] includes: voltage regulator endpoint setting transistors Tf1[n], Tf2[n], Tf3[n], Tf4[n], Tf5[n], and Tf6[n]; the voltage regulator circuit stbCKT[n] includes: voltage regulator transistors Tnmstb[n], Tgstb[n], and Tsstb[n].

[0141] In the voltage regulator setting circuit stbsCKT[n], the drain and gate terminals of the voltage regulator setting transistor Tf1[n] both receive the voltage regulator supply voltage LC, and the source terminal is electrically connected to the voltage regulator setting terminal NDints[n]. Therefore, the on / off state of the voltage regulator setting transistor Tf1[n] depends on the voltage regulator supply voltage LC. In this paper, it is assumed that the voltage regulator supply voltage LC is continuously positive. Therefore, the voltage regulator setting transistor Tf1[n] remains in the on state and conducts the positive voltage value H (LC = H) of the voltage regulator supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = LC = H.

[0142] The drain of the voltage regulator setting transistor Tf2[n] is connected to the voltage regulator setting terminal NDints[n], the control terminal is connected to the intermediate terminal NDmd[n], and the source is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf2[n] depends on the voltage of the intermediate terminal NDmd[n]. When the voltage regulator setting transistor Tf2[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = VSSQ = L-.

[0143] The drain of the voltage regulator setting transistor Tf3[n] receives the voltage regulator supply voltage LC, its control terminal is electrically connected to the voltage regulator setting terminal NDints[n], and its source is electrically connected to the voltage regulator terminal NDstb[n]. Therefore, the on / off state of the voltage regulator setting transistor Tf3[n] depends on the voltage of the voltage regulator setting terminal NDints[n]. When the voltage regulator setting transistor Tf3[n] is on, it conducts the positive voltage value H (LC = H) of the voltage regulator supply voltage LC to the voltage regulator terminal NDstb[n]. That is, NDstb[n] = LC = H.

[0144] The drain terminal of the voltage regulator setting transistor Tf4[n] is connected to the voltage regulator terminal NDstb[n], the control terminal is connected to the intermediate terminal NDmd[n], and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf4[n] depends on the voltage of the intermediate terminal NDmd[n]. When the voltage regulator setting transistor Tf4[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-.

[0145] The drain of the voltage regulator setting transistor Tf5[n] is connected to the voltage regulator setting terminal NDints[n], the control terminal is connected to the full-gate synchronization signal XON_C, and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf5[n] depends on the voltage of the full-gate synchronization signal XON_C. When the voltage regulator setting transistor Tf5[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = VSSQ = L-.

[0146] The drain terminal of the voltage regulator setting transistor Tf6[n] is connected to the voltage regulator terminal NDstb[n], the control terminal is connected to the full-gate synchronization signal XON_C, and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf6[n] depends on the voltage of the full-gate synchronization signal XON_C. When the voltage regulator setting transistor Tf6[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-.

[0147] In the voltage regulator circuit stbCKT[n], the drain terminal of the voltage regulator transistor Tnmstb[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ; the drain terminal of the voltage regulator transistor Tgstb[n] is electrically connected to the nth level pixel gate signal line G[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the pixel gate ground voltage signal line VSSG; the drain terminal of the voltage regulator transistor Tsstb[n] is electrically connected to the nth level column scan state signal line ST[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ.

[0148] The on / off states of Zener transistors Tnmstb[n], Tgstb[n], and Tsstb[n] all depend on the voltage at the Zener terminal NDstb[n]. When Zener transistor Tnmstb[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-. When Zener transistor Tgstb[n] is on, it conducts the second lowest negative voltage value L (VSSG = L) of the pixel gate ground voltage VSSG to the nth level pixel gate signal line G[n]. That is, G[n] = VSSQ = L-. When Zener transistor Tsstb[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth level column scan state signal ST[n]. That is, ST[n] = VSSQ = L-.

[0149] The above describes the circuit elements and connections within the nth-stage gate drive circuit gtCKT[n]. Next, based on the signal types associated with the nth-stage gate drive circuit gtCKT[n], the circuit elements related to each signal will be explained. The internal signals of the nth-stage gate drive circuit gtCKT[n] include signals at the intermediate terminal NDmd[n], the voltage setting terminal NDints[n], and the voltage regulating terminal NDstb[n]. The transistors associated with these internal signals will then be explained sequentially.

[0150] Depend on Figure 6 It can be seen that, depending on the connection method, transistors electrically connected to internal terminals can be divided into two categories: the first category is transistors electrically connected to internal terminals through control terminals (i.e., transistors controlled by internal terminals); and the second category is transistors electrically connected to internal terminals through drain or source terminals. Table 2 summarizes the transistors connected to each internal terminal (i.e., transistors that change the voltage of the internal terminals).

[0151] Table 2

[0152]

[0153] Next, the circuit elements related to the input signals of the nth-stage gate drive circuit gtCKT[n] will be explained. As mentioned earlier, the input signals of the nth-stage gate drive circuit gtCKT[n] include: the (n+1)th-stage column scan state signal ST[n+1], the (n-1)th-stage column scan state signal ST[n-1], the column-by-column select signal HC[k], the full gate synchronization period signal XON_C, the full gate synchronization enable signal XON_S, the intermediate endpoint reset signal rstST, the regulated endpoint supply voltage LC, the intermediate endpoint ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD.

[0154] Depend on Figure 6 It can be seen that the (n-1)th level column scan state signal line ST[n-1] is electrically connected to the control terminal of the intermediate terminal pull-up transistor Tnmu[n]. Therefore, the conduction state of the intermediate terminal pull-up transistor Tnmu[n] depends on the (n-1)th level column scan state signal ST[n-1]. Furthermore, the (n+1)th level column scan state signal line ST[n+1] is electrically connected to the control terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n]. Therefore, the conduction state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th level column scan state signal ST[n+1].

[0155] Depend on Figure 6 It can be seen that the column-by-column selection signal line HC[k] is electrically connected to the drain terminal of the status signal setting transistor Tss[n] and the drain terminal of the gate signal setting transistor Tgs1[n]. Therefore, when the status signal setting transistor Tss[n] is turned on, it conducts the column-by-column selection signal HC[k] to the nth-level column scan status signal line ST[n], making the voltage of the nth-level column scan status signal line ST[n] equal to the voltage of the column-by-column selection signal HC[k]. Furthermore, when the gate signal setting transistor Tgs1[n] is turned on, it conducts the column-by-column selection signal HC[k] to the nth-level pixel gate signal line G[n], making the voltage of the nth-level pixel gate signal line G[n] equal to the voltage of the column-by-column selection signal HC[k]. That is, G[n] = HC[k].

[0156] Depend on Figure 6It can be seen that during full-gate synchronization, the signal XON_C is electrically connected to the control terminals of the voltage regulator transistors Tf5[n] and Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n]. Therefore, the conduction state of the voltage regulator transistors Tf5[n] and Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] depends on the voltage of the signal XON_C during full-gate synchronization.

[0157] Depend on Figure 6 It can be seen that the full-gate synchronization enable signal line XON_S is electrically connected to the drain terminal of the gate signal setting transistor Tgs2[n]. Therefore, when the gate signal setting transistor Tgs2[n] is turned on, it conducts the full-gate synchronization enable signal XON_S to the nth pixel gate signal line G[n], making the voltage of the nth pixel gate signal G[n] equal to the voltage of the full-gate synchronization enable signal XON_S. That is, G[n] = XON_S.

[0158] Depend on Figure 6 It can be seen that the intermediate endpoint reset signal rstST is electrically connected to the control terminal of the intermediate endpoint reset transistor Tnmd_rst[n]. Therefore, the conduction state of the intermediate endpoint reset transistor Tnmd_rst[n] depends on the voltage of the intermediate endpoint reset signal rstST. When the intermediate endpoint reset signal rstST is set to a positive voltage value H (rstST = H) by the timing controller, causing the intermediate endpoint reset transistor Tnmd_rst[n] to conduct, the intermediate endpoint reset transistor Tnmd_rst[n] conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ to the intermediate endpoint NDmd[n]. That is, NDmd[n] = VSSQ.

[0159] Depend on Figure 6 It can be seen that the voltage supply LC of the regulated endpoint is electrically connected to the drain and control terminal of the regulated endpoint setting transistor Tf1[n], and electrically connected to the drain of the regulated endpoint setting transistor Tf3[n]. Because the voltage supply LC of the regulated endpoint is maintained at a positive voltage value H (LC = H), the regulated endpoint setting transistor Tf1[n] remains on. Furthermore, when the regulated endpoint setting transistor Tf3[n] is on, it conducts the voltage supply LC of the regulated endpoint to the regulated endpoint NDstb[n], making the regulated endpoint NDstb[n] equal to the positive voltage value H. That is, NDstb[n] = LC = H.

[0160] Depend on Figure 6It can be seen that the intermediate terminal ground voltage VSSQ is electrically connected to the sources of the voltage regulator setting transistors Tf5[n], Tf6[n], Tf2[n], Tf4[n], voltage regulator transistors Tnmstb[n], Tsstb[n], intermediate terminal pull-down transistor Tnmd_nxt[n], intermediate terminal reset transistor Tnmd_rst[n], and intermediate terminal pull-down transistor Tnmd_xon[n]. Therefore, when the voltage regulator setting transistors Tf5[n] and Tf2[n] are turned on, the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = VSSQ = L-. When the Zener transistors Tf6[n] and Tf4[n] are turned on, the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the Zener terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-. When any one of the Zener transistors Tnmstb[n], intermediate terminal pull-down transistors Tnmd_nxt[n], Tnmd_xon[n], and intermediate terminal reset transistor Tnmd_rst[n] is turned on, the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the intermediate terminal NDmd[d]. That is, NDmd[d] = VSSQ = L-. When the Zener transistor Tsstb[n] is turned on, the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the nth-level column scan status signal ST[n]. That is, ST[n] = VSSQ = L-.

[0161] Depend on Figure 6 It can be seen that the pixel gate ground voltage VSSG is electrically connected to the source of the Zener transistor Tgstb[n]. Therefore, when the Zener transistor Tgstb[n] is turned on, it conducts the second lowest negative voltage value L (VSSG = L) of the pixel gate ground voltage VSSG to the nth pixel gate signal line G[n]. That is, G[n] = VSSG = L.

[0162] Depend on Figure 6 It can be seen that the gate supply voltage VGHD is electrically connected to the drain of the intermediate terminal pull-up transistor Tnmu[n]. Therefore, when the intermediate terminal pull-up transistor Tnmu[n] is turned on, it conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n] = VGHD = H.

[0163] The output signals of the nth-level gate drive circuit gtCKT[n] are: the nth-level column scan state signal ST[n] and the nth-level pixel gate signal G[n]. Table 3 summarizes the circuit components related to the output signals of the nth-level gate drive circuit gtCKT[n].

[0164] Table 3

[0165]

[0166]

[0167] Please see Figure 7 It is a waveform diagram of the signal associated with the nth-level gate drive circuit gtCKT[n] according to the first embodiment of the present disclosure, used to generate the nth-level pixel gate signal G[n]. Figure 7 The horizontal axis represents time, and the vertical axis represents the signal associated with the gate signal G[n] of the nth pixel. Figure 7 In the diagram, FM1, which is highlighted by the dashed box, represents the change of the signal related to the nth pixel gate signal G[n] during full gate synchronization (between time points t1 and t4); FM2, which is highlighted by the dashed box, represents the change of the signal related to the nth pixel gate signal G[n] during the nth single-level scan (between time points t5 and t9).

[0168] During full gate synchronization, DURall-sync further includes three synchronization phases: STG-a1, STG-a2, and STG-a3. Synchronization phase STG-a1 is between time points t1 and t2, synchronization phase STG-a2 is between time points t2 and t3, and synchronization phase STG-a3 is between time points t3 and t4. For the N-level gate drive circuits gtCKT[1] to gtCKT[N], the circuit behavior of DURall-sync is consistent during full gate synchronization (G[1] = ... = G[N]). According to the concept disclosed herein, the N-level pixel gate signals G[1] to G[N] are simultaneously set to a positive voltage value H during synchronization phase STG-a2 (G[1] = ... = G[N] = H); and during synchronization phases STG-a1 and STG-a3, they are simultaneously set to a second-lowest negative voltage value L (G[1] = ... = G[N] = L). Accordingly, the M*N pixel transistors PXL(1,1)~PXL(M,N) in the pixel array will synchronously receive the pulses of the N-level pixel gate signals G[1]~G[N] and be turned on simultaneously. Therefore, the synchronization phase STG-a2 can also be called the all-gate-on duration.

[0169] According to the concept disclosed herein, the duration of the DURall-scan during the sequential scanning period covers N single-stage scanning periods DURscan[1] to DURscan[N]. The nth-stage single-stage scanning period DURscan[n], corresponding to the nth-stage gate drive circuit gtCKT[n], includes four scanning phases: scanning phases STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n]. Figure 7 In the scanning phase, STG-s1[n] is between time points t5 and t6, STG-s2[n] is between time points t6 and t7, STG-s3[n] is between time points t7 and t8, and STG-s4[n] is between time points t8 and t9.

[0170] Table 4 summarizes the following: Figure 7 In the process, the voltage changes of each signal at different stages.

[0171]

[0172]

[0173] Depend on Figure 7 As can be seen from Table 4, the nth-level pixel gate signal G[n] is set to a positive voltage value during the synchronization phase STG-a2 and the scanning phase STG-s2[n]. During the other synchronization phases STG-a1, STG-a3 and the scanning phases STG-s1[n], STG-s3[n], STG-s4[n], it is set to the second lowest negative voltage value L or the lowest negative voltage value L-. Therefore, it can be seen that the gate drive circuit gtCKT[n] generates a synchronization pulse synchronously with the other gate drive circuits gtCKT[1]~gtCKT[n-1], gtCKT[n+1]~gtCKT[N] during the synchronization phase STG-a2 and the scanning phase STG-s2[n] of DURscan[n] during the nth-level single-level scan.

[0174] According to the concept disclosed herein, the nth stage single-stage scan period DURscan[n] corresponding to the nth stage gate drive circuit gtCKT[n] partially overlaps with the single-stage scan periods DURscan[n-3], DURscan[n-2], DURscan[n-1], DURscan[n+1], DURscan[n+2], and DURscan[n+3] of the preceding and following three stages. Therefore, the duration of the DURall-scan during the sequential scan period is equivalent to the duration of (N+6) scan stages. The following describes the periods that overlap with the scan stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n] in the nth stage single-stage scan period DURscan[n], and the scan stages contained in the other stages DURscan[n-3] to DURscan[n+3].

[0175] The scanning phase STG-s1[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s4[n-3] of DURscan[n-3] during the (n-3)th single-stage scan period corresponding to the (n-3)th gate drive circuit gtCKT[n-3]; the scanning phase STG-s3[n-2] of DURscan[n-2] during the (n-2)th single-stage scan period corresponding to the (n-2)th gate drive circuit gtCKT[n-2]; and the scanning phase STG-s2[n-1] of DURscan[n-1] during the (n-1)th single-stage scan period corresponding to the (n-1)th gate drive circuit gtCKT[n-1].

[0176] The scanning phase STG-s2[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s4[n-2] of DURscan[n-2] during the (n-2)th single-stage scan period corresponding to the (n-2)th gate drive circuit gtCKT[n-2]; it overlaps with the scanning phase STG-s3[n-1] of DURscan[n-1] during the (n-1)th single-stage scan period corresponding to the (n-1)th gate drive circuit gtCKT[n-1]; and it overlaps with the scanning phase STG-s1[n+1] of DURscan[n+1] during the (n+1)th single-stage scan period corresponding to the (n+1)th gate drive circuit gtCKT[n+1].

[0177] The scanning phase STG-s3[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s4[n-1] of DURscan[n-1] during the (n-1)th single-stage scan period corresponding to the (n-1)th gate drive circuit gtCKT[n-1]; it overlaps with the scanning phase STG-s2[n+1] of DURscan[n+1] during the (n+1)th single-stage scan period corresponding to the (n+1)th gate drive circuit gtCKT[n+1]; and it overlaps with the scanning phase STG-s1[n+2] of DURscan[n+2] during the (n+2)th single-stage scan period corresponding to the (n+2)th gate drive circuit gtCKT[n+2].

[0178] The scanning phase STG-s4[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s3[n+1] of DURscan[n+1] during the (n+1)th single-stage scan period corresponding to the (n+1)th gate drive circuit gtCKT[n+1]; it overlaps with the scanning phase STG-s2[n+2] of DURscan[n+2] during the (n+2)th single-stage scan period corresponding to the (n+2)th gate drive circuit gtCKT[n+2]; and it overlaps with the scanning phase STG-s1[n+3] of DURscan[n+3] during the (n+3)th single-stage scan period corresponding to the (n+3)th gate drive circuit gtCKT[n+3].

[0179] As mentioned earlier, the input signals received by the nth-stage gate drive circuit gtCKT[n] can be divided into two categories. One type of input signal has a constant voltage value, while the logic level of the other type of input signal varies depending on the stage of DURall-sync during full gate synchronization and DURscan[n] during the nth-stage single-level scan. The former includes: the regulated terminal supply voltage LC with a positive voltage value H, the intermediate terminal ground voltage VSSQ with the lowest negative voltage value L-, the pixel gate ground voltage VSSG with the second lowest negative voltage value L, and the gate supply voltage VGHD with a positive voltage value H. The latter includes: the column scan state signal ST[n-1] of the (n-1)th stage, the column scan state signal ST[n+1] of the (n+1)th stage, the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C. The logic level of the input signal changes with the different stages, which in turn causes the internal and output signals of the nth-stage gate drive circuit gtCKT[n] to change accordingly.

[0180] In these input signals that change logic levels, this disclosure assumes that the high logic levels of the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the column-by-column select signal HC[k] all correspond to positive voltage values ​​H, and the low logic levels all correspond to the lowest negative voltage value L-. Furthermore, it assumes that the high logic level of the all-gate synchronization enable signal XON_S corresponds to the positive voltage value H.

[0181] Please also note that the low logic level of the full-gate synchronization enable signal XON_S corresponds to a negative voltage value, and this negative voltage value can be determined according to the product requirements of the display panel. For simplicity, it is assumed here that in the first embodiment, the low logic level of the full-gate synchronization enable signal XON_S corresponds to the second lowest negative voltage value L. In actual applications, the negative voltage value corresponding to the low logic level of the full-gate synchronization enable signal XON_S can also be the lowest negative voltage value L- or other selected negative voltage values.

[0182] The following uses Figures 8A-8C and Figures 9A-9D Explain how the nth-stage gate drive circuit gtCKT[n] changes the conduction state of its internal transistors in response to changes in the column scan state signals ST[n-1] (n-1) and ST[n+1] (n+1) ...

[0183] Please see Figures 8A-8C This is a schematic diagram illustrating the state of DURall-sync at different stages during full gate synchronization, based on a first embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. The following will not specifically describe input signals with constant voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD; rather, it will only explain the effects of changes in the (n-1)th-stage column scan state signal ST[n-1], the (n+1)th-stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the signal XON_C during full gate synchronization on the nth-stage gate drive circuit gtCKT[n].

[0184] Please also see Figure 6 , 7 8A. Figure 8A for, Figure 6The state of the nth-stage gate drive circuit gtCKT[n] during the synchronization phase STG-a1 of DURall-sync during full gate synchronization. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a1, the (n-1)th stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the (n+1)th stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, XON_S = L, and XON_C = H.

[0185] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-a1 during the synchronization phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-a1 and the on / off state of the transistors during the synchronization phase.

[0186] Since the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0187] Since the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0188] During full-gate synchronization, the signal XON_C is a positive voltage H (XON_C = H), and the regulator terminal setting transistors Tf5[n], Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] are all turned on. With the turn-on of the regulator terminal setting transistor Tf5[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the regulator terminal NDints[n] through the regulator terminal setting transistor Tf5[n]. That is, NDints[n] = VSSQ = L-. With the turn-on of the regulator terminal setting transistor Tf6[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the regulator terminal NDstb[n] through the regulator terminal setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0189] As the intermediate terminal pull-down transistor Tnmd_xon[n] is turned on, the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the intermediate terminal NDmd[n] through the intermediate terminal pull-down transistor Tnmd_xon[n]. That is, NDmd[n] = VSSQ = L-. Because the voltage of the intermediate terminal NDmd[n] is the lowest negative voltage value L- (NDmd[n] = VSSQ = L-), the voltage regulator setting transistors Tf2[n] and Tf4[n], which are connected to the intermediate terminal NDmd[n], are in the off state. Therefore, in Figure 8A In the process, the voltage regulator setting transistor Tf2[n] in the off state will not affect the voltage of the voltage regulator setting terminal NDints[n]; and the voltage regulator setting transistor Tf4[n] in the off state will not affect the voltage of the voltage regulator terminal NDstb[n].

[0190] As the gate signal setting transistor Tgs2[n] is turned on, the second lowest negative voltage value L (XON_S = L) of the all-gate synchronization enable signal XON_S is conducted to the nth pixel gate signal line G[n] through the gate signal setting transistor Tgs2[n]. That is, G[n] = XON_S = L.

[0191] exist Figure 8AIn this circuit, since both the voltage regulator terminal setting transistors Tf1[n] and Tf5[n] are in the on state, the voltage regulator terminal NDints[n] simultaneously receives the positive voltage value H (LC = H) of the voltage regulator terminal supply voltage LC through the voltage regulator terminal setting transistor Tf1[n], and the minimum negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ through the voltage regulator terminal setting transistor Tf5[n]. Therefore, the voltages of the voltage regulator terminal NDints[n] connected between the voltage regulator terminal supply voltage signal line LC and the intermediate terminal ground voltage signal line VSSQ create a voltage divider effect between the positive voltage value H (LC = H) of the voltage regulator terminal supply voltage LC and the minimum negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ. Thus, the voltage of the voltage regulator terminal NDints[n] during the synchronization phase of STG-a1 is between the minimum negative voltage value L- and the positive voltage value H. That is, L- <NDints[n]<H。

[0192] In practical applications, the voltage value of the voltage regulator setting terminal NDints[n] depends on the size relationship between the voltage regulator setting transistors Tf1[n] and Tf5[n]. For example, if the voltage regulator setting transistors Tf1[n] and Tf5[n] have the same size, the voltage value of the voltage regulator setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n] = (H + L-) / 2.

[0193] Therefore, in Figure 8A In this case, the voltage at the regulator setting terminal NDints[n] is insufficient to turn on the regulator setting transistor Tf3[n]. Therefore, the voltage at the regulator setting terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ conducted by the regulator setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0194] Consequently, the Zener transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage at the Zener terminal NDstb[n] equals the minimum negative voltage value L- (NDstb[n] = L-). Therefore, in the synchronization phase STG-a1, the Zener transistor Tnmstb[n] does not affect the voltage at the intermediate terminal NDmd[n]; the Zener transistor Tgstb[n] does not affect the voltage of the nth-level pixel gate signal G[n]; and the Zener transistor Tsstb[n] does not affect the voltage of the nth-level column scan state signal ST[n].

[0195] exist Figure 8AIn the context of the intermediate endpoint pull-down transistor Tnmd_xon[n] being turned on, the intermediate endpoint NDmd[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (NDmd[n] = VSSQ = L-). This causes the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] to be turned off, thus the column-by-column selection signal HC[k] (HC[k] = L-) does not affect the voltage of the nth pixel gate signal G[n]. Figure 8A In this circuit, the state signal setting transistor Tss[n] and the Zener transistor Tsstb[n], which may affect the voltage of the nth-level column scan state signal ST[n], are both open circuits. Therefore, the nth-level column scan state signal ST[n] is in a floating state during the synchronization phase of STG-a1.

[0196] Table 5A summarizes the following: Figure 8A In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0197] Table 5A

[0198]

[0199]

[0200]

[0201] Please also see Figure 6 , 7 8B. Figure 8B For, when Figure 6 The nth-stage gate drive circuit gtCKT[n] is shown in the state of STG-a2 during the DURall-sync synchronization phase of the full gate synchronization. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a2, the (n-1)th stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the (n+1)th stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the positive voltage value H by the timing controller, and the full gate synchronization signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, XON_S = H, and XON_C = H.

[0202] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-a2 during the synchronization phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-a2 and the on / off state of the transistors during the synchronization phase.

[0203] Since the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0204] Since the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0205] During full-gate synchronization, the signal XON_C is a positive voltage H (XON_C = H), and the regulator terminal setting transistors Tf5[n], Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] are all turned on. With the turn-on of the regulator terminal setting transistor Tf5[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the regulator terminal NDints[n] through the regulator terminal setting transistor Tf5[n]. That is, NDints[n] = VSSQ = L-. With the turn-on of the regulator terminal setting transistor Tf6[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ is conducted to the regulator terminal NDstb[n] through the regulator terminal setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0206] As the intermediate terminal pull - down transistor Tnmd_xon[n] conducts, the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ is conducted to the intermediate terminal NDmd[n] through the intermediate terminal pull - down transistor Tnmd_xon[n]. That is, NDmd[n]=VSSQ = L -. Due to the fact that the voltage of the intermediate terminal NDmd[n] is the lowest negative voltage value L - (NDmd[n]=VSSQ = L -), the voltage - stabilizing terminal setting transistors Tf2[n] and Tf4[n] are in the off state during the synchronization stage STG - a2. Therefore, in Figure 8B , the voltage - stabilizing terminal setting transistor Tf2[n] does not affect the voltage of the voltage - stabilizing setting terminal NDints[n]; and, the voltage - stabilizing terminal setting transistor Tf4[n] does not affect the voltage of the voltage - stabilizing terminal NDstb[n].

[0207] As the gate signal setting transistor Tgs2[n] conducts, the full - gate synchronization enable signal XON_S is conducted to the n - th stage pixel gate signal line G[n] through the gate signal setting transistor Tgs2[n]. Also, because the full - gate synchronization enable signal XON_S is a positive voltage value H (XON_S = H), at this time the n - th stage pixel gate signal G[n] is a positive voltage value H. That is, G[n]=XON_S = H.

[0208] In Figure 8B , since the voltage - stabilizing terminal setting transistors Tf1[n] and Tf5[n] are both in the on state, the voltage - stabilizing setting terminal NDints[n] receives the positive voltage value H (LC = H) of the voltage - stabilizing terminal supply voltage LC through the voltage - stabilizing terminal setting transistor Tf1[n], and receives the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ through the voltage - stabilizing terminal setting transistor Tf5[n]. Accordingly, the voltage - stabilizing terminal setting transistors Tf1[n] and Tf5[n] connected between the voltage - stabilizing terminal supply voltage signal line LC and the intermediate terminal ground voltage signal line VSSQ form a voltage - dividing effect between the positive voltage value H and the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ.

[0209] Therefore, the voltage of the voltage - stabilizing setting terminal NDints[n] during the synchronization stage STG - a2 is between the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ and the positive voltage value H (LC = H) of the voltage - stabilizing terminal supply voltage LC. That is, L - < NDints[n]<H. And, in Figure 8BIn this case, the voltage at the regulator setting terminal NDints[n] is insufficient to turn on the regulator setting transistor Tf3[n]. Therefore, the voltage at the regulator setting terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ conducted by the regulator setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0210] Consequently, the Zener transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of their regulated endpoint NDstb[n], which is connected to their control terminal, is equal to the minimum negative voltage value L- (NDstb[n] = L-). Therefore, in the synchronization phase STG-a2, the Zener transistor Tnmstb[n] does not affect the voltage of the intermediate endpoint NDmd[n]; the Zener transistor Tgstb[n] does not affect the voltage of the nth-level pixel gate signal G[n]; and the Zener transistor Tsstb[n] does not affect the voltage of the nth-level column scan state signal ST[n].

[0211] exist Figure 8B In the context of the intermediate endpoint pull-down transistor Tnmd_xon[n] being turned on, the intermediate endpoint NDmd[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (NDmd[n] = VSSQ = L-). This causes the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] to be turned off, thus the column-by-column selection signal HC[k] (HC[k] = L-) does not affect the voltage of the nth pixel gate signal G[n]. Figure 8B In the process, the state signal setting transistor Tss[n] and the Zener transistor Tsstb[n], which may affect the voltage of the nth-level column scan state signal ST[n], are both open circuits. Therefore, the nth-level column scan state signal ST[n] is in a floating state during the synchronization phase of STG-a2.

[0212] Table 5B summarizes the following: Figure 8B In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0213] Table 5B

[0214]

[0215]

[0216]

[0217] Please also see Figure 6 , 7 8C. Figure 8C for, Figure 6 The state of the nth-stage gate drive circuit gtCKT[n] during the synchronization phase STG-a3 of DURall-sync during full gate synchronization. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a3, the column scan state signal ST[n-1] of the (n-1)th stage is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the column scan state signal ST[n+1] of the (n+1)th stage is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, XON_S = L, and XON_C = H.

[0218] Depend on Figure 7 The waveform diagram shows that the input signals (HC[k], ST[n-1], ST[n+1], XON_C, XON_S) have the same electrical averages at STG-a1 and STG-a3 during the synchronization phase. Therefore, the nth stage gate drive circuit gtCKT[n]... Figure 8C The state, and the nth stage gate drive circuit gtCKT[n] in Figure 8A The states are the same. The details of the nth stage gate drive circuit gtCKT[n] will not be repeated here. Figure 8C The state.

[0219] Table 5C summarizes the following: Figure 8C In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0220] Table 5C

[0221]

[0222]

[0223] Please see Figures 9A-9DThis is a schematic diagram illustrating the state of DURscan[n] at different stages during the nth-stage single-stage scan, according to a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the present disclosure. The following will not specifically describe input signals with constant voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD. Instead, the effects of changes in the (n-1)th-stage column scan state signal ST[n-1], the (n+1)th-stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], the full-gate synchronization enable signal XON_S, and the signal XON_C during full-gate synchronization on the nth-stage gate drive circuit gtCKT[n].

[0224] Please also see Figure 6 , 7 9A. Figure 9A for, Figure 6 The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s1[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s1[n], the (n-1)th-stage column scan state signal ST[n-1] is set to a positive voltage value H by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full-gate synchronization period signal XON_C is set to the lowest negative voltage value L- by the timing controller. That is, ST[n-1] = H, ST[n+1] = L-, HC[k] = L-, XON_S = L, and XON_C = L-.

[0225] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-s1[n] during the scanning phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-s1[n] and the on / off state of the transistors during the scanning phase.

[0226] Because the (n-1)th column scan state signal ST[n-1] has a positive voltage value H (ST[n-1] = H) during the scan phase of STG-s1[n], the intermediate terminal pull-up transistor Tnmu[n] is turned on. At this time, the intermediate terminal pull-up transistor Tnmu[n] conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n] = VGHD = H.

[0227] Because the voltage at the intermediate terminal NDmd[n] is equal to the positive voltage value H (NDmd[n] = H), the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], the voltage regulator terminal setting transistor Tf2[n], and the voltage regulator terminal setting transistor Tf4[n] connected to the intermediate terminal NDmd[n] are all turned on during the scanning phase.

[0228] Because the (n+1)th column scan state signal ST[n+1] has the lowest negative voltage value L- (ST[n+1]=L-) during the scan phase of STG-s1[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0229] During the scanning phase, the column-by-column selection signal HC[k] has the lowest negative voltage value L- (HC[k] = L-) at STG-s1[n], and both the status signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are turned on. Therefore, the status signal setting transistor Tss[n] conducts the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] to the nth-level column scan status signal line ST[n] (ST[n] = HC[k] = L-); and the gate signal setting transistor Tgs1[n] conducts the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] to the nth-level pixel gate signal line G[n] (G[n] = HC[k] = L-).

[0230] exist Figure 9A In the diagram, the two ends of capacitor C[n] are respectively set to a positive voltage value H by the intermediate terminal NDmd[n] (NDmd[n] = VGHD = H) and a minimum negative voltage value L- by the nth pixel gate signal G[n] (G[n] = HC[k] = L-). Therefore, capacitor C[n] will be charged during the scanning phase of STG-s1[n]. The voltage difference across capacitor C[n] is expressed as capacitor voltage difference ΔVc[n].

[0231] exist Figure 9AIn [the circuit], since the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-) during the full-gate synchronization, the voltage-regulating endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] whose control terminals are connected to the signal line XON_C during the full-gate synchronization are all turned off. Therefore, during the scanning stage STG-s1[n], the voltage-regulating endpoint setting transistor Tf5[n] does not affect the voltage of the voltage-regulating setting endpoint NDints[n]; the voltage-regulating endpoint setting transistor Tf6[n] does not affect the voltage of the voltage-regulating endpoint NDstb[n]; the intermediate endpoint pull-down transistor Tnmd_xon[n] does not affect the voltage of the intermediate endpoint NDmd[n]; and the gate signal setting transistor Tgs2[n] does not affect the voltage of the gate signal G[n] of the nth-stage pixel.

[0232] Continuing from the above, the gate signal setting transistor Tgs2[n] is turned off because its control terminal receives the signal XON_C (XON_C = L-) during the full-gate synchronization with the lowest negative voltage value L-. Consequently, the full-gate synchronization enable signal XON_S (XON_S = L) set to the second lowest negative voltage value cannot be conducted to the gate signal line G[n] of the nth-stage pixel. In other words, the full-gate synchronization enable signal XON_S at this time does not affect the circuit behavior of the nth-stage gate drive circuit gtCKT[n].

[0233] In Figure 9A [the circuit], since the voltage-regulating endpoint setting transistors Tf1[n] and Tf2[n] are both in the conducting state, the voltage-regulating setting endpoint NDints[n] receives, through the voltage-regulating endpoint setting transistor Tf1[n], the positive voltage value H of the voltage-regulating endpoint supply voltage LC (LC = H), and through the voltage-regulating endpoint setting transistor Tf2[n], receives the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-). Accordingly, the voltage-regulating endpoint setting transistors Tf1[n] and Tf2[n] connected between the voltage-regulating endpoint supply voltage signal line LC and the intermediate endpoint ground voltage signal line VSSQ form a voltage-dividing effect.

[0234] Therefore, the voltage of the voltage-regulating setting endpoint NDints[n] during the synchronization stage STG-a2 is between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) and the positive voltage value H of the voltage-regulating endpoint supply voltage LC (LC = H). That is, L- < NDints[n] < H. And, in Figure 9AIn the process, the voltage at the regulator setting terminal NDints[n] is insufficient to turn on the regulator setting transistor Tf3[n]. Therefore, the voltage at the regulator terminal NDstb[n] during the synchronization phase of STG-a2 is equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ conducted by the regulator setting transistor Tf4[n]. That is, NDstb[n] = VSSQ = L-.

[0235] Consequently, the Zener transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of their regulated endpoint NDstb[n], which is connected to their control terminal, is equal to the minimum negative voltage value L- (NDstb[n] = L-). Therefore, during the scanning phase STG-s1[n], the Zener transistor Tnmstb[n] does not affect the voltage of the intermediate endpoint NDmd[n]; the Zener transistor Tgstb[n] does not affect the voltage of the nth-level pixel gate signal G[n]; and the Zener transistor Tsstb[n] does not affect the voltage of the nth-level column scan state signal ST[n].

[0236] Table 6A summarizes the following: Figure 9A In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0237] Table 6A

[0238]

[0239]

[0240] Please also see Figure 6 , 7 9B. Figure 9B for, Figure 6The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s2[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], the (n-1)th-stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the positive voltage value H by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = H, XON_S = L, and XON_C = L-.

[0241] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-s2[n] during the scanning phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-s2[n] and the on / off state of the transistors during the scanning phase.

[0242] Since the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0243] Since the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0244] exist Figure 9BIn this case, since the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-) during the full-gate synchronization, the voltage stabilizing endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] connected to the signal line XON_C during the full-gate synchronization are all turned off. Therefore, during the scanning stage STG-s1[n], the voltage stabilizing endpoint setting transistor Tf5[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the voltage stabilizing setting endpoint NDints[n]; the voltage stabilizing endpoint setting transistor Tf6[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the voltage stabilizing endpoint NDstb[n]; the intermediate endpoint pull-down transistor Tnmd_xon[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the intermediate endpoint NDmd[n]; and the gate signal setting transistor Tgs2[n] does not allow the second lowest negative voltage value L of the full-gate synchronization enable signal XON_S (XON_S = L) to affect the voltage of the nth-stage pixel gate signal G[n].

[0245] In Figure 9B In this case, since the voltage stabilizing endpoint setting transistors Tf1[n] and Tf2[n] are both in the conducting state, the voltage stabilizing setting endpoint NDints[n] receives the positive voltage value H of the voltage stabilizing endpoint supply voltage LC (LC = H) through the voltage stabilizing endpoint setting transistor Tf1[n] and the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) through the voltage stabilizing endpoint setting transistor Tf2[n] at the same time. Accordingly, the voltage stabilizing endpoint setting transistors Tf1[n] and Tf2[n] connected between the voltage stabilizing endpoint supply voltage signal line LC and the intermediate endpoint ground voltage signal line VSSQ form a voltage division effect between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) and the positive voltage value H of the voltage stabilizing endpoint supply voltage LC (LC = H).

[0246] Therefore, the voltage of the voltage stabilizing setting endpoint NDints[n] during the synchronization stage STG-a2 is between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ and the positive voltage value H of the voltage stabilizing endpoint supply voltage LC. That is, L- < NDints[n] < H. And, in Figure 9BIn this case, the voltage at the regulator setting terminal NDints[n] is insufficient to turn on the regulator setting transistor Tf3[n]. Therefore, the voltage at the regulator setting terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ conducted by the regulator setting transistor Tf4[n]. That is, NDstb[n] = VSSQ = L-.

[0247] Consequently, the Zener transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of their regulated endpoint NDstb[n], which is connected to their control terminal, is equal to the minimum negative voltage value L- (NDstb[n] = L-). Therefore, during the scanning phase STG-s2[n], the Zener transistor Tnmstb[n] does not affect the voltage of the intermediate endpoint NDmd[n]; the Zener transistor Tgstb[n] does not affect the voltage of the nth-level pixel gate signal G[n]; and the Zener transistor Tsstb[n] does not affect the voltage of the nth-level column scan state signal ST[n].

[0248] As mentioned earlier, the intermediate endpoint NDmd[n] is at... Figure 9A The transistor Tnmu has been charged to a positive voltage value H (NDmd[n] = H) due to the conduction of the intermediate terminal pull-up transistor Tnmu. The positive voltage value H (HC[k] = H) of the column selection signal HC[k] is conducted to the nth pixel gate signal line G[n] (G[n] = HC[k] = H) by setting the conduction of the gate signal Tgs1[n].

[0249] Following on, Figure 9A The intermediate terminal NDmd[n] will be charged to the positive voltage value H of the gate supply voltage VGHD (NDmd[n] = VGHD = H) due to the conduction of the intermediate terminal pull-up transistor Tnmu. To facilitate the distinction between the voltages of the intermediate terminal NDmd[n] in STG-s1[n] and STG-s2[n] during different scan phases, the voltages of the intermediate terminal NDmd[n] in STG-s1[n] and STG-s2[n] during the scan phase can be further represented as NDmd[n](@STG-s1[n]) and NDmd[n](@STG-s2[n]), respectively. The voltages of other signals in STG-s1[n] and STG-s2[n] during the scan phase can also be represented in a similar manner.

[0250] exist Figure 9B In the process, the intermediate terminal pull-up transistor Tnmu is disconnected, causing the intermediate terminal NDmd[n] to be in a floating state during the scanning phase of STG-s2[n]. When the intermediate terminal NDmd[n] is in a floating state, its level is temporarily maintained at the positive voltage value H of STG-s1[n] during the scanning phase, just as the intermediate terminal pull-up transistor Tnmu is disconnected.

[0251] During the scanning phase, the gate signal setting transistor Tgs1[n] and STG-s2[n] remain on, so that the voltage of the nth pixel gate signal G[n] during the scanning phase is equal to the voltage of the column-by-column selection signal HC[k] during the scanning phase. Furthermore, because the column-by-column selection signal HC[k] turned on by the gate signal setting transistor Tgs1[n] switches from the lowest negative voltage value L- (HC[k]=L-) of STG-s1[n] in the scanning phase to the positive voltage value H (HC[k]=H) of STG-s2[n] in the scanning phase, the nth pixel gate signal G[n] also rises from the lowest negative voltage value L- (G[n](@)STG-s1[n]=L-) of STG-s1[n] in the scanning phase to the positive voltage value H (G[n](@)STG-s2[n]=H) of STG-s2[n] in the scanning phase.

[0252] Because capacitor C is positioned between the intermediate endpoint NDmd[n] in the floating state and the nth pixel gate signal G[n], and because the intermediate endpoint NDmd[n] in the floating state temporarily maintains a positive voltage value H equal to the scan phase STG-s1[n], and capacitor C has a capacitance difference ΔVc[n], coupling occurs between the intermediate endpoint NDmd[n] and the nth pixel gate signal G[n]. Consequently, the voltage NDmd[n] (@STG-s2[n]) of the intermediate endpoint NDmd[n] in the scan phase STG-s2[n] will further increase from the positive voltage value H of the scan phase STG-s1[n] (NDmd[n] (@STG-s1[n]) = VGHD = H). At this time, the voltage NDmd[n] (@STG-s2[n]) of the intermediate endpoint NDmd[n] during the scanning phase of STG-s2[n] will rise to the sum of the positive voltage value H and the capacitor voltage difference ΔVc[n] (H+ΔVc[n]).

[0253] As can be seen from the foregoing description, the voltage NDmd[n](@STG-s2[n]) of the intermediate endpoint NDmd[n] during the scanning phase of STG-s2[n] can be expressed as follows: NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]=VGHD+ΔVc[n]=H+ΔVc[n].

[0254] Consequently, the voltage NDmd[n](@STG-s2[n])=H+ΔVc[n) at the intermediate endpoint NDmd[n] during the scanning phase allows the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] to be stably maintained in the on state during the scanning phase of STG-s2[n]. Specifically, the conduction of the state signal setting transistor Tss[n] allows the nth-level column scan state signal ST[n] to be maintained at a positive voltage value H (ST[n]=HC[k]=H). Furthermore, the conduction of the gate signal setting transistor Tgs1[n] allows the nth-level pixel gate signal G[n] to be stably maintained at a positive voltage value H (G[n]=H).

[0255] Table 6B summarizes the following: Figure 9B In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0256] Table 6B

[0257]

[0258]

[0259] Please also see Figure 6 , 7 9C. Figure 9C for, Figure 6 The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s3[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s3[n], the (n-1)th-stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the positive voltage value H by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full-gate synchronization period signal XON_C is set to the lowest negative voltage value L- by the timing controller. That is, ST[n-1] = L-, ST[n+1] = H, HC[k] = L-, XON_S = L, and XON_C = L-.

[0260] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-s3[n] during the scanning phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-s3[n] and the on / off state of the transistors during the scanning phase.

[0261] Since the (n-1)th column scan state signal ST[n-1] has the lowest negative voltage value L- (ST[n-1]=L-) during the scan phase of STG-s3[n], the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0262] Since the (n+1)th column scan state signal ST[n+1] has a positive voltage value H (ST[n+1]=H) during the scan phase of STG-s3[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] conducts the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n], making the intermediate terminal NDmd[n] equal to the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ. That is, NDmd[n]=VSSQ=L-.

[0263] exist Figure 9C During the full gate synchronization period, because the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-), the voltage regulator setting transistors Tf5[n] and Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n], which are connected to the control terminal and the signal line XON_C during the full gate synchronization period, are all disconnected. Therefore, during the scanning phase STG-s3[n], the voltage regulator setting transistor Tf5[n] will not affect the voltage of the voltage regulator setting terminal NDints[n]; the voltage regulator setting transistor Tf6[n] will not affect the voltage of the voltage regulator terminal NDstb[n]; the intermediate terminal pull-down transistor Tnmd_xon[n] will not affect the voltage of the intermediate terminal NDmd[n]; and the gate signal setting transistor Tgs2[n] will not affect the voltage of the nth pixel gate signal G[n].

[0264] exist Figure 9CIn the above, because the voltage regulator setting transistor Tf1[n] is turned on and the voltage regulator setting transistors Tf5[n] and Tf2[n] are both turned off, the voltage at the voltage regulator setting terminal NDints[n] is equal to the positive voltage value H (NDints[n] = LC = H). Consequently, the voltage regulator transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all turned on because the voltage at their control terminal NDstb[n] is equal to the positive voltage value H (NDstb[n] = H). Therefore, in the scanning phase STG-s3[n], the voltage of the intermediate endpoint NDmd[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ when the Zener transistor Tnmstb[n] is turned on (NDmd[n] = VSSQ = L-); the voltage of the nth level pixel gate signal G[n] is set to the second lowest negative voltage value L of the pixel gate ground voltage VSSG when the Zener transistor Tgstb[n] is turned on (G[n] = VSSG = L); and the voltage of the nth level column scan state signal ST[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ when the Zener transistor Tsstb[n] is turned on (ST[n] = VSSQ = L-).

[0265] In conclusion, Figure 9C In this process, the voltage of the intermediate endpoint NDmd[n] is simultaneously pulled down to the lowest negative voltage value L- (NDmd[n] = VSSQ = L-) by both the Zener transistor Tnmstb[n] and the intermediate endpoint pull-down transistor Tnmd_nxt[n]. Therefore, the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n], which are connected to the control terminal and the intermediate endpoint NDmd[n], are both in the off state. At this time, the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] will not affect the nth-level column scan state signal ST[n], nor will it affect the nth-level pixel gate signal G[n].

[0266] Table 6C summarizes the following: Figure 9C In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0267] Table 6C

[0268]

[0269]

[0270]

[0271] Please also see Figure 6 , 7 9D. Figure 9D for, Figure 6 The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s4[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s4[n], the (n-1)th-stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full-gate synchronization period signal XON_C is set to the lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, XON_S = L, and XON_C = L-.

[0272] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-s4[n] during the scanning phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-s4[n] and the on / off state of the transistors during the scanning phase.

[0273] Since the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0274] Since the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0275] exist Figure 9DIn the above, because the voltage regulator setting transistor Tf1[n] is turned on and the voltage regulator setting transistors Tf5[n] and Tf2[n] are both turned off, the voltage at the voltage regulator setting terminal NDints[n] is equal to the positive voltage value H (NDints[n] = LC = H). Consequently, the voltage regulator transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all turned on because the voltage at their control terminal NDstb[n] is equal to the positive voltage value H (NDstb[n] = H). Therefore, in the scanning phase STG-s4[n], the voltage of the intermediate terminal NDmd[n] is set to the lowest negative voltage value L- (NDmd[n]=VSSQ=L-) as the Zener transistor Tnmstb[n] is turned on; the voltage of the nth pixel gate signal G[n] is set to the second lowest negative voltage value L (G[n]=VSSG=L) as the Zener transistor Tgstb[n] is turned on; and the voltage of the nth column scan state signal ST[n] is set to the lowest negative voltage value L- (ST[n]=VSSQ=L-) as the Zener transistor Tsstb[n] is turned on.

[0276] In conclusion, Figure 9D In this process, the voltage of the intermediate endpoint NDmd[n] is pulled down to the lowest negative voltage value L- (NDmd[n] = VSSQ = L-) by the Zener transistor Tnmstb[n]. Therefore, the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n], which are connected to the intermediate endpoint NDmd[n], are both in the off state. At this time, the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] will not affect the nth-level column scan state signal ST[n], nor will it affect the nth-level pixel gate signal G[n].

[0277] exist Figure 9D During the full gate synchronization period, because the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-), the voltage regulator setting transistors Tf5[n] and Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n], which are connected to the control terminal and the signal line XON_C during the full gate synchronization period, are all disconnected. Therefore, during the scanning phase STG-s4[n], the voltage regulator setting transistor Tf5[n] will not affect the voltage of the voltage regulator setting terminal NDints[n]; the voltage regulator setting transistor Tf6[n] will not affect the voltage of the voltage regulator terminal NDstb[n]; the intermediate terminal pull-down transistor Tnmd_xon[n] will not affect the voltage of the intermediate terminal NDmd[n]; and the gate signal setting transistor Tgs2[n] will not affect the voltage of the nth pixel gate signal G[n].

[0278] Table 6D summarizes the following: Figure 9D In this context, how do input signals such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], the all-gate synchronization period signal XON_C, and the regulated terminal supply voltage LC=H affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0279] Table 6D

[0280]

[0281]

[0282] Table 7 summarizes the transistors in the nth-stage gate drive circuit gtCKT[n] of the first embodiment. Figures 8A-8C The on / off states of transistors 9A to 9D are shown in Table 7. In Table 7, the hyphen ("-") indicates that the transistor is in the off state.

[0283]

[0284]

[0285] Please also see Figure 7 , 8A ~8C, 9A~9D. Since each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to a gate signal setting transistor Tgs2[1]~Tgs2[N], and these gate signal setting transistors Tgs2[1]~Tgs2[N] are all controlled by the same full gate synchronization period signal XON_C, the behavior of the gate signal setting transistors Tgs2[1]~Tgs2[N] is consistent.

[0286] exist Figure 7 During full gate synchronization, the signal XON_C is maintained at a positive voltage value H during DURall-sync; during the nth single-stage scan, DURscan[n] is maintained at the lowest negative voltage value L-. Therefore, the gate signal setting transistors Tgs2[1] to Tgs2[N], the voltage regulator setting transistors Tf5[n] and Tf6[n], and the intermediate terminal pull-down transistor Tnmd_xon[n], which are connected to the signal line XON_C during full gate synchronization, are maintained in the on state during DURall-sync; and during the sequential scan, DURall-scan is maintained in the off state.

[0287] When the gate signal setting transistors Tgs2[1] to Tgs2[N] maintain the on state during the all-gate synchronization period DURall-sync with the positive voltage value (XON_C = H) of the all-gate synchronization period signal XON_C, the voltages of the N-stage pixel gate signals G[1] to G[n] are simultaneously determined by the voltage of the all-gate synchronization enable signal XON_S. From Figure 7 It can be seen that the all-gate synchronization enable signal XON_S is only set to the positive voltage value H (XON_S = H) during the synchronization stage STG-a2 in the all-gate synchronization period DURall-sync, and is set to the second lowest negative voltage value L in the remaining stages. Thereby, the timing controller can utilize the all-gate synchronization enable signal XON_S (XON_S = L) to synchronously set the N-stage pixel gate signals G[1] to G[N] to the positive voltage value H (G[1] =... = G[N] = H) during the synchronization stage STG-a2 in the all-gate synchronization period DURall-sync. On the other hand, by controlling the gate signal setting transistors Tgs2[1] to Tgs2[N] to maintain the off state during the n-stage single-stage scan period DURscan[n] with the lowest negative voltage value L- (XON_C = L-) of the all-gate synchronization period signal XON_C, the voltage of the all-gate synchronization enable signal XON_S does not affect the voltages of the N-stage pixel gate signals G[1] to G[N].

[0288] When the voltage regulator end point setting transistors Tf5[n], Tf6[n] maintain the on state during the all-gate synchronization period DURall-sync with the positive voltage value (XON_C = H) of the all-gate synchronization period signal XON_C, the on voltage regulator end point setting transistor Tf5[n] conducts the lowest negative voltage value (VSSQ = L-) of the intermediate end point ground voltage VSSQ to the voltage regulator setting end point NDints[n]; and, the on voltage regulator end point setting transistor Tf6[n] conducts the lowest negative voltage value (VSSQ = L-) of the intermediate end point ground voltage VSSQ to the voltage regulator end point NDstb[n]. Among them, the voltage of the voltage regulator setting end point NDints[n] is simultaneously affected by the voltage regulator end point setting transistor Tf1[n] also connected to the voltage regulator setting end point NDints[n] and is between the lowest negative voltage value -L and the positive voltage value H (-L < NDints[n] < H); the voltage regulator end point NDstb[n] is directly set to the lowest negative voltage value L- (NDstb[n] = VSSQ = L-) by the on voltage regulator end point setting transistor Tf6[n].

[0289] On the other hand, when the voltage regulator terminal setting transistors Tf5[n] and Tf6[n] remain disconnected during the nth single-stage scan due to the lowest negative voltage value L- (XON_C = L-) of the signal XON_C during the full-gate synchronization period, the disconnected voltage regulator terminal setting transistor Tf5[n] will not affect the voltage of the voltage regulator setting terminal NDints[n]; and the disconnected voltage regulator terminal setting transistor Tf6[n] will not affect the voltage of the voltage regulator terminal NDstb[n].

[0290] As mentioned above, in this paper, [n] represents the signal that changes with n = 1 to N. According to the concept disclosed herein, the sequential selection of signals HC[1] to HC[K] is the input signal of pulses generated sequentially by the timing controller after dividing the N-stage gate drive circuit gtCKT[1] to gtCKT[N] into K groups according to the different groups k = 1 to K.

[0291] For example, when the timing controller STG-s2[n-1] sets the column-by-column selection signal HC[k-1] corresponding to the (n-1)th stage gate drive circuit gtCKT[n-1] to a positive voltage value H (HC[k-1]=H), the column-by-column selection signal HC[k] corresponding to the nth stage gate drive circuit gtCKT[n] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th stage gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L- (HC[k]=HC[k+1]=L-). When the timing controller STG-s2[n] sets the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] to a positive voltage value H (HC[k]=H) during the scanning phase, the column-by-column selection signal HC[k-1] corresponding to the (n-1)th-level gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th-level gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L- (HC[k-1]=HC[k+1]=L-). When the timing controller STG-s2[n+1] sets the column-by-column selection signal HC[k+1] corresponding to the (n+1)th stage gate drive circuit gtCKT[n+1] to a positive voltage value H (HC[k+1]=H), the column-by-column selection signal HC[k-1] corresponding to the (n-1)th stage gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k] corresponding to the (n)th stage gate drive circuit gtCKT[n] are set to the lowest negative voltage value L- (HC[k-1]=HC[k]=L-).

[0292] like Figure 7As shown, the column-by-column selection signal HC[k] corresponding to the nth-stage gate drive circuit gtCKT[n] is set to a positive voltage value H by the timing controller during the scanning phase STG-s2[n] of DURscan[n] in the nth-stage single-stage scan. Furthermore, in conjunction with... Figure 9B It can be seen that when the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] is set to a positive voltage value H in the scanning phase of STG-s2[n], the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are turned on by the voltage (NDmd[n] = H + ΔVc[n]) of the intermediate terminal NDmd[n], thereby conducting the positive voltage value H of the column-by-column selection signal HC[n] (HC[n] = H) to the nth-level pixel gate signal line G[n] and the nth-level column scan state signal line ST[n]. That is, G[n] = ST[n] = H.

[0293] Since the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] is generated at different times depending on the level n = 1 to N, the timing controller can enable the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] in the nth-level gate drive circuit gtCKT[n] during the scanning phase STG-s2[n] corresponding to the nth-level gate drive circuit gtCKT[n], thereby generating the pulse of the nth-level pixel gate signal G[n] and the pulse of the nth-level column scan state signal ST[n] that correspond only to the nth level.

[0294] Also note that the scan stage STG-s2[n] corresponding to the nth gate drive circuit gtCKT[n] is equivalent to the scan stage STG-s3[n-1] corresponding to the (n-1)th gate drive circuit gtCKT[n-1]; and the scan stage STG-s1[n+1] corresponding to the (n+1)th gate drive circuit gtCKT[n+1]. Therefore, the (n-1) level pixel gate signal G[n-1] and the (n-1) level column scan state signal ST[n-1] corresponding to the (n-1) level gate drive circuit gtCKT[n-1], and the (n+1) level column scan state signal ST[n+1] corresponding to the (n+1) level pixel gate signal G[n+1], will not be set to a positive voltage value H during the same time period because the column-by-column selection signal HC[k-1] corresponding to the (n-1) level gate drive circuit gtCKT[n-1] is the lowest negative voltage value L- (HC[k-1]=L-) and the column-by-column selection signal HC[k+1] corresponding to the (n+1) level gate drive circuit gtCKT[n+1] is the lowest negative voltage value L- (HC[k+1]=L-).

[0295] As previously stated, the DURall-scan during the round-robin scan period comprises N single-stage scan periods DURscan[1] to DURscan[N]. In the first embodiment of the present invention, each gate drive circuit gtCKT[1] to gtCKT[N] corresponds to four scan stages. Therefore, in the first embodiment of the present invention, the DURall-scan during the round-robin scan period covers a total of (N+3) scan stages.

[0296] like Figure 9B As explained, the voltage value of the intermediate terminal NDmd[n] at STG-s2[n] during the scanning phase is equivalent to the sum of the voltage value of the intermediate terminal NDmd[n] at STG-s1[n] during the scanning phase and the capacitor voltage difference ΔVc[n]. That is, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]. Therefore, it can be seen that the intermediate terminal NDmd[n] is not actually turned on to a stable voltage value at STG-s2[n] during the scanning phase. Thus, the intermediate terminal NDmd[n] at STG-s2[n] can be considered to be floating during the scanning phase. To avoid leakage current in the intermediate terminal pull-down transistor Tnmd_nxt[n] and Zener transistor Tnmstb[n] due to the floating of the intermediate terminal NDmd[n], and even to prevent the gate signal setting transistor Tgs1[n] from being incompletely turned on, this disclosure can further modify the design of the gate drive circuit gtCKT[n].

[0297] To reduce leakage current, further improvements can be made. Figure 5 The gate drive circuit gtCKT[n]. Please refer to [link / reference]. Figure 10 This is a schematic diagram of a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, combined with a method to reduce leakage current. Figure 10 The diagram illustrates two methods for reducing leakage current (Method A and Method B). Please also refer to... Figure 6 , 10 .

[0298] The first method to reduce leakage current (Method A) is shown in line segment lkgCNT_1a. In Figure 5 In the middle, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal ground voltage signal line VSSQ. However, Figure 10 In the middle, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is changed to be electrically connected to the pixel gate ground voltage signal line VSSG.

[0299] If the first embodiment is not adopted Figure 10 In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th column scan state signal line ST[n-1] and the intermediate terminal ground voltage signal line VSSQ, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal has the lowest negative voltage value L- (ST[n-1] = L-), and its source terminal has the lowest negative voltage value L- (VSSQ = L-). At this time, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] is close to 0V, making it easier to generate leakage current.

[0300] On the other hand, if the first embodiment adopts Figure 10 In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th column scan state signal line ST[n-1] and the pixel gate ground voltage signal line VSSG, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal has the lowest negative voltage value L- (ST[n-1]=L-), and its source terminal has the second lowest negative voltage value L (VSSG=L). Since the pixel gate ground voltage VSSG is slightly higher than the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] exhibits a negative bias at this time. Therefore, by using this wiring method, the chance of leakage current being generated in the intermediate terminal pull-down transistor Tnmd_nxt[n] can be reduced.

[0301] The second method to reduce leakage current (Method B) is shown in line segment lkgCNT_1b. Figure 6 In the original Zener transistor Tnmstb[n], the source was electrically connected to the ground voltage signal line VSSQ at the intermediate terminal. However, Figure 10 In this process, the source of the Zener transistor Tnmstb[n] is changed to be electrically connected to the nth column scan state signal line ST[n].

[0302] Please also see Figure 7 , 9B 10. When the nth gate drive circuit gtCKT[n] is in the scanning stage STG-s2[n], the Zener transistor Tnmstb[n] is in the off state.

[0303] When the nth stage gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], if according to Figure 9B In this connection method, the control terminal of the Zener transistor Tnmstb[n] is the lowest negative voltage value L- (NDstb[n] = VSSQ = L-) from the Zener terminal NDstb[n], and its source terminal is the lowest negative voltage value L- (VSSQ = L-) from the intermediate terminal ground voltage VSSQ. Therefore, if the following connection method is adopted... Figure 9B With the connection method, when the Zener transistor Tnmstb[n] is in the scanning stage STG-s2[n] of the nth stage gate drive circuit gtCKT[n], leakage current is easily generated because the gate-source voltage difference (ΔVgs) is close to 0V.

[0304] On the other hand, when the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], if the nth-stage gate drive circuit gtCKT[n] according to Figure 10 In this connection method, the voltage at the control terminal of the Zener transistor Tnmstb[n] is equal to the lowest negative voltage value L- (ST[n-1]=L-) from the Zener terminal NDstb[n], and the voltage at its source terminal is equal to the positive voltage value H (ST[n]=HC[k]=H) from the nth column scan state signal ST[n]. Therefore, using... Figure 10 When the connection method is used, the Zener transistor Tnmstb[n] is in the scanning stage STG-s2[n] when the nth-stage gate drive circuit gtCKT[n] is in the scanning phase. Because the positive voltage value of the nth-stage column scan state signal ST[n] (ST[n]=HC[k]=H) is higher than the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the Zener transistor Tnmstb[n] exhibits a negative bias (ΔVgs<0). Therefore, when using the connection method of method B, the leakage current generated in the Zener transistor Tnmstb[n] can be reduced.

[0305] In practical applications, the gate drive circuit gtCKT[n] can reduce leakage current by using only method A (segment lkgCNT_1a), only method B (segment lkgCNT_1b), or both methods A and B (segments lkgCNT_1a and lkgCNT_1b). Regardless of whether one or both methods A and B are used, the existing methods can be directly applied. Figures 6-9D The diagram illustrates the generation of the nth-level pixel gate signal G[n] and the nth-level column scan state signal ST[n].

[0306] To extend circuit lifespan (reduce thin-film transistor stress), the gate drive circuit gtCKT[n] can employ two sets of voltage regulator circuits. Please refer to [link to relevant documentation]. Figure 11 This is a first embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, with two sets of voltage regulator circuit diagrams. The gate drive circuit gtCKT[n] includes: a capacitor C[n], an intermediate terminal pull-up circuit nmuCKT[n], a status signal setting circuit ssCKT[n], a gate signal setting circuit gsCKT[n], voltage regulator modules stbMDL-a[n], stbMDL-b[n], and an intermediate terminal pull-down circuit nmdCKT[n].

[0307] exist Figure 11 In the above, the voltage regulator module stbMDL-a[n] includes: a voltage regulator endpoint setting circuit stbsCKT-a[n] and a voltage regulator circuit stbCKT-a[n]. The voltage regulator module stbMDL-b[n] includes: a voltage regulator endpoint setting circuit stbsCKT-b[n] and a voltage regulator circuit stbCKT-b[n]. Comparison Figure 6 , 11 It can be seen that, Figure 11 The internal components and connection methods of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are the same as those of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n]. Figure 6 The voltage regulator module stbMDL[n] is similar. The internal components and connection methods of voltage regulator modules stbMDL-a[n] and stbMDL-b[n] will not be described in detail here.

[0308] Table 8 compares the internal components of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n].

[0309] Table 8

[0310]

[0311] Setting multiple sets of voltage regulator modules stbMDL-a[n] and stbMDL-b[n] in the gate drive circuit gtCKT[n] can extend the life of the transistor. The timing controller can control the gate drive circuit gtCKT[n] to alternately use voltage regulator modules stbMDL-a[n] and stbMDL-b[n] during different frame periods Tframe.

[0312] When the timing controller sets the voltage supply voltage LC-a at the regulated endpoint to a positive voltage value H (LC-a = H) and sets the voltage supply voltage LC-b at a low negative voltage value L (LC-b = L), the nth stage gate drive circuit gtCKT[n] uses the voltage regulator module stbMDL-a[n] and disables the voltage regulator module stbMDL-b[n]. When the timing controller sets the voltage supply voltage LC-a at the regulated endpoint to a low negative voltage value L (LC-a = L) and sets the voltage supply voltage LC-b at the regulated endpoint to a positive voltage value H (LC-b = H), the nth stage gate drive circuit gtCKT[n] disables the voltage regulator module stbMDL-a[n] and uses the voltage regulator module stbMDL-b[n].

[0313] Similarly, Figure 11 The nth-stage gate drive circuit gtCKT[n] can also be paired with Figure 10 Any one or two of the wiring methods described above can reduce leakage current. Such variations in application are not detailed here.

[0314] Next Figures 12-19 This disclosure describes a second embodiment of how the nth-stage gate drive circuit gtCKT[n] is designed. Figure 12 Explain the signals associated with the nth-stage gate drive circuit gtCKT[n]; Figure 13 Explain the internal circuitry of the n-stage gate drive circuit gtCKT[n]; Figure 14 Explain the circuit elements and connections of the nth-stage gate drive circuit gtCKT[n]; Figure 15 The waveform diagram illustrates how the signals associated with the nth stage gate drive circuit gtCKT[n] change in response to DURall-sync during full gate synchronization and DURscan[n] during the nth stage single-stage scan. Figures 16A-16C illustrate Figure 14 The nth gate drive circuit gtCKT[n] is in the states of STG-a1, STG-a2, and STG-a3 during the full gate synchronization period of DURall-sync; Figures 17A-17C illustrate Figure 1 The nth gate drive circuit gtCKT[n] is in different scan stages of DURall-sync during full gate synchronization, namely STG-s1[n], STG-s2[n], and STG-s3[n]. Figure 18 Explain how to Figure 14 The nth-stage gate drive circuit gtCKT[n] improves leakage current. Figure 19 This section explains how, for the purpose of extending transistor lifespan, two sets of voltage regulator circuits are set in the nth stage gate drive circuit gtCKT[n] of the second embodiment.

[0315] Please see Figure 12 This is a schematic diagram of various signals related to a second embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. Please also refer to... Figure 4 , 12 .because Figure 12 The drawing method and Figure 4 They are similar, so they will not be explained one by one here. Figure 12 Signal types and applications. (and) Figure 4 In comparison, Figure 12 The input signal is relatively small. More specifically, Figure 4 , 12 The difference is that the second embodiment does not set the full gate synchronization enable signal XON_C and the pixel gate ground voltage VSSG.

[0316] Please see Figure 13 This is a block diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] of the disclosed concept. Figure 13 It can be seen that the nth stage gate drive circuit gtCKT[n] includes: output signal setting module outSetMDL[n], intermediate endpoint setting module nmSetMDL[n], and voltage regulation module stbMDL[n].

[0317] The output signal setting module outSetMDL[n] further includes: a status signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The intermediate endpoint setting module nmSetMDL[n] further includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n], and an intermediate endpoint pull-down circuit nmdCKT[n]. The voltage regulator module stbMDL[n] further includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] that are electrically connected to each other.

[0318] The circuits in the output signal setting module outSetMDL[n] are all related to the voltage of the output signal (the nth level pixel gate signal G[n] and / or the nth level column scan state signal ST[n]). The circuits in the intermediate endpoint setting module nmSetMDL[n] are all related to the voltage of the intermediate endpoint NDmd[n]. The circuits in the voltage regulator module stbMDL[n] are all related to the voltage of the voltage regulator endpoint NDstb[n]. Figure 13 The composition and connection method of the components and Figure 5 They are largely similar, so this section will only explain the differences between the two.

[0319] Please also see Figure 5 , 13 In short, Figure 13 The second embodiment shown does not provide the signal XON_C and the pixel gate ground voltage VSSG during full gate synchronization. Therefore, Figure 13 Connection method and Figure 5 Slightly different. Figure 5 In the circuit, the nth pixel gate signal line G[n] is electrically connected to the voltage regulator circuit stbCKT[n]; however, Figure 13 In this context, the nth pixel gate signal line G[n] is not electrically connected to the voltage regulator circuit stbCKT[n]. Furthermore, in... Figure 5 In the circuit, the gate signal setting circuit gsCKT[n] is not electrically connected to the voltage regulator terminal NDstb[n]; however, Figure 13 In the circuit, the gate signal setting circuit gsCKT[n] is electrically connected to the voltage regulator terminal NDstb[n].

[0320] Please see Figure 14 This is a circuit diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. Please also refer to... Figure 13 , 14 For ease of explanation, in the following circuit diagram, we will assume that p = 1 and q = 1.

[0321] Based on this assumption, the nth-level gate drive circuit gtCKT[n] receives the column scan status signal ST[np] = ST[n-1] from the (np) = (n-1)th-level gate drive circuit gtCKT[np] = gtCKT[n-1]; and receives the column scan status signal ST[n+q] = ST[n+1] from the (n+q) = (n+1)th-level gate drive circuit gtCKT[n+q] = gtCKT[n+1]. Furthermore, the nth-level gate drive circuit gtCKT[n] transmits the nth-level column scan status signal ST[n] to the (nq) = (n-1)th-level gate drive circuit gtCKT[nq] = gtCKT[n-1]; and transmits the nth-level column scan status signal ST[n] to the (n+p) = (n+1)th-level gate drive circuit gtCKT[n+p] = gtCKT[n+p].

[0322] The following section will first explain the composition of the circuit elements in the intermediate endpoint setting module nmSetMDL[n], the output signal setting module outSetMDL[n], and the voltage regulation module stbMDL[n]. Next, the circuit elements related to each signal will be explained according to the different signal types.

[0323] The intermediate endpoint setting module nmSetMDL[n] includes: capacitor C[n], intermediate endpoint pull-up circuit nmuCKT[n], and intermediate endpoint pull-down circuit nmdCKT[n]. The intermediate endpoint pull-up circuit nmuCKT[n] includes: intermediate endpoint pull-up transistor Tnmu[n]; and the intermediate endpoint pull-down circuit nmdCKT[n] includes: intermediate endpoint pull-down transistors Tnmd_nxt[n], Tnmd_xon[n], and intermediate endpoint reset transistor Tnmd_rst[n]. The following describes the connection method of the transistors in the intermediate endpoint pull-up circuit nmuCKT[n] and the intermediate endpoint pull-down circuit nmdCKT[n].

[0324] In the intermediate terminal pull-up circuit nmuCKT[n], the drain terminal of the intermediate terminal pull-up transistor Tnmu[n] receives the gate supply voltage VGHD, the control terminal receives the (n-1)th stage column scan state signal ST[n-1], and the source terminal is electrically connected to the intermediate terminal NDmd[n]. Therefore, the on / off state of the intermediate terminal pull-up transistor Tnmu[n] depends on the voltage of the (n-1)th stage column scan state signal ST[n-1]. When the intermediate terminal pull-up transistor Tnmu[n] is on, it conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n] = VGHD = H.

[0325] The intermediate endpoint pull-down circuit nmdCKT[n] includes: an intermediate endpoint pull-down transistor Tnmd_nxt[n] and an intermediate endpoint reset transistor Tnmd_rst[n]. The drain of the intermediate endpoint pull-down transistor Tnmd_nxt[n] is connected to the intermediate endpoint NDmd[n], its control terminal receives the (n+1)th column scan status signal ST[n+1], and its source terminal is connected to the intermediate endpoint ground voltage signal line VSSQ. The drain of the intermediate endpoint reset transistor Tnmd_rst[n] is connected to the intermediate endpoint NDmd[n], its control terminal receives the intermediate endpoint reset signal rstST, and its source terminal is connected to the intermediate endpoint ground voltage signal line VSSQ.

[0326] Accordingly, the on / off state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th stage column scan state signal ST[n+1]. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0327] Furthermore, the on / off state of the intermediate endpoint reset transistor Tnmd_rst[n] depends on the intermediate endpoint reset signal rstST. When the intermediate endpoint reset signal rstST is set to a positive voltage value H by the timing controller (rstST = H), causing the intermediate endpoint reset transistor Tnmd_rst[n] to turn on, the intermediate endpoint reset transistor Tnmd_rst[n] conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ to the intermediate endpoint NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0328] Please also note that because the intermediate endpoint reset signal rstST issued by the timing controller has the lowest negative voltage value L- (rstST = L-) during both full-gate synchronization (DURall-sync) and polling (DURall-scan), the intermediate endpoint reset transistor Tnmd_rst[n] remains off during both full-gate synchronization (DURall-sync) and polling (DURall-scan). Therefore, the intermediate endpoint reset transistor Tnmd_rst[n] will not be drawn again when explaining the circuit behavior later.

[0329] The output signal setting module outSetMDL[n] includes: a status signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The status signal setting circuit ssCKT[n] includes: a status signal setting transistor Tss[n]; and the gate signal setting circuit gsCKT[n] includes: gate signal setting transistors Tgs1[n] and Tgs2[n].

[0330] In the state signal setting circuit ssCKT[n], the drain terminal of the state signal setting transistor Tss[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the nth column scan state signal line ST[n]. Therefore, the on / off state of the state signal setting transistor Tss[n] depends on the voltage of the intermediate terminal NDmd[n]. When the state signal setting transistor Tss[n] is on, it conducts the voltage of the column-by-column selection signal HC[k] to the nth column scan state signal ST[n]. That is, ST[n] = HC[k].

[0331] In the gate signal setting circuit gsCKT[n], the drain terminal of the gate signal setting transistor Tgs1[n] receives the column-by-column selection signal HC[k], its control terminal is electrically connected to the intermediate terminal NDmd[n], and its source terminal is electrically connected to the nth pixel gate signal line G[n]. The drain terminal of the gate signal setting transistor Tgs2[n] receives the full-gate synchronization enable signal XON_S, its control terminal is electrically connected to the regulated terminal NDstb[n], and its source terminal is electrically connected to the nth pixel gate signal line G[n]. Accordingly, the on / off state of the gate signal setting transistor Tgs1[n] depends on the voltage of the intermediate terminal NDmd[n].

[0332] When the gate signal setting transistor Tgs1[n] is turned on, the voltage of the column-by-column selection signal HC[k] is conducted to the nth pixel gate signal line G[n]. That is, G[n] = HC[k]. On the other hand, the on / off state of the gate signal setting transistor Tgs2[n] depends on the voltage of the regulated terminal NDstb[n]. When the gate signal setting transistor Tgs2[n] is turned on, the voltage of the full-gate synchronization enable signal XON_S is conducted to the nth pixel gate signal line G[n]. That is, G[n] = XON_S.

[0333] The voltage regulator module stbMDL[n] includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] that are electrically connected to each other. The voltage regulator endpoint setting circuit stbsCKT[n] includes: voltage regulator endpoint setting transistors Tf1[n], Tf2[n], Tf3[n], and Tf4[n]; the voltage regulator circuit stbCKT[n] includes: voltage regulator transistors Tnmstb[n] and Tsstb[n].

[0334] In the voltage regulator setting circuit stbsCKT[n], the drain and gate terminals of the voltage regulator setting transistor Tf1[n] both receive the voltage regulator supply voltage LC, and the source terminal is electrically connected to the voltage regulator setting terminal NDints[n]. Therefore, the on / off state of the voltage regulator setting transistor Tf1[n] depends on the voltage regulator supply voltage LC. In this paper, it is assumed that the voltage regulator supply voltage LC is continuously positive (LC = H). Therefore, the voltage regulator setting transistor Tf1[n] remains in the on state and conducts the positive voltage value H (LC = H) of the voltage regulator supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = LC = H.

[0335] The drain of the voltage regulator setting transistor Tf2[n] is connected to the voltage regulator setting terminal NDints[n], the control terminal is connected to the intermediate terminal NDmd[n], and the source is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf2[n] depends on the voltage of the intermediate terminal NDmd[n]. When the voltage regulator setting transistor Tf2[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = VSSQ = L-.

[0336] The drain of the voltage regulator setting transistor Tf3[n] receives the voltage regulator supply voltage LC, its control terminal is electrically connected to the voltage regulator setting terminal NDints[n], and its source is electrically connected to the voltage regulator terminal NDstb[n]. Therefore, the on / off state of the voltage regulator setting transistor Tf3[n] depends on the voltage of the voltage regulator setting terminal NDints[n]. When the voltage regulator setting transistor Tf3[n] is on, it conducts the positive voltage value of the voltage regulator supply voltage LC (LC = H) to the voltage regulator terminal NDstb[n]. That is, NDstb[n] = LC = H.

[0337] The drain terminal of the voltage regulator setting transistor Tf4[n] is connected to the voltage regulator terminal NDstb[n], the control terminal is connected to the intermediate terminal NDmd[n], and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. Therefore, the on / off state of the voltage regulator setting transistor Tf4[n] depends on the voltage of the intermediate terminal NDmd[n]. When the voltage regulator setting transistor Tf4[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-.

[0338] In the voltage regulator circuit stbCKT[n], the drain terminal of the Zener transistor Tnmstb[n] is connected to the intermediate terminal NDmd[n], the control terminal is connected to the regulated terminal NDstb[n], and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. The drain terminal of the Zener transistor Tsstb[n] is connected to the nth column scan state signal line ST[n], the control terminal is connected to the regulated terminal NDstb[n], and the source terminal is connected to the intermediate terminal ground voltage signal line VSSQ. Accordingly, the on / off state of Zener transistors Tnmstb[n] and Tsstb[n] depends on the voltage of the regulated terminal NDstb[n]. When Zener transistor Tnmstb[n] is on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-. When the Zener transistor Tsstb[n] is turned on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth column scan state signal ST[n]. That is, ST[n] = VSSQ = L-.

[0339] The above describes the circuit elements and connections within the nth-stage gate drive circuit gtCKT[n]. Next, based on the signal types associated with the nth-stage gate drive circuit gtCKT[n], the circuit elements related to each signal will be explained. The internal signals of the nth-stage gate drive circuit gtCKT[n] include signals at the intermediate terminal NDmd[n], the voltage setting terminal NDints[n], and the voltage regulating terminal NDstb[n]. The transistors associated with these internal signals will then be explained sequentially.

[0340] Depend on Figure 14 It can be seen that, depending on the connection method, transistors electrically connected to internal terminals can be divided into two categories: the first category is transistors electrically connected to internal terminals through control terminals (i.e., transistors controlled by internal terminals); and the second category is transistors electrically connected to internal terminals through drain or source terminals. Table 9 summarizes the transistors connected to each internal terminal (i.e., transistors that change the voltage of the internal terminals).

[0341] Table 9

[0342]

[0343] Next, the circuit elements related to the input signals of the nth-stage gate drive circuit gtCKT[n] will be explained. As mentioned earlier, the input signals of the nth-stage gate drive circuit gtCKT[n] include: the (n+1)th-stage column scan state signal ST[n+1], the (n-1)th-stage column scan state signal ST[n-1], the column-by-column select signal HC[k], the all-gate synchronization enable signal XON_S, the intermediate endpoint reset signal rstST, the regulated endpoint supply voltage LC, the intermediate endpoint ground voltage VSSQ, and the gate supply voltage VGHD.

[0344] Depend on Figure 14 It can be seen that the (n-1)th level column scan state signal line ST[n-1] is electrically connected to the control terminal of the intermediate terminal pull-up transistor Tnmu[n]. Therefore, the conduction state of the intermediate terminal pull-up transistor Tnmu[n] depends on the (n-1)th level column scan state signal ST[n-1]. Furthermore, the (n+1)th level column scan state signal line ST[n+1] is electrically connected to the control terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n]. Therefore, the conduction state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th level column scan state signal ST[n+1].

[0345] Depend on Figure 14 It can be seen that the column-by-column selection signal line HC[k] is electrically connected to the drain terminal of the status signal setting transistor Tss[n] and the drain terminal of the gate signal setting transistor Tgs1[n]. Therefore, when the status signal setting transistor Tss[n] is turned on, it conducts the column-by-column selection signal HC[k] to the nth-level column scan status signal line ST[n], making the voltage of the nth-level column scan status signal line ST[n] equal to the voltage of the column-by-column selection signal HC[k]. Furthermore, when the gate signal setting transistor Tgs1[n] is turned on, it conducts the column-by-column selection signal HC[k] to the nth-level pixel gate signal line G[n], making the voltage of the nth-level pixel gate signal line G[n] equal to the voltage of the column-by-column selection signal HC[k]. That is, G[n] = HC[k].

[0346] Depend on Figure 14 It can be seen that the full-gate synchronization enable signal line XON_S is electrically connected to the drain terminal of the gate signal setting transistor Tgs2[n]. Therefore, when the gate signal setting transistor Tgs2[n] is turned on, it will conduct the full-gate synchronization enable signal XON_S to the nth pixel gate signal line G[n]. That is, G[n] = XON_S.

[0347] Depend on Figure 14It can be seen that the intermediate endpoint reset signal rstST is electrically connected to the control terminal of the intermediate endpoint reset transistor Tnmd_rst[n]. Therefore, the conduction state of the intermediate endpoint reset transistor Tnmd_rst[n] depends on the voltage of the intermediate endpoint reset signal rstST. When the intermediate endpoint reset signal rstST is set to a positive voltage value H (rstST = H) by the timing controller, causing the intermediate endpoint reset transistor Tnmd_rst[n] to conduct, the intermediate endpoint reset transistor Tnmd_rst[n] conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ to the intermediate endpoint NDmd[n]. That is, NDmd[n] = VSSQ = L-.

[0348] Depend on Figure 14 It can be seen that the voltage supply LC of the regulated endpoint is electrically connected to the drain and control terminal of the regulated endpoint setting transistor Tf1[n], and electrically connected to the drain of the regulated endpoint setting transistor Tf3[n]. Because the voltage supply LC of the regulated endpoint is maintained at a positive voltage value H (LC = H), the regulated endpoint setting transistor Tf1[n] remains on. Furthermore, when the regulated endpoint setting transistor Tf3[n] is on, it conducts the positive voltage value H (LC = H) of the voltage supply LC of the regulated endpoint to the regulated endpoint NDstb[n]. That is, NDstb[n] = LC = H.

[0349] Depend on Figure 14 It can be seen that the intermediate endpoint ground voltage VSSQ is electrically connected to the source of the voltage regulator setting transistors Tf2[n], Tf4[n], voltage regulator transistors Tnmstb[n], Tsstb[n], intermediate endpoint pull-down transistor Tnmd_nxt[n], and intermediate endpoint reset transistor Tnmd_rst[n]. Therefore, when the voltage regulator setting transistor Tf2[n] is turned on, the voltage regulator setting endpoint NDints[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ. That is, NDints[n] = VSSQ = L-. When the voltage regulator setting transistor Tf4[n] is turned on, the voltage regulator endpoint NDstb[n] is set to the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ. That is, NDstb[n] = VSSQ = L-.

[0350] When any one of the Zener transistor Tnmstb[n], the intermediate terminal pull-down transistor Tnmd_nxt[n], and the intermediate terminal reset transistor Tnmd_rst[n] is turned on, the intermediate terminal NDmd[d] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ. That is, NDmd[d] = VSSQ = L-.

[0351] When the Zener transistor Tsstb[n] is turned on, it conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth column scan state signal ST[n]. That is, ST[n] = VSSQ = L-.

[0352] Depend on Figure 14 It can be seen that the gate supply voltage VGHD is electrically connected to the drain of the intermediate terminal pull-up transistor Tnmu[n]. Therefore, when the intermediate terminal pull-up transistor Tnmu[n] is turned on, it conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n] = VGHD = H.

[0353] Next, the circuit components related to the output signal of the nth-stage gate drive circuit gtCKT[n] will be described. The output signals of the nth-stage gate drive circuit gtCKT[n] are: the nth-stage column scan state signal ST[n] and the nth-stage pixel gate signal G[n]. Table 10 summarizes the circuit components related to the output signal of the nth-stage gate drive circuit gtCKT[n].

[0354] Table 10

[0355]

[0356]

[0357] Please see Figure 15 It is a waveform diagram of a signal associated with the nth-level pixel gate signal G[n] in a second embodiment of the nth-level gate drive circuit gtCKT[n] according to the present disclosure.

[0358] Figure 15 The horizontal axis represents time, and the vertical axis represents the signal associated with the gate signal G[n] of the nth pixel. Figure 15 In the diagram, FM3, indicated by the dashed box, represents the change of the signal related to the nth pixel gate signal G[n] during full gate synchronization (between time points t1 and t4); FM4, indicated by the dashed box, represents the change of the signal related to the nth pixel gate signal G[n] during the nth single-level scan (between time points t5 and t8).

[0359] During full gate synchronization, DURall-sync further includes three synchronization phases STG-a1, STG-a2, and STG-a3. Synchronization phase STG-a1 is between time points t1 and t2, synchronization phase STG-a2 is between time points t2 and t3, and synchronization phase STG-a3 is between time points t3 and t4. For the N-level gate drive circuits gtCKT[1] to gtCKT[N], the circuit behavior of STG-a1, STG-a2, and STG-a3 is consistent (G[1] = ... = G[N]). According to the concept disclosed herein, the N-level pixel gate signals G[1] to G[N] are simultaneously set to a positive voltage value H during synchronization phase STG-a2 (G[1] = ... = G[N] = H); and during synchronization phases STG-a1 and STG-a3, they are simultaneously set to a second-lowest negative voltage value L (G[1] = ... = G[N] = L). Accordingly, in the N columns of pixel transistors PXL(1~M,1)~PXL(1~M,N) of the pixel array, the N-level pixel gate signals G[1]~G[N] will be received synchronously and turned on simultaneously. Therefore, the synchronization phase STG-a2 can also be called the full gate conduction period.

[0360] According to the concept disclosed herein, the duration of DURall-scan during the sequential scanning period covers a total of N single-stage scanning periods DURscan[1] to DURscan[N]. Among them, the nth single-stage scanning period DURscan[n] corresponding to the nth stage gate drive circuit gtCKT[n] includes three scanning stages: scanning stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n]. Scanning stage STG-s1[n] is between time points t5 and t6, scanning stage STG-s2[n] is between time points t6 and t7, and scanning stage STG-s3[n] is between time points t7 and t8.

[0361] Table 11 summarizes the following: Figure 15 In the diagram, the voltage changes of each signal associated with the nth-stage gate drive circuit gtCKT[n] at different stages.

[0362]

[0363]

[0364] Depend on Figure 15As can be seen from Table 11, the nth pixel gate signal G[n] is set to a positive voltage value H (G[n] = H) during the synchronization phase STG-a2 and the scanning phase STG-s2[n]. During the other synchronization phases STG-a1, STG-a3 and the scanning phases STG-s1[n], STG-s3[n], STG-s4[n], it is set to the second lowest negative voltage value L or the lowest negative voltage value L- (G[n] = L or G[n] = L-). Therefore, it can be seen that the gate driving circuit gtCKT[n] generates synchronous pulses synchronously with the other gate driving circuits gtCKT[1]~gtCKT[n-1] and gtCKT[n+1]~gtCKT[N] during the synchronization phase STG-a2. Moreover, among the N-level gate driving circuits gtCKT[1]~gtCKT[N], only the gate driving circuit gtCKT[n] controls the n-level pixel gate signal G[n] to generate scanning pulses during the scanning phase STG-s2[n] of DURscan[n] during the n-level single-level scan.

[0365] In the second embodiment disclosed herein, the nth stage single-stage scan period DURscan[n] corresponding to the nth stage gate drive circuit gtCKT[n] partially overlaps with the single-stage scan periods DURscan[n-2], DURscan[n-1], DURscan[n+1], and DURscan[n+2] of the preceding and following two stages. Therefore, the duration of the successive scan period DURall-scan is equivalent to the duration of (N+4) scan stages. The following describes the periods that overlap with the scan stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n] in the nth stage single-stage scan period DURscan[n], and the scan stages contained in each of the other stages of the single-stage scan period.

[0366] The scanning phase STG-s1[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s3[n-2] of DURscan[n-2] during the (n-2)th single-stage scan period corresponding to the (n-2)th gate drive circuit gtCKT[n-2]; and the scanning phase STG-s2[n-1] of DURscan[n-1] during the (n-1)th single-stage scan period corresponding to the (n-1)th gate drive circuit gtCKT[n-1].

[0367] The scanning phase STG-s2[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s3[n-1] of DURscan[n-1] during the (n-1)th single-stage scan period corresponding to the (n-1)th gate drive circuit gtCKT[n-1]; and the scanning phase STG-s1[n+1] of DURscan[n+1] during the (n+1)th single-stage scan period corresponding to the (n+1)th gate drive circuit gtCKT[n+1] overlaps with the scanning phase STG-s1[n+1].

[0368] The scanning phase STG-s3[n] of DURscan[n] during the nth single-stage scan period corresponding to the nth gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s2[n+1] of DURscan[n+1] during the (n+1)th single-stage scan period corresponding to the (n+1)th gate drive circuit gtCKT[n+1]; and the scanning phase STG-s1[n+2] of DURscan[n+2] during the (n+2)th single-stage scan period corresponding to the (n+2)th gate drive circuit gtCKT[n+2].

[0369] As mentioned earlier, the input signals received by the nth-stage gate drive circuit gtCKT[n] can be divided into two categories. One type of input signal has a constant voltage value, while the logic level of the other type of input signal varies depending on the stage of DURall-sync during full-gate synchronization and DURscan[n] during the nth-stage single-stage scan. The former includes: the regulated terminal supply voltage LC with a positive voltage value H, the intermediate terminal ground voltage VSSQ with a minimum negative voltage value L-, and the gate supply voltage VGHD with a positive voltage value H. The latter includes: the column scan status signal ST[n-1] of the (n-1)th stage, the column scan status signal ST[n+1] of the (n+1)th stage, the column-by-column select signal HC[k], and the full-gate synchronization enable signal XON_S. The logic level of the input signals changes with the different stages, which in turn causes the internal and output signals of the nth-stage gate drive circuit gtCKT[n] to change as well.

[0370] In these input signals that change logic levels, this disclosure assumes that the high logic levels of the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the column-by-column select signal HC[k] all correspond to positive voltage values ​​H, and the low logic levels all correspond to the lowest negative voltage value L-. Furthermore, it assumes that the high logic level of the all-gate synchronization enable signal XON_S corresponds to the positive voltage value H.

[0371] Please also note that the low logic level of the full-gate synchronization enable signal XON_S corresponds to a negative voltage value, and this negative voltage value can be determined according to the product requirements of the display panel. For simplicity, it is assumed here that in the second embodiment, the low logic level of the full-gate synchronization enable signal XON_S corresponds to the second lowest negative voltage value L. In practical applications, the negative voltage value corresponding to the low logic level of the full-gate synchronization enable signal XON_S can also be the lowest negative voltage value L- or other selected negative voltage values.

[0372] The following uses Figures 16A-16C and Figures 17A-17C Explain how the nth-stage gate drive circuit gtCKT[n] changes the conduction state of its internal transistors in response to changes in the column scan state signals ST[n-1] (n-1) and ST[n+1] (n+1) ...

[0373] Please see Figures 16A-16C This is a schematic diagram illustrating the states of each synchronization stage during full gate synchronization in a second embodiment of the nth-stage gate drive circuit gtCKT[n] according to the present disclosure. The following explanation does not specifically address input signals with constant voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, and the gate supply voltage VGHD; rather, it focuses on the effects of changes in the (n-1)th-stage column scan state signal ST[n-1], the (n+1)th-stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], and the full gate synchronization enable signal XON_S on the nth-stage gate drive circuit gtCKT[n].

[0374] Please also see Figure 14 , 15 16A. Figure 16A for, Figure 14The state of the nth-stage gate drive circuit gtCKT[n] during the synchronization phase STG-a1 of DURall-sync during full gate synchronization. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a1, the (n-1)th stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the (n+1)th stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, and the full gate synchronization enable signal XON_S = L.

[0375] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-a1 during the synchronization phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-a1 and the on / off state of the transistors during the synchronization phase.

[0376] Because the (n-1)th column scan state signal ST[n-1] has the lowest negative voltage value L- (ST[n-1]=L-) during the synchronization phase of STG-a1, the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0377] Because the (n+1)th column scan state signal ST[n+1] has the lowest negative voltage value L- (ST[n+1]=L-) during the synchronization phase of STG-a1, the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0378] Because the voltage supplied to the regulator terminal LC is a positive voltage value H (LC = H), the regulator terminal setting transistor Tf1[n] is turned on, and Tf1[n] conducts the positive voltage value H (LC = H) of the voltage supplied to the regulator terminal LC to the regulator setting terminal NDints[n]. That is, NDints[n] = LC = H. Because the voltage of the regulator setting terminal NDints[n] is a positive voltage value H (NDints[n] = H), the regulator terminal setting transistor Tf3[n] remains on, and thus conducts the positive voltage value H (LC = H) of the voltage supplied to the regulator terminal LC to the regulator terminal NDstb[n]. That is, NDstb[n] = LC = H.

[0379] Because the voltage at the regulated terminal NDstb[n] is a positive voltage value H (NDstb[n] = H), the gate signal setting transistor Tgs2[n], the Zener transistor Tnmstb[n], and the Zener transistor Tsstb[n], which are connected to the regulated terminal NDstb[n], are all in the on state.

[0380] The gate signal setting transistor Tgs2[n], which is in the ON state, conducts the second lowest negative voltage value L (XON_S = L) of the full gate synchronization enable signal XON_S to the nth level pixel gate signal line G[n]. That is, G[n] = XON_S = L. The Zener transistor Tnmstb[n], which is in the ON state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-. The Zener transistor Tsstb[n], which is in the ON state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth level column scan state signal ST[n]. That is, ST[n] = VSSQ = L-.

[0381] Continuing from the above, because the intermediate endpoint NDmd[n] is set to the lowest negative voltage value L- (NDmd[n] = VSSQ = L-) when the Zener transistor Tnmstb[n] is turned on, the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], and the Zener endpoint setting transistors Tf2[n] and Tf4[n], which are connected to the control terminal and the intermediate endpoint NDmd[n], are all turned off. Therefore, the column-by-column selection signal HC[k] = L- will not affect the voltage of the nth-level column scan state signal ST[n] through the state signal setting transistor Tss[n], nor will it affect the voltage of the nth-level pixel gate signal G[n] through the gate signal setting transistor Tgs1[n]. Furthermore, the off-state voltage regulator setting transistor Tf2[n] ensures that the voltage of the voltage regulator setting terminal NDints[n] is only affected by the voltage regulator setting transistor Tf1[n]; the off-state voltage regulator setting transistor Tf4[n] ensures that the voltage of the voltage regulator terminal NDstb[n] is only affected by the voltage regulator setting transistor Tf3[n].

[0382] Table 12A summarizes the following: Figure 16A In the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0383] Table 12A

[0384]

[0385]

[0386] Please also see Figure 14 , 15 16B. Figure 16B for, Figure 14The state of the nth-stage gate drive circuit gtCKT[n] during the synchronization phase STG-a2 of DURall-sync during full gate synchronization. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a2, the (n-1)th stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the (n+1)th stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the positive voltage value H by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, and XON_S = H.

[0387] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-a2 during the synchronization phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-a2 and the on / off state of the transistors during the synchronization phase.

[0388] Because the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0389] Because the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0390] Because the voltage supplied to the regulator terminal LC is a positive voltage value H (LC = H), the regulator terminal setting transistor Tf1[n] is turned on. Therefore, Tf1[n] conducts the positive voltage value H (LC = H) of the voltage supplied to the regulator terminal LC to the regulator setting terminal NDints[n]. That is, NDints[n] = LC = H. Because the voltage at the regulator setting terminal NDints[n] is a positive voltage value H (NDints[n] = H), the regulator terminal setting transistor Tf3[n] remains on and conducts the positive voltage value H (LC = H) of the voltage supplied to the regulator terminal LC to the regulator terminal NDstb[n]. That is, NDstb[n] = LC = H.

[0391] Because the voltage at the regulated terminal NDstb[n] is a positive voltage value H (NDstb[n] = H), the gate signal setting transistor Tgs2[n], the Zener transistor Tnmstb[n], and the transistor Tsstb[n], which are connected to the regulated terminal NDstb[n], are all in the ON state. The ON gate signal setting transistor Tgs2[n] conducts the full-gate synchronization enable signal XON_S to the nth pixel gate signal line G[n] (G[n] = XON_S). Furthermore, because the full-gate synchronization enable signal XON_S is a positive voltage H (XON_S = H) at STG-a2 during the synchronization phase, the nth pixel gate signal G[n] under STG-a2 during the synchronization phase is also a positive voltage H. That is, G[n] = XON_S = H.

[0392] The Zener transistor Tnmstb[n] in the ON state conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n] = VSSQ = L-. The Zener transistor Tsstb[n] in the ON state conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth column scan state signal ST[n]. That is, ST[n] = VSSQ = L-.

[0393] As mentioned above, because the intermediate endpoint NDmd[n] is set to the lowest negative voltage value L- (NDmd[n] = VSSQ = L-) when the Zener transistor Tnmstb[n] is turned on, the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], and the Zener endpoint setting transistors Tf2[n] and Tf4[n], which are connected to the control terminal and the intermediate endpoint NDmd[n], are all turned off. Therefore, the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] will not affect the voltage of the nth-level column scan state signal ST[n] through the state signal setting transistor Tss[n], nor will it affect the voltage of the nth-level pixel gate signal G[n] through the gate signal setting transistor Tgs1[n]. Furthermore, the off-state voltage regulator setting transistor Tf2[n] ensures that the voltage of the voltage regulator setting terminal NDints[n] is only affected by the voltage regulator setting transistor Tf1[n]; the off-state voltage regulator setting transistor Tf4[n] ensures that the voltage of the voltage regulator terminal NDstb[n] is only affected by the voltage regulator setting transistor Tf3[n].

[0394] Table 12B summarizes the following: Figure 16B In the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0395] Table 12B

[0396]

[0397]

[0398] Please also see Figure 14 , 15 16C. Figure 16C for, Figure 14The state of the nth-stage gate drive circuit gtCKT[n] during the full gate synchronization, specifically the synchronization phase STG-a3 of DURall-sync. When the nth-stage gate drive circuit gtCKT[n] is in the synchronization phase STG-a3, the (n-1)th stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th stage gate drive circuit gtCKT[n-1], the (n+1)th stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = L-, and XON_S = L.

[0399] Depend on Figure 15 The waveform diagram shows that the levels of each input signal are the same in STG-a1 and STG-a3 during the synchronization phase. Therefore, the nth stage gate drive circuit gtCKT[n] in Figure 16C The state, and the nth stage gate drive circuit gtCKT[n] in Figure 16A The states are the same. Further details will not be provided here. Figure 16C In the nth stage gate drive circuit gtCKT[n], the circuit elements and signal states are defined.

[0400] Table 12C summarizes the following: Figure 16C In the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0401] Table 12C

[0402]

[0403]

[0404] Please see Figures 17A-17CThis is a schematic diagram illustrating the state of DURscan[n] at different stages during the nth stage single-stage scan, according to a second embodiment of the nth-stage gate drive circuit gtCKT[n] based on the present disclosure. The following will not specifically describe input signals with constant voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, and the gate supply voltage VGHD; rather, it will only explain the effects of changes in the (n-1)th stage column scan state signal ST[n-1], the (n+1)th stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], and the all-gate synchronization enable signal XON_S on the nth-stage gate drive circuit gtCKT[n].

[0405] Please also see Figure 14 , 15 17A. Figure 17A for, Figure 14 The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s1[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s1[n], the (n-1)th-stage column scan state signal ST[n-1] is set to a positive voltage value H by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the all-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1] = H, ST[n+1] = L-, HC[k] = L-, and XON_S = L.

[0406] Next, the following will explain how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal STG-a1 during the synchronization phase. Furthermore, the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal STG-a1 and the on / off state of the transistors during the synchronization phase.

[0407] Because the (n-1)th column scan state signal ST[n-1] is a positive voltage value H (ST[n-1] = H), the intermediate terminal pull-up transistor Tnmu[n] is turned on. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the turned-on state, conducts the positive voltage value H (VGHD = H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n] = VGHD = H.

[0408] Because the voltage at the intermediate endpoint NDmd[n] is a positive voltage value H (NDmd[n] = H), the gate signal setting transistor Tgs1[n], the voltage regulator setting transistors Tf2[n], and Tf4[n] are all turned on. With the gate signal setting transistor Tgs1[n] turned on, it conducts the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] to the nth pixel gate signal line G[n]. That is, G[n] = HC[k] = L-. The voltage regulator setting transistor Tf2[n], which is in the turned-on state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ to the voltage regulator setting endpoint NDints[n]. That is, NDints[n] = VSSQ = L-. The Zener terminal setting transistor Tf4[n], which is in the on state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the Zener terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-.

[0409] Because the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L- (ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0410] exist Figure 17A In the circuit, the voltage regulator setting transistor Tf1[n] is in the on state because the control terminal continuously receives the positive voltage value H (LC = H) of the voltage regulator supply voltage LC. Therefore, the voltage regulator setting transistor Tf1[n] conducts the positive voltage value H (LC = H) of the supply voltage signal LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = LC = H.

[0411] Because the voltage regulator terminal setting transistors Tf2[n] and Tf1[n] are turned on with the intermediate terminal NDmd[n] (NDmd[n] = VGHD = H) and the voltage regulator terminal supply voltage LC (LC = H), respectively, the voltage regulator terminal setting transistor Tf2[n] conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the voltage regulator setting terminal NDints[n], and the voltage regulator terminal setting transistor Tf1[n] conducts the positive voltage value H (LC = H) of the voltage regulator terminal supply voltage LC to the voltage regulator setting terminal NDints[n]. Accordingly, the voltage divider effect of the voltage regulator setting transistors Tf1[n] and Tf2[n] connected between the voltage regulator supply signal line LC and the intermediate terminal ground voltage signal line VSSQ causes the voltage of the voltage regulator setting terminal NDints[n] to be between the positive voltage H (LC = H) of the voltage regulator supply voltage LC conducted by the voltage regulator setting transistor Tf1[n] and the lowest negative voltage L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ conducted by the voltage regulator setting transistor Tf2[n]. That is, L- <NDints[n]<H。

[0412] In practical applications, the voltage value of the voltage regulator setting terminal NDints[n] during the synchronization phase of STG-a1 depends on the size relationship between the voltage regulator setting transistors Tf1[n] and Tf2[n]. For example, if the voltage regulator setting transistors Tf1[n] and Tf2[n] have the same size, the voltage value of the voltage regulator setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n] = (H + L-) / 2.

[0413] During the synchronization phase STG-a1, the voltage at the regulator setting terminal NDints[n] is between the minimum negative voltage value L- and the positive voltage value H, which is insufficient to turn on the regulator setting transistor Tf3[n]. Therefore, at this time, the voltage at the regulator terminal NDstb[n] is equal to the minimum negative voltage value L- of the intermediate terminal ground voltage VSSQ conducted by the regulator setting transistor Tf4[n] (VSSQ = L-). That is, NDstb[n] = VSSQ = L-.

[0414] Consequently, the gate signal setting transistor Tgs2[n], Zener transistor Tnmstb[n], and Tsstb[n] are all turned off because the voltage at the Zener terminal NDstb[n] is equal to the second lowest negative voltage value L (NDstb[n] = L). Therefore, during the scanning phase STG-s1[n], since the gate signal setting transistor Tgs2[n] is off, the second lowest negative voltage value L (XON_S = L) of the gate synchronization enable signal XON_S does not affect the voltage of the nth level pixel gate signal G[n]. Furthermore, during the scanning phase STG-s1[n], because the Zener transistors Tnmstb[n] and Tsstb[n] are off, the Zener transistor Tnmstb[n] does not affect the voltage at the intermediate terminal NDmd[n]; and the Zener transistor Tsstb[n] does not affect the voltage of the nth level column scan state signal ST[n].

[0415] exist Figure 17A In the diagram, the two ends of capacitor C[n] are respectively set to a positive voltage value H by the intermediate terminal NDmd[n] (NDmd[n] = VGHD = H) and a minimum negative voltage value L by the nth pixel gate signal G[n] (G[n] = HC[k] = L-). Therefore, capacitor C[n] will be charged during the scanning phase of STG-s1[n]. The voltage difference across capacitor C[n] after charging is expressed as capacitor voltage difference ΔVc[n].

[0416] Table 13A summarizes the following: Figure 17A In the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0417] Table 13A

[0418]

[0419]

[0420] Please also see Figure 14 , 15 17B. Figure 17B for, Figure 14The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s2[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], the (n-1)th-stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the positive voltage value H by the timing controller, and the all-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = L-, HC[k] = H, and XON_S = L.

[0421] Next, it will be explained how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal during the scanning phase of STG-s2[n]. Furthermore, it will be explained how the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal in STG-s2[n] and the on / off state of the transistors during the scanning phase.

[0422] Because the (n-1)th column scan state signal ST[n-1] has the lowest negative voltage value L- (ST[n-1]=L-) during the scan phase of STG-s2[n], the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0423] Because the (n+1)th column scan state signal ST[n+1] has the lowest negative voltage value L- (ST[n+1]=L-) during the scan phase of STG-s2[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is therefore disconnected. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0424] As mentioned earlier, the capacitor C[n] will... Figure 17A During the scanning phase, STG-s1[n] is charged and accumulates charge. Therefore, in Figure 17BIn the process, the gate signal setting transistor Tgs1[n] is turned on by the voltage difference between the control terminal and the source terminal (equivalent to the capacitor voltage difference ΔVc[n]). Through the conduction of the gate signal setting transistor Tgs1[n], the positive voltage value H (HC[k] = H) of the column-by-column selection signal HC[k] is conducted to the nth pixel gate signal line G[n].

[0425] Following on, Figure 17A The intermediate terminal NDmd[n] will be charged to the positive voltage value H of the gate supply voltage VGHD (NDmd[n] = VGHD = H) due to the conduction of the intermediate terminal pull-up transistor Tnmu. To facilitate the distinction between the voltages of the intermediate terminal NDmd[n] in STG-s1[n] and STG-s2[n] in different scan stages, the voltage of the intermediate terminal NDmd[n] in STG-s1[n] during the scan stage can be further expressed as NDmd[n](@STG-s1[n]); and the voltage of the intermediate terminal NDmd[n] in STG-s1[n] during the scan stage can be expressed as NDmd[n](@STG-s2[n]).

[0426] exist Figure 17B In the process, the intermediate terminal pull-up transistor Tnmu is disconnected, causing the intermediate terminal NDmd[n] to be in a floating state during the scanning phase of STG-s2[n]. When the intermediate terminal NDmd[n] is in a floating state, its voltage level remains equal to the positive voltage value H of STG-s1[n] during the scanning phase at the instant that the intermediate terminal pull-up transistor Tnmu is disconnected.

[0427] During the scanning phase, the gate signal setting transistor Tgs1[n] and STG-s2[n] remain on, so that the voltage of the nth pixel gate signal G[n] during the scanning phase is equal to the voltage of the column-by-column selection signal HC[k] during the scanning phase. Furthermore, because the column-by-column selection signal HC[k] turned on by the gate signal setting transistor Tgs1[n] switches from the lowest negative voltage value L-(HC[k](@STG-s1[n])=L-) of STG-s1[n] in the scanning phase to the positive voltage value H(HC[k](@STG-s2[n])=H) of STG-s2[n] in the scanning phase, the nth pixel gate signal G[n] also rises from the lowest negative voltage value L-(G[n](@)STG-s1[n]=L-) of STG-s1[n] in the scanning phase to the positive voltage value H(G[n](@)STG-s2[n]=H) of STG-s2[n] in the scanning phase.

[0428] Because capacitor C is positioned between the intermediate endpoint NDmd[n] in the floating state and the nth pixel gate signal G[n], and because the intermediate endpoint NDmd[n] in the floating state temporarily maintains a positive voltage value H equal to the scan phase STG-s1[n], and capacitor C has a capacitance difference ΔVc[n], coupling is formed between the intermediate endpoint NDmd[n] and the nth pixel gate signal G[n]. Consequently, the voltage NDmd[n] (@STG-s2[n]) of the intermediate endpoint NDmd[n] in the scan phase STG-s2[n] will further increase from the positive voltage value H (NDmd[n] (@STG-s1[n]) = VGHD = H) of the scan phase STG-s1[n]. At this time, the voltage NDmd[n] (@STG-s2[n]) of the intermediate endpoint NDmd[n] during the scanning phase of STG-s2[n] will rise to the sum of the positive voltage value H and the capacitor voltage difference ΔVc[n] (H+ΔVc[n]).

[0429] As can be seen from the foregoing description, the voltage NDmd[n](@STG-s2[n]) of the intermediate endpoint NDmd[n] during the scanning phase of STG-s2[n] can be expressed as follows: NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]=VGHD+ΔVc[n]=H+ΔVc[n].

[0430] Therefore, the voltage of the intermediate endpoint NDmd[n] at STG-s2[n] during the scanning phase (NDmd[n](@STG-s2[n])=H+ΔVc[n]) ensures that the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are stably maintained in the on state during the scanning phase of STG-s2[n]. Specifically, the conduction of the state signal setting transistor Tss[n] allows the nth-level column scan state signal ST[n] to maintain a positive voltage value H equal to the column-by-column selection signal HC[k] (HC[k]=H). That is, ST[n]=HC[k]=H. Furthermore, the conduction of the gate signal setting transistor Tgs1[n] allows the nth-level pixel gate signal G[n] to stably maintain a positive voltage value H equal to the column-by-column selection signal HC[k] (HC[k]=H). That is, G[n]=HC[k]=H.

[0431] Because the nth pixel gate signal G[n] is coupled to the capacitor C[n], the voltage NDmd[n] (@STG-s2[n]) at the intermediate endpoint NDmd[n] during the scanning phase is equal to the sum of the positive voltage H and the capacitor voltage difference ΔVc[n] (NDmd[n] (@STG-s2[n]) = H + ΔVc[n]), causing the gate signal setting transistor Tgs1[n], the voltage regulator setting transistor Tf2[n], and Tf4[n] connected to the intermediate endpoint NDmd[n] to all conduct. The gate signal setting transistor Tgs1[n], which is in the conducting state, conducts the positive voltage H (HC[k] = H) of the column-by-column selection signal HC[k] to the nth pixel gate signal line G[n]. That is, G[n] = HC[k] = H. The Zener terminal setting transistor Tf2[n], which is in the ON state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the Zener terminal setting transistor NDints[n]. That is, NDints[n] = VSSQ = L-. The Zener terminal setting transistor Tf4[n], which is in the ON state, conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the Zener terminal NDstb[n]. That is, NDstb[n] = VSSQ = L-.

[0432] exist Figure 17B In this circuit, the control terminal of the voltage regulator setting transistor Tf1[n] continuously receives the positive voltage value H (LC = H) of the voltage regulator supply voltage LC and remains in the on state. Therefore, the voltage regulator setting transistor Tf1[n] conducts the positive voltage value H (LC = H) of the voltage regulator supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n] = LC = H.

[0433] Since both the voltage regulator terminal setting transistors Tf1[n] and Tf2[n] are in the on state, the voltage regulator setting terminal NDints[n] simultaneously receives the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC through the voltage regulator terminal setting transistor Tf1[n], and receives the minimum negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ through the voltage regulator terminal setting transistor Tf2[n].

[0434] Accordingly, the voltage regulating terminal setting transistors Tf1[n] and Tf2[n] connected between the voltage supply signal line LC of the voltage regulating terminal and the ground voltage signal line VSSQ of the intermediate terminal form a voltage dividing effect between the positive voltage value H (LC = H) of the voltage supply LC at the voltage regulating terminal and the lowest negative voltage value L- (VSSQ = L-) of the ground voltage VSSQ at the intermediate terminal. Therefore, the voltage of the voltage regulating setting terminal NDints[n] is between the lowest negative voltage value L- and the positive voltage value H. That is, L- < NDints[n] < H.

[0435] In practical applications, the voltage value of the voltage regulating setting terminal NDints[n] during the synchronization stage STG-a2 will depend on the size relationship of the voltage regulating terminal setting transistors Tf1[n] and Tf2[n]. For example, when the sizes of the voltage regulating terminal setting transistors Tf1[n] and Tf2[n] are the same, the voltage value of the voltage regulating setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n] = (H + L-) / 2.

[0436] During the synchronization stage STG-a2, the voltage of the voltage regulating setting terminal NDints[n] is between the lowest negative voltage value L- and the positive voltage value H (L- < NDints[n] < H), which is not sufficient to turn on the voltage regulating terminal setting transistor Tf3[n]. Therefore, at this time, the voltage of the voltage regulating terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the ground voltage VSSQ conducted by the voltage regulating terminal setting transistor Tf4[n]. That is, NDstb[n] = VSSQ = L-.

[0437] Consequently, during the scanning stage STG-s2[n], the gate signal setting transistors Tgs2[n], the voltage regulating transistors Tnmstb[n] and Tsstb[n] are all turned off because the voltage of the voltage regulating terminal NDstb[n] is equal to the second lowest negative voltage value L (NDstb[n] = L). Due to the disconnection of the gate signal setting transistor Tgs2[n], the second lowest negative voltage value L (XON_S = L) of the full gate synchronization enable signal XON_S does not affect the voltage of the nth stage pixel gate signal G[n]. In addition, because the voltage regulating transistors Tnmstb[n] and Tsstb[n] are turned off, the voltage regulating transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; and, the voltage regulating transistor Tsstb[n] does not affect the voltage of the nth stage column scanning status signal ST[n].

[0438] Table 13B summarizes in Figure 17BIn the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0439] Table 13B

[0440]

[0441] Please also see Figure 14 , 15 17C. Figure 17C for, Figure 14 The state of the nth-stage gate drive circuit gtCKT[n] during the scanning phase STG-s3[n] of DURscan[n] during the nth-stage single-stage scan. When the nth-stage gate drive circuit gtCKT[n] is in the scanning phase STG-s3[n], the (n-1)th-stage column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th-stage gate drive circuit gtCKT[n-1], the (n+1)th-stage column scan state signal ST[n+1] is set to the positive voltage value H- by the (n+1)th-stage gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the all-gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1] = L-, ST[n+1] = H, HC[k] = L-, and XON_S = L.

[0442] Next, it will be explained how the on / off state of the transistors in the nth-stage gate drive circuit gtCKT[n] changes with the level of the input signal during the scanning phase of STG-s3[n]. Furthermore, it will be explained how the voltages of the internal terminals (intermediate terminal NDmd[n], voltage setting terminal NDints[n], voltage regulating terminal NDstb[n]) and the output signals (nth-stage pixel gate signal line G[n], nth-stage column scan state signal ST[n]) of the nth-stage gate drive circuit gtCKT[n] are determined in response to the level of the input signal in STG-s3[n] and the on / off state of the transistors during the scanning phase.

[0443] Since the (n-1)th column scan state signal ST[n-1] has the lowest negative voltage value L- (ST[n-1]=L-) during the scan phase of STG-s3[n], the intermediate terminal pull-up transistor Tnmu[n] is therefore disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n], which is in the disconnected state, does not affect the voltage of the intermediate terminal NDmd[n].

[0444] Since the (n+1)th column scan state signal ST[n+1] has a positive voltage value H (ST[n+1]=H) during the scan phase of STG-s3[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on. The intermediate terminal pull-down transistor Tnmd_nxt[n], in the turned-on state, conducts the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0445] Because the voltage of the intermediate terminal NDmd[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ, the status signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], the voltage regulator terminal setting transistors Tf2[n], and Tf4[n] are all turned off during the scanning phase of STG-s3[n]. Because the status signal setting transistors Tss[n] and Tgs1[n] are turned off, the lowest negative voltage value L- (HC[k] = L-) of the column-by-column selection signal HC[k] will not affect the nth-level column scan status signal ST[n] or the nth-level pixel gate signal G[n]. Furthermore, Tf2[n] being in the off state will not affect the voltage of the voltage regulator terminal NDints[n]; the voltage regulator terminal setting transistor Tf4[n] being in the off state will not affect the voltage of the voltage regulator terminal NDstb[n].

[0446] Because the voltage supplied to the regulator terminal LC is a positive voltage value H (LC = H), the regulator terminal setting transistor Tf1[n] is turned on. Therefore, the regulator terminal setting transistor Tf1[n] conducts the positive voltage value H (LC = H) of the voltage supplied to the regulator terminal LC to the regulator setting terminal NDints[n]. That is, NDints[n] = LC = H.

[0447] Because the voltage at the regulator setting terminal NDints[n] is a positive voltage value H (NDints[n] = H), the regulator setting transistor Tf3[n] remains in the on state, thereby conducting the positive voltage value H (LC = H) of the regulator supply voltage LC to the regulator terminal NDstb[n]. That is, NDstb[n] = LC = H.

[0448] Because the voltage at the regulated terminal NDstb[n] is a positive voltage value H (NDstb[n] = H), the gate signal setting transistor Tgs2[n], the Zener transistor Tnmstb[n], and the Zener transistor Tsstb[n], which are connected to the regulated terminal NDstb[n], are all in the on state during the scanning phase via STG-s3[n]. The following explanation is in order from right to left.

[0449] The gate signal setting transistor Tgs2[n] is turned on, causing the second lowest negative voltage value L (XON_S = L) of the full gate synchronization enable signal XON_S to be conducted to the nth pixel gate signal line G[n]. That is, G[n] = XON_S = L.

[0450] The Zener transistor Tnmstb[n] in the on state conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n], making the voltage at the intermediate terminal NDmd[n] equal to the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ. That is, NDmd[n] = VSSQ = L-.

[0451] The Zener transistor Tsstb[n] in the on state conducts the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the nth column scan state signal ST[n]. That is, ST[n] = VSSQ = L- in Figure 17C In this configuration, the Zener transistor Tnmstb[n] and the intermediate terminal pull-down transistor Tnmd_nxt[n] simultaneously conduct the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. Therefore, the voltage at the intermediate terminal NDmd[n] can be stably maintained at the lowest negative voltage value L-. That is, NDmd[n] = VSSQ = L-.

[0452] Table 13C is compiled in Figure 17C In the diagram, how do the input signals, such as the (n-1)th level column scan state signal ST[n-1], the (n+1)th level column scan state signal ST[n+1], and the regulated terminal supply voltage LC=H, affect the transistor's on / off state, thereby setting the voltage of the internal terminals and output signals?

[0453] Table 13C

[0454]

[0455]

[0456] Table 14 summarizes the states of the transistors shown in Figures 16-16C and 17A-17C. In Table 14, "-" represents the transistor being off.

[0457]

[0458]

[0459] Please also see Figure 15 , 16A~16C, 17A~17C. Since each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to a gate signal setting transistor Tgs2[1]~Tgs2[N], and these gate signal setting transistors Tgs2[1]~Tgs2[N] are all controlled by the same full gate synchronization period signal XON_C, the behavior of the gate signal setting transistors Tgs2[1]~Tgs2[N] is consistent.

[0460] In the second embodiment, unlike the first embodiment, a full-gate synchronization signal XON_C is not provided. In the second embodiment, the control terminal of the gate signal setting transistor Tgs2[n] is instead electrically connected to the regulated terminal NDstb[n]. Figure 15 The waveform shows that the voltage regulator endpoint NDstb[n] will maintain a positive voltage value H during full gate synchronization. By analogy, the voltage regulator endpoints NDstb[1] to NDstb[N] will all maintain a positive voltage value H (NDstb[n] = H) during full gate synchronization, and the gate signal setting transistors Tgs2[1] to Tgs2[N] will each be turned on during full gate synchronization according to their corresponding voltage regulator endpoints NDstb[1] to NDstb[N].

[0461] When the gate signal setting transistors Tgs2[1] to Tgs2[N] remain in the DURall-sync state during full gate synchronization, depending on the voltage of the regulated terminals NDstb[1] to NDstb[N], the voltages of the N-level pixel gate signals G[1] to G[n] are simultaneously determined by the voltage of the full gate synchronization enable signal XON_S. Figure 15 It can be seen that the full-gate synchronization enable signal XON_S is set to a positive voltage value H (XON_S = H) only during the synchronization phase STG-a2 of DURall-sync during full-gate synchronization, and is set to the second lowest negative voltage value L (XON_S = L) in other phases. In this way, the timing controller can synchronize the N-level pixel gate signals G[1] to G[N] to be equal to the positive voltage value H (G[1] = ... = G[N] = H) by using the full-gate synchronization enable signal XON_S equal to the positive voltage value H (XON_S = H) during the synchronization phase STG-a2 of DURall-sync during full-gate synchronization. On the other hand, during the nth single-level scan DURscan[n], whether the gate signal setting transistor Tgs2[n] is turned on or off will change with the voltage change of the regulated terminal NDstb[n].

[0462] Because the voltage regulator terminals NDstb[n] are at their lowest negative voltage value L- (NDstb[n] = L-) during the scanning phase of STG-s1[n] and STG-s2[n], the gate signal setting transistor Tgs2[n] is off during the scanning phase of STG-s1[n] and STG-s2[n] (see Figure 17A , 17B At this point, the gate signal setting transistor Tgs2[n] does not affect the gate signal G[n] of the nth pixel.

[0463] Because the voltage regulator terminal NDstb[n] has a positive voltage value H (NDstb[n] = H) during the scanning phase of STG-s3[n], the gate signal setting transistor Tgs2[n] is turned on during the scanning phase of STG-s3[n] (see Figure 17C At this point, the gate signal setting transistor Tgs2[n] conducts the second lowest negative voltage value L (XON_S = L) of the full gate synchronization enable signal XON_S to the nth pixel gate signal line G[n]. That is, G[n] = XON_S = L.

[0464] As mentioned earlier, in this paper, [n] represents the signal that changes with n = 1 to N, and [k] represents one of the groups (HC[k], where k = 1 to K) after dividing the N columns into K groups to select the signals HC[1] to HC[K] column by column. According to the concept disclosed herein, the input signals HC[1] to HC[K] are pulsed input signals generated sequentially according to the different N-level gate drive circuits gtCKT[1] to gtCKT[N].

[0465] For example, when the timing controller STG-s2[n-1] sets the column-by-column selection signal HC[k-1] corresponding to the (n-1)th stage gate drive circuit gtCKT[n-1] to a positive voltage value H (HC[k-1]=H), the column-by-column selection signal HC[k] corresponding to the nth stage gate drive circuit gtCKT[n] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th stage gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L- (HC[k]=HC[k+1]=L-). When the timing controller STG-s2[n] sets the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] to a positive voltage value H (HC[k]=H) during the scanning phase, the column-by-column selection signal HC[k-1] corresponding to the (n-1)th-level gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th-level gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L- (HC[k-1]=HC[k+1]=L-). When the timing controller STG-s2[n+1] sets the column-by-column selection signal HC[k+1] corresponding to the (n+1)th stage gate drive circuit gtCKT[n+1] to a positive voltage value H (HC[k+1]=H), the column-by-column selection signal HC[k-1] corresponding to the (n-1)th stage gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k] corresponding to the (n)th stage gate drive circuit gtCKT[n] are set to the lowest negative voltage value L- (HC[k-1]=HC[k]=L-).

[0466] like Figure 15 As shown, the column-by-column selection signal HC[k] corresponding to the nth-stage gate drive circuit gtCKT[n] is set to a positive voltage value H during the scan phase of DURscan[n] in the nth-stage single-stage scan. Furthermore, in conjunction with... Figure 17B It can be seen that when the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] is set to a positive voltage value H (HC[k] = H) during the scanning phase of STG-s2[n], the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are turned on by the intermediate terminal NDmd[n] = H + ΔVc[n], thereby transmitting the positive voltage value H (HC[k] = H) of the column-by-column selection signal HC[k] to the nth-level pixel gate signal line G[n] and the nth-level column scan state signal line ST[n]. That is, G[n] = ST[n] = H.

[0467] Since the column-by-column selection signal HC[k] corresponding to the nth-level gate drive circuit gtCKT[n] is generated at different times depending on the level n = 1 to N, in this way, the timing controller can enable the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] in the nth-level gate drive circuit gtCKT[n] during the scanning stage STG-s2[n] corresponding to the nth-level gate drive circuit gtCKT[n], thereby generating the pulse of the nth-level pixel gate signal G[n] and the pulse of the nth-level column scan state signal ST[n] that correspond only to the nth-level gate drive circuit gtCKT[n].

[0468] Also note that the scan phase STG-s2[n] corresponding to the nth stage gate drive circuit gtCKT[n] overlaps with the scan phase STG-s3[n-1] corresponding to the (n-1)th stage gate drive circuit gtCKT[n-1]; and overlaps with the scan phase STG-s1[n+1] corresponding to the (n+1)th stage gate drive circuit gtCKT[n+1]. That is, STG-s3[n-1] = STG-s2[n] = STG-s1[n+1].

[0469] Therefore, during the period corresponding to the scanning phase STG-s3[n-1]=STG-s2[n]=STG-s1[n+1], the (n-1)th level pixel gate signal G[n-1] and the (n-1)th level column scan state signal ST[n-1] corresponding to the (n-1)th level gate drive circuit gtCKT[n-1], and the (n+1)th level pixel gate signal G[n+1] and the (n+1)th level column scan state signal ST[n-1] corresponding to the (n-1)th level gate drive circuit gtCKT[n+1], are... The (n+1) level column scan state signal ST[n+1] will not be set to a positive voltage value H because the column-by-column select signal HC[k-1] corresponding to the (n-1) level gate drive circuit gtCKT[n-1] is the lowest negative voltage value L- (HC[k-1]=L-), and because the column-by-column select signal HC[k+1] corresponding to the (n+1) level gate drive circuit gtCKT[n+1] is the lowest negative voltage value L- (HC[k+1]=L-).

[0470] As previously stated, the DURall-scan during the round-robin scan period comprises N single-stage scan periods DURscan[1] to DURscan[N]. In the second embodiment of the present invention, each gate drive circuit gtCKT[1] to gtCKT[N] corresponds to three scan stages. Therefore, in the second embodiment of the present invention, the DURall-scan during the round-robin scan period covers a total of (N+2) scan stages.

[0471] like Figure 17B As explained, the voltage value of the intermediate terminal NDmd[n] at STG-s2[n] during the scanning phase is equivalent to the sum of the voltage value of the intermediate terminal NDmd[n] at STG-s1[n] during the scanning phase and the capacitor voltage difference ΔVc[n]. That is, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]. Therefore, it can be seen that the intermediate terminal NDmd[n] is not actually turned on to a stable voltage value at STG-s2[n] during the scanning phase. Thus, the intermediate terminal NDmd[n] at STG-s2[n] can be considered to be floating during the scanning phase. To avoid leakage current in the intermediate terminal pull-down transistor Tnmd_nxt[n] and Zener transistor Tnmstb[n] due to the floating of the intermediate terminal NDmd[n], and even to prevent the gate signal setting transistor Tgs1[n] from being incompletely turned on, this disclosure can further modify the design of the gate drive circuit gtCKT[n].

[0472] Please see Figure 18 This is a schematic diagram of a second embodiment of the nth-stage gate drive circuit gtCKT[n] based on the concept disclosed herein, combined with a method to reduce leakage current.

[0473] Figure 18 The diagram illustrates two methods for reducing leakage current (Method A and Method B). Please also refer to... Figure 14 , 18 .

[0474] The first method to reduce leakage current (Method A) is as follows: Figure 18 The line segment lkgCNT_2a is shown. Figure 14 In the middle, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal ground voltage signal line VSSQ. However, Figure 18 In the middle, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is changed to be electrically connected to the all-gate synchronous enable signal line XON_S.

[0475] If the second embodiment is not adopted Figure 18In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th stage column scan state signal line ST[n-1] and the intermediate terminal ground voltage signal line VSSQ, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal is the lowest negative voltage value L- (ST[n-1] = L-) of the (n-1)th stage column scan state signal line ST[n-1], and its source terminal is the lowest negative voltage value L- (VSSQ = L-) of the intermediate terminal ground voltage VSSQ. At this time, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] is close to 0V, which makes it easier to generate leakage current.

[0476] On the other hand, if the second embodiment adopts Figure 18 In method A, the control terminal and source terminal of the intermediate-terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th stage column scan state signal line ST[n-1] and the full-gate synchronization enable signal line XON_S, respectively. When the intermediate-terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal is the lowest negative voltage value L- (ST[n-1] = L-) of the (n-1)th stage column scan state signal line ST[n-1], and its source terminal is the second lowest negative voltage value L (XON_S = L) of the full-gate synchronization enable signal line XON_S. Therefore, the gate-source voltage difference (ΔVgs) of the intermediate-terminal pull-down transistor Tnmd_nxt[n] exhibits a negative bias. Therefore, by using this wiring method, the leakage current generated in the intermediate-terminal pull-down transistor Tnmd_nxt[n] can be reduced.

[0477] The second method to reduce leakage current (Method B) is as follows: Figure 18 The line segment lkgCNT_2b is shown. Figure 14 In the original Zener transistor Tnmstb[n], the source was electrically connected to the ground voltage signal line VSSQ at the intermediate terminal. However, Figure 18 In this process, the source of the Zener transistor Tnmstb[n] is changed to be electrically connected to the nth column scan state signal line ST[n].

[0478] Please also see Figure 14 , 15 17B, ​​18. (e.g.) Figure 17B As shown, when the nth-stage gate drive circuit gtCKT[n] is in the scanning stage STG-s2[n], the Zener transistor Tnmstb[n] is in the off state.

[0479] according to Figure 14In the connection method, when the Zener transistor Tnmstb[n] is off, the voltage at the control terminal of the Zener transistor Tnmstb[n] is equal to the lowest negative voltage value L- (NDstb[n] = VSSQ = L-) from the Zener terminal NDstb[n], and the voltage at its source terminal is equal to the lowest negative voltage value L- (VSSQ = L-) from the intermediate terminal ground voltage VSSQ. Therefore, if the nth stage gate drive circuit gtCKT[n] adopts Figure 14 , 17B In the connection mode, the Zener transistor Tnmstb[n] in the disconnected state is prone to leakage current during DURall-scan due to the gate-source voltage difference (ΔVgs) being close to 0V.

[0480] On the other hand, according to Figure 18 In the connection method, when the nth-stage gate drive circuit gtCKT[n] is in the off state during the DURall-scan, the voltage at the control terminal of the Zener transistor Tnmstb[n] is equal to the lowest negative voltage value L- (NDstb[n] = L-) from the Zener terminal NDstb[n], and the voltage at its source terminal is equal to the positive voltage value H (ST[n] = HC[k] = H) from the nth-stage column scan state signal ST[n].

[0481] Therefore, adopt Figure 18 When the Zener transistor Tnmstb[n] is in the off state, because the positive voltage value of the nth column scan state signal ST[n] (ST[n]=HC[k]=H) is higher than the minimum negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the Zener transistor Tnmstb[n] exhibits a negative bias (ΔVgs<0). Therefore, when using the wiring method of method B, the chance of leakage current generated by the Zener transistor Tnmstb[n] can be reduced.

[0482] In practical applications, the gate drive circuit gtCKT[n] can reduce leakage current by using only method A (segment lkgCNT_2a), only method B (segment lkgCNT_2b), or both methods A and B (segments lkgCNT_2a and lkgCNT_2b). Regardless of whether one or both methods A and B are used, the existing methods can be directly applied. Figure 15 , 16A The descriptions of ~16C and 17A~17C generate the nth-level pixel gate signal G[n] and the nth-level column scan state signal ST[n].

[0483] To extend circuit lifespan (reduce thin-film transistor stress), the gate drive circuit gtCKT[n] can employ two sets of voltage regulator circuits. Please refer to [link to relevant documentation]. Figure 19 This is a second embodiment based on the nth-stage gate drive circuit gtCKT[n] of the disclosed concept, illustrated with two sets of voltage regulator circuits. Figure 19 The internal components and connection methods of the medium voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are the same as those of the medium voltage regulator modules stbMDL-a[n] and stbMDL-b[n]. Figure 14 It is similar to the voltage regulator module stbMDL[n].

[0484] Table 15 Comparison Figure 6 The voltage regulator module stbMDL[n], and Figure 19 The components inside the voltage regulator modules stbMDL-a[n] and stbMDL-b[n].

[0485] Table 15

[0486]

[0487]

[0488] and Figure 12 Compared to the voltage regulator module stbMDL[n], the voltage regulator module stbMDL-a[n] additionally includes: voltage regulator module selection transistor Tsel-a; the voltage regulator module stbMDL-b[n] additionally includes: voltage regulator module selection transistor Tsel-b. The drain terminals of voltage regulator module selection transistors Tsel-a and Tsel-b are both electrically connected to the control terminal of gate signal setting transistor Tgs2[n], and voltage regulator module selection transistors Tsel-a and Tsel-b alternately control the on / off state of gate signal setting transistor Tgs2[n].

[0489] In the voltage regulator module stbMDL-a[n], the control terminal of the voltage regulator module selection transistor Tsel-a is controlled by the voltage supply voltage LC-a of the voltage regulator endpoint. When the voltage regulator module selection transistor Tsel-a is turned on along with the voltage supply voltage LC-a, the control terminal of the gate signal setting transistor Tgs2[n] will be set to the voltage of the voltage regulator endpoint NDstb[n]. In other words, when the timing controller enables the voltage regulator module stbMDL-a[n], it does not directly control the control terminal of the gate signal setting transistor Tgs2[n] with the voltage of the voltage regulator endpoint NDstb-a[n]. Instead, after the voltage regulator module selection transistor Tsel-a[n] is turned on, it indirectly uses the voltage of the voltage regulator endpoint NDstb-a[n] to control the control terminal of the gate signal setting transistor Tgs2[n].

[0490] Similarly, in the voltage regulator module stbMDL-b[n], the control terminal of the voltage regulator module selection transistor Tsel-b is controlled by the voltage supply voltage LC-b of the voltage regulator endpoint. When the voltage regulator module selection transistor Tsel-b is turned on along with the voltage supply voltage LC-b of the voltage regulator endpoint, the control terminal of the gate signal setting transistor Tgs2[n] will be set to the voltage of the voltage regulator endpoint NDstb-b[n]. In other words, when the timing controller enables the voltage regulator module stbMDL-b[n], it does not directly control the control terminal of the gate signal setting transistor Tgs2[n] with the voltage of the voltage regulator endpoint NDstb-b[n]. Instead, after the voltage regulator module selection transistor Tsel-b is turned on, it indirectly uses the voltage of the voltage regulator endpoint NDstb-b[n] to control the control terminal of the gate signal setting transistor Tgs2[n].

[0491] When the timing controller sets the voltage supply voltage LC-a to a positive value H (LC-a = H) and the voltage supply voltage LC-b to a minimum negative value L- (LC-b = L-), the voltage regulator selection transistor Tsel-a is turned on, and the voltage regulator selection transistor Tsel-b is turned off. At this time, the voltage of the voltage regulator terminal NDstb-a[n] is conducted to the control terminal of the gate signal setting transistor Tgs2[n] by the voltage regulator selection transistor Tsel-a. Therefore, it can be regarded as the timing controller controlling the gate drive circuit gtCKT[n] to use the voltage regulator module stbMDL-a[n] and disable the voltage regulator module stbMDL-b[n].

[0492] When the timing controller sets the voltage supply to the regulated endpoint LC-a to the lowest negative voltage value L- (LC-a = L-) and the voltage supply to the regulated endpoint LC-b to the positive voltage value H (LC-b = H), the voltage regulator selection transistor Tsel-a is turned off, and the voltage regulator selection transistor Tsel-b is turned on. At this time, the voltage of the regulated endpoint NDstb-b[n] is conducted to the control terminal of the gate signal setting transistor Tgs2[n] by the voltage regulator selection transistor Tsel-b. Therefore, it can be regarded as the timing controller controlling the gate drive circuit gtCKT[n] to disable the voltage regulator module stbMDL-a[n] and use the voltage regulator module stbMDL-b[n].

[0493] According to the concept disclosed herein, multiple sets of voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are set in the gate drive circuit gtCKT[n], which can extend the life of the transistor. The timing controller can control the gate drive circuit gtCKT[n] to alternately use the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] during different frame periods Tframe.

[0494] Please see Figure 20This is a schematic diagram summarizing embodiments of the two types of nth-stage gate drive circuits gtCKT[n] proposed in this disclosure. Please also refer to... Figure 5 , 13 20. Figure 20 Compilation Figure 5 , 13 The relationship between the circuit, internal terminals, and signals.

[0495] The internal circuitry, composition of each internal circuit, received signals, and connection relationships of the nth-stage gate drive circuit gtCKT[n] have been explained in the foregoing embodiments and will not be detailed here. Figure 20 In the diagram, solid lines indicate the same connection relationships in both embodiments; and dashed line segments L1a, L1b, L1c, L2a, and L2b indicate different connection relationships used in different embodiments.

[0496] The dashed lines L1a, L1b, and L1c represent the wiring used only in the first embodiment. Specifically, the voltage regulator circuit stbCKT[n] is electrically connected to the nth pixel gate signal line G[n] via dashed line L1a, and to the pixel gate ground voltage signal line VSSG via dashed line L1b. Furthermore, the full gate synchronization signal XON_C is electrically connected to the voltage regulator endpoint setting circuit stbsCKT[n], the intermediate endpoint pull-down circuit nmdCKT[n], and the gate signal setting circuit gsCKT[n] via dashed line L1c.

[0497] The dashed lines L2a and L2b represent the wiring used only in the second embodiment. Specifically, the gate signal setting circuit gsCKT[n] is electrically connected to the voltage regulator terminal NDstb[n] via the dashed line L2a, and the voltage regulator circuit stbCKT[n] is electrically connected to the pixel gate ground voltage signal line VSSG via the dashed line L2b.

[0498] Table 16 summarizes the components and signals for both embodiments. The components listed in Table 16 are based on a design of a set of voltage regulator modules ( Figure 6 , 14 (Compare)

[0499] Table 16

[0500]

[0501]

[0502]

[0503] As can be seen from the comparison in Table 16, the second embodiment has fewer input signals and fewer transistors than the first embodiment. In the second embodiment, the pixel gate ground voltage VSSG and the full gate synchronization signal XON_C are not used. Consequently, in the second embodiment, the Zener transistor Tgstb[n] connected to the pixel gate ground voltage signal line VSSG, as well as the Zener endpoint setting transistors Tf5[n] and Tf6[n] and the intermediate endpoint pull-down transistor Tnmd_xon[n] connected to the full gate synchronization signal XON_C, which were present in the first embodiment, are also removed.

[0504] In the second embodiment, because the full gate synchronization signal XON_C is not used, the control terminal of the gate signal setting transistor Tgs2[n] is no longer connected to the full gate synchronization signal XON_C as in the first embodiment, but is instead connected to the voltage regulator terminal NDstb[n]. Furthermore, because the voltage regulator transistor Tgstb[n] is removed, in the second embodiment, the nth pixel gate signal line G[n] is only connected to the capacitor C[n] and the source terminals of the gate signal setting transistors Tgs1[n] and Tgs2[n].

[0505] The foregoing descriptions all take the nth-level gate driver circuit gtCKT[n] of the N gate driver circuits gtCKT[1] to gtCKT[N] as an example. n and N are positive integers, and n≤N. The nth-level gate driver circuit gtCKT[n] receives the (np)th-level column scan status signal ST[np] from the (np)th-level gate driver circuit gtCKT[np], and the (n+q)th-level column scan status signal ST[n+q] from the (n+q)th-level gate driver circuit gtCKT[n+q]. When (np)<1 or (n+q)>N, since the gate driver does not include the gate driver circuits gtCKT[np] and gtCKT[n+q], the gate driver needs to be paired with a timing controller to generate the column scan status signals ST[np] and ST[n+q] in an analog manner. This part regarding the application changes and design substitutions will not be detailed in this article.

[0506] As can be seen from the two embodiments disclosed herein, the gate driver of this invention can control the generation method and sequence of N-level pixel gate signals G[1] to G[N] based on both synchronization and scanning requirements. Therefore, the gate driver of this invention can overcome the deficiency of existing technologies that cannot use GOA technology to implement gate drivers. As mentioned above, whether it is a cholesteric liquid crystal panel or a general liquid crystal panel, the gate driver will generate N-level pixel gate signals G[1] to G[N] at different times for both synchronous pulse generation and sequential pulse generation requirements. Therefore, this invention can be applied to different types of display panels.

[0507] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A gate driver characterized by, An output signal setting module electrically connected to the timing controller and an intermediate terminal, wherein During a full gate synchronization period, the N-stage gate driving circuits are synchronously set with N-stage pixel gate signals according to a full gate synchronization enable signal transmitted from the timing controller, and During an nth-stage single-stage scanning period in a round-robin scanning period, the output signal setting module selectively sets an nth-stage column scanning status signal and an nth-stage pixel gate signal in the N-stage pixel gate signals according to a voltage of the intermediate terminal, wherein The round-robin scanning period comprises N-stage single-stage scanning periods corresponding to the N-stage gate driving circuits respectively, wherein n and N are positive integers, and n is less than or equal to N; wherein further comprising: an intermediate terminal setting module electrically connected to an (n-p)-th stage gate driving circuit and an (n+q)-th stage gate driving circuit in the N-stage gate driving circuits, which selectively sets the voltage of the intermediate terminal to one of a first voltage value and a second voltage value according to an (n-p)-th column scanning status signal transmitted from the (n-p)-th stage gate driving circuit and an (n+q)-th column scanning status signal transmitted from the (n+q)-th stage gate driving circuit, wherein p and q are positive integers, and the first voltage value and the second voltage value have opposite polarities; wherein the intermediate terminal setting module comprises: an intermediate terminal pull-up circuit electrically connected to the intermediate terminal and the (n-p)-th stage gate driving circuit, which selectively conducts the first voltage value to the intermediate terminal according to the (n-p)-th column scanning status signal received from the (n-p)-th stage gate driving circuit; and an intermediate terminal pull-down circuit electrically connected to the intermediate terminal and the (n+q)-th stage gate driving circuit, which selectively conducts the second voltage value to the intermediate terminal according to the (n+q)-th column scanning status signal transmitted from the (n+q)-th stage gate driving circuit. wherein the output signal setting module comprises:

2. The gate driver of claim 1, wherein, a status signal setting circuit electrically connected to the timing controller and the intermediate terminal, which selectively conducts an scanning column selection signal transmitted from the timing controller to the nth-stage column scanning status signal according to a control of the intermediate terminal; and a gate signal setting circuit electrically connected to the timing controller and the intermediate terminal, which selectively conducts the scanning column selection signal to the nth-stage pixel gate signal according to a control of the intermediate terminal. wherein the gate driver is electrically connected to a pixel array comprising M*N pixel transistors, and the nth-stage gate driving circuit is electrically connected to an (n-q)-th stage gate driving circuit and an (n+p)-th stage gate driving circuit in the N-stage gate driving circuits, wherein 3. The gate driver of claim 1, wherein, the output signal setting module transmits the nth-stage column scanning status signal to the (n-q)-th stage gate driving circuit and the (n+p)-th stage gate driving circuit, and ​ The output signal setting module transmits the nth-stage pixel gate signal to M pixel transistors located at an nth column in the pixel array.

4. The gate driver of claim 1, wherein, The full gate synchronization period includes: a first synchronization stage; a second synchronization stage; and a third synchronization stage, wherein the first synchronization stage is earlier than the second synchronization stage, and the second synchronization stage is earlier than the third synchronization stage, and each of the N-stage single-stage scanning periods includes: a first scanning stage; a second scanning stage; and a third scanning stage, wherein the first scanning stage, the second scanning stage, and the third scanning stage are equal in length, wherein the first scanning stage is earlier than the second scanning stage, and the second scanning stage is earlier than the third scanning stage.

5. The gate driver of claim 4, wherein, During the full gate synchronization period, the output signal setting module sets the nth-stage pixel gate signal according to the full gate synchronization enable signal, wherein the timing controller sets the full gate synchronization enable signal to a first voltage value during the second synchronization stage, and the timing controller sets the full gate synchronization enable signal to a second voltage value during the first synchronization stage and the third synchronization stage, wherein the first voltage value and the second voltage value are opposite in polarity. During the first scanning stage and the second scanning stage in the nth-stage single-stage scanning period, 6. The gate driver of claim 4, wherein, the output signal setting module transmits a scanning column selection signal transmitted by the timing controller to the nth-stage column scanning state signal and the nth-stage pixel gate signal according to the control of the intermediate endpoint, wherein the timing controller sets the scanning column selection signal to a first voltage value during the second scanning stage, and the timing controller sets the scanning column selection signal to a second voltage value during the full gate synchronization period, the second scanning stage, and the third scanning stage, wherein the first voltage value and the second voltage value are opposite in polarity. The output signal setting module further includes: a capacitor electrically connected to the intermediate endpoint and the nth-stage pixel gate signal, wherein 7. The gate driver of claim 4, wherein, in the first scanning stage, the capacitor is charged when the intermediate endpoint is set to a first voltage value and the nth-stage pixel gate signal is set to a second voltage value, wherein the first voltage value and the second voltage value are opposite in polarity. After the capacitor is charged, it has a capacitor voltage difference, and in the second scanning stage in the nth-stage single-stage scanning period, the voltage of the intermediate endpoint is equal to a voltage sum of the first voltage value and the capacitor voltage difference.

8. The gate driver of claim 7, wherein, In the first scanning stage in the nth-stage single-stage scanning period, the (n-p)th-stage gate drive circuit sets the (n-p)th-stage column scanning state signal to a first voltage value, the nth-stage gate drive circuit sets the nth-stage column scanning state signal to a second voltage value, and the (n+q)th-stage gate drive circuit sets the (n+q)th-stage column scanning state signal to the second voltage value.

9. The gate driver of claim 4, wherein, ​ ​ In the second scan stage of the nth single-stage scan, the (n-p)th gate driving circuit sets the (n-p)th column scan state signal to the second voltage value, the nth gate driving circuit sets the nth column scan state signal to the first voltage value, and the (n+q)th gate driving circuit sets the (n+q)th column scan state signal to the second voltage value; and, In the third scan stage of the nth single-stage scan, the (n-p)th gate driving circuit sets the (n-p)th column scan state signal to the second voltage value, the nth gate driving circuit sets the nth column scan state signal to the second voltage value, and the (n+q)th gate driving circuit sets the (n+q)th column scan state signal to the first voltage value, wherein the first voltage value and the second voltage value are opposite in polarity.

10. The gate driver of claim 1, wherein, The nth gate driving circuit further comprises: a voltage stabilizing module comprising: a voltage stabilizing endpoint setting circuit electrically connected to the intermediate endpoint and a voltage stabilizing endpoint, continuously receiving a first voltage value, and selectively conducting the first voltage value to the voltage stabilizing endpoint according to the voltage of the intermediate endpoint; and a voltage stabilizing circuit electrically connected to the intermediate endpoint, the voltage stabilizing endpoint, and the nth column scan state signal line, selectively conducting a second voltage value to the intermediate endpoint and the nth column scan state signal line according to the voltage of the voltage stabilizing endpoint, wherein the first voltage value and the second voltage value are opposite in polarity.

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