Memory, method of operating memory, and memory system

Abstract

The present disclosure provides a memory, an operating method of the memory and a memory system, relating to the technical field of memory, aiming to improve the security of firmware. The memory includes a page buffer, the page buffer includes a sensing latch circuit, a first charging circuit and a read calibration circuit. The first charging circuit and the sensing latch circuit are coupled to a sensing node, a first end of the read calibration circuit is coupled to the sensing latch circuit, a second end of the read calibration circuit is coupled to the sensing node, and the read calibration circuit is configured to calibrate the potential of the sensing node during the sensing process. The above-mentioned memory is applied to the calibration process of the potential of the sensing node during the sensing process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of memory, and in particular, to a memory, an operating method of the memory, and a memory system. BACKGROUND

[0002] Non-volatile memory is a memory that can retain its stored data for a long time without being powered. Flash memory devices have evolved into a popular type of non-volatile memory for a wide range of applications. Flash memory devices are commonly used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular telephones, and removable memory modules, and the use of flash memory is expanding.

[0003] A flash memory device includes a memory cell, and sensing the content stored in the memory cell is also one of the important operations of the flash memory device, and the circuit that achieves this purpose is called a page buffer (PB). The page buffer determines the content in the memory cell by comparing the voltage level after discharging the sensing node with a predetermined voltage level. Thus, if there is a voltage offset in the voltage drop of the page buffer, it will result in an output error of the sensing result. How to improve the reliability of the sensing result of the page buffer is a problem to be solved. SUMMARY

[0004] Embodiments of the present disclosure provide a memory, an operating method of the memory, and a memory system, aiming at the reliability of the page buffer.

[0005] To achieve the above-mentioned purpose, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In a first aspect, a memory is provided, the memory comprising a page buffer, the page buffer comprising: a sensing latch circuit, a first charging circuit, and a read calibration circuit. The first charging circuit is coupled to a sensing node, a first end of the read calibration circuit is coupled to the sensing latch circuit, and a second end of the read calibration circuit is coupled to the sensing node, and the read calibration circuit is configured to calibrate the potential of the sensing node during a sensing process.

[0007] The page buffer of the memory provided by the above-mentioned embodiments of the present disclosure adds a read calibration circuit, which can calibrate the potential of the sensing node during the sensing process. Thus, the voltage offset caused by the process of the device in the page buffer can be eliminated, and the reliability of the sensing result of the page buffer can be improved.

[0008] In some embodiments, the read calibration circuit includes a first sub-circuit and a second sub-circuit, the first sub-circuit is configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration stage, and the second sub-circuit is configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration stage.

[0009] In these embodiments, by discharging the sensing node from the first voltage value to the second voltage value and charging the sensing node from the second voltage value to the third voltage value, which is the voltage value of the sensing node after the voltage offset is eliminated, the reliability of the sensing result of the page buffer can be improved.

[0010] In some embodiments, the first sub-circuit includes a first transistor, a second transistor and a third transistor. The first end of the first transistor is coupled to the first end of the read calibration circuit, the second end of the first transistor is coupled to the first end of the third transistor, the first end of the second transistor is coupled to the first end of the first transistor, the second end of the second transistor and the second end of the third transistor are coupled and coupled to the second end of the read calibration circuit, and the control end of the third transistor is grounded.

[0011] In some embodiments, in the first sub-stage of the calibration stage, the first transistor and the second transistor are turned on, and the third transistor is turned off. In the second sub-stage of the calibration stage, the first transistor and the third transistor are turned off, and the second transistor is turned on.

[0012] In these embodiments, in the first sub-stage of the calibration stage, the first transistor and the second transistor are controlled to be turned on, and the third transistor is controlled to be turned off, i.e. the sensing node can be discharged through the third transistor, at this time, due to the different threshold voltages of different third transistors, the second voltage value after discharging is also different, which is equivalent to recording the information of different threshold voltages through the second voltage value. In the second sub-stage of the calibration stage, the first transistor and the third transistor are controlled to be turned off, and the second transistor is controlled to be turned on, so that the sensing node can be charged through the second sub-circuit to ensure sufficient initial voltage value in the subsequent sensing stage. Thus, in the entire calibration stage, different threshold voltages are calibrated, the voltage offset in the page buffer can be eliminated, and the reliability of the sensing result of the page buffer can be improved.

[0013] In some embodiments, the sensing process further includes a sensing stage, in which the first transistor is turned on and the second transistor is turned off.

[0014] In these embodiments, during the calibration phase before the sensing phase, different second voltage values ​​can be obtained for different threshold voltages of the third transistor. By coupling and raising different second voltage values, different third voltage values ​​can be obtained. That is, the initial voltage of the sensing phase is different, thereby reducing the impact of voltage offset caused by different threshold voltages of the transistor.

[0015] In some embodiments, the second sub-circuit includes a capacitor and a second charging circuit. A first end of the capacitor is coupled to a sensing node, and a second end of the capacitor is coupled to a first node. The first node is also coupled to the output of the second charging circuit. The second charging circuit is configured to charge the first node in a second sub-stage of the calibration phase, wherein the sensing node is charged from a second voltage value to a third voltage value.

[0016] In these embodiments, the capacitor has the characteristic that its capacitance and potential difference do not change abruptly. The first node can be charged by the second charging circuit to couple and raise the voltage of the sensing node, thereby ensuring a sufficient initial voltage value for the subsequent sensing phase.

[0017] In some embodiments, the capacitor is a parasitic capacitance.

[0018] In some embodiments, the sense latch circuit includes: a first inverter and a second inverter, a fourth transistor, a fifth transistor, and a sixth transistor. A first terminal of the first inverter is coupled to a first terminal of the second inverter, a second terminal of the first inverter is coupled to a second terminal of the second inverter, a first terminal of the fourth transistor is coupled to a first terminal of the first inverter, a second terminal of the fourth transistor is coupled to a first terminal of the sixth transistor, a second terminal of the sixth transistor is grounded, a first terminal of the fifth transistor is coupled to a second terminal of the second inverter, and a second terminal of the fifth transistor is coupled to a first terminal of the sense latch circuit.

[0019] In some embodiments, the page buffer further includes an input circuit, a first end of which is coupled to a bit line and a second end of which is coupled to a sensing node.

[0020] Secondly, a method for operating a memory is provided, the method comprising: in a first sub-stage of a calibration phase, discharging a sensing node from a first voltage value to a second voltage value; in a second sub-stage of the calibration phase, charging the sensing node from the second voltage value to a third voltage value; and storing the state of a memory cell coupled to a bit line during the sensing phase.

[0021] For the benefits of the second aspect, please refer to the explanation of the first aspect.

[0022] In some embodiments, charging the sensing node from a second voltage value to a third voltage value in the second sub-stage of the calibration phase includes: applying a first voltage to the control terminal of the second transistor of the reading calibration circuit in the second sub-stage of the calibration phase.

[0023] In some embodiments, charging the sensing node from a second voltage value to a third voltage value in the second sub-stage of the calibration phase includes: charging the first node in the second sub-stage of the calibration phase.

[0024] In some embodiments, the method further includes charging the sensing node to a first voltage value prior to a first sub-stage of the calibration phase.

[0025] In some embodiments, the method further includes: acquiring the state of the memory cell coupled to the bit line during the sensing phase.

[0026] For the benefits of the second aspect, please refer to the explanation of the first aspect.

[0027] Thirdly, a memory system is provided, the memory system comprising: one or more memories of the first aspect, and a memory controller coupled to the memories and configured to control the memories.

[0028] Fourthly, an electronic device is provided, which includes the memory system described above.

[0029] It is understood that the beneficial effects of the memory, memory operation method, storage system and electronic device provided in the above embodiments of this disclosure can be referred to the beneficial effects of the memory mentioned above, and will not be repeated here. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 A schematic diagram of the structure of an exemplary system S1 having a memory system 10 provided in an embodiment of this disclosure;

[0032] Figure 2 A schematic diagram of a memory card provided in an embodiment of this disclosure;

[0033] Figure 3 A schematic diagram of another memory card provided in an embodiment of this disclosure;

[0034] Figure 4 This is a schematic diagram of the structure of a memory 101 provided in an embodiment of the present disclosure;

[0035] Figure 5 This is a schematic diagram of the structure of a page buffer 10121 provided in an embodiment of the present disclosure;

[0036] Figure 6 This is a schematic diagram of a sensing latch circuit provided in an embodiment of the present disclosure;

[0037] Figure 7 A schematic diagram of an improved page buffer provided in an embodiment of this disclosure;

[0038] Figure 8 A diagram showing the change in potential of a sensing node during the sensing phase, provided as an embodiment of this disclosure;

[0039] Figure 9 A schematic diagram of another page buffer structure provided in an embodiment of this disclosure;

[0040] Figure 10 A diagram showing the change in the potential of a sensing node during a sensing process, provided as an embodiment of this disclosure;

[0041] Figure 11 An equivalent diagram of the potential of a sensing node in the first sub-stage of a calibration phase provided in an embodiment of this disclosure;

[0042] Figure 12 An equivalent diagram of the potential of a sensing node in the second sub-stage of a calibration phase provided in an embodiment of this disclosure;

[0043] Figure 13 This is a schematic diagram of the structure of a first node and a sensing node provided in an embodiment of the present disclosure;

[0044] Figure 14 An equivalent diagram of the potential of a first latch node in the sensing phase provided in an embodiment of this disclosure;

[0045] Figure 15 A timing diagram of control signals for a first transistor in a plurality of page buffers provided in an embodiment of this disclosure;

[0046] Figure 16 A flowchart illustrating a memory operation method provided in an embodiment of this disclosure. Detailed Implementation

[0047] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0048] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0050] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "multiple" means two or more. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0053] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0054] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0055] For ease of understanding, the memory system provided in the embodiments of this disclosure will be described below.

[0056] like Figure 1 As shown, Figure 1 This is a schematic diagram of an exemplary system S1 with a memory system 10 provided for embodiments of this disclosure. System S1 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. The memory system 10 includes a memory 101 and a memory controller 102. The memory system 10 can communicate with a host computer 20 through the memory controller 102, wherein the memory controller 102 can be coupled to the memory 101 via a memory channel 30. In some embodiments, the memory 101 in this disclosure may be a three-dimensional non-volatile memory, such as NAND flash memory, which may also be simply referred to as flash memory or NAND. When the memory 101 is NAND, the memory system 10 may also be referred to as a NAND memory system. Of course, the memory 101 in this disclosure may also be other types of memory. The memory system 10 may have more than one memory 101, and each memory 101 may be managed by the memory controller 102.

[0057] In some embodiments, the host computer 20 may be a processor of an electronic device, such as a central processing unit (CPU), a system-on-chip (SoC), or an application processor (AP). The host computer 20 may send data to be stored in the memory system 10, or read data stored in the memory system 10.

[0058] The memory controller 102 can process input / output (I / O) requests received from the host computer 20, ensure data integrity and effective storage, and also manage the memory 101. The memory channel 30 can provide data via the data bus and control the communication between the memory controller 102 and the memory 101.

[0059] Continue to refer to Figure 1 The memory 101 can be any part of a memory chip (package), memory die, or memory die, and can include multiple memory blocks 1011. The size of a memory block 1011 can be a megabyte (MB), and the memory block 1011 is the smallest unit for performing an erase operation. Each memory block 1011 can include multiple memory cells, where each memory cell can be addressed by means of bit lines (BL) and word lines (WL). Bit lines and word lines can be arranged vertically (e.g., in rows and columns, respectively), thus forming an array of metal lines. The orientation of the bit lines and word lines is... Figure 1 The blocks 1011 are designated as “BL” and “WL”, respectively. In this disclosure, one or more memory blocks 1011 may also be referred to as a “memory array” or “array”. A memory array is the core area in a memory device that performs storage functions.

[0060] Memory 101 also includes a peripheral circuitry region 1012. Peripheral circuitry region 1012 (also referred to as peripheral circuitry) contains a number of digital, analog, and / or mixed-signal circuits (e.g., page buffer / sensor amplifier 10121, row decoder / word line driver 10122, column decoder / bit line driver 10123, and peripheral control circuitry 10124) to support the functionality of memory 101. Peripheral control circuitry 10124 may include registers, active and / or passive semiconductor devices such as transistors, diodes, capacitors, or resistors, as will be apparent to those skilled in the art. Peripheral control circuitry 10124 of peripheral circuitry region 1012 can be configured to initiate programming operations on selected memory cells in the NAND flash memory string within memory block 1011. In some embodiments, the peripheral control circuit 10124 receives programming commands from the memory controller 102 via an interface, and in response, sends control signals to the row decoder / word line driver 10122, the column decoder / bit line driver 10123, and the voltage generator located in the peripheral circuit region 1012. Figure 1 (not shown in the image) to initiate programming operations on the selected memory cell.

[0061] Notice, Figure 1 The layout of the electronics in memory system 10 and memory 101 is shown as an example. Memory system 10 and memory 101 may have other layouts and may include additional devices. For example, memory 101 may also include a high-voltage charge pump, input / output circuitry, etc. Memory system 10 may also include firmware and a data scrambler, etc. In some embodiments, the peripheral circuitry region 1012 and the memory array may be formed independently on separate wafers and interconnected by wafer bonding.

[0062] The memory controller 102 and one or more memories 101 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package. That is, the memory system 10 can be implemented and packaged into different types of terminal electronic products. Figure 2In one example shown, the memory controller 102 and a single memory 101 can be integrated into the memory card 40. The memory card 40 may include Personal Computer Memory Card International Association (PCMCIA), compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital memory cards (SD cards), or UFS, etc. The memory card 40 may also include a memory card connector 41 that couples the memory card 40 to the host computer 20. Figure 3 In another example shown, the memory controller 102 and multiple memories 101 may be integrated into a solid-state drive (SSD) 50. The SSD 50 may also include an SSD connector 51 that couples the SSD 50 to the host computer 20.

[0063] like Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a memory 101 provided in an embodiment of the present disclosure. The memory 101 includes one or more memory blocks 1011. Each memory block 1011 includes a memory string 60. Each memory string 60 includes memory cells 601. Memory cells 601 sharing the same bit line form a memory string 60. The memory string 60 may also include at least one field-effect transistor (e.g., a metal-oxide-semiconductor field-effect transistor, MOSFET) at each end, which is controlled by a top select transistor and a bottom select transistor, respectively. The drain terminal of the top select transistor may be coupled to a bit line 80, and the source terminal of the bottom select transistor may be coupled to an array common source (ACS) 82. The ACS 82 may be shared by the memory strings 60 throughout the memory block 1011 and is also referred to as the source line (SL).

[0064] In some embodiments, the peripheral circuitry region 1012 of memory 101 may support GIDL-assisted erase operations. Memory block 1011 may be coupled to a row decoder / word line driver 10122 via word line 81, a top select transistor, and a bottom select transistor. Memory block 1011 may be coupled to a page buffer / sensor amplifier 10121 via bit line 80. The row decoder / word line driver 10122 may select one of the memory blocks 1011 on memory 101 in response to an X-path control signal provided by peripheral control circuitry 10124. The row decoder / word line driver 10122 may pass a voltage provided from voltage generator 90 to word line 81 according to the X-path control signal. During read and program operations, the row decoder / word line driver 10122 may pass a read voltage Vread and a programmable voltage Vpgm to the selected word line 81 according to the X-path control signal received from peripheral control circuitry 10124, and pass a voltage Vpass to the unselected word line.

[0065] The column decoder / bit line driver 10123 can transmit a ban voltage Vinhibit to the non-select line and connect the select line 80 to ground based on the Y-path control signal received from the peripheral control circuit 10124. That is, the column decoder / bit line driver 10123 can be configured to select or deselect one or more memory strings 60 according to the Y-path control signal from the peripheral control circuit 10124. The page buffer / sensor amplifier 10121 can be configured to read data from and program (write) data to the memory block 1011 according to the Y-path control signal from the peripheral control circuit 10124. For example, the page buffer / sensor amplifier 10121 can store a page of data to be programmed into a memory page. In another example, the page buffer / sensor amplifier 10121 can perform a verification operation to ensure that data has been correctly programmed into each memory cell 601. In yet another example, during a read operation, the page buffer / sensor amplifier 10121 can sense the current flowing through bit line 80 that reflects the logic state (i.e., data) of memory cell 601, as well as the amplification factor that amplifies small signals to measurable signals.

[0066] The input / output buffer 91 can transmit I / O data from / to the page buffer / sensor amplifier 10121, and transmit address ADDR signals or command CMD signals to the peripheral control circuitry 10124. In some embodiments, the input / output buffer 91 can serve as an interface between the memory controller 102 and the memory 101.

[0067] Peripheral control circuitry 10124 can control page buffer / sensor amplifier 10121 and row decoder / word line driver 10122 in response to command CMD transmitted from input / output buffer 91. During programming operations, peripheral control circuitry 10124 can control row decoder / word line driver 10122 and page buffer / sensor amplifier 10121 to program selected memory cell 601. During read operations, peripheral control circuitry 10124 can control row decoder / word line driver 10122 and page buffer / sensor amplifier 10121 to read selected memory cell 601. X-path control signals include row address X-ADDR, and Y-path control signals include column address Y-ADDR, which can be used to locate selected memory cell 601 in memory block 1011. Row address X-ADDR can include page index, block index, and face index to identify memory page and memory block 1011, respectively. Column address Y-ADDR can identify a byte or word in the data of a memory page.

[0068] In some implementations, the peripheral control circuitry 10124 may include one or more control logic units. Each control logic unit described herein may be a software module and / or firmware module running on a processor, such as a microcontroller unit (MCU) as part of the peripheral control circuitry 10124, or a hardware module of a finite-state machine (FSM), such as an integrated circuit (IC), such as an application-specific IC (ASIC), a field-programmable gate array (FPGA), or a combination of software modules, firmware modules, and hardware modules.

[0069] The voltage generator 90 can generate voltages for the word line 81 and the bit line 80 under the control of the external control circuit 10124. The voltages generated by the voltage generator 90 include the read voltage Vread, the programming voltage Vpgm, the pass voltage Vpass, and the inhibit voltage Vinhibit.

[0070] In some embodiments, the memory 101 may be formed based on floating gate technology. In some embodiments, the memory 101 may be formed based on charge trapping technology. The charge trapping-based memory 101 can provide high storage density and high intrinsic reliability. The stored data or logic state (e.g., the threshold voltage Vth of the memory cell 601) depends on the amount of charge trapped in the storage layer. In some embodiments, the memory 101 may be a three-dimensional (3D) memory device, wherein the memory cells 601 may be vertically stacked on top of each other.

[0071] In some embodiments, during an erase operation, a negative voltage difference is applied between the gate and source terminal (e.g., ACS82) of memory cell 601, allowing all trapped electron charges in the storage layer of memory cell 601 to be removed, and all memory cells 601 in the same storage block 1011 can be reset to the erase state ER as logic "1". For example, this voltage difference can be induced by setting the control gate in memory cell 601 to ground and applying a positive voltage to the source line 82. In this example, a voltage pulse can be applied to memory cell 601 during the erase operation.

[0072] Specifically, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a page buffer 10121 provided in an embodiment of the present disclosure. The page buffer 10121 may include a charging circuit, a sensing latch circuit, a reading circuit, and an input circuit. The first terminal of the charging circuit (e.g., ...) Figure 5 The connection terminal a) is coupled to the first terminal of the input circuit (e.g., ...). Figure 5 In the connection terminal b), the first terminal of the charging circuit is also coupled to the sensing node (SO), and the second terminal of the input circuit (such as...) Figure 5 The connection terminal c) is coupled to the bit line BL, and the first terminal of the input circuit is coupled to the first terminal of the read circuit (e.g., ...). Figure 5 The second terminal of the reading circuit (e.g., terminal d) is the connection terminal in the circuit. Figure 5 The connection terminal e) is grounded, and the second terminal of the charging circuit (such as...) Figure 5 The connection terminal f) is coupled to the first terminal of the sensing latch circuit (e.g., ...). Figure 5 The connection terminal g), the second terminal of the sensing latch circuit (such as...) Figure 6 The connection end h) is coupled to the sensing node.

[0073] The charging circuit is used to charge the sensing node, the input circuit is used to acquire the state of the memory cell connected to the bit line, the sensing latch circuit is used to store the state of the memory cell coupled to the bit line, and the reading circuit is used to read the state of the memory cell coupled to the bit line stored by the sensing latch circuit.

[0074] Specifically, the structural diagram of the sensing latch circuit is as follows: Figure 7As shown, the sensing latch circuit includes transistors 1, 2, 3, and 4, inverter 5, and inverter 6. The input of inverter 5 is coupled to the output of inverter 6, and the output of inverter 5 is coupled to the input of inverter 6. The coupling point between the input of inverter 5 and the output of inverter 6 is the first latch node (n_s), and the coupling point between the output of inverter 5 and the input of inverter 6 is the second latch node (d_s). The first latch node is coupled to the first terminal g of the sensing latch circuit, and the second latch node is coupled to the second terminal h of the sensing latch circuit. The first terminal of transistor 1 is coupled to the first latch node, and the second terminal of transistor 1 is coupled to the first terminal of transistor 2. The control terminal of transistor 1 is configured to receive a setting signal (SET_S). The second terminal of transistor 2 is grounded, and the control terminal of transistor 2 is configured to receive a reset signal (RST_SA_LATCH). The first terminal of transistor 2 is also coupled to the second terminal of transistor 3. The first terminal of transistor 3 is coupled to the second latch node, and the control terminal of transistor 3 is configured to receive a reset signal (RSET_S). The first terminal of transistor 4 is coupled to the second terminal of transistor 3, the second terminal of transistor 4 is grounded, and the control terminal of transistor 4 is configured to receive a sensing signal (MSO_S).

[0075] In addition to the sensing latch circuit, transistors are also present in the input circuit, charging circuit, and readout circuit. Due to manufacturing processes, each transistor has a different threshold voltage, which may cause voltage shifts. This could lead to different trip voltages during the sensing process, which in turn could affect edge summation (ESUM) losses.

[0076] Therefore, embodiments of this disclosure provide an improved page buffer 70, such as Figure 7 As shown, Figure 8 This is a schematic diagram of an improved page buffer provided in an embodiment of the present disclosure. The page buffer 70 includes a sense latch circuit 71, a first charging circuit 72, and a read calibration circuit 73. The first charging circuit 72 is coupled to a sense node, the first terminal of the read calibration circuit 73 is coupled to the sense latch circuit, and the second terminal of the read calibration circuit 73 is coupled to the sense node. The read calibration circuit 73 is configured to calibrate the potential of the sense node during sensing.

[0077] For example, the sensing latch circuit 71 can be configured to store the state of the memory cell coupled to the bit line, and the first charging circuit 72 can be configured to charge the sensing node.

[0078] The sensing process can include a sensing phase, and the potential change of the sensing node during the sensing phase is shown in the figure below. Figure 9As shown. The steps of the sensing phase may include: Initially, a first charging circuit 72 charges the sensing node, charging its potential to an initial voltage Vint, which may be less than or equal to the system voltage VDD. After the sensing node is charged, the first charging circuit 72 is turned off, and the sensing node begins to discharge, coupled to the bit line. After a period of time, the voltage of the sensing node drops to a stable level. At this point, if the voltage of the sensing node is higher than the transition voltage (Vtrp), the memory cell coupled to the bit line is determined to be in a programming state; if the voltage of the sensing node is lower than the transition voltage, the memory cell coupled to the bit line is determined to be in an erase state. The determination result is stored in the sensing latch circuit 71.

[0079] In addition, the sensing process may include a calibration phase, which is performed before the sensing phase, to calibrate the initial voltage Vint of the sensing node to eliminate voltage offsets in the page buffer 70 caused by the device process, thereby improving the reliability of the sensing results of the page buffer 70.

[0080] The following section describes the working process and related structural details of the page buffer 70 during the calibration phase.

[0081] Optional, such as Figure 9 As shown, Figure 10 This is a schematic diagram of another page buffer structure provided in an embodiment of this disclosure. The read calibration circuit 73 may include a first sub-circuit 731 and a second sub-circuit 732. The first sub-circuit 731 is configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-stage of the calibration phase. The second sub-circuit 732 is configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-stage of the calibration phase. That is, the first voltage value is greater than the second voltage value, and the third voltage value is greater than the second voltage value.

[0082] The potential change of the sensing node during the sensing process is as follows Figure 10 As shown, Figure 10 The horizontal axis represents time. Figure 10 The vertical axis represents the voltage of the sensing node. Different transistors manufactured using different processes have different threshold voltages; these different processes can include a first type of transistor, a second type of transistor, and a third type of transistor. Figure 9The diagram illustrates the potential changes of sensing nodes in page buffers including three different transistor types: a first type of transistor, a second type of transistor, and a third type of transistor. At the beginning of the first sub-stage of the calibration phase, the voltage of each sensing node is charged to a first voltage value, which can be an initial voltage Vint. During this first sub-stage, the sensing nodes are discharged from the first voltage value to a second voltage value. At this point, due to the different threshold voltages of transistors from different processes, the sensing nodes of page buffers including transistors from different processes exhibit three different second voltage values. In the second sub-stage of the calibration phase, the sensing nodes are charged from the second voltage value to a third voltage value. The voltage of the sensing nodes of each type of page buffer increases by the same voltage from the second voltage value, resulting in three different third voltage values. Then, the discharge process of the sensing phase begins. Therefore, the initial voltages of the sensing nodes of page buffers including transistors from different processes are different at the beginning of the sensing phase, calibrating the voltage offset in the page buffer and improving the reliability of the sensing results.

[0083] Optional, please continue reading Figure 11 The first sub-circuit 731 includes a first transistor 7311, a second transistor 7312, and a third transistor 7313. The first terminal of the first transistor 7311 is coupled to the first terminal of the read calibration circuit 73, and the second terminal of the first transistor 7311 is coupled to the first terminal of the third transistor. The first terminal of the second transistor 7312 is coupled to the first terminal of the first transistor 7311, and the second terminals of the second transistor 7312 and the third transistor 7313 are coupled to the second terminal of the read calibration circuit 73. The control terminal of the third transistor 7313 is grounded.

[0084] For example, the first transistor 7311, the second transistor 7312, and the third transistor 7313 can be N-type metal-oxide-semiconductor (NMOS). The first terminal of the first transistor 7311 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the first transistor 7311 is configured to receive a read enable signal (rd_en). The first terminal of the second transistor 7312 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the second transistor 7312 is configured to receive a page buffer configuration signal (pb_config). The first terminal of the third transistor 7313 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the third transistor 7313 is configured to receive a sense signal (MSO_S).

[0085] Taking the first transistor 7311 as an example, if rd_en is high, the first transistor 7311 is turned on. If rd_en is low, the first transistor 7311 is turned off. That is to say, for an NMOS transistor, it is turned on when the gate is high and turned off when the gate is low.

[0086] In the first sub-stage of the calibration phase, the first transistor 7311 and the second transistor 7312 are turned on, and the third transistor 7313 is turned off.

[0087] like Figure 11 As shown, Figure 12 This is an equivalent diagram of the potential of a sensing node in the first sub-stage of a calibration phase provided in this embodiment. If pb_config is high, the second transistor 7312 is turned on, and the potential of its drain is the same as the potential of the sensing node. If rd_en is high, the first transistor 7311 is turned on, and the potential of the drain of the third transistor 7313 is the same as the potential of the sensing node. At this time, the potentials of both the drain and gate of the third transistor 7313 are the same as the potential of the sensing node. Therefore, the third transistor 7313 forms a diode connection, and the sensing node discharges through the third transistor 7313, with the voltage of the sensing node discharging from a first voltage value to a second voltage value. Since different third transistors 7313 have different threshold voltages, the second voltage value after discharging through different third transistors 7313 is different. It can also be understood that the threshold voltage information of the third transistor 7313 can be recorded through the second voltage value of the sensing node.

[0088] In the second sub-stage of the calibration phase, the first transistor 7311 and the third transistor 7313 are turned off, and the second transistor 7312 is turned on.

[0089] like Figure 12 As shown, Figure 13 This is an equivalent diagram of the potential of the sensing node in the second sub-stage of the calibration phase provided in an embodiment of this disclosure. If pb_config is high, the second transistor 7312 is turned on, and the potential of the drain of the second transistor 7312 is the same as the potential of the sensing node. If rd_en is low, the first transistor 7311 is turned off, and the sensing node stops discharging.

[0090] In addition, the output of the sensing latch circuit 71 can be regarded as the second node. If the second transistor 7312 is turned on, the sensing node and the second node are turned on, which can increase the capacitance of the sensing node, thereby improving the accuracy of the sensing node in the sensing stage and improving the reliability of the sensing results.

[0091] Optionally, the second sub-circuit 732 includes a capacitor 7321 and a second charging circuit 7322. A first terminal of the capacitor 7321 is coupled to a sensing node, and a second terminal of the capacitor 7321 is coupled to a first node. The first node is also coupled to the output terminal of the second charging circuit 7322. The second charging circuit 7322 is configured to charge the first node in a second sub-stage of the calibration phase, whereby the sensing node is charged from a second voltage value to a third voltage value.

[0092] For example, capacitor 7321 has the characteristic that its capacitance and potential difference do not change abruptly. If the voltage value at one end of capacitor 7321 is changed, the voltage value at the other end of capacitor 7321 will also change at the instant of the voltage change, but the total potential difference between the two ends of capacitor 7321 will not change. Therefore, if the second charging circuit 7322 charges the first node, assuming the voltage value of the first node increases by 3V, that is, the voltage value at the second end of capacitor 7321 increases by 3V, based on the fact that the total potential difference remains unchanged, the voltage value at the first end of capacitor 7321 also increases by 3V, that is, the voltage value of the sensing node also increases by 3V.

[0093] Therefore, in the second sub-stage of the calibration phase, the first transistor 7311 and the third transistor 7313 are turned off, and the second transistor 7312 is turned on, at which point the sensing node stops discharging. The second charging circuit 7322 charges the first node; for example, the first node can be charged to the system voltage VDD, and the sensing node is coupled up from the second voltage value to the third voltage value, wherein the difference between the third voltage value and the second voltage value can be the system voltage value.

[0094] Optionally, capacitor 7321 is a parasitic capacitance.

[0095] For example, the first node can be a node adjacent to the sensing node in the page buffer 70. No capacitor is designed between the first node and the sensing node, but parasitic capacitance exists between them due to circuit board routing. In one example, such as... Figure 9 As shown, the first node can be a node in a low voltage threshold latch (LVT Latch) circuit, where the low voltage threshold latch circuit can be used to store the number of failure bits. This allows the parasitic capacitive coupling between the first node and the sensing node to raise the voltage of the sensing node, ensuring a sufficient initial voltage value for subsequent sensing stages.

[0096] In another example, the voltage of the gate of the second transistor 7312 can be increased, thereby increasing the parasitic capacitance between the gate and source of the second transistor 7312, which can also achieve the function of coupling to raise the voltage of the sensing node.

[0097] Optional, please continue reading Figure 9 The sensing latch circuit 71 includes a first inverter 711, a second inverter 712, a fourth transistor 713, a fifth transistor 714, and a sixth transistor 715. The first terminal of the first inverter 711 is coupled to the first terminal of the second inverter 712, and the second terminal of the first inverter 711 is coupled to the second terminal of the second inverter 712. The first terminal of the fourth transistor 713 is coupled to the first terminal of the first inverter 711, and the second terminal of the fourth transistor 713 is coupled to the first terminal of the sixth transistor 715, with the second terminal of the sixth transistor 715 grounded. The first terminal of the fifth transistor 714 is coupled to the second terminal of the second inverter 712, and the second terminal of the fifth transistor 714 is coupled to the first terminal of the sensing latch circuit 71.

[0098] For example, the fourth transistor 713, the fifth transistor 714, and the sixth transistor 715 can be NMOS transistors. The first terminal of the fourth transistor 713 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the fourth transistor 713 is configured to receive a set signal (SET_S). The first terminal of the fifth transistor 714 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the fifth transistor 714 is configured to receive a reset signal (RSET_S). The first terminal of the sixth transistor 715 is the drain, the second terminal is the source, and the control terminal is the gate, wherein the control terminal of the sixth transistor 715 is configured to receive a sense signal (MSO_S).

[0099] Optional, please continue readingFigure 14 The page buffer 70 also includes an input circuit 74, with a first end coupled to a bit line and a second end coupled to a sensing node.

[0100] The input circuit 74 may include a seventh transistor 741, an eighth transistor 742, a ninth transistor 743, and a tenth transistor 744. All of these transistors are NMOS transistors. The drain of the seventh transistor 741 is coupled to the bit line, and its source is coupled to the drain of the ninth transistor 743. The drain of the eighth transistor 742 is coupled to the drain of the seventh transistor 741, and its source is grounded. The drain of the ninth transistor 743 is coupled to the sensing node, and it is also coupled to the drain of the tenth transistor 744. The source of the tenth transistor 744 is coupled to the first charging circuit 72.

[0101] Optionally, the first charging circuit 72 may include an eleventh transistor 721, a twelfth transistor 722, a thirteenth transistor 723, a fourteenth transistor 724, and a fifteenth transistor 725. The eleventh transistor 721, twelfth transistor 722, and thirteenth transistor 723 are PMOS transistors, and the fourteenth transistor 724 and fifteenth transistor 725 are NMOS transistors. The drain of the eleventh transistor 721 is coupled to the system voltage source, the source of the eleventh transistor 721 is coupled to the drain of the thirteenth transistor 723, and the gate of the eleventh transistor 721 is coupled to the first latch node (n_s). The drain of the twelfth transistor 722 is coupled to the system voltage source, and the source of the twelfth transistor 722 is coupled to the drain of the thirteenth transistor 723. The drain of the thirteenth transistor 723 is also coupled to the source of the tenth transistor 744, and the source of the thirteenth transistor 723 is coupled to the sensing node. The drain of the fourteenth transistor 724 is coupled to the drain of the tenth transistor 744, the source of the fourteenth transistor 724 is coupled to the drain of the fifteenth transistor 725, the source of the fifteenth transistor 725 is grounded, and the gate of the fifteenth transistor 725 is coupled to the first latch node (n_s).

[0102] During the sensing phase, the first transistor 7311 is turned on and the second transistor 7312 is turned off.

[0103] like Figure 14 As shown, Figure 15This is an equivalent diagram of the potential of the first latch node during the sensing phase, provided in an embodiment of this disclosure. During the sensing phase, pb_config is low, meaning the second transistor 7312 is off, and rd_en is high, meaning the first transistor 7311 is on. At this time, SET_S is also high, meaning the fourth transistor 713 is on. Specifically, during the sensing phase, assuming the potential of the first latch node is high, if the potential of the sensing node after discharge is still high, then the potential of the first latch node remains high, and the sensing latch circuit 71 stores data "1", where "1" indicates that the state of the sensed memory cell is in the programming state. If the potential of the sensing node after discharge is low, then the third transistor 7313 is on, the potential of the first latch node is pulled low, and the sensing latch circuit 71 stores data "0", where "0" indicates that the state of the sensed memory cell is in the erase state.

[0104] Additionally, the read calibration circuit 73 can also read the state of the memory cells coupled to the bit lines stored in the sense latch circuit 71. Specifically, with the first transistor 7311 and the fourth transistor 713 turned on and the second transistor 7312 turned off, assuming the sensing node is low, if the first latch node is high, then the third transistor 7313 is turned on. At this time, the potential of the first latch node is pulled low, that is, the state of the sense latch circuit 71 flips, and the state of the memory cells stored in the sense latch circuit 71 is the programming state. If the first latch node is low, then the third transistor 7313 is turned off. At this time, the potential of the first latch node is still low, that is, the state of the sense latch circuit 71 does not flip, and the state of the memory cells stored in the sense latch circuit 71 is the erase state.

[0105] Additionally, the memory may include multiple bit lines, each coupled to a page buffer. To avoid excessive instantaneous current caused by simultaneous operations, the control signals for the transistors in the page buffer are often started in a staggered manner. For the improved page buffer provided in the embodiments of this disclosure, such as... Figure 16 As shown, only the control signal (rd_en) of the second transistor 7312 needs to be interleaved. For example, the high level of rd_en1 is later than the high level of rd_en0, the high level of rd_en2 is later than the high level of rd_en1, and the high level of rd_en3 is later than the high level of rd_en2. Furthermore, the signals of other transistors (e.g., SET_S) can be activated simultaneously, thereby reducing the complexity of timing control.

[0106] Applied to the page buffer mentioned above, the operation method of the memory provided in the embodiments of this disclosure is described below, such as... Figure 16 As shown, ​A flowchart illustrating a memory operation method provided in this disclosure embodiment. The method includes the following steps.

[0107] S1601. In the first sub-stage of the calibration phase, the page buffer discharges the sensing node from a first voltage value to a second voltage value.

[0108] S1602. In the second sub-stage of the calibration phase, the page buffer charges the sensing node from the second voltage value to the third voltage value.

[0109] S1603, The page buffer stores the state of the bit-line-coupled memory cell during the sensing phase.

[0110] For example, the sensing process may include a calibration phase and a sensing phase, wherein the calibration phase is performed before the sensing phase. In the first sub-phase of the calibration phase, the first and second transistors are turned on, and the third transistor is turned off. This allows the sensing node to discharge through the third transistor. Since different third transistors have different threshold voltages, the second voltage value after discharge is also different, effectively recording the information of different threshold voltages through the second voltage value. In the second sub-phase of the calibration phase, the first and third transistors are turned off, and the second transistor is turned on. This allows the sensing node to be charged through the second sub-circuit to ensure a sufficient initial voltage value for the subsequent sensing phase. Thus, throughout the calibration phase, different threshold voltages are calibrated, eliminating voltage offset in the page buffer and improving the reliability of the page buffer sensing results. Furthermore, the specific implementation of S1601 to S1603 can be found in the above description of the reading calibration circuit, and will not be repeated here.

[0111] Optionally, S1602 may include: in the second sub-stage of the calibration phase, the page buffer applies a first voltage to the control terminal of the second transistor of the read calibration circuit.

[0112] For example, by applying a first voltage to the control terminal of the second transistor in the readout calibration circuit, the parasitic capacitance between the gate and source of the second transistor can be increased, thereby coupling up the voltage of the sensing node.

[0113] Optionally, S1602 may include: in the second sub-stage of the calibration phase, the page buffer charges the first node.

[0114] For example, there is a parasitic capacitance between the first node and the sensing node, and charging the first node can couple and raise the voltage of the sensing node.

[0115] Optionally, the method further includes: prior to the first sub-stage of the calibration phase, the page buffer charges the sensing node to a first voltage value. For example, the page buffer can charge the sensing node to the first voltage value via a first charging circuit.

[0116] Optionally, the method further includes: the page buffer acquiring the state of the memory cell coupled to the bit line during the sensing phase. For example, the page buffer may acquire the state of the memory cell coupled to the bit line via input circuitry.

[0117] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0118] Electronic devices may include the memory system described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0119] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A memory, comprising: The memory comprises a page buffer, the page buffer comprises: a sensing latch circuit; a first charging circuit coupled to a sensing node; a read calibration circuit, a first end of the read calibration circuit is coupled to the sensing latch circuit, a second end of the read calibration circuit is coupled to the sensing node, configured to calibrate a potential of the sensing node during a sensing process; the sensing process comprises a calibration phase, the read calibration circuit comprises a first sub-circuit and a second sub-circuit, the first sub-circuit is configured to discharge the sensing node from a first voltage value to a second voltage value in a first sub-phase of the calibration phase, the second sub-circuit is configured to charge the sensing node from the second voltage value to a third voltage value in a second sub-phase of the calibration phase.

2. The memory of claim 1, wherein, the first sub-circuit comprises a first transistor, a second transistor and a third transistor; a first end of the first transistor is coupled to the first end of the read calibration circuit, a second end of the first transistor is coupled to a first end of the third transistor, a first end of the second transistor is coupled to the first end of the first transistor, a second end of the second transistor and a second end of the third transistor are coupled and coupled to the second end of the read calibration circuit, a control end of the third transistor is grounded.

3. The memory of claim 2, wherein, in the first sub-phase of the calibration phase, the first transistor and the second transistor are turned on, and the third transistor is turned off; in the second sub-phase of the calibration phase, the first transistor and the third transistor are turned off, and the second transistor is turned on.

4. The memory of claim 2, wherein, the sensing process further comprises a sensing phase; in the sensing phase, the first transistor is turned on and the second transistor is turned off.

5. The memory of claim 1, wherein, the second sub-circuit comprises a capacitor and a second charging circuit, a first end of the capacitor is coupled to the sensing node, a second end of the capacitor is coupled to a first node, the first node is also coupled to an output end of the second charging circuit, the second charging circuit is configured to charge the first node in the second sub-phase of the calibration phase, and the sensing node is charged from the second voltage value to the third voltage value.

6. The memory of claim 5, wherein, the capacitor is a parasitic capacitor.

7. The memory of claim 1, wherein, the sensing latch circuit comprises a first inverter and a second inverter, a fourth transistor, a fifth transistor and a sixth transistor; a first end of the first inverter is coupled to a first end of the second inverter, a second end of the first inverter is coupled to a second end of the second inverter, a first end of the fourth transistor is coupled to the first end of the first inverter, a second end of the fourth transistor is coupled to a first end of the sixth transistor, a second end of the sixth transistor is grounded, a first end of the fifth transistor is coupled to the second end of the second inverter, and a second end of the fifth transistor is coupled to a first end of the sensing latch circuit.

8. The memory of claim 1, wherein, the page buffer further comprises an input circuit, a first end of the input circuit is coupled to a bit line, and a second end of the input circuit is coupled to the sensing node.

9. A method of operating a memory, the method comprising: the method comprises: In a first sub-phase of the calibration phase, discharging the sensing node from a first voltage value to a second voltage value; In a second sub-phase of the calibration phase, charging the sensing node from the second voltage value to a third voltage value; In a sensing phase, storing a state of a memory cell coupled to the bit line.

10. The method of claim 9, wherein, The charging the sensing node from the second voltage value to a third voltage value in the second sub-phase of the calibration phase comprises: In the second sub-phase of the calibration phase, applying a first voltage to a control terminal of a second transistor of a read calibration circuit.

11. The method of claim 9, wherein, The charging the sensing node from the second voltage value to a third voltage value in the second sub-phase of the calibration phase comprises: In the second sub-phase of the calibration phase, charging a first node.

12. The method of claim 9, wherein, The method further comprises: Before the first sub-phase of the calibration phase, charging the sensing node to the first voltage value.

13. The method of claim 9, wherein, The method further comprises: In the sensing phase, obtaining a state of a memory cell coupled to the bit line.

14. A memory system, comprising: Comprising: one or more memories as claimed in any of claims 1 to 8; a memory controller coupled to the memory and configured to control the memory.

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