Parallel read-write method of memory based on memory blocks

Abstract

The invention provides a parallel read-write method of a memory based on storage blocks, and belongs to the field of integrated circuits. The parallel read-write method comprises the following steps: a write command sending step: sending a write-in row address to the memory bank through the address bus, and locking the write-in row address in the pre-decoder after the memory bank receives the write-in row address; a writing step: writing data into the storage library; a reading command sending step: sequentially sending reading row addresses to the plurality of storage banks through the address bus, sending one reading row address every other burst time, and locking the reading row addresses in the pre-decoder after the storage banks receive the reading row addresses; and a reading step: reading the data from the plurality of storage libraries in sequence. Through the parallel read-write method of the memory based on the memory blocks, the data read-write rate of the memory can be improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a parallel reading and writing method of a memory based on a storage block. Background Art

[0002] In the existing DDR4 SDRAM (Double Data Rate 4 Synchronous Dynamic Random Access Memory), when performing a read operation, a RAS (Row Address Strobe) command is first issued to activate the WL (Word Line) associated with the RAS, and all SAs (Sense Amplifiers) connected to the WL are activated. Usually, there are 1K (1000) SAs for each data I / O (input and output interface). Then, after tRCD (RAS-to-CAS Delay, RAS to CAS delay), a CAS (Column Address Strobe) command is issued, and all SAs latch the read data. The CAS command pre-fetches 8-bit burst data and transfers it to the secondary SA, which drives the read data bus to send the read data to the data I / O. The write operation is similar to the read operation, and the time for the read operation and the write operation in SDRAM is also the same.

[0003] In recent years, emerging memories such as PCM (Phase Change Memory) have emerged. The storage cell structure of PCM is completely different from that of SDRAM, and its read and write mechanism is more complicated. In particular, the write operation, the operation of writing "1" and the operation of writing "0" require two currents with different pulse widths and shapes, usually called "set" pulses and "reset" pulses. In terms of timing, the set pulse takes longer than the reset pulse, so the time of the write operation is determined by the time of the set pulse. Generally speaking, the time of the set pulse is much longer than the time of the read operation. Therefore, unlike SDRAM, the read and write data rates of PCM are very asymmetric, and the write data rate is much lower than the read data rate. Usually, the write data rate is only 1 / 4 to 1 / 6 of the read data rate. Summary of the invention

[0004] The present invention aims to provide a parallel reading and writing method for a memory based on a storage block, which can improve the data reading and writing rate.

[0005] The parallel reading and writing method of a memory based on a memory block of the present invention comprises: providing the memory block-based memory bank interleaving mode memory, comprising: a plurality of memory bank groups arranged in a vertical direction, a horizontal spacing area is arranged between the memory bank groups, a plurality of data input and output interfaces arranged in a horizontal direction are arranged in the horizontal spacing area, a vertical spacing area is arranged in the middle of the memory bank group in a horizontal direction, an address bus extending in a vertical direction is arranged in the vertical spacing area; the memory bank group comprises a plurality of memory banks arranged in a vertical direction, each of the memory banks comprises: a plurality of memory block groups arranged in a horizontal direction, a pre-decoder arranged in the vertical spacing area, the pre-decoder is electrically connected to the plurality of memory block groups via a pre-decoder line extending in a horizontal direction, the pre-decoder line is electrically connected to the address bus, the memory block group of each memory bank is electrically connected to the corresponding memory block group of other memory banks via a global data bus extending in a vertical direction and the corresponding data input and output interface; The storage block group includes a plurality of storage blocks, the plurality of storage blocks are electrically connected to a local data bus and the pre-decoder line respectively, the local data bus is electrically connected to the global data bus; the storage block includes: a row decoder, a column decoder, and a plurality of storage sub-blocks, the number of storage sub-blocks in each storage block is equal to half of the burst length; the storage sub-block includes: a storage array, a first DC sense amplifier electrically connected to the storage array, a second DC sense amplifier, a first write head and a second write head, a first data latch electrically connected to the first DC sense amplifier, the first write head and the local data bus respectively, and a second data latch electrically connected to the second DC sense amplifier, the second write head and the local data bus respectively; the first DC sense amplifier, the first write head and the first data latch are arranged at the top of the storage array, and the second DC sense amplifier, the second write head and the second data latch are arranged at the bottom of the storage array.

[0006] A write command sending step: sending a write row address to the storage library through the address bus, and the storage library locks the write row address in the pre-decoder after receiving the write row address; a write step: writing data to the storage library; a read command sending step: sending a read row address to a plurality of the storage libraries in sequence through the address bus, sending one read row address every burst time, and the storage library locks the read row address in the pre-decoder after receiving the read row address; a read step: reading data from a plurality of the storage libraries in sequence.

[0007] The data reading and writing rate of the memory can be improved by the parallel reading and writing method of the memory based on the storage block of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic block diagram of a memory of the present invention.

[0009] Figure 2 is a schematic block diagram of a storage repository of the memory of the present invention.

[0010] Figure 3 It is a schematic block diagram of a storage block group of the memory of the present invention.

[0011] Figure 4 It is a schematic block diagram of a storage block and a storage sub-block of the memory of the present invention.

[0012] Figure 5 It is a flow chart of the parallel reading and writing method of the memory of the present invention.

[0013] Figure 6 It is a flow chart of the writing steps of the parallel reading and writing method of the memory of the present invention.

[0014] Figure 7 It is a timing diagram of the parallel reading and writing method of the memory of the present invention.

[0015] Figure 8 It is a flow chart of the reading steps of the parallel reading and writing method of the memory of the present invention.

[0016] Explanation of symbols

[0017] 10 storage blocks

[0018] 11 Storage sub-blocks

[0019] 12 First DC SA

[0020] 13 First WH

[0021] 14First data latch

[0022] 15 Storage Array

[0023] 22nd DC SA

[0024] 23 Second WH

[0025] 24 Second data latch

[0026] 30 Pre-decoder

[0027] 100 storage block groups

[0028] 101 Local Data Bus

[0029] 102 pre-decoder line

[0030] 103 Global Data Bus

[0031] 104 Address bus

[0032] 200 data I / O

[0033] 300 Repositories

[0034] 301 vertical partition

[0035] 302 horizontal spacer

[0036] 400 Repository Group DETAILED DESCRIPTION

[0037] The memory and data reading and writing method thereof of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 is a schematic block diagram of the memory of the present invention. Figure 1 As shown, the memory of the present invention includes: a plurality of memory bank groups 400 arranged in a vertical direction, a horizontal spacing area 302 is arranged between the memory bank groups 400, a plurality of data I / Os 200 arranged in a horizontal direction are arranged in the horizontal spacing area 302, a vertical spacing area 301 is arranged in the middle of the memory bank group 400 in the horizontal direction, and an address bus 104 extending in the vertical direction is arranged in the vertical spacing area 301.

[0038] The memory in this embodiment is PCM, but the present invention is not limited thereto. In other embodiments, it may be other emerging memories. The memory in this embodiment is a memory of the class x16 SDRAM DDR4, so it includes two memory bank groups 400, 16 data I / Os 200 are arranged in the horizontal spacing area 302, and 8 data I / Os 200 are arranged on both sides of the vertical spacing area 301. However, the present invention is not limited thereto. In other embodiments, the number of memory bank groups 400 and data I / Os 200 may also be other values. In addition, a chip pad is also arranged in the horizontal spacing area 302.

[0039] Figure 2 Schematic diagram of the storage library of the present invention. Figure 1 and Figure 2 As shown, the memory bank group 400 includes a plurality of memory banks 300 arranged in a vertical direction, each memory bank 300 includes: a plurality of memory block groups 100 arranged in a horizontal direction, a predecoder 30 arranged in a vertical spacing area 301, the predecoder 30 is electrically connected to the plurality of memory block groups 100 via a predecoder line 102 extending in a horizontal direction, the predecoder line 102 is electrically connected to an address bus 104, and the memory block group 100 of each memory bank 300 is electrically connected to the corresponding memory block group 100 of other memory banks 300 via a global data bus 103 extending in a vertical direction and a corresponding data I / O 200.

[0040] In this embodiment, each memory bank group 400 includes 4 memory banks 300, so the entire memory has a total of 8 memory banks 300. Each memory bank 300 includes 16 memory block groups 100, and 8 memory block groups 100 are respectively arranged on both sides of the vertical spacing area 301. These 16 memory block groups 100 are electrically connected to a corresponding data I / O 200 through a global data bus 103, so there are a total of 16 global data buses 103. The corresponding memory block groups 100 in the 8 memory banks 300 share a global data bus 103, so 8 memory block groups 100 share a global data bus 103. In this embodiment, the global data bus 103 is universal for reading and writing, but the present invention is not limited to this. In other embodiments, it can also be a separate read bus and write bus. Each memory bank 300 includes 2 pre-decoders 30, and these 2 pre-decoders 30 are electrically connected to the 16 memory block groups 100 in the memory bank 300 through a pre-decoder line 102.

[0041] Figure 3 Schematic block diagram of the storage block group of the present invention. Figure 3 As shown, the storage block group 100 includes a plurality of storage blocks 10, and the plurality of storage blocks 10 are electrically connected to a local data bus 101 and a pre-decoder line 102, respectively, and the local data bus 101 is electrically connected to a global data bus 103. In this embodiment, each storage block group 100 includes 8 storage blocks 10. However, the present invention is not limited thereto, and in other embodiments, the number of storage blocks 10 may also be other values.

[0042] Figure 4 Schematic block diagram of a memory block and a memory sub-block of the memory of the present invention. Figure 4 As shown, the storage block 10 includes: a row decoder, a column decoder, and a plurality of storage sub-blocks 11. The number of storage sub-blocks 11 in each storage block 10 is equal to half of the burst length. The memory of this embodiment adopts a DDR4-like mode, and the burst length is 8, so each storage block 10 of the memory of this embodiment includes 4 storage sub-blocks 11.

[0043] The storage sub-block 11 includes: a storage array 15, a first direct current SA 12 and a second direct current SA 22 electrically connected to the storage array 15, a first WH (write head) 13 and a second WH 23, a first data latch 14 electrically connected to the first direct current SA 12, the first WH 13 and a local data bus 101, and a second data latch 14 electrically connected to the second direct current SA 12, the second WH 13 and the local data bus 101.

[0044] The first direct current SA 12 , the first WH 13 and the first data latch 14 are disposed at the top of the memory array 15 , and the second direct current SA 22 , the second WH 23 and the second data latch 24 are disposed at the bottom of the memory array 15 .

[0045] Because the first direct current SA 12 and the second direct current SA 22 are both relatively large, if they are both arranged at the top of the storage array 15 or at the bottom of the storage array 15, it will take up more space and increase the size of the entire storage. Therefore, the first direct current SA 12 and the second direct current SA 22 are arranged alternately, which can save space and reduce the size of the entire storage.

[0046] Specifically, the memory block 10 further includes: a plurality of WLs, a plurality of first BLs (Bit Lines), a plurality of second BLs, a control circuit and a timing circuit.

[0047] The memory cells of each row in the memory array 15 are electrically connected to a WL, and the memory cells of each column are electrically connected to a first BL or a second BL. The row decoder is electrically connected to the plurality of WLs, and is used to select the WL according to the row address transmitted from the pre-decoder line 102. The column decoder is electrically connected to the plurality of first BLs and the plurality of second BLs, and is used to select the first BL or the second BL according to the column address transmitted from the pre-decoder line 102. The memory cell to be read or the memory cell to be written is selected according to the selected WL and the first BL or the second BL.

[0048] The number of BLs in each storage sub-block 11 depends on the density of the memory chip, which is in the mega (Mb) level or the giga (Gb) level. Usually, there are 64 to 512 first BLs and 64 to 512 second BLs in each storage sub-block 11. These first BLs share one first direct current SA 12 and one first WH 13, and these second BLs share one second direct current SA 12 and one second WH 13.

[0049] The parallel reading and writing method of the present invention is described below. Figure 5 is a flow chart of the parallel reading and writing method of the memory of the present invention, such as Figure 5 As shown, the data parallel reading and writing method of the present invention includes:

[0050] Write command sending step S100 : sending a write row address to the memory bank 300 via the address bus 104 . After receiving the write row address, the memory bank 300 latches the write row address in the pre-decoder 30 .

[0051] In this embodiment, the write row address 1 is sent to the first memory bank group 400 (ie, Figure 1 The first repository 300 (i.e., Figure 1 The topmost memory bank 300, referred to herein as memory bank 300A), latches the write row address in the pre-decoder 30 of the memory bank 300A.

[0052] Writing step S200: writing data into the storage library 300 .

[0053] Read command sending step S300 : sending read row addresses to multiple memory banks 300 in sequence through the address bus 104 , sending one read row address every burst time, and after receiving the read row address, the memory bank 300 latches the read row address in the pre-decoder 30 .

[0054] In this embodiment, after the write row address 1 is issued, after a burst time (5 ns in this embodiment), the read row address 1 is sent to the memory bank 300A through the address bus 104, and the read row address 1 is latched in the pre-decoder 30 of the memory bank 300A. After the read row address 1 is issued, after 5 ns, the read row address 2 is sent to the second memory bank 300 (referred to as the memory bank 300B) through the address bus 104, and the read row address 2 is latched in the pre-decoder 30 of the memory bank 300B. After the read row address 2 is issued, after 5 ns, the read row address 3 is sent to the third memory bank 300 (referred to as the memory bank 300C) through the address bus 104, and the read row address 3 is latched in the pre-decoder 30 of the memory bank 300C. After the read row address 3 is issued, after 5 ns, the read row address 4 is sent to the fourth memory bank 300 (referred to as the memory bank 300D) through the address bus 104, and the read row address 4 is latched in the pre-decoder 30 of the memory bank 300D. After the read row address 4 is sent, after 5 ns, the read row address 5 is sent to the memory bank 300A through the address bus 104, and the read row address 5 is latched in the pre-decoder 30 of the memory bank 300A. And so on. In this embodiment, a total of 16 read row addresses are sent, and after the read row address 16 is sent, after a specific time, the write row address 2 is sent.

[0055] Reading step S400: reading data from a plurality of storage libraries 300 in sequence.

[0056] Figure 6 1 is a flow chart of the writing steps of the parallel reading and writing method of the memory of the present invention. Figure 6 As shown, preferably, the writing step S200 includes:

[0057] Address latching step S201: After the write row address is sent, after a specific time, the write column address is sent to the memory bank 300 through the address bus 104. After receiving the write column address, the memory bank 300 latches the write column address in the pre-decoder 30, and then transmits the write row address and the write column address to the corresponding storage block 10 of the memory bank 300 through the pre-decoder line 102. The storage block 10 latches the write row address in the row decoder and latches the write column address in the column decoder, and then the storage block 10 disconnects from the pre-decoder line 102.

[0058] In this embodiment, after the write row address is issued, after 5 ns, the write column address is sent to the memory bank 300A through the address bus 104, and the write column address is latched in the pre-decoder 30 of the memory bank 300A. Then, the write row address and the write column address are transmitted to the memory block 10 corresponding to the write row address and the write column address of the memory bank 300A through the pre-decoder line 102, and the memory block 10 latches the write row address in the row decoder and latches the write column address in the column decoder, and then the memory block 10 is disconnected from the pre-decoder line 102.

[0059] The present invention adopts RAS / CAS address multiplexing, because the write operation can only be performed after the row address and the column address are latched in the storage block 10, so the write operation can be performed after the CAS. That is, RAS determines a row address, and then CAS determines a column address, and then the write operation is performed. Since nothing happens between RAS and CAS, its tRCD does not need to be as long as SDRAM, and only 1-2 clock cycles are needed. This will speed up the reading speed. In this embodiment, tRCD is 5ns.

[0060] Transmission step S202 : the data I / O 200 transmits the write data to the storage block 10 via the global data bus 103 and the local data bus 101 .

[0061] Data writing step S203: select the storage unit to be written according to the write row address and the write column address, then latch the write data transmitted from the local data bus 101 in the corresponding first data latch 14 or the second data latch 24, and finally write the write data into the selected multiple storage units through the corresponding first write head 13 or the second write head 23.

[0062] In this embodiment, the row decoder selects a WL of the storage block 10 according to the write row address, and the column decoder selects 4 first BLs and 4 second BLs of the storage block 10 according to the write column address, thereby selecting 8 storage cells to be written, and then the 8 write data transmitted from the local data bus 101 are respectively latched in the 4 first data latches 14 and the 4 second data latches 24 corresponding to the selected 8 storage cells, and finally the 8 write data are written into the selected 8 storage cells through the corresponding 4 first WHs 13 and 4 second WHs 23.

[0063] Standby step S204: the storage block 10 reconnects the pre-decoder line 102 and enters the standby state.

[0064] Figure 7 : is a timing diagram of the parallel read and write method of the memory of the present invention. For simplification, Figure 7 Only the column address is shown, and the row address is not shown. Figure 7 As shown, after the write column address 1 is issued, after a specific time CWL (CAS Write Latency, write CAS latency), the data I / O 200 sends 8 write data to the storage block 10 through the global data bus 103 and the local data bus 101, and then the storage block 10 starts the data writing step S203 (referred to as writing 1 herein). The duration of the data writing step S203 is called the writing cycle Tw. In this embodiment, the writing cycle Tw is 100ns.

[0065] Figure 8 1 is a flow chart of the reading steps of the parallel reading and writing method of the memory of the present invention. Figure 8 As shown, preferably, the reading step S400 includes:

[0066] Address latching step S401: After the read row address is sent, after a specific time, the read column address is sent to the memory bank 300 through the address bus 104. After receiving the read column address, the memory bank 300 latches the read column address in the pre-decoder 30, and then transmits the read row address and the read column address to the corresponding storage block 10 of the memory bank 300 through the pre-decoder line 102. The storage block 10 latches the read row address in the row decoder and latches the read column address in the column decoder, and then the storage block 10 disconnects from the pre-decoder line 102.

[0067] In this embodiment, after the read row address 1 is issued, after 5 ns, the read column address 1 is sent to the memory bank 300A through the address bus 104, and the read column address 1 is latched in the pre-decoder 30 of the memory bank 300A. Then, the read row address 1 and the read column address 1 are transmitted to the memory block 10 corresponding to the read row address 1 and the read column address 1 of the memory bank 300A through the pre-decoder line 102, and the memory block 10 latches the read row address 1 in the row decoder and latches the read column address 1 in the column decoder, and then the memory block 10 is disconnected from the pre-decoder line 102.

[0068] Data reading step S402: The storage unit to be read is selected according to the read row address and the read column address, and the corresponding first DC SA 12 or second DC SA 22 reads the read data stored in the selected storage unit, and latches the read data in the corresponding first data latch 14 or second data latch 24, and then sends the read data to the local data bus 101.

[0069] In this embodiment, the row decoder selects a WL of the storage block 10 according to the read row address, such as Figure 4 The column decoder selects the 4 first BLs and 4 second BLs of the storage block 10 according to the read column address, as shown in FIG. Figure 4 As shown by the vertical dotted line in . Because the memory of this embodiment adopts a DDR4-like mode, there are 4 first BLs and 4 second BLs in this embodiment. However, the present invention is not limited to this, and in other embodiments, it can also be other numbers. In this way, 8 storage cells can be selected on the selected WL. Then the 4 first DC SAs 12 and 4 second DC SAs 22 corresponding to these 8 storage cells read the data stored in these 8 storage cells, and latch the read 8 data in the corresponding 4 first data latches 14 and 4 second data latches 24 respectively, and then send these 8 data to the local data bus 101.

[0070] Standby step S403: the memory block 10 reconnects to the pre-decoder line 102 and enters a standby state, waiting for the pre-decoder line 102 to transmit the next row address and column address.

[0071] Transmission step S404: 8 read data are transmitted to the data I / O 200 via the local data bus 101 and the global data bus 103. Because the memory of this embodiment adopts a DDR4-like mode, and the global data bus 103 of the DDR4 mode is just 8 bits wide, it can just transmit these 8 read data.

[0072] like Figure 7As shown, in this embodiment, after the write column address 1 is issued, after 5ns, the read column address 1 is issued, and after a delay for a period of time, it reaches a storage block 10 in the memory bank 300A (referred to as storage block 10A herein), and then the data of the relevant storage unit of the storage block 10A is read (i.e., read 1). After the read column address 1 is issued, after 5ns, the read column address 2 is issued, after a delay for a period of time, the read column address 2 reaches a storage block 10 in another memory bank 300 (referred to as storage block 10B herein), and then the data of the relevant storage unit of the storage block 10B is read (i.e., read 2). After the read column address 2 is issued, after 5ns, the read column address 3 is issued, after a delay for a period of time, the read column address 3 reaches a storage block 10 in another memory bank 300 (referred to as storage block 10C herein), and then the data of the relevant storage unit of the storage block 10C is read (i.e., read 3). After the read column address 3 is issued, after 5 ns, the read column address 4 is issued. After a delay, the read column address 4 reaches a storage block 10 (herein referred to as storage block 10D) in another memory bank 300, and then the data of the relevant storage unit of the storage block 10D is read (i.e., read 4). After the read column address 4 is issued, after 5 ns, the read column address 5 is issued. After a delay, the read column address 5 reaches the storage block 10A, and then the data of the relevant storage unit of the storage block 10A is read (i.e., read 5). And so on. In this embodiment, there are 16 read column addresses in total.

[0073] After the read column address 16 is issued, after a period of time, the write column address 2 is issued, and after a period of delay, the write column address 2 reaches another storage block 10. After the write column address 2 is issued, after 5ns, the read column address 17 is issued, and after a period of delay, the read column address 17 reaches the storage block 10A, and then the data of the relevant storage unit of the storage block 10A is read. After the read column address 17 is issued, after 5ns, the read column address 18 is issued, and after a period of delay, the read column address 18 reaches the storage block 10B, and then the data of the relevant storage unit of the storage block 10B is read. And so on.

[0074] In this embodiment, the reading cycle Tr (i.e., the duration of the data reading step S402) is 10 ns. Figure 7 It can be seen that before reading 1 is completed, the read column address 2 has reached the storage block 10B, and then reading 2 begins. However, the operation of the storage block 10B will not affect the storage block 10A, because each storage block 10 is independent. At this time, the storage block 10A has also disconnected from the pre-decoder line 102, so it will not receive the column address again until the storage block 10A completes the data reading step.

[0075] A read row address is sent every other burst time (5ns), that is, the sending time of read row address 2 is 5ns later than that of read row address 1. Thus, the sending time of read column address 2 is also 5ns later than that of read column address 1. The time when read column address 2 arrives at storage block 10B is also 5ns later than that when read column address 1 arrives at storage block 10A. Figure 7 As shown, after the read column address 1 reaches the storage block 10A, after a read cycle Tr, the storage block 10A completes the data reading step and sends the read data to the local data bus 101. After a period of delay, the read data reaches the data I / O 200. That is, after the read column address 1 is issued, after CL (CAS Latency), the read data is transmitted to the data I / O 200. After the burst time (5ns), the read data transmitted from the storage block 10B arrives at the data I / O 200. After another 5ns, the read data transmitted from the storage block 10C arrives at the data I / O 200. And so on. In this way, 16 seamless continuous bursts are realized, plus the previous burst of write data, a total of 17, each burst is 5ns, a total of 85ns. Therefore, in a write cycle Tw of 100ns, there is 85ns of time for data transmission on the data I / O 200. In this way, the read / write rate can reach 85% of the maximum rate, that is, 3200*85%=2720MB / s, which is much higher than the 640MB / s of the prior art. Therefore, the data parallel read / write method of the present invention can greatly improve the read / write rate of the memory.

[0076] Because the read and write operations of each storage block 10 are independent and self-consistent, the read operation during the write operation can be to read any storage block 10 in any storage library 300. Even if the storage block 10 being read and written is the same, it is also possible. In the write operation, the write data will be latched in the first data latch 14 or the second data latch 24. In addition, because most random access memories are read-intensive, that is, the number of reads is more than the number of writes, during a write operation, more than 10 read operations often occur. Therefore, in practical applications, it is most likely to perform 16 read operations in parallel during each write operation.

[0077] When the read operation of the storage bank 300A is completed, the storage block 10A of the storage bank 300A becomes a standby state, and the row address and column address latched in the row decoder and column decoder of the storage block 10A are released. However, the row address latched in the pre-decoder 30 of the storage bank 300A is still valid. Therefore, if the next address transmitted to the storage bank 300A is a different column address on the same row, the storage bank 300A can directly read the data of these columns without re-latching the row address. If it is a different row address, the storage bank 300A first replaces the previously latched row address with a new row address, and then reads.

[0078] This means that, in the present invention, a series of commands in SDRAM DDR can be performed without a precharge command, for example, row activation of a memory bank 300, precharge, and activation of another row of the same memory bank 300. That is, the present invention implements a memory bank interleaving pattern that is exactly the same as that of SDRAM DDR without the selected WL remaining activated. In the present invention, the selected row address remains activated in the predecoder 30, and the memory block 10 is not precharged until the CAS, and the WL of the memory block 10 is activated. When the memory bank 300 is activated, the memory block 10 does not activate many SAs, and the memory block 10 is in a standby state when it is not read, so that the power consumption is very low.

[0079] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any professional and technical personnel in the field may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.

Claims

1. A parallel reading and writing method for a memory based on a storage block, characterized in that: include: The memory based on the storage block is provided, comprising: A plurality of memory bank groups (400) arranged in a vertical direction, a horizontal spacing area (302) being arranged between the memory bank groups (400), a plurality of data input / output interfaces (200) arranged in a horizontal direction being arranged in the horizontal spacing area (302), a vertical spacing area (301) being arranged in the middle of the memory bank groups (400) in a horizontal direction, and an address bus (104) extending in a vertical direction being arranged in the vertical spacing area (301); The memory bank group (400) comprises a plurality of memory banks (300) arranged in a vertical direction, each of the memory banks (300) comprising: a plurality of memory block groups (100) arranged in a horizontal direction, a predecoder (30) arranged in the vertical spacing area (301), the predecoder (30) being electrically connected to the plurality of memory block groups (100) via a predecoder line (102) extending in a horizontal direction, the predecoder line (102) being electrically connected to the address bus (104), the memory block group (100) of each memory bank (300) being electrically connected to the corresponding memory block group (100) of other memory banks (300) via a global data bus (103) extending in a vertical direction and the corresponding data input / output interface (200); The storage block group (100) comprises a plurality of storage blocks (10), the plurality of storage blocks (10) are electrically connected to a local data bus (101) and the pre-decoder line (102) respectively, and the local data bus (101) is electrically connected to the global data bus (103); The storage block (10) comprises: a row decoder, a column decoder, and a plurality of storage sub-blocks (11), wherein the number of storage sub-blocks (11) in each storage block (10) is equal to half of the burst length; The storage sub-block (11) comprises: a storage array (15), a first DC sense amplifier (12) electrically connected to the storage array (15), a second DC sense amplifier (22), a first write head (13) and a second write head (23), a first data latch (14) electrically connected to the first DC sense amplifier (12), the first write head (13) and the local data bus (101), respectively, and a second data latch (24) electrically connected to the second DC sense amplifier (22), the second write head (23) and the local data bus (101), respectively; The first DC sense amplifier (12), the first write head (13) and the first data latch (14) are arranged at the top of the storage array (15), and the second DC sense amplifier (22), the second write head (23) and the second data latch (24) are arranged at the bottom of the storage array (15); Write command sending step S100: sending a write row address to the memory bank (300) via the address bus (104); after receiving the write row address, the memory bank (300) locks the write row address in the pre-decoder (30); Writing step S200: writing data into the storage library (300); Read command sending step S300: sending a read row address to a plurality of memory banks (300) in sequence through the address bus (104), sending one read row address every other burst time, and after receiving the read row address, the memory bank (300) locks the read row address in the pre-decoder (30); Reading step S400: reading data from the plurality of storage libraries (300) in sequence.

2. The parallel reading and writing method of a memory based on a storage block according to claim 1, characterized in that: The writing step S200 includes: Address latching step S201: after the write row address is sent, after a specific time, the write column address is sent to the memory bank (300) through the address bus (104); after the memory bank (300) receives the write column address, it latches the write column address in the pre-decoder (30), and then transmits the write row address and the write column address to the corresponding memory block (10) of the memory bank (300) through the pre-decoder line (102); the memory block (10) latches the write row address in the row decoder and latches the write column address in the column decoder, and then the memory block (10) is disconnected from the pre-decoder line (102); Transmission step S202: the data input / output interface (200) transmits the write data to the storage block (10) via the global data bus (103) and the local data bus (101); Data writing step S203: selecting the storage unit to be written according to the write row address and the write column address, then latching the write data transmitted by the local data bus (101) in the corresponding first data latch (14) or the second data latch (24), and finally writing the write data into the selected multiple storage units through the corresponding first write head (13) or the second write head (23); Standby step S204: the storage block (10) reconnects to the pre-decoder line (102) and enters a standby state.

3. The data parallel reading and writing method based on the storage block of claim 1 is characterized in that: The reading step S400 includes: Address latching step S401: after the read row address is sent, after a specific time, the read column address is sent to the memory bank (300) through the address bus (104); after the memory bank (300) receives the read column address, the read column address is latched in the pre-decoder (30); and then the read row address and the read column address are transmitted to the corresponding memory block (10) of the memory bank (300) through the pre-decoder line (102); the memory block (10) latches the read row address in the row decoder and latches the read column address in the column decoder; and then the memory block (10) is disconnected from the pre-decoder line (102); Data reading step S402: selecting the storage unit to be read according to the read row address and the read column address, the corresponding first DC sensing amplifier (12) or the second DC sensing amplifier (22) reading the read data stored in the selected storage unit, latching the read data in the corresponding first data latch (14) or the second data latch (24), and then sending the read data to the local data bus (101); Standby step S403: the storage block (10) reconnects to the pre-decoder line (102) and enters a standby state; Transmission step S404: transmitting the read data to the data input-output interface (200) via the local data bus (101) and the global data bus (103).

4. The parallel reading and writing method of a memory based on a storage block according to claim 1, characterized in that: The storage block (10) further comprises: a plurality of word lines, a plurality of first bit lines, a plurality of second bit lines, a control circuit and a timing circuit. The memory cells in each row of the memory array (15) are electrically connected to one of the word lines, and the memory cells in each column are electrically connected to one of the first bit lines or one of the second bit lines; The first bit line and the second bit line are arranged at intervals, the first bit line is electrically connected to the first DC sensing amplifier (12) and the first write head (13), and the second bit line is electrically connected to the second DC sensing amplifier (22) and the second write head (23); The row decoder is electrically connected to the plurality of word lines and is used to select the word line according to the row address transmitted from the pre-decoder line (102); The column decoder is electrically connected to the plurality of first bit lines and the plurality of second bit lines, and is used to select the first bit line or the second bit line according to the column address transmitted by the pre-decoder line (102); The memory cell to be read or the memory cell to be written is selected according to the selected word line and the first bit line or the second bit line.

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