Flash memory controller, operation method of flash memory controller and storage device

Abstract

The invention relates to a flash memory controller, an operation method of the flash memory controller and a storage device. The flash memory controller comprises an error correction code circuit. The error correction code circuit is used for performing a word line dimension error correction code operation on specific data from a host to generate word line dimension check code data and performing a finger sub-block dimension error correction code operation on the specific data to generate finger sub-block dimension check code data. The specific data is to be stored in the flash memory module to form a super block, the super block is composed of a plurality of finger-shaped sub-blocks in the vertical direction and a plurality of super word lines in the horizontal direction, and when a data error occurs in the super block, the super word lines are stored in the super block. The word line dimension check code data and the finger-shaped sub-block dimension check code data are used for correcting data errors in the super block to obtain the specific data.

Description

Technical Field

[0001] The present invention relates to a flash memory data management mechanism, and more particularly to a flash memory controller, an operating method of the flash memory controller and a storage device. Background Art

[0002] Generally speaking, a conventional flash memory controller generates a corresponding check code when executing data writing, so that when a write failure, a word line break, or a word line short circuit occurs, the corresponding check code can be used to perform a certain degree of error correction. However, the error correction capability of a conventional flash memory controller is limited and cannot effectively correct errors occurring in a data unit within a three-dimensional block, resulting in a higher error rate in data reading. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to provide a flash memory control, a flash memory control operation method and a corresponding storage device to solve the above-mentioned problem.

[0004] According to an embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is used to couple between a host and a flash memory module and includes a specific buffer and an error correction code circuit. The specific buffer is used to receive and buffer a specific data from the host, and the specific data will be stored in the flash memory module to form a super block, and the super block is composed of a plurality of finger sub-blocks in the vertical direction and a plurality of super word lines in the horizontal direction. The error correction code circuit is coupled to the specific buffer and is used to perform a word line dimension error correction code operation on the specific data to generate a word line dimension check code data and to perform a finger sub-block dimension error correction code operation on the specific data to generate a finger sub-block dimension check code data. When a data error occurs in the super block, the word line dimension check code data and the finger sub-block dimension check code data are used to correct the data error in the super block to obtain the specific data.

[0005] According to an embodiment of the present invention, a storage device is also disclosed. The storage device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of channels, each channel includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks on a plurality of planes. The flash memory controller is coupled to the flash memory module and includes a specific buffer and an error correction code circuit. The specific buffer is used to receive and buffer a specific data from a host, and the specific data is to be stored in the flash memory module to form a super block, and the super block is composed of a plurality of finger sub-blocks in the vertical direction and a plurality of super word lines in the horizontal direction. The error correction code circuit is coupled to the specific buffer and is used to perform a word line dimension error correction code operation on the specific data to generate a word line dimension check code data and to perform a finger sub-block dimension error correction code operation on the specific data to generate a finger sub-block dimension check code data. When a data error occurs in the super block, the word line dimension check code data and the finger sub-block dimension check code data are used to correct the data error in the super block to obtain the specific data.

[0006] According to an embodiment of the present invention, an operating method of a flash memory controller is disclosed. The flash memory controller is coupled between a host and a flash memory module, and the operating method includes: providing a specific buffer for receiving and buffering a specific data from the host, the specific data to be stored in the flash memory module to form a super block, the super block is composed of a plurality of finger sub-blocks in a vertical direction and a plurality of super word lines in a horizontal direction; providing an error correction code circuit for performing a word line dimension error correction code operation on the specific data to generate a word line dimension check code data and performing a finger sub-block dimension error correction code operation on the specific data to generate a finger sub-block dimension check code data; and when a data error occurs in the super block, using the word line dimension check code data and the finger sub-block dimension check code data to correct the data error in the super block to obtain the specific data.

[0007] According to an embodiment of the present invention, a flash memory controller is disclosed, which is coupled between a host and a flash memory module, and includes a specific buffer and an error correction code circuit. The specific buffer is used to receive and buffer a specific data from the host, and the specific data will be stored in the flash memory module to form a super block, and the super block is composed of a plurality of finger sub-blocks in the vertical direction and a plurality of word lines in the horizontal direction. The error correction code circuit, coupled to the specific buffer, includes a word line dimension check code buffer and a finger sub-block dimension check code buffer. The word line dimension check code buffer includes a plurality of groups of word line dimension sub-buffers, each group of word line dimension sub-buffers includes a plurality of sub-buffers; the finger sub-block dimension check code buffer includes a plurality of finger sub-block dimension sub-buffers. The ECC circuit performs a word line dimension ECC operation on the specific data by using the word line dimension ECC buffer to generate a word line dimension ECC data and performs a finger sub-block dimension ECC operation on the specific data and a result of the word line dimension ECC operation by using the finger sub-block dimension ECC buffer to generate a finger sub-block dimension ECC data. When a data error occurs in the super block, the word line dimension ECC data and the finger sub-block dimension ECC data are used to correct the data error in the super block to obtain the specific data.

[0008] According to an embodiment of the present invention, an operation method of a flash memory controller is disclosed. The flash memory controller is used to couple between a host and a flash memory module. The operation method includes: providing a specific buffer to receive and buffer a specific data from the host. The specific data will be stored in the flash memory module to form a super block. The super block is composed of a plurality of finger sub-blocks in a vertical direction and a plurality of word lines in a horizontal direction; providing an error correction code circuit. The error correction code circuit includes: a word line dimension check code buffer, including a plurality of groups of word line dimension sub-buffers, each group of word line dimension sub-buffers including a plurality of sub-buffers ; and a finger sub-block dimension check code buffer, comprising a plurality of finger sub-block dimension sub-buffers; performing a word line dimension error correction code operation on the specific data by using the word line dimension check code buffer to generate a word line dimension check code data and performing a finger sub-block dimension error correction code operation on the specific data and a calculation result of the word line dimension error correction code operation by using the finger sub-block dimension check code buffer to generate a finger sub-block dimension check code data; and, when a data error occurs in the super block, using the word line dimension check code data and the finger sub-block dimension check code data to correct the data error in the super block to obtain the specific data.

[0009] According to an embodiment of the present invention, a storage device is also disclosed. The storage device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of channels, each channel includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks on a plurality of planes. The flash memory controller is coupled to the flash memory module and includes a specific buffer and an error correction code circuit. The specific buffer is used to receive and buffer a specific data from the host, and the specific data will be stored in the flash memory module to form a super block, and the super block is composed of a plurality of finger sub-blocks in the vertical direction and a plurality of word lines in the horizontal direction. The error correction code circuit, coupled to the specific buffer, includes a word line dimension check code buffer and a finger sub-block dimension check code buffer. The word line dimension check code buffer includes a plurality of groups of word line dimension sub-buffers, and each group of word line dimension sub-buffers includes a plurality of sub-buffers; the finger sub-block dimension check code buffer includes a plurality of finger sub-block dimension sub-buffers. The ECC circuit performs a word line dimension ECC operation on the specific data by using the word line dimension ECC buffer to generate a word line dimension ECC data and performs a finger sub-block dimension ECC operation on the specific data and a result of the word line dimension ECC operation by using the finger sub-block dimension ECC buffer to generate a finger sub-block dimension ECC data. When a data error occurs in the super block, the word line dimension ECC data and the finger sub-block dimension ECC data are used to correct the data error in the super block to obtain the specific data.

[0010] According to an embodiment of the present invention, a flash memory controller is disclosed. The flash memory controller is coupled between a host and a flash memory module and includes an error correction code circuit. The error correction code circuit is used to perform a data read operation on a specific data of a super block in the flash memory module, the super block is composed of a plurality of finger sub-blocks in a vertical direction and a plurality of word lines in a horizontal direction. When performing the data read operation, the error correction code circuit performs a finger sub-block dimension error correction code operation on the data of the plurality of finger sub-blocks in a first word line of the super block to correct errors occurring in the vertical direction of the first word line, and the error correction code circuit performs a word line dimension error correction code operation on the data of the plurality of word lines in a first finger sub-block of the super block to correct errors occurring in the horizontal direction of the first finger sub-block.

[0011] According to an embodiment of the present invention, an operating method of a flash memory controller is disclosed. The flash memory controller is used to couple between a host and a flash memory module, and the operating method includes: providing and using an error correction code circuit to perform a data read operation using specific data of a super block in the flash memory module, the super block being composed of a plurality of finger sub-blocks in a vertical direction and a plurality of word lines in a horizontal direction; performing a finger sub-block dimension error correction code operation on the data of the plurality of finger sub-blocks in a first word line of the super block during the data read operation to correct errors occurring in the vertical direction of the first word line; and performing a word line dimension error correction code operation on the data of the plurality of word lines in a first finger sub-block of the super block to correct errors occurring in the horizontal direction of the first finger sub-block.

[0012] According to an embodiment of the present invention, a storage device is disclosed. The storage device includes a flash memory module and a flash memory controller. The flash memory module includes a plurality of channels, each channel includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks on a plurality of planes. The flash memory controller is used to couple between a host and the flash memory module and includes an error correction code circuit. The error correction code circuit is used to perform a data read operation on a specific data of a super block in the flash memory module, the super block is composed of a plurality of finger sub-blocks in a vertical direction and a plurality of word lines in a horizontal direction. When performing the data read operation, the error correction code circuit performs a finger sub-block dimension error correction code operation on the data of the plurality of finger sub-blocks in a first word line of the super block to correct errors occurring in the vertical direction of the first word line, and the error correction code circuit performs a word line dimension error correction code operation on the data of the plurality of word lines in a first finger sub-block of the super block to correct errors occurring in the horizontal direction of the first finger sub-block. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a schematic diagram of a storage device such as a flash memory device according to an embodiment of the present invention.

[0014] Figure 2 FIG. 4 is a schematic structural diagram of a three-dimensional physical block of a flash memory module according to an embodiment of the present invention.

[0015] Figure 3 FIG. 4 is a schematic diagram of an example of a physical block and a super block performing a word line dimension data protection operation of a flash memory module according to an embodiment of the present invention.

[0016] Figure 4The diagram is a schematic diagram of a physical block and a super block of a flash memory module that performs word line dimension data protection and can simultaneously perform finger sub-block dimension protection operations on data of a finger sub-block according to an embodiment of the present invention.

[0017] Figure 5 It is a schematic diagram of a physical block and a super block of a flash memory module according to another embodiment of the present invention that performs word line dimension data protection and can simultaneously perform finger sub-block dimension protection operations on data of two finger sub-blocks.

[0018] Figure 6 It is a schematic diagram of a super block of a flash memory module that performs word line dimension data protection and can simultaneously perform finger sub-block dimension protection operations on data of two finger sub-blocks according to another embodiment of the present invention.

[0019] Figure 7 FIG. 4 is a schematic diagram of an error correction code circuit according to an embodiment of the present invention.

[0020] Figure 8 1 is a schematic diagram of an example of a super block in which a flash memory controller adopts an SLC write mode to write data to a flash memory module and performs data protection operations in word line dimensions and finger sub-block dimensions according to an embodiment of the present invention.

[0021] Fig. 9 FIG. 4 is a schematic diagram of a portion of a specific exemplary operation of an error correction code circuit operating in an SLC mode according to an embodiment of the present invention.

[0022] Fig.10 FIG. 4 is a schematic diagram of another part of a specific exemplary operation of an error correction code circuit operating in an SLC mode according to an embodiment of the present invention.

[0023] Fig.11 FIG. 4 is a schematic diagram of another part of a specific exemplary operation of an error correction code circuit operating in an SLC mode according to an embodiment of the present invention.

[0024] Fig.12 FIG. 4 is a schematic diagram of another part of a specific exemplary operation of an error correction code circuit operating in an SLC mode according to an embodiment of the present invention.

[0025] Fig.13 FIG. 4 is a schematic diagram of another part of a specific exemplary operation of an error correction code circuit operating in an SLC mode according to an embodiment of the present invention.

[0026] Fig.14 According to an embodiment of the present invention Figure 7FIG. 1 is a schematic diagram of an ECC protection operation performed by an ECC circuit on a super word line WL0 in a QLC mode.

[0027] Fig.15 FIG. 4 is a schematic diagram of an ECC circuit performing an ECC protection operation on a super word line WL1 in a QLC mode according to an embodiment of the present invention.

[0028] Fig.16 FIG. 4 is a schematic diagram of an ECC circuit performing an ECC protection operation on a super word line WL2 in a QLC mode according to an embodiment of the present invention.

[0029] Fig.17 2 is a schematic diagram of an ECC circuit performing an ECC protection operation on even-numbered super word lines such as WL0 and WL2 in a QLC mode to generate data of a merged partial word line dimension check code R0 according to an embodiment of the present invention.

[0030] Fig.18 1 is a schematic diagram of the change in the data amount of the merged partial word line dimension check code R0 recorded in the shared buffer when the error correction code circuit sequentially merges the data of the partial word line dimension check code R0 of multiple even-numbered super word lines and multiple odd-numbered super word lines in the QLC mode according to an embodiment of the present invention.

[0031] Fig.19 1 is a flow chart of an error correction operation / process performed by an error correction code circuit according to an embodiment of the present invention when reading data.

[0032]

Explanation of symbols

[0033] 100: Storage device

[0034] 101: Host

[0035] 110: Flash memory module

[0036] 1051: Shared Buffer

[0037] 1052: Error correction code circuit

[0038] 1055A: First dimension check code buffer

[0039] 1055B: Second dimension check code buffer

[0040] 1101: Block

[0041] 1102: Chip

[0042] 1056_0~1056_15,1057_0,1057_1: sub-buffer DETAILED DESCRIPTION

[0043] The present invention aims to provide a distributed error correction code protection mechanism for a fault-tolerant RAID (Redundant Array of Independent Disks) that performs two different dimensional check codes for the storage of flash memory data, an encoding circuit and operation that implements the distributed error correction code protection mechanism while minimizing circuit cost, and a decoding circuit (i.e., an error correction circuit) and operation for correcting errors when reading flash memory data. The mechanism of the present invention can effectively correct errors and significantly reduce the bit error rate during data storage. Specifically, the present invention uses a specific encoding (such as an encoding operation of exclusive-OR (XOR) operation, but not limited to) and error correction of a wordline dimension parity code to correct errors in a super wordline or two adjacent super wordlines, and uses the same specific encoding and error correction of a finger subblock dimension parity code to correct errors in a finger subblock or two adjacent finger subblocks, wherein the encoding and error correction of the wordline dimension parity code can be regarded as protecting data in the horizontal direction of a storage block, and the encoding and error correction of the finger subblock dimension parity code can be regarded as protecting data in the vertical direction of a storage block, and the related operations will be described in subsequent sections. Due to the distributed and two different dimensional error correction code protection mechanism, the present invention can correct data errors more effectively and significantly reduce the bit error rate. It should be noted that the embodiments of the present invention can also use other encoding types of parity code encoding operations, not limited to exclusive-OR operations.

[0044] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a storage device 100 according to an embodiment of the present invention, for example, a flash memory device. The flash memory device 100 is externally coupled to a host 101 and includes a flash memory module 110 and a flash memory controller 105. The flash memory module 110 is a flash memory module with a three-dimensional planar structure; however, this is not a limitation of the present case.

[0045] The flash memory controller 105 includes a specific data buffer 1051 such as a time sharing buffer (TSB), hereinafter referred to as the shared buffer 1051 . In addition, the flash memory controller 105 includes an ECC circuit 1052. The ECC circuit 1052 has a coding function and a decoding function (i.e., an error correction operation). The ECC circuit 1052 includes a first dimension check code buffer 1055A and a second dimension check code buffer 1055B. The ECC circuit 1052 uses the first dimension check code buffer 1055A to encode and temporarily store the check code of the XOR operation in the word line dimension, and uses the second dimension check code buffer 1055B to encode and temporarily store the check code of the XOR operation in the finger sub-block dimension. The flash memory controller 105 will write the data and the corresponding check codes of different dimensions into different data units (e.g., a page unit, or a data page or a storage page) stored in different channels, different chips, and different storage planes in the flash memory module 110 based on the distributed ECC protection mechanism of the fault-tolerant disk array method. The error correction code circuit 1052 is used to perform an error correction code decoding operation when the flash memory controller 105 reads data from the flash memory module 110 to adaptively correct part of the data errors or bit errors, and then the flash memory controller 105 transmits, for example, the corrected data to the host 101. Equivalently, the flash memory module 110 includes a plurality of channels, each channel includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks on a plurality of planes.

[0046] The flash memory module 110 includes a plurality of flash memory chips 1102. Each flash memory chip 1102 includes a plurality of physical storage blocks 1101. A physical storage block 1101 can be used as a single-level cell (SLC) block or a multi-level cell block. Each cell of the single-level cell block can store 2 bits of data, and each cell of the multi-level cell block can store 2 bits of data. N 1 bit of data, N is greater than or equal to 2 and is an integer. A multi-level cell data block, for example, a cell including an MLC block (multi-level cell block) can store 2 2 The data of the TLC block (triple-level cellblock) can store 2 3 The unit of QLC block (quad-level cell block) can store 2 4bit data, and so on. In addition, it should be noted that, in one embodiment, when the amount of data stored is less than a specific amount of data, a physical block of the flash memory module 110 is used as an SLC data block, and the flash memory controller 105 writes data in the physical block in the SLC write mode, and when the amount of data stored is greater than the specific amount of data, the physical block of the flash memory module 110 is used as an MLC, TLC or QLC data block, and the flash memory controller 105 writes data in the MLC, TLC or QLC write mode; in other words, a data page of a physical block (or a super block) includes a single data page size in the single-layer cell write mode, includes 2 sub-data page sizes in the 2-layer cell write mode, includes 3 sub-data page sizes in the 3-layer cell write mode, and includes 4 sub-data page sizes in the 4-layer cell write mode.

[0047] In one embodiment, in order to improve the efficiency of data writing and reduce the error rate, the flash memory module 110 includes multiple channels (two channels in the embodiment of the present case, but not limited to this). When one channel executes the writing of a certain data page, another channel can be used to execute the writing of another data page without waiting for the channel. Each channel has its own sequencer in the flash memory controller 105 and includes multiple flash memory chips (two chips in the embodiment of the present case, but not limited to this). Therefore, one channel can execute the writing of different data pages to multiple flash memory chips at the same time without waiting for one of the chips. In addition, each flash memory chip can have a folded design and have two different storage planes. When writing data, one flash memory chip can use two data blocks on two different planes to execute the writing of different data pages at the same time without waiting for one of the data blocks. In addition, the flash memory controller 105 can be connected to the flash memory module 110 through multiple channels, so that different channels can be used to write data to different flash memory chips 1102 at the same time, thereby increasing writing efficiency. The flash memory controller 105 will write and store the checksums for data protection of two different dimensions into different data units of different channels, different chips and different storage planes in a distributed manner of a fault-tolerant disk array.

[0048] Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a 3D physical block of a flash memory module 110 according to an embodiment of the present invention. Figure 2As shown, the three-dimensional physical block has a plurality of wordline layers formed by stacking a plurality of wordline layers on a horizontal XY plane, which can be used to store the data size of a wordline layer (hereinafter referred to as a wordline), and has a plurality of bitlines on a vertical Z axis, wherein data of a finger structure on different wordline layers and corresponding to the same bitline is a sub-block, hereinafter referred to as a finger sub-block, which can be used to store the data size of a finger sub-block.

[0049] The technical solution provided by the present invention is to use a wordline dimension check code to protect data on a wordline and / or two adjacent wordlines to properly correct data bit errors occurring on the one or two adjacent wordlines, such as data errors that may be caused by one wordline open or two wordlines short, and to use a finger sub-block dimension check code to protect data on a finger sub-block and / or two adjacent finger sub-blocks in a wordline to properly correct data bit errors occurring on a finger sub-block and / or two adjacent finger sub-blocks in the wordline, such as bit errors occurring on the one finger structure and / or two finger structures mentioned above.

[0050] In addition, it should be noted that in order to implement the distributed error correction code protection mechanism of the fault-tolerant disk array, one of the storage blocks (or blocks) in this case is a super block. A super block is a super block, wherein the data units of the super block are formed by data units of physical blocks with the same block index number on multiple different channels, different flash memory chips, and different storage planes, for example, a super block B_N includes data units of 16 physical blocks, for example, formed by data units of physical blocks with the same block index number N on 2 different channels, 2 different flash memory chips, and 4 different storage planes; in addition, a word line of the super block is a super word line, and the data units of the super word line are formed by data units of physical word lines with the same word line index number in physical blocks with the same block index number on multiple different channels, different flash memory chips, and different storage planes, for example, the data units of the Mth super word line of a super block B_N are formed by data units of the Mth physical word line in multiple physical blocks with the same block index number N on 2 different channels, 2 different flash memory chips, and 4 different storage planes. In addition, the data units of the super word line can be divided into data units formed by multiple super finger sub-blocks. The data units of a super finger sub-block of the super word line are formed by data units of physical finger sub-blocks with the same finger sub-block index number in physical word lines with the same word line index number in physical blocks with the same block index number on multiple different channels, different flash memory chips, and different storage planes. For example, the data units of the Kth super finger sub-block of the Mth super word line of a super block B_N are formed by data units of the Kth finger sub-block in the Mth physical word line in multiple physical blocks with the same block index number N on 2 different channels, 2 different flash memory chips, and 4 different storage planes. It should be noted that the number of channels, the number of flash memory chips, and the number of storage planes mentioned above are not limitations of the present invention.

[0051] Figure 3 FIG. 1 is a schematic diagram of an example of a physical block and a super block performing a word line dimension data protection operation of a flash memory module 110 according to an embodiment of the present invention. Figure 3Part (a) shows a simplified example of a physical block. In the SLC write mode, a 3D physical block includes and can store (Z+1) word lines, each word line includes FN (e.g., 4, but not limited) finger sub-blocks, and the 3D physical block includes (Z+1)×FN data units, wherein each data unit is, for example, a data page unit size, such as 16KB (but not limited). That is to say, for example, from the perspective of word line WL0, the word line WL0 can store, for example, 4 data units, which correspond to and are located on 4 finger sub-blocks SB0, SB1, SB2, and SB3, respectively, and from the perspective of each finger sub-block, for example, SB0, the finger sub-block SB0 can store (Z+1) data units, which correspond to and are located on (Z+1) word lines WL0 to WLZ, respectively. In the SLC write mode, a data unit includes a data page size of, for example, 16KB, and in the MLC write mode, a data unit is a data page size including 2 sub-data pages, for example, 32KB, in the TLC write mode, a data unit is a data page size including 3 sub-data pages, for example, 48KB, and in the QLC write mode, a data unit is a data page size including 4 sub-data pages, for example, 64KB, and so on.

[0052] Figure 3 Part (b) shows a simplified example of a super block. For example, in the SLC write mode (but not limited to), a super block is formed by 16 three-dimensional physical blocks (but not limited to), and these three-dimensional physical blocks correspond to 2 different channels CH0 and CH1, 2 different flash memory chips CE0 and CE, and 4 different storage planes PL0 to PL3. Therefore, in this embodiment, a super block can store and include 16×(Z+1)×FN data units. Figure 3As shown in part (b) of the present invention, in order to avoid data bit errors caused by an open circuit of one word line and / or a short circuit of two word lines, the flash memory controller 105 of the present invention, for example, performs an XOR operation on all data units on the finger sub-blocks corresponding to the same number (for example, any one of SB0, SB1, SB2 or SB3) of all even-numbered super word lines of the super block to generate a check code unit (for example, a size of 16KB), and performs an XOR operation on all data units on the finger sub-blocks corresponding to the same number of all odd-numbered super word lines of the super block to generate a check code unit (for example, a size of 16KB). In this way, 8 check code units P0 can be generated, and the 8 check code units P0 are The check code unit is correspondingly and sequentially written into the four data units (corresponding to different finger sub-block numbers SB0, SB1, SB2 or SB3, respectively) of the last storage plane PL3 of the last chip CE1 of the last channel CH1 of the last even-numbered super word line (e.g., WLZ-1), and is correspondingly and sequentially written into the four data units (or called data pages, corresponding to different finger sub-block numbers SB0, SB1, SB2 or SB3, respectively) of the last storage plane PL3 of the last chip CE1 of the last channel CH1 of the last odd-numbered super word line (e.g., WLZ), to perform data protection operations in the word line dimension.

[0053] For example, if Figure 3 As shown, assuming that the value of Z is an odd value, when the flash memory controller 105 performs data reading, if all data units on all finger sub-blocks of an odd-numbered super word line (for example, with number WL3) of a physical block B1 corresponding to the channel CH0, the chip CE0 and the storage plane PL0 are all wrong (E1 represents the data unit in which the error occurs), then the flash memory controller 105 can use the 4 check code units stored in the 4 storage pages on the last storage plane PL3 of the last chip CE1 of the last channel CH1 of the last odd-numbered super word line WLZ in the super block to respectively correct the erroneous data of the four parts of the aforementioned error E1.

[0054] In addition, if errors occur in two data units on some finger sub-blocks SB0 and SB1 of an odd-numbered super word line, such as WL1, of a physical block B2 corresponding to channel CH0, chip CE0 and storage plane PL2 (E2 indicates the data unit in which the error occurs) and / or errors occur in two data units on some finger sub-blocks SB2 and SB3 of an odd-numbered super word line, such as WL1, of a different physical block B3 corresponding to channel CH0, chip CE0 and storage plane PL3 (E3 indicates the data unit in which the error occurs), the flash memory controller 105 may also use four check code units stored in four storage pages on the last storage plane PL3 of the last chip CE1 of the last channel CH1 of the last odd-numbered super word line WLZ in the super block to respectively correct some of the data errors in the aforementioned errors E2 and E3.

[0055] In addition, if a total of 8 data units on all finger sub-blocks of two adjacent word lines such as WLN-1 and WLN (one of which is an even-numbered word line and the other is an odd-numbered word line) of a physical block B4 corresponding to the channel CH0, the chip CE1 and the storage plane PL0 are all wrong (E4 represents the data unit in which the error occurs), the flash memory controller 105 can also use all 8 check code units of the check code P0 on the super word lines WLZ-1 and WLZ to correspondingly correct the aforementioned error E4. In other words, no matter whether the data of a physical word line is wrong or the data of two adjacent physical word lines are wrong, the flash memory controller 105 can use the check code P0 generated by the above XOR operation to correct the data error to achieve data protection operation in the word line dimension.

[0056] Figure 4 1 is a schematic diagram of a flash memory module 110 that performs word line dimension data protection and a physical block and a super block that can simultaneously perform finger sub-block dimension protection operations on data in a finger sub-block according to an embodiment of the present invention. Figure 4 As shown in part (a) of FIG. 1 , similarly, a word line such as WL0 in a physical block corresponding to the same channel, the same chip and the same plane includes, for example, FN (for example, 4) finger sub-blocks, and a plurality of word lines with the same number such as WL0 in a plurality of physical blocks corresponding to a plurality of different channels, a plurality of different chips and a plurality of different planes will form a super word line layer, as shown in FIG. Figure 4As shown in part (b), a super word line, such as WL0, includes multiple word lines with the same number, such as WL0, in multiple physical blocks corresponding to multiple different channels CH0 and CH1, multiple different chips CE0 and CE1, and multiple different planes PL0 to PL3, and the super word line includes FN super finger sub-blocks, each super finger sub-block includes multiple data units with the same word line number and the same finger sub-block number in multiple physical blocks corresponding to multiple different channels CH0 and CH1, multiple different chips CE0 and CE1, and multiple different planes PL0 to PL3.

[0057] exist Figure 4 In order to correct a bit error in a finger sub-block and perform a protection operation on the finger sub-block dimension, the flash memory controller 105 of the present case can, for example, perform an XOR operation on all data units on each numbered (odd numbered or even numbered) super word line of the super block corresponding to different finger sub-blocks, different channels, different chips and different planes to generate a corresponding plurality of check code units (for example, 16KB in size), and write these check code units into the last storage page unit on the last super finger sub-block stored on these super word lines, for example, the flash memory controller 105 can perform an XOR operation on all data units on each numbered (odd numbered or even numbered) super word line of the super block corresponding to different finger sub-blocks, different channels, different chips and different planes to generate a corresponding plurality of check code units (for example, 16KB in size), and write these check code units into the last storage page unit on the last super finger sub-block stored on these super word lines, for example, the flash memory controller The controller 105 performs an XOR operation on all data units on different channels, different chips and different planes of all four finger sub-blocks of an even-numbered super word line WL0 of the super block to generate a check code data unit (e.g., 16KB in size in SLC mode and 64KB in size in QLC mode), and writes and stores it in the last data unit of the even-numbered super word line WL0 (i.e., a data unit of the last channel, the last chip, the last plane and the last finger sub-block). The generation method of the check code units of the finger sub-block dimension of other numbered super word lines is the same as described above. It should be noted that, in one embodiment, since the check code units of the word line dimension mentioned above can be used to correct the errors of a physical finger sub-block occurring in the last even-numbered super word line and the last odd-numbered super word line, in one embodiment, it is not necessary to generate and store the check code units of the finger sub-block dimension in the last even-numbered super word line and the last odd-numbered super word line. The write storage locations of the check code units of the finger sub-block dimension mentioned above are as follows: Figure 4 as shown in part (b).

[0058] When something like Figure 4When all data units of a finger sub-block, such as SB0, in a physical block B1 shown in parts (a) and (b) are erroneous, the flash memory controller 105 can respectively use the check code unit (indicated by the check code P1) stored on the last storage page unit on the last super finger sub-block of each numbered super word line to correct the data units of the finger sub-block SB0 of the physical block B1 in each numbered super word line, and, for example, use the check code unit of the word line dimension to correct the data errors of the physical finger sub-block B1 occurring in the last even-numbered super word line and the last odd-numbered super word line.

[0059] Figure 5 FIG. 1 is a schematic diagram of a flash memory module 110 that performs word line dimension data protection and simultaneously performs finger sub-block dimension protection operations on data of two finger sub-blocks and a super block according to another embodiment of the present invention. Figure 5 As shown in part (a) of the embodiment, in one case, data units of two adjacent finger sub-blocks such as SB0 and SB1 of a physical block such as B1 may have errors. Therefore, in one embodiment, in order to correct the bit errors in the two finger sub-blocks to perform the protection operation of the finger sub-block dimension, the flash memory controller 105 of the present case, for example, performs an XOR operation on all data units corresponding to different channels, different chips and different planes on multiple even-numbered finger sub-blocks (such as SB0 and SB2) in each numbered super word line of the super block to generate a check code unit (such as 16KB in size), and the check code unit is The unit is written into the last storage page unit stored on the last even-numbered finger sub-block (e.g., SB2) among the multiple even-numbered finger sub-blocks, and an XOR operation is performed on all data units corresponding to different channels, different chips, and different planes on the multiple odd-numbered finger sub-blocks (e.g., SB1, SB3) in each numbered super word line of the super block to generate a check code unit (e.g., 16KB in size), and the check code unit is written into the last storage page unit stored on the last odd-numbered finger sub-block (e.g., SB3) among the multiple odd-numbered finger sub-blocks, such as Figure 5 The check code P1 of part (b) is shown.

[0060] Therefore, when something like Figure 5When all data units of an even-numbered finger sub-block SB0 and an odd-numbered finger sub-block SB1 in a physical block B1 shown in parts (a) and (b) are wrong, the flash memory controller 105 can use the check code unit (indicated by the check code P1) stored on the last storage page unit on the last even-numbered super finger sub-block SB2 of each numbered super word line to correct the data units of the even-numbered finger sub-block SB0 of the physical block B1 in each numbered super word line, and use the check code unit (indicated by the check code P1) stored on the last storage page unit on the last odd-numbered super finger sub-block SB3 of each numbered super word line to correct the data units of the odd-numbered finger sub-block SB1 of the physical block B1 in each numbered super word line.

[0061] Similarly, in this case, errors in the data units of the finger sub-blocks SB0 and SB1 corresponding to the physical block B1 in the super word line numbered WLZ-1 or WLZ can also be corrected by a corresponding part of the check code units in the check code P0, so in one embodiment, for the protection of the finger sub-blocks, the flash memory controller 105 does not need to perform the error correction code protection operation of the finger sub-block dimension for the data units on the last odd-numbered and the last even-numbered super word lines.

[0062] Figure 6 1 is a schematic diagram of a super block of a flash memory module 110 that performs word line dimension data protection and simultaneously performs finger sub-block dimension protection operations on data of two finger sub-blocks according to another embodiment of the present invention. Figure 5 The difference between part (b) is that in Figure 6 In the embodiment of the present invention, the flash memory controller 105 performs finger sub-block dimension error correction code protection operations on the data units on the last even-numbered and last odd-numbered super word lines, respectively, and stores the generated check code units in the penultimate data page of the last even-numbered finger sub-block and the penultimate data page of the last odd-numbered finger sub-block in the last even-numbered super word line, and in the penultimate data page of the last even-numbered finger sub-block and the penultimate data page of the last odd-numbered finger sub-block in the last odd-numbered super word line, respectively.

[0063] In addition, in other embodiments, such as for the TLC write mode, a data unit may include three data pages (or sub-data pages), such as an upper data page, a middle data page, and a lower data page. The data protection operations in the word line dimension and the finger sub-block dimension are also performed on different sub-data pages respectively. For example, the data protection operation in the finger sub-block dimension performs an XOR operation to sequentially generate check code data corresponding to the upper data page of the even-numbered finger sub-block for all upper data pages of, for example, an even-numbered finger sub-block in a super word line, generate check code data corresponding to the middle data page of the even-numbered finger sub-block for all middle data pages of, for example, an even-numbered finger sub-block in the super word line, and generate check code data corresponding to the upper data page of the even-numbered finger sub-block for all lower data pages of, for example, an even-numbered finger sub-block in the super word line. Similarly, different check code data corresponding to different sub-data pages can be generated for all different sub-data pages of, for example, an odd-numbered finger sub-block in the super word line. The aforementioned word line dimension data protection operation is also applied to different sub-data pages to perform different XOR operations. In addition, performing different XOR operations on different sub-data pages is also applicable to other write modes, such as MLC write mode or QLC write mode, etc.; to avoid the specification being too lengthy, it will not be repeated here.

[0064] By using the ECC protection operations in two different dimensions, namely the word line dimension and the finger sub-block dimension, the flash memory controller 105 can correct data errors such as a word line open circuit, two line layer short circuits, and one or two finger sub-blocks, thereby greatly improving the accuracy of data storage.

[0065] In addition, in one embodiment, in order to simplify the circuit cost as much as possible and to support multiple different write modes and multiple different product specifications at the same time, taking the size of a data page in the SLC mode as 16KB, the capacity of the check code buffer 1055A in the error correction code circuit 1052 can be designed to be, for example, 256KB or 512KB in size, so that the data of each data page or the corresponding check code can be simultaneously moved to the check code buffer 1055A to perform XOR operations at the same time, and the capacity of the check code buffer 1055B can be designed to be, for example, 32KB or 256KB to perform XOR operations on finger sub-blocks; the capacity of the check code buffer 1055A is 256KB because a super block has, for example, 16 physical blocks, but the design of the above content values ​​is not a limitation of the present case.

[0066] Figure 71 is a schematic diagram of an error correction code circuit 1052 according to an embodiment of the present invention. In one embodiment, in order to reduce the circuit cost as much as possible, the capacity of the check code buffer 1055A is 256KB and is evenly divided into 16 sub-buffers 1056_0 to 1056_15 (i.e., word line dimension sub-buffers), wherein sub-buffers 1056_0 to 1056_3 are the first group, sub-buffers 1056_4 to 1056_7 are the second group, sub-buffers 1056_8 to 1056_11 are the third group, and sub-buffers 1056_12 to 1056_15 are the fourth group. Each sub-buffer has a capacity of 16KB and can store a check code data of a word line dimension, such as a corresponding check code data in RAID0_0 to RAID0_15. For example, sub-buffer 1056_0 can store a check code data RAID0_0 of 16KB of a word line dimension. In addition, for example, in the SLC write mode, the check code data corresponding to the size of a page data is stored, and in the QLC write mode, the check code data corresponding to the size of a sub-page data is stored.

[0067] The check code buffer 1055B has a capacity of 32KB and is evenly divided into two sub-buffers 1057_0 and 1057_1 (i.e., finger sub-block dimension sub-buffers) to store check codes RAID1_0 and RAID1_1 respectively. Each sub-buffer has a capacity of 16KB and can be used to temporarily store check codes of the finger sub-block dimension.

[0068] Figure 8 1 is a schematic diagram of an example of a super block in which the flash memory controller 105 uses the SLC write mode to write data to the flash memory module 110 and performs data protection operations in the word line dimension and the finger sub-block dimension according to an embodiment of the present invention. Figure 8As shown, the word line dimension check code data R0 is stored in the last data unit (e.g., data page) of all super finger sub-blocks of the last even-numbered super word line and the last data unit (e.g., data page) of all super finger sub-blocks of the last odd-numbered super word line. The word line dimension check code data R0, for example, includes a plurality of parts of word line dimension check code data R0(WL_even:SB0), R0(WL_even:SB1), R0(WL_even:SB2), R0(WL_even:SB3), R0(WL_odd:SB0), R0(WL_odd:SB1), R0(WL_odd:SB2), R0(WL_odd:SB3), which Part of the word line dimension check code data R0 (WL_even: SB0), R0 (WL_even: SB1), R0 (WL_even: SB2), R0 (WL_even: SB3) are respectively used to protect the data units of multiple different super finger sub-blocks SB0, SB1, SB2, SB3 in multiple even-numbered super word lines, and part of the word line dimension check code data R0 (WL_odd: SB0), R0 (WL_odd: SB1), R0 (WL_odd: SB2), R0 (WL_odd: SB3) are respectively used to protect the data units of multiple different super finger sub-blocks SB0, SB1, SB2, SB3 in multiple odd-numbered super word lines.

[0069] As for the check code data in the finger sub-block dimension, for a super word line such as WL0, the flash memory controller 105 uses the last data unit in the last even-numbered finger sub-block such as SB2 to store the XOR check code data generated by all the data units of all the even-numbered super finger sub-blocks SB0 and SB2 in the super word line such as WL0. For example, all the data units (numbered 1 to 16) in the super finger sub-block SB0 of the super word line WL0 are used together with the data units (numbered 33 to 47) in the super finger sub-block SB2 of the super word line WL0 to generate the check code R1 (WL0:SB0&2). The check code R1 (WL0:SB0&2) is stored in the last data unit (e.g., data page) in the super finger sub-block SB2. The check code R1 (WL0:SB0&2) can be used to correct errors in the data units of the even-numbered super finger sub-blocks of the super word line WL0.

[0070] Similarly, the flash memory controller 105 utilizes the last data unit in the last odd-numbered finger sub-block, such as SB3, to store the XOR check code data generated by all the data units of all the odd-numbered super finger sub-blocks SB1 and SB3 in the super word line, such as WL0. For example, all the data units (numbered 17 to 32) in the super finger sub-block SB1 of the super word line WL0 are used to generate the check code R1 (WL0:SB1&3) with the data units (numbered 48 to 62) in the super finger sub-block SB3 of the super word line WL0. The check code R1 (WL0:SB1&3) is stored in the last data unit (e.g., a data page) in the super finger sub-block SB3. The check code R1 (WL0:SB1&3) can be used to correct errors in the data units of the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL0.

[0071] Similarly, by doing so, the flash memory controller 105 can also perform an XOR operation on multiple data units in the even-numbered super finger sub-blocks SB0 and SB2 of a super word line WL1 to generate a check code R1 (WL1: SB0&2). The check code R1 (WL1: SB0&2) is stored in the last data unit in its last even-numbered super finger sub-block SB2 and can be used to correct errors in the data units of the even-numbered super finger sub-blocks of the super word line WL1. In addition, the flash memory controller 105 can also perform an XOR operation on multiple data units in the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL1 to generate a check code R1 (WL1: SB1&3). The check code R1 (WL1: SB1&3) is stored in the last data unit in its last odd-numbered super finger sub-block SB3 and can be used to correct errors in the data units of the odd-numbered super finger sub-blocks of the super word line WL1. Similarly, the flash memory controller 105 can also generate check codes R1(WL2:SB0&2), R1(WL2:SB1&3) and R1(WL3:SB0&2), R1(WL3:SB1&3) for the super word line WL2 and the super word line WL3, respectively, and store and write these check codes into the locations of the corresponding multiple data pages. The above operations are similar, so they will not be repeated to save space in the specification.

[0072] Figures 9 to 13 This is a schematic diagram of a specific implementation example of the error correction code circuit 1052 operating in the SLC mode according to an embodiment of the present invention. Fig. 9As shown in part (a), the sequential error correction code circuit 1052 first uses the first sub-buffer 1056_0 in the first group of sub-buffers to perform an XOR operation on all data units (numbered 1 to 16) in a super finger sub-block SB0 of a super word line WL0 and stores the generated 16KB check code R0 (WL0:SB0), and then uses the second sub-buffer 1056_1 in the first group of sub-buffers to perform an XOR operation on all data units (numbered 17 to 32) in a super finger sub-block SB1 of the super word line WL0 and stores the generated 16KB check code R0 (WL0:SB1). At this time, the other sub-buffers are empty and do not temporarily store check codes.

[0073] Then, if Fig. 9 As shown in part (b), the ECC circuit 1052 uses the third sub-buffer 1056_1 of the first group of sub-buffers to perform an XOR operation on all data units (numbered 33 to 47) in the super finger sub-block SB2 of the super word line WL0 and stores the generated 16KB check code R0 (WL0:SB2). At the same time, the ECC circuit 1052 reads the check code R0 (WL0:SB0) previously temporarily stored in the first sub-buffer 1056_0 of the first group of sub-buffers, and uses the sub-buffer 1056_1 to perform an XOR operation on all data units (numbered 33 to 47) in the super finger sub-block SB2 of the super word line WL0. The buffer 1057_0 performs an XOR operation on the two check codes R0 (WL0:SB0) and R0 (WL0:SB2) and stores the generated check code R1 (WL0:SB0&2). Then, the generated check code R1 (WL0:SB0&2) can be written into the last data unit stored in the last even-numbered super finger sub-block SB2 of the super word line WL0 and can be used to correct errors in the data units of the even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0.

[0074] Then, if Fig.10As shown in part (a), the error correction code circuit 1052 uses the fourth sub-buffer 1056_3 in the first group of sub-buffers to perform an XOR operation on all data units (numbered 48 to 62) in the super finger sub-block SB3 of the super word line WL0 and stores the generated 16KB check code R0 (WL0: SB3). At the same time, the error correction code circuit 1052 reads the check code R0 (WL0: SB1) previously temporarily stored in the second sub-buffer 1056_1 in the first group of sub-buffers. Buffer 1057_1 performs an XOR operation on the two check codes R0 (WL0:SB1) and R0 (WL0:SB3) and stores the generated check code R1 (WL0:SB1&3). Then, the generated check code R1 (WL0:SB1&3) can be written into the last data unit stored in the last odd-numbered super finger sub-block SB3 of the super word line WL0 and can be used to correct errors in the data units of the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL0.

[0075] Then, if Fig.10 As shown in part (b), in order to perform the XOR operation of the next super word line and store the check code data, the encoding circuit 105 clears the check code data temporarily stored in the sub-buffers 1057_0 and 1057_1. It should be noted that in one embodiment, the encoding circuit 105 writes the check codes R0 (WL0: SB0), R0 (WL0: SB1), R0 (WL0: SB2), and R0 (WL0: SB3) temporarily stored in the four sub-buffers 1056_0, 1056_1, 1056_2, and 1056_3 of the first group of sub-buffers into the last data unit of the four super finger sub-blocks stored in the last even-numbered super word line (e.g., WLZ-1).

[0076] Similarly, if Fig.11 As shown in part (a), the sequential error correction code circuit 1052 uses the first sub-buffer 1056_4 of the second group of sub-buffers to perform an XOR operation on all data units (e.g., data pages) in the super finger sub-block SB0 of the super word line WL1 and stores the generated 16KB check code R0 (WL1:SB0), and then uses the second sub-buffer 1056_5 of the second group of sub-buffers to perform an XOR operation on all data units (e.g., data pages) in the super finger sub-block SB1 of the super word line WL1 and stores the generated 16KB check code R0 (WL1:SB1).

[0077] Then, if Fig.11As shown in part (b), the error correction code circuit 1052 uses the third sub-buffer 1056_6 of the second group of sub-buffers to perform an XOR operation on all data units (e.g., data pages) in the super finger sub-block SB2 of the super word line WL1 and stores the generated 16KB check code R0 (WL1:SB2). At the same time, the error correction code circuit 1052 reads the check code R0 (WL1:SB0) previously stored in the first sub-buffer 1056_4 of the second group of sub-buffers. Device 1057_0 performs an XOR operation on the two check codes R0 (WL1:SB0) and R0 (WL1:SB2) and stores the generated check code R1 (WL1:SB0&2). Then, the generated check code R1 (WL1:SB0&2) can be written into the last data unit stored in the last even-numbered super finger sub-block SB2 of the super word line WL1 and can be used to correct errors in the data units of the even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL1.

[0078] Then, if Fig.12 As shown in part (a), the error correction code circuit 1052 uses the fourth sub-buffer 1056_7 of the second group of sub-buffers to perform an XOR operation on all data units (e.g., data pages) in the super finger sub-block SB3 of the super word line WL1 and stores the generated 16KB check code R0 (WL1: SB3). At the same time, the error correction code circuit 1052 reads the check code R0 (WL1: SB1) previously temporarily stored in the second sub-buffer 1056_5 of the second group of sub-buffers, and uses the sub-buffer 1056_7 to perform an XOR operation on all data units (e.g., data pages) in the super finger sub-block SB3 of the super word line WL1. Device 1057_1 performs an XOR operation on the two check codes R0 (WL1:SB1) and R0 (WL1:SB3) and stores the generated check code R1 (WL1:SB1&3). Then, the generated check code R1 (WL1:SB1&3) can be written into the last data unit stored in the last odd-numbered super finger sub-block SB3 of the super word line WL1 and can be used to correct errors in the data units of the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL1.

[0079] Then, if Fig.12As shown in part (b), in order to perform the XOR calculation of the next super word line, the encoding circuit 105 clears the check code data temporarily stored in the sub-buffers 1057_0 and 1057_1. It should be noted that at this time, the encoding circuit 105 reads out the check codes R0(WL1:SB0), R0(WL1:SB1), R0(WL1:SB2), and R0(WL1:SB3) temporarily stored in the sub-buffers 1056_4, 1056_5, 1056_6, and 1056_7 of the second group of sub-buffers and writes them into the last data unit of each of the four super finger sub-blocks of the last odd-numbered super word line (e.g., WLZ).

[0080] It should be noted that after completing an XOR operation between an even-numbered super word line and an odd-numbered super word line, the error correction code circuit 1052 clears the check code data temporarily stored in the first and second sub-buffers 1056_0 to 1056_7 for the next round of XOR operation between an even-numbered super word line and an odd-numbered super word line. In addition, in the SLC write mode of this embodiment, the other second and third sub-buffers 1056_8 to 1056_15 are not used, and these sub-buffers 1056_8 to 1056_15 will be used in, for example, the QLC mode, which will be described later.

[0081] Similarly, if Fig.13 As shown in part (a), the ECC circuit 1052 will respectively use the first, second, third and fourth sub-buffers 1056_0 to 1056_3 in the first group of sub-buffers to perform XOR operations on the data units in the super finger sub-blocks SB0, SB1, SB2 and SB3 of the super word line WL2 and store the generated 16KB check codes R0 (WL2: SB0), R0 (WL2: SB1), R0 (WL2: SB2) and R0 (WL2: SB3) respectively. At the same time, the ECC circuit 1052 can also use the sub-buffers 1057_0 and 1057_1 in the same way as the super word line WL0 to generate and temporarily store the finger sub-block check codes R1 (WL2: SB0&2) and R1 (WL2: SB1&3). The ECC circuit 1052 will write the locations of the multiple data pages corresponding to the super block where the above-mentioned different check codes are stored, which will not be repeated.

[0082] Similarly, Fig.13As shown in part (b), the error correction code circuit 1052 can also use the sub-buffers 1056_4, 1056_5, 1056_6, and 1056_7 in the second group of sub-buffers to respectively perform XOR operations on the data units in the super finger sub-blocks SB0, SB1, SB2, and SB3 of the super word line WL3 and store the generated 16KB check codes R0(WL3:SB0), R0(WL3:SB1), and R0(WL3: SB2), R0(WL3:SB3), and the error correction code circuit 1052 can also use the sub-buffers 1057_0 and 1057_1 in the same way as the super word line WL1 to respectively generate and temporarily store the finger sub-block check codes R1(WL3:SB0&2), R1(WL3:SB1&3). The error correction code circuit 1052 will write the locations of multiple data pages corresponding to the storage of the above-mentioned different check codes in the super block, which will not be repeated.

[0083] For an even-numbered super word line, in the same manner as described above, the error correction code circuit 1052 can use multiple sub-buffers in the first group of sub-buffers to perform XOR operations on multiple data units of multiple finger sub-blocks with different numbers in an even-numbered super word line, such as multiple page data, and store the resulting multiple partial word line check code units. Then, the error correction code circuit 1052 can use a sub-buffer 1057_0 to perform an XOR operation again on the partial word line check code units temporarily stored in the multiple even-numbered sub-buffers in the first group of sub-buffers and store the resulting one finger sub-block check code unit, and the error correction code circuit 1052 can use another sub-buffer 1057_1 to perform an XOR operation again on the partial word line check code units temporarily stored in the multiple odd-numbered sub-buffers in the first group of sub-buffers and store the resulting one finger sub-block check code unit.

[0084] In addition, for an odd-numbered super word line, similarly, the error correction code circuit 1052 can use multiple sub-buffers in the second group of sub-buffers to perform XOR operations on multiple data units of multiple finger sub-blocks with different numbers in an odd-numbered super word line, such as multiple page data, and store the resulting multiple partial word line check code units. Then, the error correction code circuit 1052 can use a sub-buffer 1057_0 to perform an XOR operation again on the partial word line check code units temporarily stored in multiple even-numbered sub-buffers in the second group of sub-buffers and store the resulting one finger sub-block check code unit, and the error correction code circuit 1052 can use another sub-buffer 1057_1 to perform an XOR operation again on the partial word line check code units temporarily stored in multiple odd-numbered sub-buffers in the second group of sub-buffers and store the resulting one finger sub-block check code unit.

[0085] According to the same method, the error correction code circuit 1052 can generate a plurality of finger sub-block check code units R1(WL0:SB0&2), R1(WL0:SB1&3), R1(WL1:SB0&2), R1(WL1:SB1&3), R1(WL2:SB0&2), R1(WL2:SB1&3), R1(WL3:SB0&2), R1(WL3:SB1&3), ..., R1(WLN-1:SB0&2), R1(WLN-1:SB1&3), R1(WLN:SB0&2), R1(WLN:SB1&3) ... and write these check code units into Figure 8 Position shown.

[0086] In addition, in one embodiment, the error correction code circuit 1052 may write the error correction code units stored in the memory after generating the error correction code units of a multiple word line check code units of an even numbered super word line and a multiple word line check code units of an odd numbered super word line. Figure 8 The position of the R0 check code shown in the figure, after generating multiple word line check code units of the next even-numbered super word line and multiple word line check code units of the next odd-numbered super word line, performing an XOR operation on the multiple word line check code units of the two even-numbered super word lines to generate multiple merged word line check code units and performing an XOR operation on the multiple word line check code units of the two odd-numbered super word lines to generate another multiple merged word line check code units, and correspondingly writing them into Figure 8 Thus, when the relevant operation of the last super word line WLZ is completed, the error correction code circuit 1052 also completes the writing. Figure 8 The R0 check code (ie, the final word line check code unit generated by the word line dimension protection operation) is shown.

[0087] Fig.14 According to an embodiment of the present invention Figure 7The schematic diagram of the error correction code protection operation performed by the error correction code circuit 1052 on a super word line WL0 in the QLC mode is shown. In this embodiment, since the overall capacity of the sub-buffers 1057_0 and 1057_1 is smaller than the size of the check code data generated corresponding to a super word line in the QLC mode, the sub-buffers 1057_0 and 1057_1 are not used in this embodiment, and the check code is exchanged and stored outside the error correction code circuit 1052, for example, first temporarily stored in a shared buffer (, or first temporarily stored in an SRAM (not shown in the figure) in the controller 105. In the QLC mode, a data unit has 4 sub-storage pages, and the size of each sub-storage page is, for example, 16KB, that is, a data unit in the QLC mode can store 4 times the amount of data that a data unit in the aforementioned SLC mode can store.

[0088] At this time, for a super word line, such as an even-numbered super word line WL0, first in step S1, the error correction code circuit 1052 uses the first sub-buffer 1056_0 in the first group of sub-buffers to perform an XOR operation on the first sub-data page (e.g., LSB (Lower Significant Bit) page) of all data units in an even-numbered super finger sub-block SB0 of the even-numbered super word line, such as WL0, to generate and temporarily store a check code R0 (WL0: SB0, LSB) of 16KB size, and uses the second sub-buffer 1056_1 in the first group of sub-buffers to perform an XOR operation on the second sub-data page (e.g., MSB (Middle Significant Bit) page) of all data units in the even-numbered super finger sub-block SB0 of the even-numbered super word line WL0. The third sub-buffer 1056_2 in the first group of sub-buffers is used to perform an XOR operation on the third sub-data page (e.g., USB (Upper Significant Bit) page) of all data units in the super finger sub-block SB0 of the even-numbered super word line WL0 to generate and temporarily store the check code R0 (WL0: SB0, USB) of 16KB in size, and the fourth sub-buffer 1056_3 in the first group of sub-buffers is used to perform an XOR operation on the fourth sub-data page (e.g., TSB (Top Significant Bit) page) of all data units in the super finger sub-block SB0 of the even-numbered super word line WL0 to generate and temporarily store the check code R0 (WL0: SB0, USB) of 16KB in size. Bit) page) to generate and temporarily store a 16KB check code R0 (WL0: SB0, TSB). That is, the controller 105 uses four sub-buffers in the first group of sub-buffers to perform four XOR operations on parts of four different sub-data pages of multiple data units in the super finger sub-block SB0 of the super word line WL0 to generate and temporarily store four 16KB check code data R0 (WL0: SB0, LSB), R0 (WL0: SB0, MSB), R0 (WL0: SB0, USB), and R0 (WL0: SB0, TSB).

[0089] Similarly, for different super finger sub-blocks SB1, SB2, SB3 of the super word line WL0, the controller 105 may also respectively utilize the second group of sub-buffers 1056_4, 1056_5, 1056_6 and 1056_7, the third group of sub-buffers 1056_8, 1056_9, 1056_10 and 1056_11, and the fourth group of sub-buffers 1056_12, 1056_13, 1056_14 and 1056_15 to perform four XO operations on the four different sub-data pages of the multiple data units in the super finger sub-blocks SB1, SB2, SB3 of the even-numbered super word line WL0. R operation (a total of 12 times) is used to generate and temporarily store 12 16KB checksum data, R0(WL0:SB1,LSB), R0(WL0:SB1,MSB), R0(WL0:SB1,USB), R0(WL0:SB1,TSB), R0(WL0:SB2,LSB), R0(WL0:SB2,MSB), R0(WL0:SB2,USB), R0(WL0:SB2,TSB), R0(WL0:SB3,LSB), R0(WL0:SB3,MSB), R0(WL0:SB3,USB), R0(WL0:SB3,TSB), such as Fig.14 It should be noted that the above-mentioned verification code data can be regarded as part of the preliminary word line dimension verification code R0.

[0090] Then in step S2, the error correction code circuit 1052 transmits and exchanges the word line dimension check code data R0(WL0:SB0), R0(WL0:SB1), R0(WL0:SB2), R0(WL0:SB3) of the super finger sub-blocks SB0, SB1, SB2, SB3 of the super word line WL0 stored in the four groups of sub-buffers for temporary storage and backup to the shared buffer 1051. For example, R0(WL0:SB0) is 64KB data including 4 16KB check code data R0(WL0:SB0,LSB), R0(WL0:SB0,MSB), R0(WL0:SB0,USB), R0(WL0:SB0,TSB), and the others are similar.

[0091] Next, in step S3, the error correction code circuit 1052 uses the four sub-buffers in the first group of sub-buffers to respectively check the word line dimension check codes R0(WL0:SB0,LSB), R0(WL0:SB0,MSB), R0(WL0:SB0,USB), R0(WL0:SB0,TSB) and R0(WL0:SB2,LSB), R0(WL0:SB2,MSB), R0(WL0:SB2,USB), R0(WL0:SB2,TSB) of the parts corresponding to the four different sub-data pages of the multiple data units of the even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0. SB) respectively perform XOR operation to generate and temporarily store the finger sub-block dimension check code data R1(WL0:SB0&2,LSB), R1(WL0:SB0&2,MSB), R1(WL0:SB0&2,USB), R1(WL0:SB0&2,TSB) of the even-numbered super finger sub-blocks SB0 and SB2 of the even-numbered super word line WL0, wherein, for example, the check code data R1(WL0:SB0&2,LSB) of 16KB size is generated by performing an XOR operation on R0(WL0:SB0,LSB) and R0(WL0:SB2,LSB), and the others are similar.

[0092] Similarly, the error correction code circuit 1052 uses the four sub-buffers in the second group of sub-buffers to respectively check the word line dimension check codes R0(WL0:SB1, LSB), R0(WL0:SB1, MSB), R0(WL0:SB1, USB), R0(WL0:SB1, TSB) and R0(WL0:SB3, LSB), R0(WL0:SB3, MSB), R0(WL0:SB3, USB), R0(WL0:SB3, TSB) of the parts corresponding to the four different sub-data pages of the multiple data units of the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL0. ) respectively perform XOR operations to generate and temporarily store the finger sub-block dimension check code data R1(WL0:SB1&3,LSB), R1(WL0:SB1&3,MSB), R1(WL0:SB1&3,USB), R1(WL0:SB1&3,TSB) of the odd-numbered super finger sub-blocks SB1 and SB3 of the even-numbered super word line WL0, wherein, for example, the check code data R1(WL0:SB1&3,LSB) of 16KB size is generated by performing an XOR operation on R0(WL0:SB1,LSB) and R0(WL0:SB3,LSB), and the others are similar. At this time, the shared buffer 1051 records the data of the word line dimension check code of part of the super word line WL0, and the first group of sub-buffers and the second group of sub-buffers respectively record the data of the finger sub-block dimension check code of the even-numbered super finger sub-blocks of the super word line WL0 and the data of the finger sub-block dimension check code of the odd-numbered super finger sub-blocks.

[0093] Then in step S4, the error correction code circuit 1052 writes the data of the finger sub-block dimension check code temporarily stored in the first group of sub-buffers and the second group of sub-buffers into the four sub-data pages of the last data unit of the last even-numbered super finger sub-block of the super word line WL0 of the flash memory module 110, so as to complete the data write protection of the finger sub-block dimension check code of the super word line WL0 and clear the four groups of sub-buffers.

[0094] Next refer to Fig.15 , Fig.15 FIG. 1 is a schematic diagram of an error correction code circuit 1052 performing an error correction code protection operation on a super word line WL1 in a QLC mode according to an embodiment of the present invention. Fig.14In the embodiment shown, for the next super word line, for example, an odd-numbered super word line WL1, first, in step S5, the sequential error correction code circuit 1052 also uses the first sub-buffer 1056_0 in the first group of sub-buffers to perform an XOR operation on the first sub-data page (for example, LSB) of all data units in an even-numbered super finger sub-block SB0 of the odd-numbered super word line, for example, WL1, to generate and temporarily store a check code R0 (WL1: SB0, LSB) of 16KB in size, and uses the first sub-buffer 1056_0 in the first group of sub-buffers to generate and temporarily store a check code R0 (WL1: SB0, LSB) of 16KB in size. The second sub-buffer 1056_1 of the first group of sub-buffers is used to perform an XOR operation on the second sub-data page (for example, MSB) of all data units in the even-numbered super finger sub-block SB0 of the odd-numbered super word line WL1 to generate and temporarily store a 16KB check code R0 (WL1:SB0,MSB), the third sub-buffer 1056_2 of the first group of sub-buffers is used to perform an XOR operation on the third sub-data page (for example, USB (Upper Significant Bit)) of all data units in the super finger sub-block SB0 of the odd-numbered super word line WL1 to generate and temporarily store a 16KB check code R0 (WL1:SB0,USB), and the fourth sub-buffer 1056_3 of the first group of sub-buffers is used to perform an XOR operation on the fourth sub-data page (for example, TSB) of all data units in the super finger sub-block SB0 of the odd-numbered super word line WL1 to generate and temporarily store a 16KB check code R0 (WL1:SB0,TSB).

[0095] Similarly, for different super finger sub-blocks SB1, SB2, SB3 of the super word line WL1, the controller 105 may also respectively utilize the second group of sub-buffers 1056_4, 1056_5, 1056_6 and 1056_7, the third group of sub-buffers 1056_8, 1056_9, 1056_10 and 1056_11, and the fourth group of sub-buffers 1056_12, 1056_13, 1056_14 and 1056_15 to perform four XO operations on the four different sub-data pages of the multiple data units in the super finger sub-blocks SB1, SB2, SB3 of the odd-numbered super word line WL1. R operation (a total of 12 times) is used to generate and temporarily store 12 16KB checksum data, R0(WL1:SB1,LSB), R0(WL1:SB1,MSB), R0(WL1:SB1,USB), R0(WL1:SB1,TSB), R0(WL1:SB2,LSB), R0(WL1:SB2,MSB), R0(WL1:SB2,USB), R0(WL1:SB2,TSB), R0(WL1:SB3,LSB), R0(WL1:SB3,MSB), R0(WL1:SB3,USB), R0(WL1:SB3,TSB), such as Fig.15 It should be noted that the above-mentioned verification code data can be regarded as part of the preliminary word line dimension verification code R0.

[0096] Then in step S6, the error correction code circuit 1052 transmits and exchanges the word line dimension check code data R0(WL1:SB0), R0(WL1:SB1), R0(WL1:SB2), R0(WL1:SB3) of the super finger sub-blocks SB0, SB1, SB2, SB3 of the super word line WL1 in the four groups of sub-buffers for temporary storage and backup to the shared buffer 1051. For example, R0(WL1:SB0) is 64KB data including 4 16KB check code data R0(WL1:SB0,LSB), R0(WL1:SB0,MSB), R0(WL1:SB0,USB), R0(WL1:SB0,TSB), and the others are similar. At this time, the shared buffer 1051 also records the word line dimension check code data R0(WL0:SB0), R0(WL0:SB1), R0(WL0:SB2), R0(WL0:SB3) of the super finger sub-blocks SB0, SB1, SB2, SB3 of the previous super word line WL0.

[0097] Next, in step S7, the error correction code circuit 1052 similarly uses the four sub-buffers in the first group of sub-buffers to respectively check the word line dimension check codes R0(WL1:SB0,LSB), R0(WL1:SB0,MSB), R0(WL1:SB0,USB), R0(WL1:SB0,TSB) and R0(WL1:SB2,LSB), R0(WL1:SB2,MSB), R0(WL1:SB2,USB), R0(WL1:SB2) of the parts corresponding to the four different sub-data pages of the multiple data units of the even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL1. ,TSB) are respectively XOR-operated to generate and temporarily store the finger sub-block dimension check code data R1(WL1:SB0&2,LSB), R1(WL1:SB0&2,MSB), R1(WL1:SB0&2,USB), R1(WL1:SB0&2,TSB) of the even-numbered super finger sub-blocks SB0 and SB2 of the odd-numbered super word line WL1, wherein, for example, the check code data R1(WL1:SB0&2,LSB) of 16KB size is generated by performing an XOR operation on R0(WL1:SB0,LSB) and R1(WL0:SB2,LSB), and the others are similar.

[0098] Similarly, the error correction code circuit 1052 uses the four sub-buffers in the second group of sub-buffers to respectively check the word line dimension check codes R0(WL1:SB1, LSB), R0(WL1:SB1, MSB), R0(WL1:SB1, USB), R0(WL1:SB1, TSB) and R0(WL1:SB3, LSB), R0(WL1:SB3, MSB), R0(WL1:SB3, USB), R0(WL1:SB3, TSB) of the parts corresponding to the four different sub-data pages of the multiple data units of the odd-numbered super finger sub-blocks SB1 and SB3 of the super word line WL1. ) respectively perform XOR operations to generate and temporarily store the finger sub-block dimension check code data R1(WL1:SB1&3,LSB), R1(WL1:SB1&3,MSB), R1(WL1:SB1&3,USB), R1(WL1:SB1&3,TSB) of the odd-numbered super finger sub-blocks SB1 and SB3 of the odd-numbered super word line WL1, wherein, for example, the check code data R1(WL1:SB1&3,LSB) of 16KB size is generated by performing an XOR operation on R0(WL0:SB1,LSB) and R0(WL0:SB3,LSB), and the others are similar. At this time, the shared buffer 1051 records the data of the word line dimension check codes of part of the super word lines WL0 and WL1, and the first group of sub-buffers and the second group of sub-buffers respectively record the data of the finger sub-block dimension check codes of the even-numbered super finger sub-blocks of the super word line WL1 and the data of the finger sub-block dimension check codes of the odd-numbered super finger sub-blocks.

[0099] Then, in step S8, the error correction code circuit 1052 writes the data of the finger sub-block dimension check code temporarily stored in the first group of sub-buffers and the second group of sub-buffers into the four sub-data pages of the last data unit of the last even-numbered super finger sub-block of the super word line WL1 of the flash memory module 110, so as to complete the data write protection of the finger sub-block dimension check code of the super word line WL1 and clear the four groups of sub-buffers.

[0100] Next refer to Fig.16 , Fig.16 FIG. 1 is a schematic diagram of an error correction code circuit 1052 performing an error correction code protection operation on a super word line WL2 in a QLC mode according to an embodiment of the present invention. Fig.15 In the embodiment shown, for the next super word line, for example, an even-numbered super word line WL2, the error correction code circuit 1052 is similarly configured as follows: Fig.16In step S9 to step S12, the data of the finger sub-block dimension check code temporarily stored in the first group of sub-buffers and the second group of sub-buffers are written into the four sub-data pages of the last data unit of the last even-numbered super finger sub-block of the super word line WL2 of the flash memory module 110, so as to complete the data write protection of the finger sub-block dimension check code of the super word line WL2 and clear the four groups of sub-buffers. At this time, the shared buffer 1051 records the first two super word lines. The data R0(WL0:SB0), R0(WL0:SB1), R0(WL0:SB2), R0(WL0:SB3) of the word line dimension check code of the part of the level word line WL0, the data R0(WL1:SB0), R0(WL1:SB1), R0(WL1:SB2), R0(WL1:SB3) of the word line dimension check code of the part of WL1, and the data R0(WL2:SB0), R0(WL2:SB1), R0(WL2:SB2), R0(WL2:SB3) of the word line dimension check code of the part of WL2; Fig.16 The operation of the embodiment is the same as Fig.14 and Fig.15 The operation of the embodiment of the present invention will not be described in detail to avoid making the description too lengthy.

[0101] To avoid taking up too much space in the shared buffer 1051 and reduce circuit cost, please refer to Fig.17 , Fig.17 1 is a schematic diagram of the ECC circuit 1052 performing an ECC protection operation on even-numbered super word lines such as WL0 and WL2 in QLC mode to generate data of the merged partial word line dimension check code R0 according to an embodiment of the present invention. Fig.17 As shown, continued Fig.16In the embodiment, in step S13, the error correction code circuit 1052 first loads the data R0 (WL2: SB0), R0 (WL2: SB1), R0 (WL2: SB2), and R0 (WL2: SB3) of the word line dimension check code of the latest super word line WL2 recorded in the shared buffer 1051 into the four groups of sub-buffers respectively, and then in step S14, the error correction code circuit 1052 then loads the data R0 (WL2: SB0), R0 (WL2: SB1), R0 (WL2: SB2), and R0 (WL2: SB3) of the word line dimension check code of the latest super word line WL2 recorded in the shared buffer 1051 into the four groups of sub-buffers respectively. The word line dimension check code data R0 (WL0: SB0), R0 (WL0: SB1), R0 (WL0: SB2), R0 (WL0: SB3) of the part of the line WL0, for example, are respectively loaded and stored in the four groups of sub-buffers, and the four groups of sub-buffers are used to respectively check the word line dimension check code data R0 (WL0: SB0), R0 (WL0: SB1), R0 (WL0: SB2), R0 (WL0: SB3) of the part of the word line WL0 and the part of the word line WL2. The dimension check code data R0(WL2:SB0), R0(WL2:SB1), R0(WL2:SB2), and R0(WL2:SB3) are XORed (the four groups of sub-buffers have a total of 16 sub-buffers, so 16 XOR operations are performed) to generate the merged partial word line dimension check code data R0(WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2), and R0(WL0&2:SB3), that is, even The data of the word line dimension check code of the merged part of the even-numbered super word lines WL0 and WL2 can protect the data of the even-numbered super word lines WL0 and WL2 to perform word line dimension error correction protection operations, wherein R0(WL0&2:SB0) includes R0(WL0&2:SB0,LSB), R0(WL0&2:SB0,MSB), R0(WL0&2:SB0,USB), R0(WL0&2:SB0,TSB), and the others are similar and will not be described in detail. After generating the data of the merged partial word line dimension check code, in step S15, the error correction code circuit 1052 exchanges and transmits the data R0(WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2), and R0(WL0&2:SB3) of the merged partial word line dimension check code stored in the four groups of sub-buffers and stores them in the shared buffer 1051, and clears the four groups of sub-buffers to prepare for the error correction code protection operation for the next super word line.

[0102] Therefore, the shared buffer 1051 originally needs to store data of word line dimension check codes of a portion of, for example, 3 super word lines, but after generating data of word line dimension check codes of a portion after the merger, the shared buffer 1051 only needs to store data of word line dimension check codes of a portion of, for example, 2 super word lines. Therefore, by merging data of word line dimension check codes of a portion of multiple even-numbered super word lines recorded in the shared buffer 1051, it is possible to avoid occupying too much space in the shared buffer 1051 and reduce circuit costs. Similarly, by merging data of word line dimension check codes of a portion of multiple odd-numbered super word lines recorded in the shared buffer 1051, it is possible to avoid occupying too much space in the shared buffer 1051 and reduce circuit costs.

[0103] Fig.18 1 is a schematic diagram of the change in the amount of data of the merged partial word line dimension check code R0 recorded in the shared buffer 1051 when the error correction code circuit 1052 sequentially merges the data of the partial word line dimension check code R0 of multiple even-numbered super word lines and multiple odd-numbered super word lines in the QLC mode according to an embodiment of the present invention. Fig.18 In the process shown, at step S21, the shared buffer 1051 records the data R0(WL0:SB0), R0(WL0:SB1), R0(WL0:SB2), R0(WL0:SB3) of the word line dimension check code of the super word line WL0 and the data R0(WL1:SB0), R0(WL1:SB1), R0(WL1:SB2), R0(WL1:SB3) of the word line dimension check code of the super word line WL1. The data of each portion of the word line dimension check code, such as R0(WL0:SB0), is a data size of 64KB. At this time, for example, the total data amount of the partial word line dimension check code recorded in the shared buffer 1051 is 8×64KB; but it is not limited.

[0104] exist Fig.18In step S22, the error correction code circuit 1052 generates data R0 (WL2:SB0), R0 (WL2:SB1), R0 (WL2:SB2), and R0 (WL2:SB3) of the word line dimension check code of part of the super word line WL2, and exchanges and transmits the data of these word line dimension check codes, and backs them up and temporarily stores them in the shared buffer 1051. At this time, for example, the total data amount of the part of the word line dimension check code recorded in the shared buffer 1051 is 12×64KB. Then, the data R0(WL2:SB2) and R0(WL2:SB3) of the partial word line dimension check code of the super word line WL2 will be loaded from the shared buffer 1051 to the first and second groups of sub-buffers of the error correction code circuit 1052 to generate the check code data of the finger sub-block dimension of the super word line WL2, and then after the check code data of the finger sub-block dimension of the super word line WL2 is generated, the data of the partial word line dimension check code of the even-numbered super word lines WL0 and WL2 will be moved, exchanged and transmitted to the error correction code circuit 1052 to use the four groups of sub-buffers to merge the data of the partial word line dimension check code of the even-numbered super word lines WL0 and WL2 to generate the merged partial word line dimension check code data R0(WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2) of the even-numbered super word lines WL0 and WL2. , R0(WL0&2:SB3), the merged partial word line dimension check code data R0(WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2), R0(WL0&2:SB3) will be exchanged and stored in the shared buffer 1051. At this time, the shared buffer 1051 records the partial word line dimension check code data R0(WL1:SB0), R0(WL1:SB1), R0(WL1:SB2), R0(WL1:SB3) and data recording the word line dimension check code of the merged part R0(WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2), R0(WL0&2:SB3). For example, the total data volume of the word line dimension check code of the part recorded in the shared buffer 1051 is 8×64KB.

[0105] Then, in Fig.18In step S23, similarly, the data R0 (WL3:SB0), R0 (WL3:SB1), R0 (WL3:SB2), and R0 (WL3:SB3) of the word line dimension check code of the super word line WL3 generated by the error correction code circuit 1052 will be exchanged, transmitted, and backed up and temporarily stored in the shared buffer 1051. At this time, for example, the total data amount of the word line dimension check code recorded in the shared buffer 1051 is 12×64KB. Then, similarly, the data R0(WL3:SB2) and R0(WL3:SB3) of the partial word line dimension check code of the super word line WL3 are loaded from the shared buffer 1051 to the first and second groups of sub-buffers of the error correction code circuit 1052 to generate the check code data of the finger sub-block dimension of the super word line WL3, and then after the check code data of the finger sub-block dimension of the super word line WL3 is generated, the data of the partial word line dimension check code of the odd-numbered super word lines WL1 and WL3 are transferred and exchanged to the error correction code circuit 1052 to merge the data of the partial word line dimension check code of the even-numbered super word lines WL1 and WL3 by using the four groups of sub-buffers to generate the merged partial word line dimension check code data R0(WL1&3:SB0), R0(WL1&3:SB1), R0 of the even-numbered super word lines WL1 and WL3. (WL1&3:SB2), R0(WL1&3:SB3), the merged part of the word line dimension check code data R0(WL1&3:SB0), R0(WL1&3:SB1), R0(WL1&3:SB2), R0(WL1&3:SB3) will be swapped back to the shared buffer 1051. At this time, the shared buffer 1051 records the merged part of the word line dimension check code data R0 (WL0&2:SB0), R0(WL0&2:SB1), R0(WL0&2:SB2), R0(WL0&2:SB3) and R0(WL1&3:SB0), R0(WL1&3:SB1), R0(WL1&3:SB2), R0(WL1&3:SB3). For example, the total data volume of the word line dimension check code recorded in the shared buffer 1051 is 8×64KB. Fig.18 As shown in step S24.

[0106] Fig.18 The operations and processes of step S25 to step S28 are similar to the above steps. In step S25, the word line dimension check code of the newly-incoming even-numbered super word line, such as part of WL4, is XOR-operated with the word line dimension check code of the combined part of the previous multiple even-numbered super word lines WL0 and WL2 to generate data of the word line dimension check code of the combined part of the multiple even-numbered super word lines WL0, WL2, and WL4 (such as Fig.18 In step S26), and in step S27, the word line dimension check code of the newly-incoming odd-numbered super word line, such as WL5, is XOR-operated with the word line dimension check code of the combined part of the previous plurality of odd-numbered super word lines WL1 and WL3 to generate data of the word line dimension check code of the combined part of the plurality of odd-numbered super word lines WL1, WL3, and WL5 (such as Fig.18 The error correction code circuit 1052 combines the data of the word line dimension check codes of a portion of the even-numbered super word lines (or a portion of the odd-numbered super word lines), such as Fig.18 As shown, even if the total number of super word lines in a super block is quite large, the shared buffer 1051 can be controlled to, for example, only temporarily store data of a word line dimension check code that is at most 3 times the size of a super word line, thereby avoiding occupying too much capacity of the shared buffer 1051. In other words, the circuit cost of the shared buffer 1051 can be reduced.

[0107] It should be noted that the design of the four groups of sub-buffers of the error correction code circuit 1052 can be applied to the MLC write mode or the TLC write mode in addition to the SLC write mode and the QLC write mode. In one embodiment, when operating in the MLC write mode, the error correction code circuit 1052 can, for example, use the first two sub-buffers of a group of sub-buffers (corresponding to the upper data page and the lower data page of the MLC write mode) to perform an XOR operation, and the last two sub-buffers of the group of sub-buffers are idle. In one embodiment, when operating in the TLC write mode, the error correction code circuit 1052 can, for example, use the first three sub-buffers of a group of sub-buffers (corresponding to the upper data page, the middle data page, and the lower data page of the TLC write mode) to perform an XOR operation, and the last sub-buffer of the group of sub-buffers is idle.

[0108] In addition, in one embodiment, the QLC write mode may be a two-stage write programming operation, for example, in the first stage, the LSB page and the MSB page of a data unit are first written by using the MLC write operation, and then in the second stage, the USB page and the TSB page of a data unit are written by using the MLC write operation to complete the write operation in the QLC mode. In this embodiment, the buffers 1057_0 and 1057_1 may be used to generate and temporarily store part of the check code data of the finger sub-block dimension as described in the above paragraph in the SLC mode, without the need to exchange and backup the generated check code data and store them in the shared buffer 1051. For example (but not limited to), in the QLC mode, for the four sub-data pages of a data unit, in the first stage of the MLC write programming operation, the flash memory controller 105 writes two sub-data pages (such as the LSB page and the MSB page) of the data unit, and in the second stage of the MLC write programming operation, the flash memory controller 105 writes the other two sub-data pages (such as the USB page and the TSB page) of the data unit. Therefore, when two sub-data pages (e.g., LSB page, MSB page) of all data cells of a super finger sub-block such as SB0 of a super word line such as WL0 are written through the first stage MLC write programming operation, the error correction code circuit 1052 can be similar to Fig.14 As shown in FIG. 1 , the first two sub-buffers 1056_0 and 1056_1 in the first group of sub-buffers are used to generate and store the word line dimension check code data R0 (WL0: SB0, LSB) and R0 (WL0: SB0, MSB) corresponding to the data of the LSB page and the MSB page. Similarly, when two sub-data pages (such as USB pages and TSB pages) of all data units of a super finger sub-block such as SB0 of a super word line such as WL0 are written through the second stage MLC write programming operation, the error correction code circuit 1052 can be the same as Fig.14 As shown in the figure, the last two sub-buffers 1056_2 and 1056_3 in the first group of sub-buffers are used to generate and store the word line dimension check code data R0 (WL0: SB0, USB) and R0 (WL0: SB0, TSB) corresponding to the data of the USB page and the TSB page. The above operation is also applicable to the sub-data pages of all data units of other super finger sub-blocks such as SB1, SB2, and SB3 of the super word line such as WL0, to generate the following respectively: Fig.14 The partial word line dimension check code data R0 (WL0: SB1, LSB) to R0 (WL0: SB3, TSB) generated in step S1 are shown.

[0109] This embodiment and Fig.14The difference between the embodiment shown is that, in the present embodiment, since a write programming operation is performed on two sub-data pages, when the four groups of sub-buffers respectively generate corresponding word line dimension check code data, the error correction code circuit 1052 can simultaneously use a buffer 1057_0 to perform an XOR operation on a portion of the word line dimension check code data of a sub-data page, such as an LSB page, of a data unit of an even-numbered super finger sub-block of a super word line and a portion of the word line dimension check code data of a sub-data page, such as an LSB page, of a data unit of another even-numbered super finger sub-block of the super word line to generate a portion of the finger sub-block dimension check code data corresponding to the sub-data page, such as the LSB page, of a data unit of a plurality of even-numbered super finger sub-blocks, such as R1 (WL0: SB0&2, LSB), and write the corresponding word line dimension check code data of the last data unit stored in the even-numbered super finger sub-block. The above operation is also applicable to the MSB page, USB page, TSB page, and the sub-data page of the data unit of the odd-numbered super finger sub-block. Another buffer 1057_1 can be used to perform an XOR operation on the word line dimension check code data of the sub-data page of the data unit of an odd-numbered super finger sub-block of the super word line, such as the LSB page, and the word line dimension check code data of the sub-data page of the data unit of another odd-numbered super finger sub-block of the super word line, such as the LSB page, to generate a portion of the finger sub-block dimension check code data corresponding to the sub-data page of the data unit of multiple even-numbered super finger sub-blocks, such as the LSB page, and write it into the corresponding sub-data page position of the last data unit stored in the odd-numbered super finger sub-block; in order to avoid the specification being too lengthy, it will not be described in detail. In this way, in this embodiment, it is not necessary as Fig.14 The example of using the two groups of sub-buffers to generate the finger sub-block dimension check code data is shown, and the finger sub-block dimension check code data can be generated and temporarily stored by using the two buffers 1057_0 and 1057_1 in the SLC write mode.

[0110] In addition, in the present embodiment, for the error correction operation when reading data after writing in SLC mode, multiple data units of an even-numbered super word line, such as WL0, include data units of, for example, 4 finger sub-blocks SB0 to SB3, wherein multiple data units of two even-numbered finger sub-blocks SB0 and SB2 are used together to generate a corresponding finger sub-block check code unit (e.g., 16KB), which can be used to correct an error in one of the data units of the two even-numbered finger sub-blocks SB0 and SB2. In addition, multiple data units of two odd-numbered finger sub-blocks SB1 and SB3 are used together to generate a corresponding finger sub-block check code unit (e.g., 16KB), which can be used to correct an error in one of the data units of the two odd-numbered finger sub-blocks SB1 and SB3.

[0111] In addition, the data unit of the first even-numbered finger sub-block SB0 mentioned above is also used together with the data unit of the first even-numbered finger sub-block SB0 of multiple even-numbered super word lines such as WL2, WL4, etc. to generate a corresponding word line dimension check code unit (e.g., 16KB), and the data unit of the second even-numbered finger sub-block SB2 mentioned above is also used together with the data unit of the second even-numbered finger sub-block SB2 of multiple even-numbered super word lines such as WL2, WL4, etc. to generate another corresponding word line dimension check code unit (e.g., 16KB). Similarly, the data units of the first odd-numbered finger sub-block SB1 mentioned above will also be used together with the data units of the first odd-numbered finger sub-block SB1 of multiple other even-numbered super word lines such as WL2, WL4, etc. to generate another corresponding word line dimension check code unit (e.g., 16KB), and the data units of the second odd-numbered finger sub-block SB3 mentioned above will also be used together with the data units of the second odd-numbered finger sub-block SB3 of multiple other even-numbered super word lines such as WL2, WL4, etc. to generate another corresponding word line dimension check code unit (e.g., 16KB).

[0112] In the present embodiment, when performing an error correction operation for data reading, the error correction code circuit 1052 first performs error correction in a first dimension, such as a finger sub-block dimension. If the errors in the finger sub-block dimension are too many to be corrected, then error correction in a related second dimension, such as a word line dimension, is performed. If the errors in the word line dimension are too many to be corrected, then error correction in another finger sub-block dimension is performed. Error correction is performed in a recursive manner until the error is successfully corrected. At this time, the error correction returns to the previous step to correct other errors.

[0113] Please refer to Fig.19 , Fig.19FIG. 1 is a flow chart of an error correction operation / process performed by the error correction code circuit 1052 when reading data according to an embodiment of the present invention. Fig.19 As shown in the process flow, in this embodiment, the error correction code circuit 1052 reads multiple data units of two even-numbered super finger sub-blocks SB0 and SB2 of a specific super word line such as WL0 and then performs an error correction operation, but this is not a limitation of the present case. Fig.19 The operation is also applicable to the data reading of the data units of the two even-numbered super finger sub-blocks SB0 and SB2 of other super word lines or is also applicable to the data reading of the data units of the two odd-numbered super finger sub-blocks SB1 and SB3.

[0114] In addition, the error correction code circuit 1052 can perform Fig.19 One or more layers of error correction operations / processes are shown. The error correction code circuit 1052 repeats the steps of this process in a recursive manner to perform error correction on the data of different selected super word lines in order to maximize the chance of decoding the correct data of one or more super word lines.

[0115] The process starts from step S1901, and the error correction code circuit 1052 reads data of the super word line WL0, for example, by performing an error correction protection operation of the finger sub-block dimension using the finger sub-block dimension check code data such as R1 (WL0:SB0&2) to read and perform error correction on the data units of the two even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0.

[0116] In step S1902, the error correction code circuit 1052 determines whether the result of the error correction operation using the finger sub-block dimension check code data is successful. For example, if the number of errors in the data units of the two even-numbered super finger sub-blocks SB0 and SB2 is less than or equal to the correctable error amount, for example, in the XOR operation, when only one data unit in the two even-numbered super finger sub-blocks SB0 and SB2 has an error, it can be corrected by the finger sub-block dimension check code R1 (WL0:SB0&2), then the result of the error correction operation using the finger sub-block dimension check code data will be successful, that is, the error correction can be performed to obtain the correct data units of the two even-numbered super finger sub-blocks SB0 and SB2, and the reading of the data of the two even-numbered super finger sub-blocks SB0 and SB2 is completed, and the process enters step S1903 ("end"), indicating that the correct data units of the two even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0 have been obtained.

[0117] On the contrary, if the finger sub-block dimension check code R1 (WL0:SB0&2) cannot be successfully used to perform error correction on the data units of the two even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0, for example, in the XOR operation, more than one data unit in the two even-numbered super finger sub-blocks SB0 and SB2 has an error and cannot be corrected by the finger sub-block dimension check code R1 (WL0:SB0&2), then the error correction result of the finger sub-block dimension will fail, that is, the correct data units of the two even-numbered super finger sub-blocks SB0 and SB2 cannot be obtained. At this time, the error correction code circuit 1052 will then use different parts of the word line dimension check code data R0 (WL_even:SB0), R0 (WL_even:SB2) for the data units of the two even-numbered super finger sub-blocks SB0 and SB2 respectively (for example Figure 8 As shown) to correct the error of the word line dimension, at this time, the process will branch to perform two steps S1904A and S1904B.

[0118] In step S1904A, the ECC circuit 1052 uses part of the word line dimension check code data R0 (WL_even: SB0) for the data unit of an even-numbered super finger sub-block SB0 (eg Figure 8 For example, the error correction code circuit 1052 additionally reads the data units of the even-numbered super finger sub-block SB0 respectively in the other multiple even-numbered super word lines (at this time, it is not necessary to read the data units of the super finger sub-blocks with different numbers), so as to use part of the word line dimension check code data R0 (WL_even:SB0) to perform error correction on the data units of the even-numbered super finger sub-block SB0 respectively in the super word line WL0 and the other multiple even-numbered super word lines.

[0119] Similarly, in step S1904B, the ECC circuit 1052 uses a portion of the word line dimension check code data R0 (WL_even: SB2) for the data units of an even-numbered super finger sub-block SB2 (eg Figure 8 As shown) in the figure, error correction of the word line dimension is performed. For example, the error correction code circuit 1052 additionally reads the data units of the even-numbered super finger sub-block SB2 respectively possessed by other multiple even-numbered super word lines (at this time, it is not necessary to read the data units of other super finger sub-blocks with different numbers), so as to utilize part of the word line dimension check code data R0 (WL_even:SB2) to perform error correction on the data units of the even-numbered super finger sub-block SB2 respectively possessed by the super word line WL0 and other multiple even-numbered super word lines.

[0120] The combined results of the above two branch steps S1904A and S1904B may result in a total of four possible results, as shown in the following table:

[0121]

[0122] In result A1, the error correction code circuit 1052 can use different parts of the word line dimension check code data R0 (WL_even: SB0) and R0 (WL_even: SB2) to successfully perform word line dimension error correction on the data units of the even-numbered super finger sub-blocks SB0 and SB2, respectively. For example (but not limited to), when one data unit of each of the even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0 is erroneous, even if the finger sub-block dimension check code data such as R1 (WL0: SB0&2) cannot be successfully used to perform error correction on the data units of the two even-numbered super finger sub-blocks SB0 and SB2 of the super word line WL0, the error correction code circuit 1052 can still have the opportunity to use the word line dimension check code data R0 (WL_even: SB0) and R0 (WL_even: SB2) to correct the errors of the two data units, thereby achieving the effect of data protection. At this point, the errors of the two data units have been successfully corrected, so the process does not need to return to step S1901 to perform another error correction on the finger sub-block dimension. Therefore, the process now proceeds to step S1903.

[0123] In possible result A2, it indicates that the error correction code circuit 1052 can successfully perform data protection error correction for the data units of the even-numbered super finger sub-block SB0 of the super word line WL0 using partial word line dimension check code data R0 (WL_even: SB0), but cannot successfully perform data protection error correction for the data units of the even-numbered super finger sub-block SB2 of the super word line WL0 using partial word line dimension check code data R0 (WL_even: SB2). For example (but not limited to), when one data unit of the even-numbered super finger sub-block SB0 of the super word line WL0 is wrong (the number of errors is less than or equal to the number that can be corrected) and more than one data unit of the even-numbered super finger sub-block SB2 is wrong (for example, 3 data units are wrong, that is, the number of errors exceeds the number that can be corrected), the error correction code circuit 1052 can use the word line dimension check code data R0 (WL_even:SB0) to successfully correct the data unit error of the even-numbered super finger sub-block SB0 to obtain the correct data of the even-numbered super finger sub-block SB0 of the super word line WL0, but cannot obtain the correct data of the even-numbered super finger sub-block SB2 of the super word line WL0. At this time, in this case, the error correction code circuit 1052 can determine that the data units of the even-numbered super finger sub-block SB0 of all other even-numbered super word lines are correct, so that the correct data of the even-numbered super finger sub-block SB0 of all even-numbered super word lines can be obtained. However, in this example, the error correction code circuit 1052 cannot use the word line dimension check code data R0 (WL_even:SB2) to correct the error in the data unit of the even-numbered super finger sub-block SB2. At this time, the error correction code circuit 1052 cannot determine whether the data of the even-numbered super finger sub-block SB2 of all other even-numbered super word lines can be corrected. For example, the even-numbered super finger sub-block SB2 of the super word line WL0 has a data unit error, and the even-numbered super finger sub-block SB2 of other even-numbered super word lines such as WL2 and WL4 also has a data unit error (the even-numbered super finger sub-block SB2 of other even-numbered super word lines has no error), thereby causing the error correction code circuit 1052 to be unable to use the word line dimension check code data R0 (WL_even:SB2) to correct the erroneous data unit of the even-numbered super finger sub-block SB2 of the super word line WL0.

[0124] At this time, the error correction code circuit 1052 will record the result of error correction using the word line dimension check code R0 (WL_even:SB2) as failure, and trigger and start the error correction of the next layer (i.e., the second layer) to decode the correct data. For example, the error correction code circuit 1052 will read and error correct the even-numbered super finger sub-blocks SB0 and SB2 of the even-numbered super word line, such as WL2, based on the same process steps as above. In the above example, if only one data unit in the even-numbered super finger sub-block SB2 of the super word line, such as WL2, is erroneous, the error correction code circuit 1052 can use a corresponding finger sub-block dimension check code to correct the error to obtain the correct data of the even-numbered super finger sub-block SB2 of the super word line WL2. Since this process is a second-level error correction process, when correct data is obtained, the error correction code circuit 1052 will return to the error correction process of the previous level (i.e., the first level). When the data of the even-numbered super finger sub-block SB2 of the super word line WL2 is correct, the error correction of the relevant word line dimension is performed again to determine whether the data of the even-numbered super finger sub-block SB2 of all other even-numbered super word lines can be corrected. For example, there is an error in a data unit of the even-numbered super finger sub-block SB2 of the super word line WL0, and the error in the even-numbered super finger sub-block SB2 of the super word line WL2 has been corrected, but there is still an error in a data unit of the even-numbered super finger sub-block SB2 of the super word line WL4 (the even-numbered super finger sub-blocks SB2 of other even-numbered super word lines have no errors), so the result of performing the error correction of the relevant word line dimension again is still failure.

[0125] At this time, the error correction code circuit 1052 will return to the second-level error correction process and continue to select other super word lines, such as the even-numbered super finger sub-blocks SB2 of WL4, to perform error correction operations. Similarly, the error correction code circuit 1052 will read and perform error correction on the even-numbered super finger sub-blocks SB0 and SB2 of the even-numbered super word line, such as WL4, based on the same process steps mentioned above. Taking the above example, if only one data unit in the even-numbered super finger sub-block SB2 of the super word line, such as WL4, is erroneous, the error correction code circuit 1052 can use a corresponding finger sub-block dimension check code to correct the error to obtain the correct data of the even-numbered super finger sub-block SB2 of the super word line WL4. Since this process is a second-layer error correction process, when correct data is obtained, the error correction code circuit 1052 will return to the error correction process of the previous layer (i.e., the first layer). After the errors in the even-numbered super finger sub-blocks SB2 of the super word lines WL2 and WL4 have been corrected, only the even-numbered super finger sub-block SB2 of the super word line WL0 has one data unit error. Therefore, when the error correction code circuit 1052 returns to the error correction process of the previous layer (i.e., the first layer), the error in the even-numbered super finger sub-block SB2 of the super word line WL0 can be corrected to obtain correct data. At this time, the result of the error correction of the relevant word line dimension will be modified to success.

[0126] Similarly, possible result A3 indicates that the error correction code circuit 1052 can successfully perform data protection error correction for the data unit of the even-numbered super finger sub-block SB2 using part of the word line dimension check code data R0 (WL_even: SB2), but cannot successfully perform data protection error correction for the data unit of the even-numbered super finger sub-block SB0 using part of the word line dimension check code data R0 (WL_even: SB0); similarly, if the result of the word line dimension error correction is a failure, the error correction code circuit 1052 will trigger and start the next layer of error correction process in the same process steps as in possible result A2 to try to decode the correct data. In order to simplify the length of the specification, it will not be described in detail.

[0127] Similarly, possible result A4 indicates that the error correction code circuit 1052 cannot use part of the word line dimension check code data R0 (WL_even: SB2) to successfully perform data protection error correction for the data unit of the even-numbered super finger sub-block SB2, and cannot use part of the word line dimension check code data R0 (WL_even: SB0) to successfully perform data protection error correction for the data unit of the even-numbered super finger sub-block SB0, that is, the results of the error correction of the two word line dimensions are both failures; similarly, for the case where the result of the error correction of each word line dimension is failure, the error correction code circuit 1052 will trigger and start the next layer of error correction process in the same process steps as in possible result A2 to try to decode the correct data. In order to simplify the length of the specification, it will not be described in detail.

[0128] As mentioned above, the error correction code circuit 1052 can perform multiple layers of error correction processes to resolve or correct errors as much as possible to obtain correct data. In one embodiment, the error correction code circuit 1052 can only perform N layers of error correction processes at most, where N is equal to 3, for example (but not limited to). In practice, for example, the error correction code circuit 1052 can first determine how many layers of error correction processes have been triggered each time step S1901 is performed. When it is determined that the error correction code circuit 1052 has reached 3 layers, the error correction code circuit 1052 can automatically terminate data reading and determine that the current data unit has too many errors and cannot be correctly read out, thereby reducing the complexity of calculation.

[0129] In other words, in the embodiment of the present invention, for the error correction operation flow when performing data reading, when the error correction code circuit 1052 performs the error correction flow of the i-th layer (such as Fig.19 ), if it is determined that the error correction result of a word line dimension in the error correction process of the i-th layer is a failure, the error correction code circuit 1052 will trigger and start the error correction process of the (i+1)th layer to try to solve the other data units that were originally to be processed by the error correction of the word line dimension. If the result of the error correction process of the (i+1)th layer is successful, the error correction code circuit 1052 will recursively return to the error correction process of the previous layer (i.e., the i-th layer) to perform the error correction operation of the word line dimension or the error correction operation of the corresponding finger sub-block dimension again. In this way, the error rate when reading data can be greatly reduced by alternately performing error correction operations of two different dimensions.

[0130] In other words, the above-mentioned error correction code circuit 1052 is capable of performing a first-level error correction operation, performing a first-level finger sub-block dimension error correction on the data of the multiple finger sub-blocks in the first word line. When the result of the first-level finger sub-block dimension error correction is failure, the error correction code circuit 1052 performs a first-level word line dimension error correction on a first finger sub-block in the first word line and multiple finger sub-blocks in other word lines having the same number as the first finger sub-block, and records the result of the first-level word line dimension error correction corresponding to the first finger sub-block in the first word line. In addition, when the result of the first-level wordline dimension error correction corresponding to the first finger sub-block in the first wordline is failure, the error correction code circuit 1052 triggers and starts a second-level error correction operation to perform a second-level finger sub-block dimension error correction on the data of the plurality of finger sub-blocks in the second wordline corresponding to a finger sub-block in the plurality of finger sub-blocks having the same number as the first finger sub-block in the other wordline. In addition, when the result of the second-level finger sub-block dimension error correction is success, the error correction code circuit 1052 returns to the first-level error correction operation according to the result of the second-level finger sub-block dimension error correction to update the result of the first-level wordline dimension error correction to success. In addition, when the result of the second-level finger sub-block dimension error correction is failure, the error correction code circuit 1052 performs a second-level word line dimension error correction on a second finger sub-block in the second word line and a plurality of finger sub-blocks in other word lines having the same number as the second finger sub-block, and records the result of the second-level word line dimension error correction corresponding to the second finger sub-block in the second word line. In addition, when the result of the second-level word line dimension error correction corresponding to the second finger sub-block in the second word line is failure, the error correction code circuit 1052 may also trigger and start a third-level error correction operation, and perform a third-level finger sub-block dimension error correction on the data of a plurality of finger sub-blocks in a third word line corresponding to a finger sub-block among the plurality of finger sub-blocks in other word lines having the same number as the second finger sub-block.

[0131] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A flash memory controller, coupled between a host and a flash memory module, comprising: a specific buffer for receiving and buffering specific data from the host, the specific data to be stored in the flash memory module to form a super block, the super block consisting of a plurality of finger sub-blocks in a vertical direction and a plurality of super word lines in a horizontal direction; and an ECC circuit, coupled to the specific buffer, for performing a word-line dimension ECC operation on the specific data to generate a word-line dimension check code data and performing a finger sub-block dimension ECC operation on the specific data to generate a finger sub-block dimension check code data; When a data error occurs in the super block, the word line dimension check code data and the finger sub-block dimension check code data are used to correct the data error in the super block to obtain the specific data.

2. The flash memory controller according to claim 1, wherein: The word line dimension ECC operation and the finger sub-block dimension ECC operation are both implemented by an exclusive OR operation.

3. The flash memory controller according to claim 1, wherein: The flash memory controller writes and stores the word line dimension check code data into the corresponding M last data pages of the M finger sub-blocks in the last even-numbered super word line in the super block and the corresponding M last data pages of the M finger sub-blocks in the last odd-numbered super word line, where M is an even number.

4. The flash memory controller according to claim 3, wherein: One data page of the super block includes a single data page size in the single-layer cell write mode, includes 2 sub-data page sizes in the 2-layer cell write mode, includes 3 sub-data page sizes in the 3-layer cell write mode, and includes 4 sub-data page sizes in the 4-layer cell write mode.

5. The flash memory controller according to claim 3, wherein: A portion of the word line dimension check code data stored on a corresponding last data page of an even-numbered finger sub-block in the last even-numbered super word line is used to correct errors occurring in data with the same even-numbered finger sub-block in multiple even-numbered super word lines in the super block, and a portion of the word line dimension check code data stored on a corresponding last data page of an odd-numbered finger sub-block in the last even-numbered super word line is used to correct errors occurring in data with the same odd-numbered finger sub-block in multiple odd-numbered super word lines in the super block.

6. The flash memory controller according to claim 3, wherein: A portion of the word line dimension check code data stored on a corresponding last data page of an even-numbered finger sub-block in the last odd-numbered super word line is used to correct errors occurring in data having the same even-numbered finger sub-block in multiple odd-numbered super word lines in the super block, and a portion of the word line dimension check code data stored on a corresponding last data page of an odd-numbered finger sub-block in the last odd-numbered super word line is used to correct errors occurring in data having the same odd-numbered finger sub-block in multiple odd-numbered super word lines in the super block.

7. The flash memory controller according to claim 1, wherein: The flash memory controller writes and stores different parts of the finger sub-block dimension check code data into the last data page of the last even-numbered finger sub-block and the last data page of the last odd-numbered finger sub-block respectively included in a plurality of super word lines in the super block.

8. The flash memory controller according to claim 7, wherein: A portion of the finger sub-block dimension check code data stored on the last data page of the last even-numbered finger sub-block in a specific super word line in the super block is used to correct errors occurring in data in multiple even-numbered finger sub-blocks in the specific super word line, and another portion of the finger sub-block dimension check code data stored on the last data page of the last odd-numbered finger sub-block in the specific super word line is used to correct errors occurring in data in multiple odd-numbered finger sub-blocks in the specific super word line.

9. The flash memory controller according to claim 7, wherein: The corresponding M last data pages of the M finger sub-blocks in the last even-numbered super word line in the super block and the corresponding M last data pages of the M finger sub-blocks in the last odd-numbered super word line are used to store the word line dimension check code data; the two second-to-last data pages respectively included in the last even-numbered finger sub-block and the last odd-numbered finger sub-block in the last even-numbered super word line are used to store a part of the finger sub-block check code data to respectively correct the errors occurring in the data of multiple even-numbered finger sub-blocks and the errors occurring in the data of multiple odd-numbered finger sub-blocks in the last even-numbered super word line; and the two second-to-last data pages respectively included in the last even-numbered finger sub-block and the last odd-numbered finger sub-block in the last odd-numbered super word line are used to store another part of the finger sub-block check code data to respectively correct the errors occurring in the data of multiple even-numbered finger sub-blocks and the errors occurring in the data of multiple odd-numbered finger sub-blocks in the last odd-numbered super word line.

10. A storage device comprising: A flash memory module includes a plurality of channels, each channel includes a plurality of flash memory chips, and each flash memory chip includes a plurality of blocks on a plurality of planes; as well as A flash memory controller, coupled to the flash memory module, includes: a specific buffer for receiving and buffering specific data from a host, the specific data to be stored in the flash memory module to form a super block, the super block consisting of a plurality of finger sub-blocks in a vertical direction and a plurality of super word lines in a horizontal direction; as well as an ECC circuit, coupled to the specific buffer, for performing a word-line dimension ECC operation on the specific data to generate a word-line dimension check code data and performing a finger sub-block dimension ECC operation on the specific data to generate a finger sub-block dimension check code data; When a data error occurs in the super block, the word line dimension check code data and the finger sub-block dimension check code data are used to correct the data error in the super block to obtain the specific data.

11. The storage device according to claim 10, characterized in that The flash memory controller writes and stores different parts of the finger sub-block dimension check code data into the last data page of the last even-numbered finger sub-block and the last data page of the last odd-numbered finger sub-block respectively included in a plurality of super word lines in the super block.

12. An operating method of a flash memory controller, the flash memory controller being coupled between a host and a flash memory module, and the operating method comprising: A specific buffer is provided to receive and buffer a specific data from the host, the specific data to be stored in the flash memory module to form a super block, the super block is composed of a plurality of finger sub-blocks in a vertical direction and a plurality of super word lines in a horizontal direction; Providing an ECC circuit for performing a word-line dimension ECC operation on the specific data to generate a word-line dimension check code data and performing a finger sub-block dimension ECC operation on the specific data to generate a finger sub-block dimension check code data; and When a data error occurs in the super block, the word line dimension check code data and the finger sub-block dimension check code data are used to correct the data error in the super block to obtain the specific data.

13. The operating method according to claim 12, characterized in that: The word line dimension ECC operation and the finger sub-block dimension ECC operation are both implemented by an exclusive OR operation.

14. The operating method according to claim 12, characterized in that: Also included are: The word line dimension check code data is written and stored into the corresponding M last data pages of the M finger sub-blocks in the last even-numbered super word line and the corresponding M last data pages of the M finger sub-blocks in the last odd-numbered super word line in the super block, where M is an even number.

15. The operating method according to claim 14, characterized in that: One data page of the super block includes a single data page size in the single-layer cell write mode, includes 2 sub-data page sizes in the 2-layer cell write mode, includes 3 sub-data page sizes in the 3-layer cell write mode, and includes 4 sub-data page sizes in the 4-layer cell write mode.

16. The operating method according to claim 14, characterized in that: A portion of the word line dimension check code data stored on a corresponding last data page of an even-numbered finger sub-block in the last even-numbered super word line is used to correct errors occurring in data with the same even-numbered finger sub-block in multiple even-numbered super word lines in the super block, and a portion of the word line dimension check code data stored on a corresponding last data page of an odd-numbered finger sub-block in the last even-numbered super word line is used to correct errors occurring in data with the same odd-numbered finger sub-block in multiple odd-numbered super word lines in the super block.

17. The operating method according to claim 14, characterized in that: A portion of the word line dimension check code data stored on a corresponding last data page of an even-numbered finger sub-block in the last odd-numbered super word line is used to correct errors occurring in data having the same even-numbered finger sub-block in multiple odd-numbered super word lines in the super block, and a portion of the word line dimension check code data stored on a corresponding last data page of an odd-numbered finger sub-block in the last odd-numbered super word line is used to correct errors occurring in data having the same odd-numbered finger sub-block in multiple odd-numbered super word lines in the super block.

18. The operating method according to claim 14, characterized in that: Also included are: Different parts of the finger sub-block dimension check code data are respectively written and stored in the last data page of the last even-numbered finger sub-block and the last data page of the last odd-numbered finger sub-block respectively included in a plurality of super word lines in the super block.

19. The operating method according to claim 18, characterized in that: A portion of the finger sub-block dimension check code data stored on the last data page of the last even-numbered finger sub-block in a specific super word line in the super block is used to correct errors occurring in data in multiple even-numbered finger sub-blocks in the specific super word line, and another portion of the finger sub-block dimension check code data stored on the last data page of the last odd-numbered finger sub-block in the specific super word line is used to correct errors occurring in data in multiple odd-numbered finger sub-blocks in the specific super word line.

20. The operating method according to claim 18, characterized in that: The corresponding M last data pages of the M finger sub-blocks in the last even-numbered super word line in the super block and the corresponding M last data pages of the M finger sub-blocks in the last odd-numbered super word line are used to store the word line dimension check code data; the two second-to-last data pages respectively included in the last even-numbered finger sub-block and the last odd-numbered finger sub-block in the last even-numbered super word line are used to store a part of the finger sub-block check code data to respectively correct the errors occurring in the data of multiple even-numbered finger sub-blocks and the errors occurring in the data of multiple odd-numbered finger sub-blocks in the last even-numbered super word line; and the two second-to-last data pages respectively included in the last even-numbered finger sub-block and the last odd-numbered finger sub-block in the last odd-numbered super word line are used to store another part of the finger sub-block check code data to respectively correct the errors occurring in the data of multiple even-numbered finger sub-blocks and the errors occurring in the data of multiple odd-numbered finger sub-blocks in the last odd-numbered super word line.

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