Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a wafer, the wafer including functional surfaces and non-functional surfaces; forming a functional layer structure on the surface of the functional surfaces; obtaining the warpage of the wafer; and, based on the warpage, performing at least one stress neutralization treatment on the surface of the non-functional surfaces to form a stress neutralization structure, the stress neutralization structure including at least one stress layer, the stress neutralization treatment including: forming an initial stress layer on the surface of the non-functional surfaces; and performing a stress enhancement treatment on the initial stress layer to form the stress layer. The warpage of the wafer is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] As technological advancements follow Moore's Law, three-dimensional integrated circuits (3D ICs) are attracting increasing attention from researchers. Current development trends in 3D ICs have shifted from horizontal to vertical planes, such as 3D memories, 3D through-silicon vias (TSVs), and monolithic 3D circuits.

[0003] Due to the mismatch in coefficients of thermal expansion (CTE) between different stacked materials deposited on the wafer, the film and the wafer shrink at different rates as the temperature decreases. The residual stress generated within the wafer causes it to bend upwards or downwards, resulting in wafer warping.

[0004] Excessive bending or warping of wafers, or differences in warping in different directions, can limit wafer processing or even prevent wafers from being processed on the same machine, increasing device manufacturing costs.

[0005] Therefore, improving wafer warpage is an ongoing problem that needs to be addressed. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve wafer warpage.

[0007] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a wafer, the wafer including functional surfaces and non-functional surfaces; forming a functional layer structure on the surface of the functional surfaces; acquiring the warpage of the wafer; and, based on the warpage, performing at least one stress neutralization treatment on the surface of the non-functional surfaces to form a stress neutralization structure, the stress neutralization structure including at least one stress layer, the stress neutralization treatment comprising: forming an initial stress layer on the surface of the non-functional surfaces; and performing a stress enhancement treatment on the initial stress layer to form the stress layer.

[0008] Optionally, the warping of the wafer includes: the wafer bending towards a non-functional surface, or the wafer bending towards a functional surface.

[0009] Optionally, when the wafer bends toward the functional surface, the initial stress layer has an initial compressive stress; the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0010] Optionally, the process for stress-enhancing the initial stress layer includes: ion implantation.

[0011] Optionally, the material of the initial stress layer includes silicon oxide or silicon carbide.

[0012] Optionally, the implanted ions in the ion implantation process include nitrogen ions.

[0013] Optionally, when the wafer bends toward the non-functional surface, the initial stress layer has an initial tensile stress; the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

[0014] Optionally, the process for stress-enhancing the initial stress layer includes a plasma treatment process, wherein the gas used in the plasma treatment process is of at least one type of the reactive gas that forms the initial stress layer.

[0015] Optionally, the material of the initial stress layer includes silicon nitride or silicon oxynitride, wherein the silicon oxynitride includes silicon oxynitride.

[0016] Optionally, when the material of the initial stress layer includes silicon nitride, the gas used in the plasma processing for stress enhancement of the initial stress layer includes nitrogen.

[0017] Optionally, the reaction time of the plasma treatment process includes 40 to 80 seconds.

[0018] Optionally, the process for forming the initial stress layer includes plasma-enhanced chemical vapor deposition.

[0019] Optionally, when the material of the initial stress layer includes silicon nitride, the process parameters of the plasma-enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia, and nitrogen, the flow rate of silane in the total flow rate ranges from 15% to 25%, the flow rate of ammonia in the total flow rate ranges from 25% to 35%, and the flow rate of nitrogen in the total flow rate ranges from 45% to 55%; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 to 8 tors; and the power range is 200 watts to 300 watts.

[0020] Optionally, when the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, wherein the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0021] Optionally, the first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; or the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

[0022] Optionally, the materials of the multiple stress layers are the same.

[0023] Optionally, the materials of the multiple stress layers are not entirely the same.

[0024] Optionally, the thickness of the multiple stress layers is the same.

[0025] Optionally, the thickness of the multiple stress layers is not exactly the same.

[0026] Optionally, before forming a stress-neutralizing structure on the non-functional surface, a protective layer is further formed on the surface of the functional layer structure.

[0027] Optionally, forming a stress-neutralizing structure further includes: obtaining the warpage of the wafer, wherein the warpage of the wafer is within a preset range.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0029] The method of forming the present invention involves performing at least one stress neutralization treatment on the non-functional surface. The stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer. Multiple stress layers are sequentially stress-enhanced, resulting in an overall stress enhancement of the formed stress-neutralized structure, improving wafer warpage, and ensuring that the wafer warpage meets a preset range.

[0030] Furthermore, the process for stress-enhancing the initial stress layer includes a plasma treatment process, wherein the gas used in the plasma treatment process is at least one type of the same as the reactive gas used to form the initial stress layer. This ensures that no other types of gaseous impurities are introduced during the stress-enhancing treatment of the initial stress layer, which is beneficial for increasing the stress of the formed stress layer.

[0031] Furthermore, the plasma processing gas used in the stress-enhancing treatment of the initial stress layer includes nitrogen. The nitrogen-containing plasma provides sufficient energy to open the Si-H and NH bonds in the silicon nitride film. This process allows hydrogen to be eliminated, and the resulting Si-N bonds can enhance the stress of the silicon nitride.

[0032] Furthermore, when the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, wherein the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness. The thickness range of the single-layer initial stress layer is set according to the wafer warpage. Since the initial stress layer film is relatively thin, plasma treatment can significantly enhance the stress of the thin initial stress layer film, thereby increasing the stress of the stress layer. Attached Figure Description

[0033] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0034] Figures 2 to 5 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention. Detailed Implementation

[0036] As described in the background section, improving wafer warpage is an ongoing problem that needs to be addressed.

[0037] Specifically, methods to improve wafer warpage typically include: (1) thermal annealing: usually used to solve isotropic wafer warpage, which has the property of heating the entire wafer, causing different areas of the wafer to heat up at different rates, resulting in uneven temperature distribution and uneven wafer deformation due to heat; (2) ion implantation: generating stress opposite to warpage by doping with ions, thereby reducing the degree of warpage, but at the same time requiring the addition of a back mask and implantation process, making the process complex; (3) thin film deposition: forming an auxiliary thin film on the back with the opposite stress type to the wafer to counteract the wafer stress. Conventional PECVD can prepare thin films using a high-frequency power source, but the stress of the obtained thin film is low and cannot effectively improve the wafer warpage.

[0038] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure. This method involves performing at least one stress neutralization treatment on the non-functional surface. The stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer. The multiple stress layers are sequentially stress-enhanced, resulting in an overall stress enhancement of the formed stress-neutralized structure, improving wafer warpage, and ensuring that the wafer warpage meets a preset range.

[0039] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure in an embodiment of the present invention.

[0041] Please refer to Figure 1 The process of forming the semiconductor structure includes:

[0042] Step S10: Provide a wafer, the wafer including functional and non-functional surfaces;

[0043] Step S20: Form a functional layer structure on the surface of the functional surface;

[0044] Step S30: Obtain the warpage status of the wafer;

[0045] Step S40: Based on the warping condition, perform at least one stress neutralization treatment on the non-functional surface to form a stress neutralization structure. The stress neutralization structure includes at least one stress layer. The stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer.

[0046] The formation method involves performing at least one stress neutralization treatment on the non-functional surface. This stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer. Multiple stress layers are sequentially stress-enhanced, resulting in an overall stress enhancement of the formed stress-neutralized structure, improving wafer warpage, and ensuring that the wafer warpage meets a preset range.

[0047] The wafer warpage includes: the wafer bending toward a non-functional surface, or the wafer bending toward a functional surface.

[0048] In one embodiment, when the wafer bends toward the functional surface, the initial stress layer has an initial compressive stress; the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0049] In this embodiment, when the wafer bends toward the non-functional surface, the initial stress layer has an initial tensile stress; the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

[0050] Next, combined Figures 2 to 5 Each step is analyzed and explained. Figures 2 to 5 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention.

[0051] Please combine Figure 2 Step S10: Provide a wafer 100, which includes a functional surface S1 and a non-functional surface S2; Step S20: Form a functional layer structure on the surface of the functional surface S1.

[0052] The functional layer structure comprises a stack of multiple thin films, with stress mismatch between the multiple thin films and stress mismatch between the functional layer structure and the wafer 100.

[0053] Please continue to refer to this. Figure 2 It also includes: forming a protective layer 101 on the surface of the functional layer structure.

[0054] The protective layer 101 is used to protect the surface of the functional layer structure.

[0055] In this embodiment, the material of the protective layer 101 includes silicon oxide.

[0056] Please continue to combine Figure 2 Step S30: Obtain the warpage of the wafer 100, wherein the warpage of the wafer 100 includes: the wafer 100 bending toward the non-functional surface S2.

[0057] In this embodiment, the warpage of the wafer 100 further includes: the warpage of the wafer 100 bending toward the non-functional surface S2 is greater than a preset value.

[0058] The preset value is the standard value for determining whether wafer warpage will affect production and yield. Wafers with warpage within the preset range meet the requirements for production and yield.

[0059] In this embodiment, the wafer 100 bends toward the non-functional surface S2, generating compressive stress on the surface of the non-functional surface S2 of the wafer 100.

[0060] Next, please combine Figure 3 and Figure 4 Step S40: Based on the warping condition, perform at least one stress neutralization treatment on the non-functional surface to form a stress neutralization structure. The stress neutralization structure includes at least one stress layer. The stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer.

[0061] The stress in the stress layer is greater than the stress in the initial stress layer.

[0062] When the initial stress layer has an initial tensile stress, the material of the initial stress layer includes silicon nitride or silicon oxynitride, and the silicon oxynitride includes silicon oxynitride.

[0063] When the initial stress layer has an initial compressive stress, the material of the initial stress layer includes silicon oxide or silicon carbide.

[0064] In this embodiment, the multiple stress layers are made of the same material. This allows for better control of the stress in each stress layer and accurate calculation of the number of stress layers to be formed.

[0065] In other embodiments, the materials of the multiple stress layers can not be exactly the same. This gives the stress-neutralizing structure greater freedom in material selection.

[0066] In this embodiment, the thickness of the multiple stress layers is the same. This allows for better control of the stress in each stress layer and accurate calculation of the number of stress layers to be formed.

[0067] In other embodiments, the thicknesses of the multiple stress layers are not entirely the same. This allows for a large process window for the formation of the stress-neutralizing structure, eliminating the need for each stress layer to have the same thickness.

[0068] Please refer to Figure 3 The non-functional surface S2 is subjected to a first stress neutralization treatment, and a first stress layer 102 is formed on the non-functional surface S2.

[0069] The method for forming the first stress layer 102 includes: forming an initial stress layer on the surface of the non-functional surface S2; and performing stress enhancement treatment on the initial stress layer to form the first stress layer 102.

[0070] The material of the initial stress layer includes silicon nitride or silicon oxynitride.

[0071] In this embodiment, the initial stress layer is made of silicon nitride. The material of the initial stress layer has initial tensile stress, which can neutralize the compressive stress on the surface of the non-functional surface S2, improving wafer warpage.

[0072] The initial stress layer has an initial tensile stress, and the process for stress-enhancing the initial stress layer includes a plasma treatment process, wherein the gas used in the plasma treatment process is of the same type as at least one of the reaction gases that form the initial stress layer.

[0073] The gas used in the plasma treatment process is at least one type of the same as the reactive gas used to form the initial stress layer. This ensures that no other types of gaseous impurities are introduced during the stress enhancement treatment of the initial stress layer, which is beneficial for increasing the stress of the formed stress layer, making the stress of the stress layer greater than that of the initial stress layer.

[0074] In this embodiment, the gas used in the plasma processing for stress enhancement of the initial stress layer includes nitrogen.

[0075] The plasma treatment process for stress-enhancing the initial stress layer uses nitrogen gas. The nitrogen-containing plasma provides sufficient energy to open the Si-H and NH bonds in the silicon nitride film. This process allows hydrogen to be eliminated, and the resulting Si-N bonds enhance the stress in the silicon nitride.

[0076] In this embodiment, the process for forming the initial stress layer includes plasma-enhanced chemical vapor deposition (PECVD).

[0077] The process parameters of the plasma-enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia, and nitrogen, the flow rate of silane in the total flow rate ranges from 15% to 25%, the flow rate of ammonia in the total flow rate ranges from 25% to 35%, and the flow rate of nitrogen in the total flow rate ranges from 45% to 55%; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 to 8 tors; and the power range is 200 watts to 300 watts.

[0078] The nitrogen gas used in the plasma treatment process is the same type of nitrogen gas used in the plasma-enhanced chemical vapor deposition process. Therefore, no new impurities are introduced when using the plasma treatment process to enhance the stress of the initial stress layer.

[0079] In this embodiment, the reaction time of the plasma treatment process includes 40 seconds to 80 seconds.

[0080] When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, wherein the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0081] In this embodiment, the first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

[0082] The thickness range of the single-layer initial stress layer is set according to the warpage of the wafer. The initial stress layer is relatively thin, so plasma treatment can significantly enhance the stress of the thin initial stress layer film, thereby increasing the stress of the first stress layer 102.

[0083] Please refer to Figure 4 A second stress neutralization treatment is performed on the surface of the non-functional surface S2 to form a second stress layer 103 on the surface of the first stress layer 102.

[0084] The method for forming the second stress layer 103 includes: forming an initial stress layer on the surface of the first stress layer 102; and performing stress enhancement treatment on the initial stress layer to form the second stress layer 103.

[0085] The process for stress-enhancing the initial stress layer includes a plasma treatment process, wherein the gas used in the plasma treatment process is of the same type as at least one of the reaction gases that form the initial stress layer.

[0086] The gas used in the plasma treatment process is at least one type of the same as the reactive gas used to form the initial stress layer. This ensures that no other types of gaseous impurities are introduced during the stress-enhancing treatment of the initial stress layer, which is beneficial for increasing the stress of the formed stress layer.

[0087] In this embodiment, the initial stress layer is made of silicon nitride. The silicon nitride material has initial tensile stress, which can neutralize the compressive stress on the non-functional surface S2, improving wafer warpage. The plasma processing for stress-enhancing the initial stress layer uses nitrogen gas. The nitrogen-containing plasma provides sufficient energy to open the Si-H and NH bonds in the silicon nitride film. This process allows hydrogen to be eliminated, and the resulting Si-N bonds enhance the stress in the silicon nitride.

[0088] In this embodiment, the process for forming the initial stress layer includes plasma-enhanced chemical vapor deposition (PECVD).

[0089] The process parameters of the plasma-enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia, and nitrogen, the flow rate of silane in the total flow rate ranges from 15% to 25%, the flow rate of ammonia in the total flow rate ranges from 25% to 35%, and the flow rate of nitrogen in the total flow rate ranges from 45% to 55%; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 to 8 torr; and the power range is 200 watts to 300 watts.

[0090] The nitrogen gas used in the plasma treatment process is the same type of nitrogen gas used in the plasma-enhanced chemical vapor deposition process. Therefore, no new impurities are introduced when using the plasma treatment process to enhance the stress of the initial stress layer.

[0091] In this embodiment, the reaction time of the plasma treatment process includes 40 to 80 seconds.

[0092] In this embodiment, only the process of two stress neutralization treatments is illustrated. The stress neutralization structure includes a first stress layer 102 and a second stress layer 103 on the surface of the first stress layer 102.

[0093] In other embodiments, the stress neutralization process may include one or more steps until the resulting stress neutralization structure brings the wafer warpage within a preset range.

[0094] In this embodiment, the first stress layer 102 and the second stress layer 103 are made of the same material. In other embodiments, the first stress layer and the second stress layer may be made of different materials.

[0095] In this embodiment, the first stress layer 102 and the second stress layer 103 have the same thickness.

[0096] In other embodiments, the thicknesses of the first stress layer and the second stress layer may be different.

[0097] When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, wherein the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

[0098] In this embodiment, the first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

[0099] The thickness range of the single-layer initial stress layer is set according to the warpage of the wafer. The initial stress layer is relatively thin, so plasma treatment can significantly enhance the stress of the thin initial stress layer film, thereby increasing the stress of the second stress layer 103.

[0100] Please refer to Figure 5 After forming a stress-neutralizing structure, the warpage of the wafer 100 is obtained, and the warpage of the wafer is within a preset range.

[0101] In this embodiment, the preset range includes: less than or equal to 20 micrometers.

[0102] Figure 6 This is a schematic diagram of the formation process of a semiconductor structure in another embodiment of the present invention.

[0103] Please refer to Figure 6 , Figure 6 Semiconductor structure and Figure 3 The difference in the semiconductor structure is that, in this embodiment, the wafer is bent toward the functional surface, and the initial stress layer has an initial compressive stress; the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

[0104] Based on the warping, the non-functional surface is subjected to at least one stress neutralization treatment to form a stress neutralization structure. The stress neutralization structure includes at least one stress layer. The stress neutralization treatment includes: forming an initial stress layer on the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer.

[0105] In this embodiment, it is illustrated that a stress neutralization treatment is performed on the surface of the non-functional surface S2 to form a stress layer 202 on the surface of the non-functional surface S2.

[0106] The method for forming the stress layer 202 includes: forming an initial stress layer on the surface of the non-functional surface S2; and performing stress enhancement treatment on the initial stress layer to form the stress layer 202.

[0107] The material of the initial stress layer includes silicon oxide or silicon carbide.

[0108] In this embodiment, the initial stress layer is made of silicon oxide. The initial stress layer material has initial compressive stress, which can neutralize the tensile stress on the non-functional surface S2, improving wafer warpage.

[0109] The process for stress-enhancing the initial stress layer includes: ion implantation.

[0110] In this embodiment, the implanted ions in the ion implantation process include nitrogen ions. Doping silicon oxide with nitrogen (forming SiOxNγ silicon oxynitride) effectively increases compressive stress because the Si-O bonds in silicon oxide are relatively long and have low bond energies. However, when nitrogen is incorporated into silicon oxide, the Si-N bonds are shorter and stronger than the Si-O bonds. This change in chemical bonding makes the overall network structure of the material denser, increasing the material's shrinkage and thus introducing higher intrinsic compressive stress. The shorter bond length of the Si-N bonds compared to the Si-O bonds causes the lattice structure to tend to compress during deposition or growth, and this compressibility naturally leads to the intrinsic compressive stress exhibited in the silicon oxynitride film.

[0111] In this embodiment, the process for forming the initial stress layer includes plasma-enhanced chemical vapor deposition (PECVD).

[0112] In this embodiment, Figure 6 The diagram illustrates only one stress neutralization process, and the stress neutralization structure includes a stress layer 202.

[0113] In other embodiments, the stress neutralization process may include multiple steps, and the stress neutralization structure may include multiple stress layers, until the formed stress neutralization structure brings the warpage of the wafer within a preset range.

[0114] In one embodiment, the multiple stress layers are made of the same material. This allows for better control of the stress in each stress layer and accurate calculation of the number of stress layers to be formed.

[0115] In other embodiments, the materials of the multiple stress layers can not be exactly the same. This gives the stress-neutralizing structure greater freedom in material selection.

[0116] In one embodiment, the multiple stress layers have the same thickness. This allows for better control of the stress in each stress layer and accurate calculation of the number of stress layers to be formed.

[0117] In other embodiments, the thicknesses of the multiple stress layers are not entirely the same. This allows for a large process window for the formation of the stress-neutralizing structure, eliminating the need for each stress layer to have the same thickness.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A wafer is provided, the wafer including functional and non-functional surfaces; A functional layer structure is formed on the surface of the functional surface; The warpage of the wafer is obtained, and the warpage of the wafer includes: the wafer bending towards a non-functional surface, or the wafer bending towards a functional surface; Based on the described warping, the non-functional surface is subjected to... At least one stress neutralization treatment is performed to form a stress neutralization structure, the stress neutralization structure including at least one stress layer, the stress neutralization treatment including: forming an initial stress layer on the surface of the non-functional surface; and performing a stress enhancement treatment on the initial stress layer to form the stress layer; When the wafer is bent toward the functional surface, the process of stress-enhancing the initial stress layer includes: ion implantation process; When the wafer is bent toward the non-functional surface, the process for stress-enhancing the initial stress layer includes: plasma treatment.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the wafer bends toward the functional surface, the initial stress layer has an initial compressive stress; the compressive stress of the stress layer is greater than the initial compressive stress of the initial stress layer.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the initial stress layer includes silicon oxide or silicon carbide.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The implanted ions in the ion implantation process include nitrogen ions.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the wafer bends toward the non-functional surface, the initial stress layer has an initial tensile stress; the tensile stress of the stress layer is greater than the initial tensile stress of the initial stress layer.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The gas used in the plasma processing is of the same type as at least one of the reactive gases used to form the initial stress layer.

7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The material of the initial stress layer includes silicon nitride or silicon oxynitride, wherein the silicon oxynitride includes silicon oxynitride.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gas used in the plasma treatment process for stress enhancement of the initial stress layer includes nitrogen.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The reaction time of the plasma treatment process includes 40 to 80 seconds.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the initial stress layer includes plasma-enhanced chemical vapor deposition.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, When the initial stress layer material includes silicon nitride, the process parameters of the plasma-enhanced chemical vapor deposition process include: the reaction gases include silane, ammonia, and nitrogen, the flow rate of silane in the total flow rate ranges from 15% to 25%, the flow rate of ammonia in the total flow rate ranges from 25% to 35%, and the flow rate of nitrogen in the total flow rate ranges from 45% to 55%; the temperature range is 375 degrees Celsius to 425 degrees Celsius; the pressure range is 6 to 8 torr; and the power range is 200 watts to 300 watts.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, When the wafer warpage is within a first preset range, the initial stress layer has a first thickness; when the wafer warpage is within a second preset range, the initial stress layer has a second thickness, wherein the first preset range is smaller than the second preset range, and the first thickness is smaller than the second thickness.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The first preset range is 50 micrometers to 100 micrometers, and the first thickness is 15 angstroms to 25 angstroms; the first preset range is greater than 100 micrometers, and the second thickness is 25 angstroms to 35 angstroms.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the multiple stress layers are the same.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The materials of the multiple stress layers are not entirely the same.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the multiple stress layers is the same.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thicknesses of the multiple stress layers are not entirely the same.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before forming a stress-neutralizing structure on the non-functional surface, the method further includes forming a protective layer on the surface of the functional layer structure.

19. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming a stress-neutralizing structure also includes: obtaining the warpage of the wafer, wherein the warpage of the wafer is within a preset range.

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