3DIC photoelectric integrated semiconductor packaging structure and preparation method thereof

Abstract

The invention provides a preparation method of a 3DIC photoelectric integrated semiconductor packaging structure, and the method comprises the steps: carrying out the integrated packaging of an optical chip module, a 3D stacked chip and a horizontal storage chip through a TSV substrate, a rewiring layer, a first electric chip, a second electric chip, a dielectric layer and a conductive column, enabling the optical chip module to be connected with the 3D stacked chip through the first electric chip, enabling the optical chip module to be connected with the 3D stacked chip through the second electric chip, and enabling the optical chip module to be connected with the horizontal storage chip through the second electric chip; and the 3D stacked chip is connected with the horizontal storage chip through the second electric chip, so that short-distance connection between the optical integrated circuit and the electric integrated circuit is realized, the transmission distance of photoelectric signals is greatly reduced, the packaging area is reduced, the power consumption is reduced, and high-density integrated packaging of the photoelectric chip is met.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and relates to a 3DIC optoelectronic integrated semiconductor packaging structure and a preparation method thereof. Background Art

[0002] With the rapid development of information technology and the sharp increase in data traffic, integrated circuit packaging technology is moving towards low cost, high reliability, fast transmission and high-density circuits. The demand for data center interconnection bandwidth will continue to grow at an exponential rate. It is predicted that by 2030, data center energy consumption will continue to grow, and the global data center power consumption will exceed 3PWh, and in the worst case it may be as high as 8PWh. In order to meet the demand for Internet traffic, the bandwidth of data center nodes needs to reach 10Tb / s. In order to slow down the trend of data center energy consumption growth, it is necessary to find ways to reduce the power consumption of systems and devices.

[0003] The number of input / output (I / O) pins of each package structure doubles almost every 6 years, and the total I / O bandwidth doubles every 3 to 4 years. To solve the rate difference between the number of pins and the bandwidth, the I / O bandwidth needs to be increased. Light has the characteristics of low signal attenuation, low energy consumption, high bandwidth and compatibility with CMOS, which can directly affect the bandwidth and energy consumption of I / O. Therefore, in order to increase the I / O bandwidth and minimize energy consumption, it is necessary to introduce silicon photonics technology. Among them, the integration of light and electricity is crucial. How to combine and package optical integrated circuits (PICs) and electrical integrated circuits (EICs) is an urgent problem to be solved.

[0004] Most existing optoelectronic integrated semiconductor packaging structures directly bond the optical integrated chip and the electrical integrated chip to the substrate, and electrically connect them to the substrate through wire-bonds or flip-chip bonding. The direct signal transmission distance between the PIC and the EIC is too long.

[0005] Therefore, how to provide a 3DIC optoelectronic integrated semiconductor packaging structure and its preparation method to achieve high-density integrated packaging of optical chips and electrical chips, shorten the transmission distance of each module, and reduce transmission power consumption has become an important problem that technical personnel in this field need to solve urgently.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a 3DIC optoelectronic integrated semiconductor packaging structure and a preparation method thereof, so as to solve the problems in the prior art that it is difficult to integrate optical chips and electrical chips into high-density packaging and the transmission distance of each module is too long.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a 3DIC optoelectronic integrated semiconductor packaging structure, comprising the following steps:

[0009] Providing a TSV substrate, forming a first rewiring layer on a first surface of the TSV substrate, wherein a TSV metal column is disposed in the TSV substrate, a top of the TSV metal column is exposed on the first surface of the TSV substrate, and the first rewiring layer is electrically connected to the TSV metal column;

[0010] Providing a first electrical chip and a second electrical chip, and bonding the first electrical chip and the second electrical chip to the first rewiring layer so that the first electrical chip and the second electrical chip are electrically connected to the first rewiring layer respectively;

[0011] forming a dielectric layer covering the first electrical chip and the second electrical chip on the first rewiring layer;

[0012] Forming a conductive column in the dielectric layer, the conductive column penetrating the dielectric layer to be electrically connected to the first rewiring layer, and thinning the dielectric layer to expose the conductive column, the first electrical chip, and the second electrical chip;

[0013] forming a second rewiring layer on the dielectric layer, wherein the second rewiring layer is electrically connected to the top of the conductive column;

[0014] providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate;

[0015] Thinning the TSV substrate to expose the bottom end of the TSV metal column, forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected to the TSV metal column;

[0016] forming a metal bump on the third rewiring layer, wherein the metal bump is electrically connected to the third rewiring layer;

[0017] Providing a second supporting substrate, bonding the metal bump to the second supporting substrate, and removing the first supporting substrate;

[0018] An optical chip module, a 3D stacked chip and a horizontal memory chip are provided, and the optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the second rewiring layer, the optical chip module, the 3D stacked chip and the first electrical chip are electrically connected through the second rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal memory chip and the second electrical chip are connected through the second rewiring layer to form an electrical integrated circuit.

[0019] Optionally, after bonding the first electrical chip and the second electrical chip to the first rewiring layer, the method further includes thinning the first electrical chip and the second electrical chip.

[0020] Optionally, after bonding the optical chip module, the 3D stacked chip and the horizontal memory chip to the second rewiring layer, the method further includes removing the second supporting substrate.

[0021] Optionally, the method for forming the first rewiring layer includes a Damascene process, the method for forming the second rewiring layer includes a Damascene process, and the method for forming the third rewiring layer includes a Damascene process.

[0022] Optionally, a vertical projection of the optical chip module on the second re-wiring layer at least partially overlaps with a vertical projection of the first electrical chip on the second re-wiring layer.

[0023] Optionally, the first electrical chip comprises an ASIC chip, and the ASIC chip is used to convert the electrical signal of the 3D stacked chip into an optical signal.

[0024] Optionally, the method further includes forming a filling layer in gaps between the optical chip module, the 3D stacked chip, the horizontal memory chip and the second rewiring layer.

[0025] Optionally, after bonding the 3D stacked chip to the second rewiring layer, the method further includes bonding a backplane power supply chip to the 3D stacked chip, wherein the backplane power supply chip is electrically connected to the 3D stacked chip.

[0026] Optionally, the 3D stacked chip includes a logic chip and a memory chip, and the memory chip is located on the logic chip and electrically connected to the logic chip.

[0027] Optionally, before forming the second rewiring layer on the dielectric layer, the method further includes forming a first heat dissipation layer on the upper surface of the first electrical chip and / or forming a second heat dissipation layer on the upper surface of the second electrical chip.

[0028] Optionally, the number of the horizontal storage chips is one or more, and the number of the second electrical chips is one or more.

[0029] The present invention also provides a 3DIC optoelectronic integrated semiconductor packaging structure, comprising:

[0030] A TSV substrate, wherein a TSV metal column is provided in the TSV substrate, a top end of the TSV metal column is exposed on a first surface of the TSV substrate, and a bottom end of the TSV metal column is exposed on a second surface of the TSV substrate;

[0031] A first rewiring layer, located on a first surface of the TSV substrate and electrically connected to the TSV metal pillar;

[0032] A first electrical chip and a second electrical chip are bonded to the first rewiring layer and are electrically connected to the first rewiring layer respectively;

[0033] a dielectric layer, located on the first rewiring layer and surrounding the first electrical chip and the second electrical chip;

[0034] A conductive column, penetrating the dielectric layer and electrically connected to the first rewiring layer;

[0035] a second rewiring layer, located on the dielectric layer and electrically connected to the conductive pillar;

[0036] A third rewiring layer, located on the second surface of the TSV substrate and electrically connected to the bottom end of the TSV metal column;

[0037] a metal bump, located on the third rewiring layer and electrically connected to the third rewiring layer;

[0038] The optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the second rewiring layer. The optical chip module, the 3D stacked chip and the first electrical chip are electrically connected through the second rewiring layer to form an optical integrated circuit. The 3D stacked chip, the horizontal memory chip and the second electrical chip are connected through the second rewiring layer to form an electrical integrated circuit.

[0039] Optionally, a vertical projection of the optical chip module on the second re-wiring layer at least partially overlaps with a vertical projection of the first electrical chip on the second re-wiring layer.

[0040] Optionally, the first electrical chip comprises an ASIC chip, and the ASIC chip converts the electrical signal of the 3D stacked chip into an optical signal.

[0041] Optionally, a filling layer is further included, and the filling layer is located in the gap between the optical chip module, the 3D stacked chip, the horizontal memory chip and the second rewiring layer.

[0042] Optionally, a backplane power supply chip is further included, wherein the backplane power supply chip is bonded to the 3D stacked chip and electrically connected to the 3D stacked chip.

[0043] Optionally, the 3D stacked chip includes a logic chip and a memory chip, and the memory chip is located on the logic chip and electrically connected to the logic chip.

[0044] Optionally, a first heat dissipation layer and / or a second heat dissipation layer are further included, wherein the first heat dissipation layer is located on the upper surface of the first electric chip, and the second heat dissipation layer is located on the upper surface of the second electric chip.

[0045] Optionally, the number of the horizontal storage chips is one or more, and the number of the second electrical chips is one or more.

[0046] As described above, the 3DIC optoelectronic integrated semiconductor packaging structure and preparation method thereof of the present invention, through the TSV substrate, the rewiring layer, the first electrical chip, the second electrical chip, the dielectric layer and the conductive column, the optical chip module, the 3D stacked chip and the horizontal storage chip are collectively packaged, wherein the optical chip module is connected to the 3D stacked chip through the first electrical chip, and the 3D stacked chip is connected to the horizontal storage chip through the second electrical chip, thereby realizing the short-distance connection between the optical integrated circuit and the electrical integrated circuit, thereby greatly reducing the transmission distance of the optoelectronic signal, reducing the packaging area, reducing the power consumption, and meeting the high-density integrated packaging of the optoelectronic chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Shown is a schematic diagram of an optoelectronic integrated semiconductor packaging structure.

[0048] Figure 2 Shown is a process flow chart of a method for preparing a 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0049] Figure 3 It is a schematic diagram of the structure after the first rewiring layer is formed in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0050] Figure 4 It is a schematic diagram of the structure after bonding the first electric chip and the second electric chip in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0051] Figure 5It is a schematic diagram of the structure after grinding the first electric chip and the second electric chip in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0052] Figure 6 It is a schematic diagram of the structure after forming a dielectric layer in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0053] Figure 7 It is a schematic structural diagram showing the formation of conductive pillars in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0054] Figure 8 It is a schematic diagram of the structure after grinding the medium layer in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0055] Fig. 9 It is a schematic diagram of the structure after the second rewiring layer is formed in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0056] Fig.10 It is a schematic structural diagram showing the formation of a first supporting substrate in the method for preparing a 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0057] Fig.11 It is a schematic diagram of the structure after grinding the TSV substrate and forming the third rewiring layer in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0058] Fig.12 It is a schematic diagram of the structure after metal bumps are formed in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0059] Fig.13 It is a schematic diagram of the structure after forming the second supporting substrate in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0060] Fig.14 It is a schematic diagram of the structure after removing the first supporting substrate in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0061] Fig.15 It is a schematic structural diagram showing the bonding of the optical module chip, the 3D stacked chip and the horizontal memory chip on the second rewiring layer in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0062] Fig.16It is a schematic diagram of the structure after the backplane power supply chip is bonded to the 3D stacked chip in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0063] Fig.17 It is a schematic diagram of the structure after removing the second supporting substrate in the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0064] Description of Reference Numerals

[0065] 11 System board

[0066] 12 Electric Chip

[0067] 121 Substrate

[0068] 122 Logic Chip

[0069] 123 HBM chip

[0070] 13 Optical chip module

[0071] 131 Substrate

[0072] 132 ASIC chips

[0073] 133 Optical Chip

[0074] 21 TSV substrate

[0075] 22 TSV metal pillars

[0076] 23 First rewiring layer

[0077] 24 First Electric Chip

[0078] 25 Second Electric Chip

[0079] 26 Dielectric layer

[0080] 27 Conductive column

[0081] 28 Second rewiring layer

[0082] 29 First heat dissipation layer

[0083] 210 Second heat dissipation layer

[0084] 211 first supporting substrate

[0085] 212 First separation layer

[0086] 213 Third rewiring layer

[0087] 214 metal bumps

[0088] 215 second supporting substrate

[0089] 216 Second separation layer

[0090] 217 Optical chip module

[0091] 218 3D stacked chips

[0092] 2181 Logic Chip

[0093] 2182 Memory Chip

[0094] 219 Horizontal Memory Chip

[0095] 220 Filling layer

[0096] 221 Backplane Power Supply Chip

[0097] Steps S1 to S10 DETAILED DESCRIPTION

[0098] See also Figure 1 , showing a schematic diagram of an optoelectronic integrated semiconductor packaging structure, the optoelectronic integrated semiconductor packaging structure includes a system board 11, an electric chip 12 and an optical chip module 13, wherein the electric chip 12 and the optical chip module 13 are both electrically connected to the system board. The electric chip 12 includes a logic chip 122 and an HBM chip 123, wherein the Chinese full name of HBM is High Bandwidth Memory, and the HBM chip 123 is connected to the logic chip 122 through a substrate 121, and the optical chip module 13 includes an ASIC chip 132 and an optical chip 133, wherein the Chinese full name of ASIC is Application Specific Integrated Circuit, and the English full name is Application Specific Integrated Circuit, and the ASIC chip 132 is connected to the optical chip 133 through a substrate 131. It can be seen that in the optoelectronic integrated semiconductor packaging structure, the electric chip 12 needs to be connected to the optical chip module 13 through the system board 11, so that the transmission distance between the optoelectronic signals is too long and the packaging area is large.

[0099] Through extensive analysis and research, the inventors of this application have proposed a 3DIC optoelectronic integrated semiconductor packaging structure and a preparation method thereof, which realizes a short-distance connection between an optical integrated circuit and an electrical integrated circuit, reduces the transmission distance of optoelectronic signals, reduces the packaging area, and reduces power consumption, thereby meeting the high-density integrated packaging of optoelectronic chips.

[0100] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0101] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0102] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0103] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0104] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0105] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0106] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0107] See also Figure 2, which is a process flow chart of a method for preparing a 3DIC optoelectronic integrated semiconductor packaging structure of the present invention, comprising the following steps:

[0108] S1: providing a TSV substrate, forming a first rewiring layer on a first surface of the TSV substrate, wherein a TSV metal column is provided in the TSV substrate, a top of the TSV metal column is exposed on the first surface of the TSV substrate, and the first rewiring layer is electrically connected to the TSV metal column;

[0109] S2: providing a first electrical chip and a second electrical chip, and bonding the first electrical chip and the second electrical chip to the first rewiring layer so that the first electrical chip and the second electrical chip are electrically connected to the first rewiring layer respectively;

[0110] S3: forming a dielectric layer covering the first electrical chip and the second electrical chip on the first rewiring layer;

[0111] S4: forming a conductive column in the dielectric layer, wherein the conductive column penetrates the dielectric layer to be electrically connected to the first rewiring layer, and thinning the dielectric layer to expose the conductive column, the first electrical chip, and the second electrical chip;

[0112] S5: forming a second rewiring layer on the dielectric layer, wherein the second rewiring layer is electrically connected to the top of the conductive pillar;

[0113] S6: providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate;

[0114] S7: thinning the TSV substrate to expose the bottom end of the TSV metal column, forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected to the TSV metal column;

[0115] S8: forming a metal bump on the third rewiring layer, wherein the metal bump is electrically connected to the third rewiring layer;

[0116] S9: providing a second supporting substrate, bonding the metal bump to the second supporting substrate, and removing the first supporting substrate;

[0117] S10: Provide an optical chip module, a 3D stacked chip and a horizontal memory chip, bond the optical chip module, the 3D stacked chip and the horizontal memory chip on the second rewiring layer, the optical chip module, the 3D stacked chip and the first electrical chip are electrically connected through the second rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal memory chip and the second electrical chip are connected through the second rewiring layer to form an electrical integrated circuit.

[0118] The following will be combined Figures 3 to 17 , detailing the various steps of the method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention.

[0119] First see Figure 3 , perform step S1: provide a TSV substrate 21, form a first rewiring layer 23 on the first surface of the TSV substrate 21, a TSV metal column 22 is provided in the TSV substrate 21, the first surface of the TSV substrate 21 exposes the top of the TSV metal column 22, and the first rewiring layer 23 is electrically connected to the TSV metal column 22.

[0120] As an example, the TSV substrate 21 may include a wafer-level substrate of a size of 4 inches, 6 inches, 8 inches, 12 inches, etc., to further improve process efficiency, but the size of the TSV substrate 21 is not limited thereto.

[0121] As an example, the first rewiring layer 23 may be a rewiring layer using a Damascus process, including a dielectric layer and metal wiring embedded in the dielectric layer, wherein the material of the dielectric layer may include silicon oxide or silicon nitride, etc., and the material of the metal wiring may include copper, aluminum, etc. A smaller line width and line spacing can be obtained through the first rewiring layer 23 to meet subsequent high-density connection requirements. The material, number of layers, layout, preparation method, etc. of the first rewiring layer 23 can be selected as needed, and no excessive restrictions are made here.

[0122] Please refer to Figure 4 , execute the step S2: provide a first electrical chip 24 and a second electrical chip 25, and bond the first electrical chip 24 and the second electrical chip 25 to the first rewiring layer 23 so that the first electrical chip 24 and the second electrical chip 25 are electrically connected to the first rewiring layer 23 respectively.

[0123] As an example, the first electrical chip 24 includes an ASIC chip, and the ASIC chip can be used to stack the subsequent 3D chip 218 (such as Fig.15 ) is converted into an optical signal, but the type of the first electrical chip 24 is not limited thereto and can be selected according to needs.

[0124] As an example, the bonding replaces the traditional bump or solder ball interconnection by direct copper-to-copper connection, which can simplify the bonding interconnection process, reduce the size of the stack and package, reduce the power of the interconnection channel, and improve the heat dissipation capability.

[0125] As an example, see Figure 5After bonding the first electric chip 24 and the second electric chip 25 to the first rewiring layer 23, the step of thinning the first electric chip 24 and the second electric chip 25 is also included. Mechanical grinding, chemical mechanical grinding, plasma dry chemical etching and other processes can be used to thin the first electric chip 24 and the second electric chip 25 to facilitate subsequent processes. No excessive limitations are made here. In this embodiment, a mechanical grinding process is used to achieve a smooth ground surface. The thinning of the first electric chip 24 and the second electric chip 25 can shorten the transmission distance and reduce the thickness of the package.

[0126] Please see again Figure 6 , executing the step S3: forming a dielectric layer 26 covering the first electrical chip 24 and the second electrical chip 25 on the first rewiring layer 23 .

[0127] As an example, the material of the dielectric layer 26 may be silicon oxide, but is not limited thereto. Inorganic materials such as silicon nitride or aluminum oxide may also be used as required, and no excessive restrictions are imposed herein.

[0128] Please see again Figures 7 and 8 , performing the step S4: forming a conductive column 27 in the dielectric layer 26, the conductive column 27 penetrates the dielectric layer 26 to be electrically connected to the first rewiring layer 23, thinning the dielectric layer 26 to expose the conductive column 27, the first electrical chip 24 and the second electrical chip 25, wherein, Figure 7 It is a schematic diagram showing the structure obtained after forming the conductive pillar 27. Figure 8 It is a schematic diagram showing the structure obtained after the dielectric layer 26 is thinned.

[0129] As an example, forming the conductive column 27 may include the steps of forming a through hole (not shown) penetrating the dielectric layer 26, and the step of filling the through hole with metal. The punching method may include a laser punching method or a mechanical drilling method, which may be selected according to needs, and the method of filling the metal may be an electroplating method, etc. The specific steps for preparing the conductive column 27, the size of the conductive column 27, and the distribution of the conductive column 27 are not overly restricted here, and may be selected according to needs. The material of the conductive column 27 may be copper metal, but is not limited thereto, and other conductive metal materials may also be used.

[0130] As an example, mechanical grinding, chemical mechanical grinding, plasma dry chemical etching or other suitable processes can be used to thin the dielectric layer 26 to expose the conductive pillars 27, the first electrical chip 24 and the second electrical chip 25. No excessive limitations are made here. In this embodiment, a chemical mechanical grinding process is used to obtain a relatively flat surface to facilitate subsequent processes.

[0131] Please see again Fig. 9 , executing the step S5: forming a second rewiring layer 28 on the dielectric layer 26 , wherein the second rewiring layer 28 is electrically connected to the top of the conductive pillar 27 .

[0132] As an example, the second rewiring layer 28 may be a rewiring layer using a Damascus process, including a dielectric layer and metal wiring embedded in the dielectric layer, wherein the material of the dielectric layer may include silicon oxide or silicon nitride, etc., and the material of the metal wiring may include copper, aluminum, etc. The material, number of layers, layout, preparation method, etc. of the second rewiring layer 28 can be selected as needed, and no excessive restrictions are made here.

[0133] As an example, before forming the second rewiring layer 28 on the dielectric layer 26, a step of forming a first heat dissipation layer 29 on the upper surface of the first electric chip 24 and / or a second heat dissipation layer 210 on the upper surface of the second electric chip 25 can be performed to improve the heat dissipation capability and reduce power consumption. In this embodiment, a metal layer, preferably a copper layer, is electroplated on the invalid area (area without electrical connection) on the back of the first electric chip 24 and the second electric chip 25 to conduct heat for the first electric chip 24 and the second electric chip 25.

[0134] Please see again Fig.10 , perform the step S6: provide a first supporting substrate 211 , and bond the second rewiring layer 28 to the first supporting substrate 211 .

[0135] As an example, the first supporting substrate 211 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so that the first supporting substrate 211 can provide support for the subsequent preparation process. In order to facilitate the subsequent removal of the first supporting substrate 211, in this embodiment, a first separation layer 212 is preferably formed on the surface of the first supporting substrate 211, and the first separation layer 212 includes but is not limited to one of a tape and a polymer layer. For example, the first separation layer 212 can selectively use a photothermal conversion layer, so that the first separation layer 212 can be subsequently heated by, for example, laser to separate the first supporting substrate 211 from the second rewiring layer 28, thereby improving the convenience of operation.

[0136] Please see again Fig.11 , perform the step S7: thinning the TSV substrate 21 to expose the bottom end of the TSV metal column 22, forming a third rewiring layer 213 on the second surface of the TSV substrate 21, and the third rewiring layer 213 is electrically connected to the TSV metal column 22.

[0137] As an example, a chemical mechanical polishing process may be used to expose the bottom end of the TSV metal column 22 and provide the TSV substrate 21 with a relatively flat surface to facilitate subsequent processes. Of course, only a process such as mechanical polishing may be used to expose the TSV metal column 22, and no further limitations are given here.

[0138] As an example, the third rewiring layer 213 may be a rewiring layer using a Damascus process, including a dielectric layer and metal wiring embedded in the dielectric layer, wherein the material of the dielectric layer may include silicon oxide or silicon nitride, etc., and the material of the metal wiring may include copper, aluminum, etc. The material, number of layers, layout, preparation method, etc. of the third rewiring layer 213 can be selected as needed, and no excessive restrictions are made here.

[0139] Please see again Fig.12 , executing step S8: forming a metal bump 214 on the third re-distribution layer 213 , wherein the metal bump 214 is electrically connected to the third re-distribution layer 213 .

[0140] As an example, the metal bump 214 may be a C24 metal bump to facilitate subsequent electrical lead-out, but is not limited thereto and will not be excessively limited herein.

[0141] Please see again Figure 13 to Figure 14 , perform step S9: provide a second supporting substrate 215 , bond the metal bump 214 to the second supporting substrate 215 , and remove the first supporting substrate 211 . Figure 7 It is a schematic diagram showing a structure obtained after the metal bump 214 is bonded to the second supporting substrate 215. Figure 8 The schematic diagram shows the structure obtained after removing the first supporting substrate 211 .

[0142] As an example, the second supporting substrate 215 may include a glass substrate, a metal substrate, a semiconductor substrate, etc., so that the second supporting substrate 215 can provide support for the subsequent preparation process. In order to facilitate the subsequent removal of the second supporting substrate 215, in this embodiment, a second separation layer 216 is preferably formed on the surface of the second supporting substrate 215. The second separation layer 216 includes but is not limited to one of a tape and a polymer layer. For example, the second separation layer 216 can selectively use a photothermal conversion layer, so that the second separation layer 216 can be subsequently heated by, for example, a laser to separate the second supporting substrate 215 from the metal bump 214, thereby improving the convenience of operation.

[0143] Please see again Fig.15, execute the step S10: provide an optical chip module 217, a 3D stacked chip 218 and a horizontal storage chip 219, bond the optical chip module 217, the 3D stacked chip 218 and the horizontal storage chip 219 to the second rewiring layer 28, the optical chip module 217, the 3D stacked chip 218 and the first electrical chip 24 are electrically connected through the second rewiring layer 28 to form an optical integrated circuit, the 3D stacked chip 218, the horizontal storage chip 219 and the second electrical chip 25 are connected through the second rewiring layer 28 to form an electrical integrated circuit.

[0144] Specifically, the optical chip module 217 is electrically connected to the first electrical chip 24 through the second rewiring layer 28, the conductive pillar 27 and the first rewiring layer 23, and the first electrical chip 24 is electrically connected to the 3D stacked chip 218 through the first rewiring layer 23, the conductive pillar 27 and the second rewiring layer 28, thereby forming an optical integrated circuit, the 3D stacked chip 218 is electrically connected to the second electrical chip 25 through the second rewiring layer 28, the conductive pillar 27 and the first rewiring layer 23, and the second electrical chip 25 is electrically connected to the horizontal storage chip 219 through the first rewiring layer 23, the conductive pillar 27 and the second rewiring layer 28, thereby forming an electrical integrated circuit.

[0145] As an example, a vertical projection of the optical chip module 217 on the second re-wiring layer 28 at least partially overlaps with a vertical projection of the first electrical chip 24 on the second re-wiring layer 28 .

[0146] As an example, the vertical projection of the 3D stacked chip 218 on the second re-wiring layer 28 at least partially overlaps with the vertical projection of the first electrical chip 24 on the second re-wiring layer 28, and the vertical projection of the 3D stacked chip 218 on the second re-wiring layer 28 at least partially overlaps with the vertical projection of the second electrical chip 25 on the second re-wiring layer 28.

[0147] As an example, a vertical projection of the horizontal memory chip 219 on the second rewiring layer 28 at least partially overlaps with a vertical projection of the second electrical chip 25 on the second rewiring layer 28 .

[0148] As an example, the optical chip module 217, the 3D stacked chip 218 and the horizontal storage chip 219 are all electrically connected to the second rewiring layer 28 by inverted bonding. There are no excessive restrictions on the types of the optical chip module 217, the 3D stacked chip 218 and the horizontal storage chip 219.

[0149] As an example, a filling layer 220 for filling the gaps is formed between the optical chip module 217, the 3D stacked chip 218, the horizontal memory chip 219 and the second rewiring layer 28 to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas, etc. The material of the filling layer 220 can be selected as needed, and it can be an insulating material, and there is no excessive restriction here.

[0150] As an example, the 3D stacked chip 218 includes a logic chip 2181 and a memory chip 2182 . The memory chip 2182 is located on the logic chip 2181 and is electrically connected to the logic chip 2181 , that is, the memory chip is vertically expanded on the logic chip by using 3D stacking.

[0151] As an example, see Fig.16 , also includes the step of bonding the backplane power supply chip 221 to the 3D stacked chip 218, and the backplane power supply chip 221 is electrically connected to the 3D stacked chip 218.

[0152] As an example, see Fig.17 , further comprising the step of removing the second support substrate 215 , wherein the second support substrate 215 is removed based on the second separation layer 216 .

[0153] As an example, the number of the horizontal storage chips 219 is one or more, and the number of the second electrical chips 25 is one or more. The specific number may be determined according to the specific situation. No excessive restrictions are made here. Vertically stacking multiple layers of storage chips on the 3D stacked chip 218 is prone to cause insufficient heat dissipation problems. In this embodiment, the storage chip is horizontally expanded on the second rewiring layer 28 through the horizontal storage chip 219, so as to improve the storage performance without affecting the heat dissipation capability, thereby meeting the requirements of high performance and high computing power.

[0154] At this point, a 3DIC optoelectronic integrated semiconductor packaging structure is obtained. Fig.17The 3DIC optoelectronic integrated semiconductor packaging structure includes a TSV substrate 21, a first rewiring layer 23, a first electric chip 24, a second electric chip 25, a dielectric layer 26, a conductive column 27, a second rewiring layer 28, a third rewiring layer 213, a metal bump 214, an optical chip module 217, a 3D stacked chip 218 and a horizontal storage chip 219, wherein a TSV metal column 22 is provided in the TSV substrate 21, the first surface of the TSV substrate 21 exposes the top of the TSV metal column 22, and the second surface of the TSV substrate 21 exposes the bottom of the TSV metal column 22; the first rewiring layer 23 is located on the first surface of the TSV substrate 21 and is electrically connected to the TSV metal column 22; the first electric chip 24 and the second electric chip 25 are bonded to the first rewiring layer 23 and are electrically connected to the first rewiring layer 23 respectively; the dielectric layer 26 is located on the first rewiring layer 23 and surrounds the first electric chip 24 The conductive pillar 27 penetrates the dielectric layer 26 and is electrically connected to the first rewiring layer 23; the second rewiring layer 28 is located on the dielectric layer 26 and is electrically connected to the conductive pillar 27; the third rewiring layer 213 is located on the second surface of the TSV substrate 21 and is electrically connected to the bottom of the TSV metal pillar 22; the metal bump 214 is located on the third rewiring layer 213 and is electrically connected to the third rewiring layer 213; the optical chip module 217, the 3D stacked chip 218 and the horizontal storage chip 219 are bonded to the second rewiring layer 28, the optical chip module 217, the 3D stacked chip 218 and the first electrical chip 24 are electrically connected through the second rewiring layer 28 to form an optical integrated circuit, and the 3D stacked chip 218, the horizontal storage chip 219 and the second electrical chip 25 are connected through the second rewiring layer 28 to form an electrical integrated circuit.

[0155] As an example, the first rewiring layer 23 may be a rewiring layer using a damascene process, the second rewiring layer 28 may be a rewiring layer using a damascene process, and the third rewiring layer 213 may be a rewiring layer using a damascene process.

[0156] As an example, the first electrical chip 24 may be an ASIC chip, which is used to convert the electrical signal of the 3D stacked chip 218 into an optical signal.

[0157] As an example, a filling layer 220 is provided in the gaps between the optical chip module 217, the 3D stacked chip 218, the horizontal storage chip 219 and the second rewiring layer 28 to form a protective layer, improve the bonding strength, and avoid the influence of moisture, gas, etc.

[0158] As an example, a backplane power supply chip 221 may be further included, wherein the backplane power supply chip 221 is bonded to the 3D stacked chip 218 and electrically connected to the 3D stacked chip 218 .

[0159] As an example, the 3D stacked chip 218 includes a logic chip 2181 and a memory chip 2182 , and the 3D stacked chip 218 vertically expands the memory chip 2182 on the logic chip 2181 by using 3D stacking.

[0160] As an example, a first heat dissipation layer 29 is further provided on the upper surface of the first electronic chip 24 , and / or a second heat dissipation layer 210 is further provided on the upper surface of the second electronic chip 25 , so as to improve the heat dissipation capability.

[0161] As an example, the number of the horizontal storage chips 219 is one or more, and the number of the second electrical chips 25 is one or more. The specific number may be determined according to the specific situation and is not excessively limited here.

[0162] In summary, the preparation method of the 3DIC optoelectronic integrated semiconductor packaging structure of the present invention is to package the optical chip module, 3D stacked chip and horizontal storage chip collectively through the TSV substrate, the rewiring layer, the first electrical chip, the second electrical chip, the dielectric layer and the conductive column, wherein the optical chip module is connected to the 3D stacked chip through the first electrical chip, and the 3D stacked chip is connected to the horizontal storage chip through the second electrical chip, thereby realizing the short-distance connection between the optical integrated circuit and the electrical integrated circuit, thereby greatly reducing the transmission distance of the optoelectronic signal, reducing the packaging area, reducing power consumption, and meeting the high-density integrated packaging of the optoelectronic chip. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0163] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a 3DIC optoelectronic integrated semiconductor packaging structure, characterized in that: Providing a TSV substrate, forming a first rewiring layer on a first surface of the TSV substrate, wherein a TSV metal column is disposed in the TSV substrate, a top of the TSV metal column is exposed on the first surface of the TSV substrate, and the first rewiring layer is electrically connected to the TSV metal column; Providing a first electrical chip and a second electrical chip, and bonding the first electrical chip and the second electrical chip to the first rewiring layer so that the first electrical chip and the second electrical chip are electrically connected to the first rewiring layer respectively; forming a dielectric layer covering the first electrical chip and the second electrical chip on the first rewiring layer; Forming a conductive column in the dielectric layer, the conductive column penetrating the dielectric layer to be electrically connected to the first rewiring layer, and thinning the dielectric layer to expose the conductive column, the first electrical chip, and the second electrical chip; forming a second rewiring layer on the dielectric layer, wherein the second rewiring layer is electrically connected to the top of the conductive pillar; providing a first supporting substrate, and bonding the second rewiring layer to the first supporting substrate; Thinning the TSV substrate to expose the bottom end of the TSV metal column, forming a third rewiring layer on the second surface of the TSV substrate, wherein the third rewiring layer is electrically connected to the TSV metal column; forming a metal bump on the third rewiring layer, wherein the metal bump is electrically connected to the third rewiring layer; Providing a second supporting substrate, bonding the metal bump to the second supporting substrate, and removing the first supporting substrate; An optical chip module, a 3D stacked chip and a horizontal memory chip are provided, and the optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the second rewiring layer, the optical chip module, the 3D stacked chip and the first electrical chip are electrically connected through the second rewiring layer to form an optical integrated circuit, and the 3D stacked chip, the horizontal memory chip and the second electrical chip are connected through the second rewiring layer to form an electrical integrated circuit.

2. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: After bonding the first electrical chip and the second electrical chip to the first rewiring layer, the method further includes a step of thinning the first electrical chip and the second electrical chip.

3. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: After bonding the optical chip module, the 3D stacked chip and the horizontal memory chip to the second rewiring layer, the method further includes a step of removing the second supporting substrate.

4. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method of forming the first rewiring layer includes a damascene process, the method of forming the second rewiring layer includes a damascene process, and the method of forming the third rewiring layer includes a damascene process.

5. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: A vertical projection of the optical chip module on the second redistribution layer at least partially overlaps with a vertical projection of the first electrical chip on the second redistribution layer.

6. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The first electrical chip includes an ASIC chip, and the ASIC chip is used to convert the electrical signal of the 3D stacked chip into an optical signal.

7. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The method also includes the step of forming a filling layer in gaps between the optical chip module, the 3D stacked chip, the horizontal memory chip and the second rewiring layer.

8. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: After bonding the 3D stacked chip to the second rewiring layer, the method further includes bonding a backplane power supply chip to the 3D stacked chip, wherein the backplane power supply chip is electrically connected to the 3D stacked chip.

9. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The 3D stacked chip includes a logic chip and a memory chip, wherein the memory chip is located on the logic chip and is electrically connected to the logic chip.

10. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: Before forming the second rewiring layer on the dielectric layer, the method further includes forming a first heat dissipation layer on the upper surface of the first electrical chip and / or forming a second heat dissipation layer on the upper surface of the second electrical chip.

11. The method for preparing the 3DIC optoelectronic integrated semiconductor packaging structure according to claim 1, characterized in that: The number of the horizontal storage chips is one or more, and the number of the second electrical chips is one or more.

12. A 3DIC optoelectronic integrated semiconductor packaging structure, characterized in that: include: A TSV substrate, wherein a TSV metal column is provided in the TSV substrate, a top end of the TSV metal column is exposed on a first surface of the TSV substrate, and a bottom end of the TSV metal column is exposed on a second surface of the TSV substrate; A first rewiring layer, located on a first surface of the TSV substrate and electrically connected to the TSV metal pillar; A first electrical chip and a second electrical chip are bonded to the first rewiring layer and are electrically connected to the first rewiring layer respectively; a dielectric layer, located on the first rewiring layer and surrounding the first electrical chip and the second electrical chip; A conductive column, penetrating the dielectric layer and electrically connected to the first rewiring layer; a second rewiring layer, located on the dielectric layer and electrically connected to the conductive pillar; A third rewiring layer, located on the second surface of the TSV substrate and electrically connected to the bottom end of the TSV metal column; a metal bump, located on the third rewiring layer and electrically connected to the third rewiring layer; The optical chip module, the 3D stacked chip and the horizontal memory chip are bonded to the second rewiring layer. The optical chip module, the 3D stacked chip and the first electrical chip are electrically connected through the second rewiring layer to form an optical integrated circuit. The 3D stacked chip, the horizontal memory chip and the second electrical chip are connected through the second rewiring layer to form an electrical integrated circuit.

13. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: A vertical projection of the optical chip module on the second redistribution layer at least partially overlaps with a vertical projection of the first electrical chip on the second redistribution layer.

14. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: The first electrical chip includes an ASIC chip, and the ASIC chip converts the electrical signal of the 3D stacked chip into an optical signal.

15. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: It also includes a filling layer, which is located in the gap between the optical chip module, the 3D stacked chip, the horizontal memory chip and the second rewiring layer.

16. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: It also includes a backplane power supply chip, which is bonded to the 3D stacked chip and electrically connected to the 3D stacked chip.

17. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: The 3D stacked chip includes a logic chip and a memory chip, wherein the memory chip is located on the logic chip and is electrically connected to the logic chip.

18. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: It also includes a first heat dissipation layer and / or a second heat dissipation layer, wherein the first heat dissipation layer is located on the upper surface of the first electric chip, and the second heat dissipation layer is located on the upper surface of the second electric chip.

19. The 3DIC optoelectronic integrated semiconductor packaging structure according to claim 11, characterized in that: The number of the horizontal storage chips is one or more, and the number of the second electrical chips is one or more.

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