Optoelectronic system package structure and method of manufacturing the same

Abstract

The application provides an optoelectronic system packaging structure and a preparation method thereof. Through the setting of a 3D stacked logic storage module, a storage module, an optical module, a rewiring layer, a metal column, an ASIC chip and a TSV composite adapter plate, a complete optoelectronic system packaging structure can be formed, the transmission distance of each module is shorter, the signal transmission is faster, the transmission power consumption is effectively reduced, and the packaging area is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing and relates to a photoelectric system packaging structure and a preparation method thereof. Background Art

[0002] As global internet traffic grows, the demand for data center interconnect bandwidth will continue to grow exponentially. To meet this demand, data center node bandwidth must reach 10Tb / s. To mitigate the increasing energy consumption of data centers, it is imperative to find ways to reduce the power consumption of systems and devices. The goal of integrated circuit packaging is to achieve lower costs, greater reliability, faster speeds, and higher density circuits.

[0003] The number of input / output (I / O) pins in a package structure has been doubling roughly every six years, while the total I / O bandwidth has been doubling roughly every three to four years, resulting in a rate difference. Due to the advantages of optical technology, such as low signal attenuation, low energy consumption, high bandwidth, and CMOS compatibility, the industry generally believes that the integration of optical and electrical components with silicon photonics can reduce chip size, cost, and power consumption, while also improving reliability. Therefore, the introduction of silicon photonics technology is essential. The packaging of optical integrated circuits (PICs) and electrical integrated circuits (EICs) is crucial; improper integration of optical and electrical components can negate the potential advantages of silicon photonics.

[0004] Most existing optoelectronic integrated semiconductor packaging structures directly bond optical and electrical integrated chips to a substrate, electrically connecting them to the substrate through wire bonding or flip-chip bonding. However, this packaging method has drawbacks such as long transmission distance, high transmission power consumption, and large packaging area, making it difficult to meet the needs of high-density, high-performance integrated packaging.

[0005] Therefore, it is necessary to provide a photoelectric system packaging structure and a preparation method thereof. Summary of the Invention

[0006] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an optoelectronic system packaging structure and a preparation method thereof, so as to solve the problem that the prior art optoelectronic interconnect packaging is difficult to meet the requirements of high-density, high-performance integrated packaging.

[0007] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a photovoltaic system packaging structure, comprising the following steps:

[0008] providing a supporting substrate;

[0009] forming a metal pillar on the supporting substrate;

[0010] Providing an ASIC chip and a TSV composite adapter board, bonding the ASIC chip and the TSV composite adapter board to the supporting substrate, wherein the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, and the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board;

[0011] forming a packaging layer on the supporting substrate, wherein the packaging layer covers the ASIC chip, the TSV composite adapter plate, and the metal pillar, and exposes the metal pillar, the first connector, and the second connector;

[0012] forming a first redistribution layer on the packaging layer, wherein the first redistribution layer is electrically connected to the metal pillar, the first connector, and the second connector;

[0013] Providing a 3D stacked logic storage module, a storage module, and an optical module, and bonding the 3D stacked logic storage module, the storage module, and the optical module to the first rewiring layer, wherein the 3D stacked logic storage module, the storage module, and the optical module are all electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip, and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board, and the storage module are electrically connected;

[0014] removing the supporting substrate to expose the encapsulation layer;

[0015] forming a second redistribution layer on a surface of the packaging layer, wherein the second redistribution layer is electrically connected to the metal pillar;

[0016] A metal bump is formed on the second redistribution layer, and the metal bump is electrically connected to the second redistribution layer.

[0017] Optionally, the method further includes providing a substrate and bonding the substrate to the metal bump, and the substrate is electrically connected to the metal bump.

[0018] Optionally, the method further includes providing a heat sink and bonding the heat sink to the substrate.

[0019] Optionally, the 3D stacked logic memory module includes stacked interconnected memory chips and backside power supply logic chips, wherein the steps of preparing the 3D stacked logic memory module include:

[0020] providing a first semiconductor substrate;

[0021] forming a first transistor layer on the front surface of the first semiconductor substrate;

[0022] forming a first signal wiring layer on the first transistor layer, and the first signal wiring layer is electrically connected with the first transistor layer;

[0023] forming a third re-wiring layer on the first signal wiring layer, and the third re-wiring layer is electrically connected with the first signal wiring layer;

[0024] providing a storage chip, the storage chip comprises a second semiconductor substrate, a second transistor layer and a composite wiring layer, the composite wiring layer comprises a second signal wiring layer and a second power wiring layer, and the second signal wiring layer and the second power wiring layer are both electrically connected with the second transistor layer;

[0025] forming a fourth re-wiring layer on the composite wiring layer, and the fourth re-wiring layer is electrically connected with the second signal wiring layer and the second power wiring layer;

[0026] bonding the third re-wiring layer and the fourth re-wiring layer, and the third re-wiring layer and the fourth re-wiring layer are electrically connected;

[0027] thinning the first semiconductor substrate from the back surface of the first semiconductor substrate;

[0028] forming a passivation layer on the back surface of the first semiconductor substrate;

[0029] forming a metal connecting column penetrating through the passivation layer, the first semiconductor substrate and the first transistor layer, and a first end of the metal connecting column is electrically connected with the first signal wiring layer and the first transistor layer;

[0030] forming a first power wiring layer on the surface of the passivation layer, and the first power wiring layer is electrically connected with a second end of the metal connecting column;

[0031] forming a metal connecting bump on the surface of the first power wiring layer, and the metal connecting bump is electrically connected with the first power wiring layer.

[0032] Optionally, the line width of the TSV composite adapter plate is 0.4-1 μm, and the line distance is 0.4-1 μm.

[0033] Optionally, the method further comprises the step of forming an underfill layer between the first re-wiring layer and the 3D stacked logic storage module, the storage module and the optical module.

[0034] The application further provides an optoelectronic system packaging structure, which comprises:

[0035] a first re-wiring layer, the first re-wiring layer comprises a first surface and an opposite second surface;

[0036] a 3D stacked logic memory module, a memory module, and an optical module, wherein the 3D stacked logic memory module, the memory module, and the optical module are bonded to the first surface of the first rewiring layer, and the 3D stacked logic memory module, the memory module, and the optical module are all electrically connected to the first rewiring layer;

[0037] a second redistribution layer, the second redistribution layer comprising a first side and an opposite second side;

[0038] a metal post, the metal post being located between the second surface of the first redistribution layer and the first surface of the second redistribution layer, with a first end of the metal post being electrically connected to the first redistribution layer, and a second end of the metal post being electrically connected to the second redistribution layer;

[0039] An ASIC chip and a TSV composite adapter board, wherein the ASIC chip and the TSV composite adapter board are located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board, the first connector and the second connector are both electrically connected to the first rewiring layer, and the 3D stacked logic memory module, the ASIC chip, and the optical module are electrically connected, and the 3D stacked logic memory module, the TSV composite adapter board, and the memory module are electrically connected;

[0040] an encapsulation layer, the encapsulation layer being located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and covering the ASIC chip, the TSV composite adapter plate, and the metal pillar;

[0041] A metal bump is located on the second surface of the second redistribution layer and is electrically connected to the second redistribution layer.

[0042] Optionally, the TSV composite adapter plate has a line width of 0.4 μm to 1 μm, and a line spacing of 0.4 μm to 1 μm.

[0043] Optionally, the device further includes a substrate electrically connected to the metal bump, and a heat sink bonded to the substrate.

[0044] Optionally, the 3D stacked logic storage module includes stacked interconnected memory chips and backside power supply logic chips.

[0045] As described above, the optoelectronic system packaging structure and preparation method of the present invention can form a complete optoelectronic system packaging structure by 3D stacking logic storage modules, storage modules, optical modules, rewiring layers, metal pillars, ASIC chips and TSV composite adapter plates. This can also shorten the transmission distance of each module, speed up signal transmission, effectively reduce transmission power consumption, and shrink the packaging area. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 Shown is a schematic diagram of the process flow for preparing a photovoltaic system packaging structure according to an embodiment of the present invention.

[0047] Figure 2 Shown is a schematic structural diagram of a supporting substrate provided in an embodiment of the present invention.

[0048] Figure 3 It is a schematic diagram of the structure after the ASIC chip, TSV composite adapter plate and metal pillars are formed in an embodiment of the present invention.

[0049] Figure 4 It is a schematic diagram of the structure after the encapsulation layer is formed in an embodiment of the present invention.

[0050] Figure 5 It is a schematic diagram of the structure after the encapsulation layer is thinned in an embodiment of the present invention.

[0051] Figure 6 It is a schematic structural diagram after forming the first rewiring layer in an embodiment of the present invention.

[0052] Figure 7 It shows a schematic diagram of the structure after bonding the 3D stacked logic storage module, storage module and optical module in an embodiment of the present invention.

[0053] Figure 8 It is a schematic structural diagram after forming metal bumps in an embodiment of the present invention.

[0054] Figure 9 It is a schematic structural diagram of the heat dissipation element after forming the heat dissipation element in an embodiment of the present invention.

[0055] Figure 10 It is a schematic structural diagram of the bonding of the third redistribution layer and the fourth redistribution layer when preparing a 3D stacked logic memory module according to an embodiment of the present invention.

[0056] Figure 11 It is a schematic diagram of the structure after metal connecting pillars are formed when preparing a 3D stacked logic storage module in an embodiment of the present invention.

[0057] Figure 12 Shown is a schematic structural diagram of a 3D stacked logic storage module prepared in an embodiment of the present invention.

[0058] Description of Reference Numerals

[0059] 100 Support substrate

[0060] 200 separation layer

[0061] 300 dielectric layer

[0062] 400 Metal Columns

[0063] 500 ASIC chips

[0064] 501 first connecting piece

[0065] 600 TSV composite adapter plate

[0066] 601 Second connecting piece

[0067] 700 encapsulation layer

[0068] 810 First Rewiring Layer

[0069] 820 Second rewiring layer

[0070] 910 3D stacked logic memory module

[0071] 911 back-side power supply logic chip

[0072] 9111 First semiconductor substrate

[0073] 9112 First transistor layer

[0074] 9113 First signal wiring layer

[0075] 9114 passivation layer

[0076] 9115 First power wiring layer

[0077] 912 memory chip

[0078] 9121 Second semiconductor substrate

[0079] 9122 Second transistor layer

[0080] 9123 Composite Wiring Layer

[0081] 913 Third Rewiring Layer

[0082] 914 Fourth Rewiring Layer

[0083] 915 Metal Connecting Column

[0084] 916 Metal Connector Bumps

[0085] 920 storage module

[0086] 930 optical module

[0087] 110 bottom fill layer

[0088] 120 metal bumps

[0089] 130 substrate

[0090] 140 heat sink DETAILED DESCRIPTION

[0091] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0092] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0093] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0094] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0095] like Figure 1The embodiment provides a preparation method of an optoelectronic system packaging structure. The 3D stacking of a logic storage module, a storage module, an optical module, a rewiring layer, a metal column, an ASIC chip and a TSV composite adapter board can form a complete optoelectronic system packaging structure, the transmission distance of each module can be shorter, the signal transmission can be faster, the transmission power consumption can be effectively reduced, and the packaging area can be reduced.

[0096] The following is described in conjunction with the specification Figures 1 to 12 Further description is made on the optoelectronic system packaging structure and the preparation method thereof in the embodiment.

[0097] Firstly, referring to Figure 1 and Figure 2 , a support substrate 100 is provided in step S1.

[0098] Specifically, the support substrate 100 can include a glass substrate, a silicon substrate, a germanium substrate and the like, so as to provide a supporting effect through the support substrate 100. The type of the support substrate 100 is not limited here and can be selected as required.

[0099] The support substrate 100 can include a wafer level or a substrate level, and the specific size can be selected as required and is not limited here.

[0100] Further, in order to facilitate the subsequent separation operation of the support substrate 100, a separation layer 200 can be formed on the surface of the support substrate 100. The separation layer 200 can include one of a tape layer or a polymer layer, so as to facilitate the peeling operation through laser irradiation or thermal processing technology.

[0101] Then, referring to Figure 1 and Figure 3 , a metal column 400 is formed on the support substrate 100 in step S2.

[0102] Specifically, the metal column 400 can include but is not limited to one of a copper column, a silver column, a gold column and a titanium column. When the metal column 400 is formed, a dielectric layer 300 can be first formed on the support substrate 100, and then the metal column 400 can be formed on the dielectric layer 300 through a method such as electroplating.

[0103] Then, referring to Figure 1 and Figure 3, execute step S3, provide an ASIC chip 500 and a TSV composite transfer board 600, bond the ASIC chip 500 and the TSV composite transfer board 600 to the supporting substrate 100, and the surface of the ASIC chip 500 has a first connector 501 electrically connected to the ASIC chip 500, and the surface of the TSV composite transfer board 600 has a second connector 601 electrically connected to the TSV composite transfer board 600.

[0104] Specifically, the first connector 501 is electrically connected to the pad on the ASIC chip 500. The first connector 501 enables electrical connection between the ASIC chip 500 and external components, and prevents damage to the ASIC chip 500 during subsequent thinning operations. Similarly, the provision of the second connector 601 enables electrical connection between the TSV composite transfer board 600 and external components, and prevents damage to the TSV composite transfer board 600 during subsequent thinning operations.

[0105] The TSV composite transfer board 600 may include a TSV layer and a rewiring layer located on a surface of the TSV layer and electrically connected to the TSV layer, so as to achieve a smaller line width / line spacing through the TSV composite transfer board 600 to meet the requirements of high-density electrical connection. The line width of the TSV composite transfer board 600 may be 0.4μm to 1μm, such as 0.4μm, 0.5μm, 0.8μm, 1μm, etc. The line spacing of the TSV composite transfer board 600 may be 0.4μm to 1μm, such as 0.4μm, 0.5μm, 0.8μm, 1μm, etc. The preparation and specific structure of the TSV composite transfer board 600 are not excessively limited herein.

[0106] Next, see Figure 1 、 Figure 4 and Figure 5 , perform step S4 to form a packaging layer 700 on the supporting substrate 100, the packaging layer 700 covers the ASIC chip 500, the TSV composite adapter plate 600 and the metal pillar 400, and exposes the metal pillar 400, the first connector 501 and the second connector 601.

[0107] Specifically, the material of the encapsulation layer 700 may include epoxy resin, etc., and the method of forming the encapsulation layer 700 may include molding, etc. After forming the encapsulation layer 700, the encapsulation layer 700 is preferably planarized by grinding to form a flat surface. The specific material and preparation method of the encapsulation layer 700 are not excessively limited here.

[0108] Next, see Figure 1 and Figure 6, executing step S5 to form a first redistribution layer 810 on the packaging layer 700, and the first redistribution layer 810 is electrically connected to the metal pillar 400, the first connector 501 and the second connector 601.

[0109] Specifically, the first rewiring layer 810 can be prepared using steps such as coating, exposure, development, deposition, and etching. The first rewiring layer 810 includes a dielectric layer and a metal wiring layer. The dielectric layer may be made of one or a combination of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass. The metal wiring layer may be made of one or a combination of copper, aluminum, nickel, gold, silver, and titanium. The specific structure, material, and preparation method of the first rewiring layer 810 are not overly limited herein and may be selected as needed.

[0110] Next, see Figure 1 and Figure 7 , execute step S6, provide a 3D stacked logic storage module 910, a storage module 920 and an optical module 930, and bond the 3D stacked logic storage module 910, the storage module 920 and the optical module 930 to the first rewiring layer 810, the 3D stacked logic storage module 910, the storage module 920 and the optical module 930 are all electrically connected to the first rewiring layer 810, and the 3D stacked logic storage module 910, the ASIC chip 500 and the optical module 930 are electrically connected, and the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 are electrically connected.

[0111] Because the 3D stacked logic memory module 910, the TSV composite adapter plate 600, and the memory module 920 are electrically connected, the configuration of the memory module 920 allows for further expansion of memory cells in the horizontal direction. The TSV composite adapter plate 600 bridges the 3D stacked logic memory module 910 and the memory module 920, achieving high integration and high-density connectivity. Because the 3D stacked logic memory module 910, the ASIC chip 500, and the optical module 930 are electrically connected, electrical signals can be converted into optical signals for transmission via the ASIC chip 500 and the optical module 930, thereby achieving optoelectronic interconnection.

[0112] The specific structures of the ASIC chip 500 and the optical module 930 are not limited here.

[0113] See Figure 12 The 3D stacked logic memory module 910 preferably includes a stacked interconnected memory chip 912 and a backside power supply logic chip 911, wherein, Figures 10 to 12 The steps of preparing the 3D stacked logic storage module 910 can include, but are not limited to, the following steps:

[0114] A first semiconductor substrate 9111 is provided;

[0115] A first transistor layer 9112 is formed on the front surface of the first semiconductor substrate 9111;

[0116] A first signal wiring layer 9113 is formed on the first transistor layer 9112, and the first signal wiring layer 9113 is electrically connected with the first transistor layer 9112;

[0117] A third rewiring layer 913 is formed on the first signal wiring layer 9113, and the third rewiring layer 913 is electrically connected with the first signal wiring layer 9113;

[0118] A storage chip 912 is provided, which includes a second semiconductor substrate 9121, a second transistor layer 9122, and a composite wiring layer 9123, the composite wiring layer 9123 includes a second signal wiring layer and a second power supply wiring layer, and the second signal wiring layer and the second power supply wiring layer are both electrically connected with the second transistor layer 9122;

[0119] A fourth rewiring layer 914 is formed on the composite wiring layer 9123, and the fourth rewiring layer 914 is electrically connected with the second signal wiring layer and the second power supply wiring layer;

[0120] The third rewiring layer 913 and the fourth rewiring layer 914 are bonded, and the third rewiring layer 913 and the fourth rewiring layer 914 are electrically connected;

[0121] The first semiconductor substrate 9111 is thinned from the back surface of the first semiconductor substrate 9111;

[0122] A passivation layer 9114 is formed on the back surface of the first semiconductor substrate 9111;

[0123] A metal connecting column 915 is formed through the passivation layer 9114, the first semiconductor substrate 9111, and the first transistor layer 9112, and a first end of the metal connecting column 915 is electrically connected with the first signal wiring layer 9113 and the first transistor layer 9112;

[0124] A first power supply wiring layer 9115 is formed on the surface of the passivation layer 9114, and the first power supply wiring layer 9115 is electrically connected with a second end of the metal connecting column 915;

[0125] A metal connecting bump 916 is formed on the surface of the first power supply wiring layer 9115, and the metal connecting bump 916 is electrically connected with the first power supply wiring layer 9115.

[0126] The first semiconductor substrate 9111 and the second semiconductor substrate 9121 can be silicon substrates, but are not limited thereto. The first semiconductor substrate 9111 after thinning can have a thickness of 1-10 μm, such as 1 μm, 2 μm, 3 μm, 5 μm, 8 μm, 10 μm, etc. The first semiconductor substrate 9111 after thinning can protect the first transistor layer 9112, so as to avoid damaging the first transistor layer 9112. The thickness of the first semiconductor substrate 9111 after thinning is preferably 1-3 μm, so as to shorten the transmission path of power supply and signals and reduce the size of the package.

[0127] The passivation layer 9114 can avoid the diffusion of metal material into the first transistor layer 9112 when the metal connecting column 915 is prepared, so as to avoid short circuit and the like. The passivation layer 9114 can include an epoxy layer, a polyamide layer, a silicon nitride layer, a silicon oxide layer, etc. The material, thickness and preparation method of the passivation layer 9114 are not limited herein.

[0128] Further, referring to Figure 8 After the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 are bonded, an underfill layer 110 can be formed between the 3D stacked logic storage module 910, the TSV composite adapter board 600, the storage module 920 and the first re-wiring layer 810, so as to protect the 3D stacked logic storage module 910, the TSV composite adapter board 600 and the storage module 920 by the underfill layer 110. The filling method and the type of the material of the underfill layer 110 are not limited herein, and can be selected as required.

[0129] Next, referring to Figure 1 and Figure 8 Step S7 is performed to remove the support substrate 100, so as to expose the package layer 700.

[0130] Specifically, the separation layer 200 can be conveniently removed by laser irradiation or thermal processing, so as to remove the separation layer 200 and the support substrate 100, and to perform subsequent processes.

[0131] Next, see Figure 1 and Figure 8 , performing step S8 to form a second redistribution layer 820 on the surface of the packaging layer 700 , and the second redistribution layer 820 is electrically connected to the metal pillar 400 .

[0132] Specifically, the material, structure and preparation of the second re-distribution layer 820 may refer to the first re-distribution layer 810 , and will not be described in detail here.

[0133] Next, see Figure 1 and Figure 8 , performing step S9 to form a metal bump 120 on the second redistribution layer 820 , and the metal bump 120 is electrically connected to the second redistribution layer 820 .

[0134] For details, see Figure 8 By setting up the second rewiring layer 820, power can be provided vertically to the 3D stacked logic storage module 910, storage module 920 and optical module 930, thereby effectively shortening the transmission distance, making the signal transmission faster, and effectively reducing the transmission power consumption.

[0135] In this embodiment, a complete optoelectronic system packaging structure can be formed by stacking the 3D stacked logic storage module 910, the storage module 920, the optical module 930, the first rewiring layer 810, the second rewiring layer 820, the metal pillar 400, the ASIC chip 500 and the TSV composite adapter plate 600. This can shorten the transmission distance of each module, speed up signal transmission, effectively reduce transmission power consumption, and shrink the packaging area.

[0136] Furthermore, when the support substrate 100 is wafer-level or substrate-level, a dicing process may be included to separate the prepared wafer-level or substrate-level package structure into multiple independently arranged individual package structures to improve production efficiency. The dicing process may be mechanical dicing or laser dicing, and is not excessively limited herein.

[0137] For further information, see Figure 9 The method may further include providing a substrate 130 and bonding the substrate 130 to the metal bump 120, and the substrate 130 is electrically connected to the metal bump 120. The type and size of the substrate 130 are not limited herein.

[0138] For further information, see Figure 9 , and may further include the steps of providing a heat sink 140 and bonding the heat sink 140 to the substrate 130 .

[0139] Specifically, the heat sink 140 is in contact with the 3D stacked logic storage module 910, the storage module 920, and the optical module 930. The heat sink 140 effectively dissipates heat for the 3D stacked logic storage module 910, the storage module 920, and the optical module 930. The specific type of the heat sink 140 is not particularly limited herein.

[0140] See Figures 2 to 12 This embodiment further provides a photoelectric system packaging structure, the photoelectric system packaging structure comprising:

[0141] A first redistribution layer 810, wherein the first redistribution layer 810 includes a first surface and an opposite second surface;

[0142] 3D stacked logic memory module 910, memory module 920, and optical module 930, wherein the 3D stacked logic memory module 910, the memory module 920, and the optical module 930 are bonded to the first surface of the first re-distribution layer 810, and the 3D stacked logic memory module 910, the memory module 920, and the optical module 930 are all electrically connected to the first re-distribution layer 810;

[0143] A second redistribution layer 820, wherein the second redistribution layer 820 includes a first surface and an opposite second surface;

[0144] a metal pillar 400, wherein the metal pillar 400 is located between the second surface of the first redistribution layer 810 and the first surface of the second redistribution layer 820, and a first end of the metal pillar 400 is electrically connected to the first redistribution layer 810, and a second end of the metal pillar 400 is electrically connected to the second redistribution layer 820;

[0145] An ASIC chip 500 and a TSV composite adapter plate 600 are located between the second surface of the first redistribution layer 810 and the first surface of the second redistribution layer 820. The surface of the ASIC chip 500 has a first connector 501 electrically connected to the ASIC chip 500. The surface of the TSV composite adapter plate 600 has a second connector 601 electrically connected to the TSV composite adapter plate 600. The first connector 501 and the second connector 601 are both electrically connected to the first redistribution layer 810. The 3D stacked logic memory module 910, the ASIC chip 500, and the optical module 930 are electrically connected. The 3D stacked logic memory module 910, the TSV composite adapter plate 600, and the memory module 920 are electrically connected.

[0146] The packaging layer 700 is located between the second surface of the first redistribution layer 810 and the first surface of the second redistribution layer 820 and covers the ASIC chip 500, the TSV composite adapter plate 600, and the metal pillar 400;

[0147] The metal bump 120 is located on the second surface of the second redistribution layer 820 , and the metal bump 120 is electrically connected to the second redistribution layer 820 .

[0148] As an example, the line width of the TSV composite transfer board 600 is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

[0149] As an example, the device further includes a substrate 130 electrically connected to the metal bump 120 and a heat sink 140 bonded to the substrate 130 .

[0150] As an example, the 3D stacked logic memory module 910 includes stacked and interconnected memory chips 912 and a backside power supply logic chip 911 .

[0151] Among them, the optoelectronic system packaging structure can be directly prepared using the above-mentioned preparation process, so the materials, structure, etc. of the optoelectronic system packaging structure can refer to the above content and will not be elaborated here. Of course, according to needs, the optoelectronic system packaging structure can also be prepared using other preparation processes.

[0152] In summary, the optoelectronic system packaging structure and preparation method of the present invention can form a complete optoelectronic system packaging structure by 3D stacking logic storage modules, storage modules, optical modules, rewiring layers, metal pillars, ASIC chips and TSV composite adapter plates. This can also shorten the transmission distance of each module, speed up signal transmission, effectively reduce transmission power consumption, and shrink the packaging area.

[0153] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a photoelectric system packaging structure, characterized in that: The following steps are involved: providing a supporting substrate; forming a metal pillar on the supporting substrate; Providing an ASIC chip and a TSV composite adapter board, bonding the ASIC chip and the TSV composite adapter board to the supporting substrate, wherein the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, and the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board; forming a packaging layer on the supporting substrate, wherein the packaging layer covers the ASIC chip, the TSV composite adapter plate, and the metal pillar, and exposes the metal pillar, the first connector, and the second connector; forming a first redistribution layer on the packaging layer, wherein the first redistribution layer is electrically connected to the metal pillar, the first connector, and the second connector; Providing a 3D stacked logic storage module, a storage module, and an optical module, and bonding the 3D stacked logic storage module, the storage module, and the optical module to the first rewiring layer, wherein the 3D stacked logic storage module, the storage module, and the optical module are all electrically connected to the first rewiring layer, and the 3D stacked logic storage module, the ASIC chip, and the optical module are electrically connected, and the 3D stacked logic storage module, the TSV composite adapter board, and the storage module are electrically connected; removing the supporting substrate to expose the encapsulation layer; forming a second redistribution layer on a surface of the packaging layer, wherein the second redistribution layer is electrically connected to the metal pillar; A metal bump is formed on the second redistribution layer, and the metal bump is electrically connected to the second redistribution layer.

2. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The method further includes providing a substrate and bonding the substrate to the metal bumps, and the substrate is electrically connected to the metal bumps.

3. The method for preparing the optoelectronic system packaging structure according to claim 2, characterized in that: The method further includes providing a heat sink and bonding the heat sink to the substrate.

4. The method for preparing the optoelectronic system packaging structure according to claim 1, wherein: The 3D stacked logic memory module includes stacked and interconnected memory chips and backside power supply logic chips, wherein the steps of preparing the 3D stacked logic memory module include: providing a first semiconductor substrate; forming a first transistor layer on the front surface of the first semiconductor substrate; forming a first signal wiring layer on the first transistor layer, wherein the first signal wiring layer is electrically connected to the first transistor layer; forming a third redistribution layer on the first signal wiring layer, wherein the third redistribution layer is electrically connected to the first signal wiring layer; A memory chip is provided, the memory chip comprising a stacked second semiconductor substrate, a second transistor layer, and a composite wiring layer, the composite wiring layer comprising a second signal wiring layer and a second power wiring layer, wherein the second signal wiring layer and the second power wiring layer are both electrically connected to the second transistor layer; forming a fourth redistribution layer on the composite wiring layer, wherein the fourth redistribution layer is electrically connected to the second signal wiring layer and the second power wiring layer; Bonding the third redistribution layer to the fourth redistribution layer, and electrically connecting the third redistribution layer to the fourth redistribution layer; thinning the first semiconductor substrate from the back side of the first semiconductor substrate; forming a passivation layer on the back side of the first semiconductor substrate; forming a metal connection column penetrating the passivation layer, the first semiconductor substrate, and the first transistor layer, wherein a first end of the metal connection column is electrically connected to both the first signal wiring layer and the first transistor layer; forming a first power wiring layer on the surface of the passivation layer, wherein the first power wiring layer is electrically connected to the second end of the metal connection column; A metal connection bump is formed on a surface of the first power wiring layer, and the metal connection bump is electrically connected to the first power wiring layer.

5. The method for preparing the optoelectronic system packaging structure according to claim 1, wherein: The line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

6. The method for preparing the optoelectronic system packaging structure according to claim 1, characterized in that: The method further includes forming an underfill layer between the first rewiring layer and the 3D stacked logic memory module, the memory module, and the optical module.

7. An optoelectronic system packaging structure, characterized in that: The optoelectronic system packaging structure includes: a first redistribution layer, the first redistribution layer comprising a first side and an opposite second side; a 3D stacked logic memory module, a memory module, and an optical module, wherein the 3D stacked logic memory module, the memory module, and the optical module are bonded to the first surface of the first rewiring layer, and the 3D stacked logic memory module, the memory module, and the optical module are all electrically connected to the first rewiring layer; a second redistribution layer, the second redistribution layer comprising a first side and an opposite second side; a metal post, the metal post being located between the second surface of the first redistribution layer and the first surface of the second redistribution layer, with a first end of the metal post being electrically connected to the first redistribution layer, and a second end of the metal post being electrically connected to the second redistribution layer; An ASIC chip and a TSV composite adapter board, wherein the ASIC chip and the TSV composite adapter board are located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, the surface of the ASIC chip has a first connector electrically connected to the ASIC chip, the surface of the TSV composite adapter board has a second connector electrically connected to the TSV composite adapter board, the first connector and the second connector are both electrically connected to the first rewiring layer, and the 3D stacked logic memory module, the ASIC chip, and the optical module are electrically connected, and the 3D stacked logic memory module, the TSV composite adapter board, and the memory module are electrically connected; an encapsulation layer, the encapsulation layer being located between the second surface of the first rewiring layer and the first surface of the second rewiring layer, and covering the ASIC chip, the TSV composite adapter plate, and the metal pillar; A metal bump is located on the second surface of the second redistribution layer and is electrically connected to the second redistribution layer.

8. The optoelectronic system packaging structure according to claim 7, wherein: The line width of the TSV composite adapter plate is 0.4 μm to 1 μm, and the line spacing is 0.4 μm to 1 μm.

9. The optoelectronic system packaging structure according to claim 7, wherein: The invention also includes a substrate electrically connected to the metal bump and a heat sink bonded to the substrate.

10. The optoelectronic system packaging structure according to claim 7, wherein: The 3D stacked logic memory module includes stacked and interconnected memory chips and back-side power supply logic chips.

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