Separate rail power architecture

Abstract

Embodiments disclosed herein relate to a split rail power architecture, and more particularly, to providing isolation and control of the power supply via power management circuitry. In an example, an integrated circuit device is provided that includes: a device voltage supply (VDS) (105); an input / output (I / O) voltage supply (VDDIO) (106) coupled to the VDDS (105); and a level shifter circuit (115) coupled to the VDDIOs (106). The level shifter circuit (115) includes: a pair of cross-coupled PMOS transistors (116 and 118); a pair of NMOS transistors (117 and 119) coupled between the PMOS transistors (116 and 118) and a ground connection (114); and an inverter circuit (110) coupled to the VDDS (105) and the level shifter circuit (115). The level shifter circuit (115) further includes a capacitor (120) coupled to the PMOS transistors (116 and 118) and the ground connection (114) and in parallel with respect to the NMOS transistor (117).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Indian Provisional Patent Application No. 202341059467, filed on September 5, 2023, entitled “Solving SplitRail Architecture Challenges,” which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention generally relates to a split rail architecture for a power supply of a system. Background Art

[0004] In electronic systems that include multiple power supplies and multiple components that may use different ones of the power supplies, split-rail power supply technology may be used to control the power provided to each component at different times. For example, in applications where an integrated circuit interfaces with other peripherals and devices that use multiple power supplies, split-rail power supply technology may be included to perform regulator selection and sequencing of the power supplies.

[0005] In existing solutions, split rail support can be provided by including multiple instances of power management unit (PMU) circuitry or logic (e.g., power-on reset circuitry, brownout detector circuitry, and bandgap circuitry) for each power supply. In this way, each power supply can be safely ramped up or down without causing problems with coupled components. However, these solutions increase the cost, power, and design area requirements of the system in the case of using additional analog PMU circuitry and / or other hardware components.

[0006] In other existing solutions, split rail support may be provided via external power management circuitry, such as daisy-chained low dropout regulators (LDOs), which may control power switching on input / output pins of the system. These systems may require dedicated GPIO pins to drive power status indications of the external power management circuitry to ensure proper switching on and off of the different power supplies. While providing effective power control, these solutions also increase cost, power, and physical area requirements due to more pin counts and external components. Summary of the invention

[0007] Various embodiments disclosed herein relate to a split rail architecture for a power supply in a system, and more particularly, to providing isolation and control of the power supply via a power management circuit system. In an example, an integrated circuit device is provided, comprising: a device voltage supply; an input / output (I / O) voltage supply coupled to the device voltage supply; and a level shifter circuit coupled to the I / O voltage supply. The level shifter circuit comprises: a pair of cross-coupled p-type metal oxide semiconductor field effect transistors (PMOS transistors); a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection; and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further comprises a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and connected in parallel with respect to a first one of the pair of NMOS transistors.

[0008] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. It should be understood that this Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and 1B An example circuit architecture is shown that may be used in accordance with embodiments.

[0010] Figure 2 Depicted is an example graphical representation of the output of an example power management circuitry according to an embodiment.

[0011] Figure 3 An example block diagram of a system using power management circuitry according to an embodiment is shown.

[0012] Figure 4 An example sequence of steps is depicted for configuring components of power management circuitry according to an embodiment.

[0013] The drawings are not necessarily drawn to scale. In the drawings, the same reference numerals designate corresponding parts throughout the several views. In some embodiments, components or operations may be separated into different blocks or may be combined into a single block. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure are described in specific contexts, such as in microcontroller units (MCUs) and embedded systems or systems on a chip. Some embodiments may use other circuits, components, architectures, topologies, and applications that exhibit increased power control when using split-rail power supplies.

[0015] Discussed herein are enhanced components, techniques, and systems related to split-rail power supplies for providing isolation and control of power supplies via power management circuitry. In electronic systems, multiple power supplies may be included to power different components at varying voltages and times. Importantly, isolating and controlling power supplies across power domains can prevent coupled loads (e.g., peripheral devices) from operating before the expected time. To this end, level shifter circuits may be implemented to control the logic state of the power supplies based on various inputs. For example, in a system including two power supplies that operate at different times and produce different voltages, the level shifter circuitry may control the startup sequence of the power supplies so that one of the power supplies does not produce an erroneous voltage until the other power supply is turned on and stabilized. For example, the power management circuitry may coordinate power transitions (e.g., power-on, reset, etc.) by waiting until the first power supply is stable before allowing the circuitry powered by the second power supply to operate. Since the power supplies may operate at different voltages, the power management circuitry may include one or more level shifters to convert these signals and other signals provided by the circuitry powered by the first power supply to the appropriate voltage for the circuitry powered by the second power supply.

[0016] Various example systems employ split rail support circuits that can isolate and stabilize the output of the power supplies in the system. Some examples may utilize additional power management unit (PMU) circuitry for each power supply, such as power-on reset circuitry, brownout detector circuitry, and bandgap circuitry. In this way, each power supply can be safely ramped up or down without causing problems with coupled components. Other examples may include daisy-chained low dropout regulators (LDOs) that can control power switches on the input / output pins of the system. However, the problem is that two examples include additional circuitry that may not only increase the cost and design area of ​​the system on chip, but also increase latency and power consumption in the system because additional analog PMU circuitry is required based on the increase in hardware components.

[0017] Some examples of the present disclosure include a unique level shifter topology that utilizes a capacitor coupled between a pair of cross-coupled p-channel metal oxide semiconductor field effect transistors (also referred to as PMOS transistors) and a pair of n-channel MOSFETs (also referred to as NMOS transistors). The capacitor can increase the time that a node in the level shifter maintains a certain logic state until the circuit can stabilize or until a control power supply can be turned on and monitor another power supply coupled to the level shifter. Advantageously, such a topology can reduce latency within an embedded system, increase isolation between two power supplies, stabilize the output values ​​of the power supplies, and reduce design costs and area requirements by alleviating the need for additional PMU circuitry, among other benefits. In addition, the described topology can reduce power consumption of a system or its components because the split rail support elements of the topology can be disconnected or powered off during operation after resolution of the logic state.

[0018] In an example embodiment, an integrated circuit device is provided, comprising: a device voltage supply; an input / output (I / O) voltage supply coupled to the device voltage supply; and a level shifter circuit coupled to the I / O voltage supply. The level shifter circuit comprises: a pair of cross-coupled p-type metal oxide semiconductor field effect transistors (PMOS transistors); a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection; and an inverter circuit coupled to the device voltage supply and the level shifter circuit. The level shifter circuit further comprises a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and connected in parallel with respect to a first one of the pair of NMOS transistors.

[0019] In another example embodiment, a level shifter circuit is provided. The level shifter circuit includes: an input terminal; a first transistor coupled between a first power supply node and a first node; a second transistor coupled between the first node and a ground node; a third transistor coupled between a second power supply node and a second node; a fourth transistor coupled between the second node and a ground node; a capacitor coupled between the second node and the ground node; a fifth transistor coupled between the second power supply node and a third node; and a sixth transistor coupled between the third node and the ground node. The first transistor includes a gate coupled to the input terminal. The second transistor includes a gate coupled to the input terminal. The third transistor includes a gate coupled to the third node. The fourth transistor includes a gate coupled to the first node. The fifth transistor includes a gate coupled to the second node. The sixth transistor includes a gate coupled to the input terminal.

[0020] In yet another example embodiment, a system is provided that includes: a processor; a memory coupled to the processor; and a power management circuit system coupled to the processor. The power management circuit system includes: a first voltage supply; a second voltage supply coupled to the first voltage supply; and a level shifter circuit coupled to the second voltage supply. The level shifter circuit includes: a pair of cross-coupled p-type metal oxide semiconductor field effect transistors (PMOS transistors); a pair of n-type transistors (NMOS transistors) coupled between the pair of cross-coupled PMOS transistors and a ground connection; and an inverter circuit coupled to the first voltage supply and the level shifter circuit. The level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and connected in parallel with respect to a first one of the pair of NMOS transistors.

[0021] Figure 1A and 1B An example circuit architecture is shown that may be used in accordance with embodiments. Figure 1A and 1B The circuit architectures 101 and 102 are respectively included, which include various components capable of providing split rail power support for the power supplies in the system, such as VDDS 105 and VDDIO 106. The circuit architecture 101 includes an inverter 110, a level shifter 115, and a buffer 125. The inverter 110 includes transistors 111 and 112. The level shifter 115 includes transistors 116, 117, 118, and 119. The circuit architecture 102 also includes an inverter 110, a level shifter 115, and a buffer 125, and further includes clamping diodes 126 and 127.

[0022] In various examples, the circuit architectures 101 and 102 may be embodied in a circuit system used in an embedded system or a system on a chip (SoC), such as a microcontroller unit (MCU) (e.g., Figure 3 MCU 305). For example, the power management circuit system (e.g., Figure 3 Elements inside or outside the power management circuit system 320) may utilize circuit architectures 101 and 102 or components thereof.

[0023] First reference Figure 1A , the circuit architecture 101 includes: an inverter 110, which can be configured to be coupled to VDDS 105; a level shifter 115, which can be configured to be coupled to VDDIO 106; and a buffer 125, which can be coupled to the inverter 110, the level shifter 115 and VDDIO 106.

[0024] VDDS 105 represents a first power supply for the system that is capable of providing a positive supply voltage to components (e.g., MCU circuitry 345) of the system (e.g., MCU 305). VDDS 105 may be an internal power supply that may be ramped up (i.e., turned on, driven to reach a desired positive supply voltage) and ramped down (i.e., turned off to reach a 0V supply voltage) at different times based on signals provided by a power management unit (PMU) of the system (e.g., PMU 325). The PMU may control the operation of VDDS 105 so that VDDS 105 may power certain components of the system via the positive supply voltage at certain times and conserve power at other times.

[0025] VDDIO 106 represents a second power supply for the system that can provide a positive supply voltage to peripheral devices inside or outside the system. VDDIO 106 may be an additional internal power supply that may be coupled to a peripheral device of the system at an input / output (I / O) pin or port of the system. VDDIO 106 may ramp up or ramp down independently of VDDS 105. However, a problem is that if VDDIO 106 ramps up before VDDS 105 ramps up, VDDIO 106 may provide an erroneous signal to the peripheral device without controlling VDDIO 106. Therefore, a circuit architecture 101 may be included in the system to provide split rail power supply control of VDDIO 106.

[0026] In circuit architecture 101, VDDS 105 is configured to be coupled to inverter 110. Inverter 110 includes transistors 111 and 112 coupled to each other. Transistor 111 may be a p-channel (or p-type) metal oxide semiconductor field effect transistor (MOSFET) (also referred to as a PMOS transistor), and transistor 112 may be an n-channel (or n-type) MOSFET (also referred to as an NMOS transistor). Transistors 111 and 112 each include a gate, a drain, and a source. VDDS 105 may be coupled to the source of transistor 111. The gates and drains of transistors 111 and 112 may be coupled together. The source of transistor 112 may be coupled to ground connection 114, and further coupled to level shifter 115 and buffer 125.

[0027] The gate of transistor 111 may be further coupled to receive enable 107. Enable 107 may be a signal provided by a processor, controller, or other processing device (e.g., processor 310) that is capable of controlling the operation of inverter 110 and, therefore, level shifter 115. Inverted enable 108 is the complementary signal of enable 107 and may be measured at the drains of transistors 111 and 112. In other words, inverted enable 108 has a value opposite to that of enable 107. Based on the values ​​of enable 107 and inverted enable 108, inverter 110 may output a signal having a value (e.g., VSS 113) to level shifter 115 and buffer 125.

[0028] Level shifter 115 represents a circuit capable of receiving a first signal having a given logic state and a first voltage at enable 107, and producing a second signal having the same logic state (or in some instances an opposite state) and having a second voltage that may be different from the first voltage at output 130. In other words, given the logic states low or "0" and high or "1", for example, in a first voltage domain powered by a first power supply, a logic high may be represented by 1.8V, and in a second voltage domain powered by a second power supply, a logic high may be represented by 3.3V. Level shifter 115 may also be used in applications where a logic high is represented by the same voltage (e.g., 3.3V) in both voltage domains and signal isolation is required.

[0029] Level shifter 115 includes: a pair of cross-coupled PMOS transistors, transistors 116 and 118; a pair of NMOS transistors, transistors 117 and 119; and capacitor 120. Each of transistors 116, 117, 118, and 119 has a gate, a source, and a drain. The sources of transistors 116 and 118 are coupled to VDDIO 106, to buffer 125, and to each other. The gate of transistor 116 is coupled to the drain of transistor 118 and to the drain of transistor 119. The drain of transistor 116 is coupled to the gate of transistor 118, to the drain of transistor 117, and to a first terminal of capacitor 120. The drain of transistor 118 is coupled to an input of buffer 125 and to a drain of transistor 119. The sources of transistors 117 and 119 are coupled to inverter 110, to a second terminal of capacitor 120, to buffer 125, and to each other. The gate of transistor 117 is coupled to receive inverted enable 108 , and the gate of transistor 119 is coupled to receive enable 107 .

[0030] Buffer 125 represents a digital buffer device capable of isolating an input signal received from level shifter 115 from output 130. Output 130 may have a logic value of "0" or "1" based on the values ​​of enable 107 and invert enable 108 applied to inverter 110 and level shifter 115. In various examples, output 130 may be available at a signal pad of VDDIO 106 for use by one or more peripherals or devices in or connected to the system.

[0031] In a first example, the circuitry of a processor powered by VDDS 105 may provide an input signal having a high value at enable 107 to inverter 110. Enable 107 may be high or "1", and therefore, inverted enable 108 may be low or "0". Based on enable 107 being a high value, transistor 119 may be turned on and conducting, while transistor 117 may not be conducting. When transistor 119 is conducting, transistor 116 may be pulled apart, which may prevent transistor 118 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, the value at node 121 may be high, or "1". Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may be low, or "0". When the input of buffer 125 is coupled at node 122 , buffer 125 may receive an input having a value of “0” and, therefore, buffer 125 may produce an output 130 having a value of “0” in the VDDIO 106 domain.

[0032] In a second example, the circuitry of a processor powered by VDDS 105 may provide an input signal having a low value at enable 107 to inverter 110. Enable 107 may be low or "0", and therefore, inverted enable 108 may be high or "1". Based on enable 107 being a low value, transistor 117 may receive a high value and turn on to conduct, while transistor 119 may not conduct. When transistor 117 is conducting, transistor 118 may be pulled apart, which may prevent transistor 116 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, the value at node 121 may be low, or "0". Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may be high, or "1". When the input of buffer 125 is coupled at node 122, buffer 125 may receive an input having a value of "1", and therefore, buffer 125 may produce an output 130 having a value of "1" in the VDDIO 106 domain. Importantly, when VDDIO 106 ramps up before VDDS 105, circuit architecture 101 may be used to produce output 130 having a stable high value when enable 107 is low, which may prevent VDDIO 106 from providing an unknown value to a peripheral device without control via VDDS 105. Inclusion of capacitor 120 may cause the value at node 121 to be low, and therefore the value of 122 to be high, for a duration long enough for VDDS 105 and enable 107 to turn on to begin control of VDDIO 106.

[0033] In a third example, enable 107 and inverted enable 108 may be floating values. In other words, enable 107 and inverted enable 108 may have values ​​between "0" and "1". Based on enable 107 and inverted enable 108 having non-zero values, two transistors 117 and 119 may be partially turned on. Capacitor 120 may turn on transistor 118 more than transistor 116. In this way, the value at node 122 may be stabilized as a non-floating value. Therefore, output 130 may be a non-floating value, thereby preventing VDDIO 106 from supplying a floating value or an unstable value to a peripheral device.

[0034] Next reference Figure 1B , Figure 1B Circuit architecture 102 is shown. Circuit architecture 102 includes the same elements as circuit architecture 101 and further includes clamping diodes 126 and 127.

[0035] Clamping diode 126 may be a diode-connected PMOS transistor, and clamping diode 127 may be a diode-connected NMOS transistor. The source and gate of clamping diode 126 may be coupled to VDDIO 106 and the sources of transistors 116 and 118. The drain of clamping diode 126 may be coupled to the drain of transistor 118, the gate of transistor 116, and the drain of transistor 119, or in other words, at node 122, feeding buffer 125. The source and gate of clamping diode 127 may be coupled to inverter 110, the sources of transistors 117 and 119, at capacitor 120, or in other words, to VSS 113. The drain of clamping diode 127 may be coupled to the drain of transistor 117 and to the first terminal of capacitor 120, or in other words, at node 121. During operation, clamping diodes 126 and 127 may protect buffer 125 from corrupting the signal flowing through the circuit.

[0036] Figure 2 Depicted are example graphical representations of signals of an example power management circuitry measured at different times in accordance with an embodiment. Figure 2 A graphical representation 200 is shown, which references Figure 1A and 1B 1 and 102, the graphical representation shows sample values ​​measured at nodes in the circuit architectures 101 and 102, respectively, with respect to voltage 201 and time 202. More specifically, the graphical representation 200 includes waveforms showing the values ​​of VDDIO 106, VDDS 105, enable 107, inverted enable 108, node 122, node 121, and output 130 at times 202-1, 202-2, 202-3, 202-4, 202-5, 202-6, 202-7, and 202-8.

[0037] In various examples, times 202-1, 202-2, 202-3, 202-4, 202-5, 202-6, 202-7, and 202-8 represent chronological times at which a system including elements arranged via circuit architecture 101 or circuit architecture 102 is operating. The values ​​shown in each waveform are either high or low values. A "high" value may be equivalent to a logical high state (e.g., "1"). A "low" value may be equivalent to a logical low state (e.g., "0").

[0038] Time 202-1 represents a first time during which VDDIO 106 is ramped up or turned on. At this time, VDDS 105 may not be turned on and therefore has a low voltage 201. When enable 107 is low (because the circuitry providing the signal at enable 107 is powered by the disconnected VDDS 105) and inverted enable 108 is high, VDDIO 106 may be ramped up. When VDDIO 106 is ramped up before VDDS 105 is ramped up, elements of circuit architecture 101 or 102 may be used to prevent VDDIO 106 from providing erroneous signals to peripherals and devices coupled to VDDIO 106. More specifically, based on enable 107 being a low value and inverted enable 108 being a high value, transistor 117 may receive a high value (e.g., a positive voltage) and be turned on to conduct, while transistor 119 may be non-conducting. When transistor 117 is turned on, transistor 118 may be pulled apart, which may prevent transistor 116 from turning on based on the cross-coupling of transistors 116 and 118. Thus, at time 202-1, the value at node 121 may be low, or "0". Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Thus, at time 202-1, the value at node 122 may be high. When the input of buffer 125 is coupled at node 122, buffer 125 may receive an input having a value of "1", and thus, buffer 125 may produce output 130 having a high value at time 202-1. Circuitry coupled to output 130 may gate the output of VDDIO 106 circuitry based on output 130 being high. Inclusion of capacitor 120 may cause the value at node 121 to be low, and therefore the value of 122 to be high, for a period long enough (ie, the time between times 202 - 1 and 202 - 2 ) to cause VDDS 105 and enable 107 to turn on to begin controlling VDDIO 106 at time 202 - 2 .

[0039] At time 202-2, VDDIO 106 remains on, and when enable 107 is at a high value, VDDS 105 turns on and begins to ramp up. When enable 107 changes to a high value, inverting enable 108 changes to a low value. Based on enable 107 being a high value, transistor 119 may turn on and conduct, while transistor 117 may not conduct. When transistor 119 is on, transistor 116 may be pulled apart, which may prevent transistor 118 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, the value at node 121 may change from a low value to a high value. Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may change to a low value at time 202-2. When the input of buffer 125 is coupled at node 122, buffer 125 may receive an input having a value of "0", and therefore, buffer 125 may produce output 130 having a value of "0" at time 202-2 because when VDDS 105 is turned on, control of VDDIO 106 may no longer be required. This may indicate a normal operating condition, and circuitry coupled to output 130 may respond normally to the output of VDDIO 106 circuitry based on output 130 being low.

[0040] At time 202-3, VDDS 105 ramps down to a low value, while VDDIO 106 remains on. Therefore, enable 107 ramps down to a low value and inverted enable 108 ramps up to a high value. Similar to time 202-1, transistor 117 may be turned on to conduct, and transistor 119 may be turned off. When transistor 117 is turned on, transistor 118 may be pulled apart, which may prevent transistor 116 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, at time 202-3, the value at node 121 may be low, or "0". Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may return to a high value at time 202-3. When the input of buffer 125 is coupled at node 122, buffer 125 may receive an input having a value of "1", and therefore, buffer 125 may produce output 130 having a high value at time 202-3 to control VDDIO 106. Inclusion of capacitor 120 may cause the value at node 121 to be low, and therefore the value of 122 to be high, for a period long enough (i.e., the time between times 202-3 and 202-4) to cause VDDS 105 and enable 107 to turn on to begin controlling VDDIO 106 at time 202-3.

[0041] At time 202-4, VDDIO 106 ramps down to a low value. At this point, both VDDS 105 and VDDIO 106 are disconnected, so no current can flow through the circuit system and to any peripherals or other devices. Therefore, at time 202-4, all waveforms can show low values ​​because no transistors are turned on.

[0042] At time 202-5, enable 107 ramps to a high value, causing VDDS 105 to turn on and ramp to a high value. At this time, VDDIO 106 remains off. Since VDDIO 106 is off, components of circuit architecture 101 or 102 may not be needed to control VDDIO 106, so output 130 can remain low.

[0043] At time 202-6, VDDS 105 remains on due to enable 107 remaining on, and VDDIO 106 begins to ramp up to a high value. Based on enable 107 being a high value when VDDIO 106 ramps up, transistor 119 may be turned on and conducting, while transistor 117 may not be conducting. While transistor 119 is conducting, transistor 116 may be pulled apart, which may prevent transistor 118 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, the value at node 121 may change from a low value to a high value. Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may change to a low value at time 202-5. When the input of buffer 125 is coupled at node 122 , buffer 125 may receive an input having a value of “0” and, therefore, buffer 125 may generate output 130 having a value of “0” at time 202 - 5 because control of VDDIO 106 may not be needed when VDDS 105 is on.

[0044] At time 202-7, enable 107 may change from a high value to a low value, and therefore, VDDS 105 may be turned off. However, VDDIO 106 may remain on at time 202-7. Transistor 117 may be turned on to conduct, and transistor 119 may be turned off. When transistor 117 is turned on, transistor 118 may be pulled apart, which may prevent transistor 116 from conducting based on the cross-coupling of transistors 116 and 118. Therefore, at time 202-7, the value at node 121 may be low, or "0". Due to the configuration of the transistors in level shifter 115, the value measured at node 122 may be opposite to the value at node 121. Therefore, the value at node 122 may return to a high value at time 202-7. When the input of buffer 125 is coupled at node 122, buffer 125 may receive an input having a value of "1", and therefore, buffer 125 may produce output 130 having a high value at time 202-3 to control VDDIO 106. Inclusion of capacitor 120 may cause the value at node 121 to be low, and therefore the value of 122 to be high, for a period long enough (i.e., the time between times 202-3 and 202-4) to cause VDDS 105 and enable 107 to turn on to begin controlling VDDIO 106 at time 202-7.

[0045] At time 202-8, enable 107 remains off and, therefore, causes VDDS 105 and VDDIO 106 to ramp down to a low value. At this point, all transistors may stop conducting. Therefore, node 122 returns to a low value as does output 130.

[0046] Although only a few times are depicted and described with respect to graphical representation 200, any combination or variation of ramping up and ramping down of VDDS 105 and VDDIO 106 in any order is contemplated. Importantly, however, when VDDIO 106 is on and VDDS 105 is off, the value at node 122 can be high for a sufficient time to produce a high value at output 130 to control VDDIO 106 while VDDS 105 is off for that duration due to capacitor 120.

[0047] Figure 3 An example block diagram of a system using power management circuitry according to an embodiment is shown. Figure 3The block diagram 300 includes a microcontroller unit (MCU) 305, its components, and peripherals 350. The MCU 305 further includes a processor 310, a memory 315, a power management circuit system 320, and an MCU circuit system 345. The power management circuit system 320 includes a power management unit (PMU) 325, a device power supply 330, an input / output (I / O) power supply 335, and a level shifter circuit system 340. In various examples, the elements of the power management circuit system 320 can be implemented using a split-rail power architecture (e.g., Figure 1A Circuit Architecture 101 or Figure 1B The circuit architecture 102) implements the split rail support technology.

[0048] MCU 305 represents an embedded system or system on a chip capable of performing various functions via hardware, software, firmware, or a combination or variation thereof. To perform functions, MCU 305 may include processor 310 , memory 315 , power management circuitry 320 , and MCU circuitry 345 .

[0049] Processor 310 represents one or more processor cores capable of executing software and firmware. Examples of the one or more processor cores may include DSPs, general purpose central processing units, special purpose processors or circuits (e.g., ASICs), and logic devices (e.g., FPGAs), as well as any other type of processing device, combination, or variation thereof. Processor 310 may be coupled to memory 315 (from which the processor may execute software and firmware) and power management circuitry 320.

[0050] Memory 315 may include any non-transitory computer-readable storage media capable of reading from and writing to various components (e.g., processor 310, MCU circuitry 345, and peripherals 350), as well as other elements. In some embodiments, memory 315 may include volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Examples of storage media include random access memory, read-only memory, magnetic disks, optical disks, optical media, flash memory, virtual and non-virtual memory, cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other suitable storage media. Memory 315 may store data for use by processor 310, MCU circuitry 345, and peripherals 350.

[0051] Power management circuitry 320 represents components capable of providing power to components internal to MCU 305 (e.g., VDDS 105) and components external to peripherals 350 (e.g., VDDIO 106). Power management circuitry 320 includes PMU 325, device power supply 330, I / O power supply 335, and level shifter circuitry 340. Power management circuitry 320 may be coupled to receive signals from processor 310, such as initialization or enable signals, trim data, etc., and coupled to provide power to MCU circuitry 345 and peripherals 350.

[0052] MCU circuitry 345 represents on-chip circuitry and hardware devices of MCU 305. MCU circuitry 345 may perform various functions of MCU 305 when driven by power supplied by device power supply 330. Examples of MCU circuitry 345 may include analog-to-digital converters, oscillators, logic devices, and the like.

[0053] The PMU 325 represents one or more power management circuits capable of initializing the device power 330 and the I / O power 335. For example, the PMU 325 may include a power-on reset (POR) circuit, a brownout detector circuit, and a bandgap reference circuit, among other circuits and hardware components. The elements of the PMU 325 may be initialized sequentially to safely start the device power 330 and the I / O power 335.

[0054] The device power supply 330 represents a power supply of the MCU 305 that can power various components within the MCU 305 (e.g., the MCU circuit system 345). For example, the device power supply 330 can be Figure 1A and 1B The I / O power supply 335 represents a power supply of the MCU 305 that can power various other components (e.g., peripheral devices 350) that are internal or external to the MCU 305 and can be connected to the I / O pins of the MCU 305. For example, the I / O power supply 330 can be Figure 1A and 1B Example of VDDIO 106.

[0055] In various examples, the PMU 325 may be configured to control the operation of the device power supply 330. For example, the PMU 325 may receive a signal from the processor 310 to begin initialization of the device power supply 330. This may require ramping up reference circuitry and power-on reset circuitry to ensure that the device power supply 330 generates the necessary voltages for the desired operation. The device power supply 330 may be configured to control the operation of the I / O power supply 335. For example, the device power supply 330 may include software and / or firmware that, when executed, ramps up the I / O power supply 335 and ensures that the I / O power supply 335 generates a stable voltage with a value suitable for the desired operation. However, in some cases, the I / O power supply 335 may be turned on before the device power supply 330. In these cases, the level shifter circuitry 340 may be used to disable the I / O power supply 335 or prevent the I / O power supply 335 from providing a voltage signal to the peripheral device 350 via the I / O pin of the MCU 305.

[0056] The level shifter circuit system 340 represents a circuit that is capable of receiving a first signal of a given logic state and a first voltage and generating a second signal having the same logic state (or in some examples, an opposite state) and having a second voltage that may be different from the first voltage. In various examples, several level shifter circuits may be used in the MCU 305. However, at least one of the level shifter circuits may include Figure 1A Circuit Architecture 101 or Figure 1B Components included and arranged in the circuit architecture 102 for controlling the I / O power supply 335. For example, the level shifter circuit with the circuit architecture 101 can be used in various scenarios. For example, if the device power supply 330 is not turned on, the level shifter circuit can be used to prevent the I / O power supply 335 from supplying an output voltage to the peripheral device 350. By way of another example, when both the device power supply 330 and the I / O power supply 335 are ramped up at the same time, the level shifter circuit can be used to stabilize the output voltage of the I / O power supply 335. However, if the device power supply 330 is ramped up before the I / O power supply 335, then the level shifter circuit system 340 may not be needed to change the output value of the I / O power supply 335.

[0057] After safely ramping up, the I / O power supply 335 can generate a power supply voltage controlled by the mentioned device power supply 330 or level shifter circuit system 340. The I / O power supply 335 can be coupled to the peripheral device 350 at the I / O pin of the MCU 305. The peripheral device 350 represents a component, circuit, system, sub-circuit, subsystem, etc. that is capable of interfacing with the MCU 305 and performing one or more functions. In, for example Figure 3In various examples of the examples illustrated in FIG, the peripheral device 350 is external to the MCU 305, or located off-chip. However, in other examples, the peripheral device 350 may be located within the MCU 305 or on-chip. Additional peripheral devices may also be included on-chip or off-chip, and may each perform different functions when driven by the I / O power supply 335.

[0058] Figure 4 An example sequence of steps is depicted for configuring components of power management circuitry according to an embodiment. Figure 4 Include references Figure 1A and 1B Process 400 of manufacturing, coupling, attaching, or otherwise connecting components of circuit architecture 101 or 102 together for use, for example, Figure 3 The steps in the system of MCU 305.

[0059] In operation 405, a pair of PMOS transistors (e.g., transistors 116 and 118) may be coupled together in a cross-coupled configuration. Transistors 116 and 118 each have a gate, a source, and a drain. The sources of transistors 116 and 118 may be coupled together. The gate of transistor 116 may be coupled to the drain of transistor 118. The drain of transistor 116 may be coupled to the gate of transistor 118.

[0060] In operation 410, a pair of NMOS transistors may be coupled to the cross-coupled PMOS transistor pair. More specifically, a first NMOS transistor (transistor 117) may be coupled to portions of transistors 116 and 118, and a second NMOS transistor (transistor 119) may be coupled to portions of transistors 116 and 118. Similar to transistors 116 and 118, transistors 117 and 119 each have a gate, a drain, and a source. The drain of transistor 117 may be coupled to the drain of transistor 116. The drain of transistor 117 may be further coupled to the gate of transistor 118. The drain of transistor 119 may be coupled to the drain of transistor 118. The drain of transistor 119 may be further coupled to the gate of transistor 116. The sources of transistors 117 and 119 may be coupled together and to a ground connection.

[0061] Next, in operation 415, capacitor 120 may be coupled to the pair of cross-coupled PMOS transistors 116 and 118, NMOS transistors 117 and 119, and to a ground connection. More specifically, capacitor 120 may be coupled to the drains of transistors 116 and 117, to the gate of transistor 118, and to the sources of transistors 117 and 119.

[0062] In operation 420, a level shifter 115 including transistors 116, 117, 118, and 119 and capacitor 120 may be coupled to inverter 110, VDDIO 106, and to buffer 125. Specifically, inverter 110 may be coupled to the sources of transistors 117 and 119 and to capacitor 120. VDDIO 106 may be coupled to the sources of transistors 116 and 118. Buffer 125 may be coupled to receive inputs from inverter 110, level shifter 115, and VDDIO 106. For example, buffer 125 may be coupled to inverter 110, the sources of transistors 117 and 119, and capacitor 120 at a first input terminal. Buffer 125 may be coupled to level shifter 115 at the drain of transistor 118 at a second input terminal. Buffer 125 may be coupled to VDDIO 106 at a third input and to the sources of transistors 116 and 118 .

[0063] In other examples, the operations of process 400 may occur in various orders and may include additional or fewer connections. For example, additional transistors, such as clamping diodes 126 and 127, may be included and coupled to level shifter 115 and buffer 125.

[0064] Although some examples provided herein are described in the context of power management systems, level shifter circuits, embedded systems or systems on a chip, sub-circuits, systems, subsystems, components, devices, architectures, or environments, it should be understood that the circuits, devices, logic elements and other components, systems and methods described herein are not limited to these embodiments and may be applicable to various other processes, systems, applications, devices, etc., such as other circuits, logic devices, transistors, etc., in the context of, for example, split-rail power support. Thus, aspects of the invention may be embodied as other systems, methods, and other configurable systems.

[0065] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", etc. should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". As used herein, the terms "connected", "coupled" or any variation thereof mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements can be physical, logical or a combination thereof. In addition, the words "herein", "above", "below" and words of similar meaning, when used in this application, shall refer to the application as a whole, rather than to any particular part of the application. Where the context permits, words used in the singular or plural in the above specific embodiments may also include the plural or singular, respectively. The word "or", when referring to a list of two or more items, covers all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0066] The phrases "in some embodiments," "according to some embodiments," "in the illustrated embodiments," "in other embodiments," etc. generally mean that the particular feature, structure, or characteristic following the phrase is included in at least one embodiment of the present technology, and may be included in more than one embodiment. Additionally, these phrases do not necessarily refer to the same embodiment or different embodiments.

[0067] The above specific implementation of the example of technology is not intended to be exhaustive or to limit the technology to the exact form disclosed above. Although the specific examples of technology are described above for illustrative purposes, it will be recognized by those skilled in the relevant art that various equivalent modifications can be made within the scope of technology. For example, although the process or block is presented in a given order, the alternative embodiment can perform a routine with steps in a different order or adopt a system with blocks, and some processes or blocks can be deleted, moved, added, subdivided, combined and / or modified to provide an alternative or sub-combination. Each of these processes or blocks may be implemented in various different ways. And, although the process or block is sometimes shown as a serial execution, these processes or blocks can be executed or implemented in parallel instead, or can be executed at different times. In addition, any specific number mentioned herein is only an example; alternative embodiments can adopt different values ​​or ranges.

[0068] The teaching content of the technology provided herein can be applied to other systems, not necessarily the system described above. The elements and actions of the various examples described above can be combined to provide further embodiments of the technology. Some alternative embodiments of the technology can include not only the additional elements of those embodiments mentioned above, but also fewer elements.

[0069] According to the above specific embodiments, these and other changes can be made to the technology. Although the above description describes certain examples of the technology and describes the expected best mode, no matter how detailed the above content appears in this article, the technology can be practiced in many ways. The details of the system can have considerable changes in its specific embodiment while still being covered by the technology disclosed herein. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be understood to imply that the terms are redefined herein as any specific characteristics, features or aspects of the technology associated with the terms. In general, unless these terms are clearly defined in the above specific embodiment part, the terms used in the attached claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification. Therefore, the actual scope of the present technology not only covers the disclosed examples, but also covers all equivalent ways of practicing or realizing the present technology under the claims.

[0070] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but applicants consider various aspects of the technology in any number of claim forms. For example, although only one aspect of the technology is described as a computer-readable media claim, other aspects may also be embodied as a computer-readable media claim, or in other forms, such as means plus function claims. It is expected that any claim processed under 35 U.S.C. §112(f) will begin with "members for", but the use of the term "for" in any other context is not intended to invoke processing under 35 U.S.C. §112(f). Therefore, applicants reserve the right to seek additional claims after filing this application to seek such additional claim forms in this application or a continuation application.

Claims

1. An integrated circuit device, comprising: Device voltage supply; an input / output (I / O) voltage supply coupled to the device voltage supply; and a level shifter circuit coupled to the I / O voltage supply, wherein the level shifter circuit comprises: a pair of cross-coupled PMOS transistors; a pair of NMOS transistors coupled between the pair of cross-coupled PMOS transistors and a ground connection; and an inverter circuit coupled to the device voltage supply and the level shifter circuit; and Wherein the level shifter circuit further includes a capacitor coupled to the pair of cross-coupled PMOS transistors and the ground connection and connected in parallel with respect to a first one of the pair of NMOS transistors.

2. The integrated circuit device of claim 1 , wherein the pair of NMOS transistors comprises a first NMOS transistor and a second NMOS transistor, wherein a source of each of the pair of NMOS transistors is coupled to the ground connection, and wherein a drain of each of the pair of NMOS transistors is coupled to the pair of PMOS transistors.

3. The integrated circuit device of claim 2, wherein the pair of cross-coupled PMOS transistors comprises a first PMOS transistor and a second PMOS transistor, and wherein the capacitor is connected to a drain of the first PMOS transistor and a gate of the second PMOS transistor.

4. The integrated circuit device of claim 3, further comprising a buffer coupled to the level shifter circuit and the ground connection, wherein the buffer comprises an input node connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor.

5. The integrated circuit device according to claim 4, wherein the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor and the capacitor, and wherein the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor and the input node of the buffer.

6. The integrated circuit device of claim 5 , wherein the inverter circuit comprises a third PMOS transistor coupled in series with a third NMOS transistor, wherein a source of the third PMOS transistor is connected to the device voltage supply, wherein a source of the third NMOS transistor is coupled to the ground connection, and wherein a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor.

7. The integrated circuit device according to claim 6, wherein each gate of the third PMOS transistor and the third NMOS transistor is coupled to the gate of the second NMOS transistor, and wherein the drain of the third PMOS transistor and the drain of the third NMOS transistor are each connected to the gate of the first NMOS transistor.

8. A level shifter circuit, comprising: Input terminal; a first transistor coupled between a first power supply node and a first node, wherein the first transistor includes a gate coupled to the input terminal; a second transistor coupled between the first node and a ground node, wherein the second transistor includes a gate coupled to the input terminal; a third transistor coupled between the second power supply node and the second node, wherein the third transistor includes a gate coupled to the third node; a fourth transistor coupled between the second node and the ground node, wherein the fourth transistor includes a gate coupled to the first node; a capacitor coupled between the second node and the ground node; a fifth transistor coupled between the second power supply node and the third node, wherein the fifth transistor includes a gate coupled to the second node; and A sixth transistor is coupled between the third node and the ground node, wherein the sixth transistor includes a gate coupled to the input terminal.

9. The level shifter circuit of claim 8, further comprising a seventh transistor coupled between the second power supply node and the third node, wherein the seventh transistor includes a gate coupled to the second power supply node.

10. The level shifter circuit of claim 9, further comprising an eighth transistor coupled between the second node and the ground node, wherein the eighth transistor includes a gate coupled to the ground node. 11 . The level shifter circuit of claim 10 , wherein the seventh transistor and the eighth transistor are diode-connected transistors.

12. The level shifter circuit of claim 8, further comprising a buffer comprising a first input, a second input, and a third input, wherein the first input is coupled to the second power supply node, the second input is coupled to the third node, and the third input is coupled to the ground node. 13 . The level shifter circuit of claim 10 , wherein the first transistor, the third transistor, the fifth transistor, and the seventh transistor are PMOS transistors. 14 . The level shifter circuit of claim 10 , wherein the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are NMOS transistors.

15. A system comprising: processor; a memory coupled to the processor; and a power management circuit system coupled to the processor and comprising: a first voltage supply; A second voltage supply coupled to the first voltage supply; and a level shifter circuit coupled to the second voltage supply, wherein the level shifter circuit comprises: a pair of cross-coupled PMOS transistors; a pair of NMOS transistors coupled between the pair of cross-coupled PMOS transistors and a ground connection; and an inverter circuit coupled to the first voltage supply and the level shifter circuit; and Wherein the level shifter circuit further includes a capacitor connected to the pair of cross-coupled PMOS transistors and the ground connection and connected in parallel with respect to a first one of the pair of NMOS transistors.

16. The system of claim 15, wherein the pair of NMOS transistors includes a first NMOS transistor and a second NMOS transistor, wherein a source of each of the pair of NMOS transistors is coupled to the ground connection, wherein a drain of each of the pair of NMOS transistors is coupled to the pair of PMOS transistors, wherein the pair of cross-coupled PMOS transistors includes a first PMOS transistor and a second PMOS transistor, and wherein the capacitor is connected to a drain of the first PMOS transistor and a gate of the second PMOS transistor.

17. The system of claim 16, further comprising a buffer coupled to the level shifter circuit and the ground connection, wherein the buffer comprises an input node connected to a gate of the first PMOS transistor and a drain of the second PMOS transistor.

18. The system of claim 17, wherein the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor, the gate of the second PMOS transistor, and the capacitor, and wherein the drain of the second NMOS transistor is connected to the gate of the first PMOS transistor, the drain of the second PMOS transistor, and the input node of the buffer.

19. The system of claim 18, wherein the inverter circuit comprises a third PMOS transistor coupled in series with a third NMOS transistor, wherein a source of the third PMOS transistor is connected to the first voltage supply, wherein a source of the third NMOS transistor is coupled to the ground connection, and wherein a drain of the third PMOS transistor is connected to a drain of the third NMOS transistor.

20. The system of claim 19, wherein each gate of the third PMOS transistor and the third NMOS transistor is coupled to a gate of the second NMOS transistor, and wherein the drain of the third PMOS transistor and the drain of the third NMOS transistor are each connected to a gate of the first NMOS transistor.

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