An automatic correction circuit and method for the offset voltage of an operational amplifier

Abstract

The application relates to an operational amplifier offset voltage automatic correction circuit and method, which comprises an operational amplifier main circuit, the operational amplifier main circuit comprises an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, and the operational amplifier main circuit at least comprises a same-phase input end Vi+, an opposite-phase input end Vi- and an output end Vout; an automatic correction circuit, the automatic correction circuit comprises a correction control circuit and a correction flag generation circuit connected in sequence, the correction control circuit is electrically connected with the operational amplifier main circuit, and the correction flag generation circuit is electrically connected with the output end Vout of the operational amplifier main circuit. The application can adapt to a wide power voltage range, has higher offset correction precision, the proposed offset voltage automatic correction circuit does not need additional comparators and filters and other analog circuits, only uses digital logic to complete automatic correction control, and reduces the circuit complexity and cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to an operational amplifier offset voltage automatic correction circuit and method. BACKGROUND

[0002] The operational amplifier is one of the most commonly used analog circuits, which is widely used in the fields of signal processing, instruments and automatic control. The input offset voltage is a key technical index of the operational amplifier, which represents the voltage value that needs to be compensated at the input end in order to make the output also 0 when the differential input of the operational amplifier is 0. The existence of the offset voltage will seriously deteriorate the gain error and linearity of the operational amplifier, thereby reducing the sensitivity and increasing the error of the circuit system. Therefore, in actual circuit design, various methods must be used to reduce the offset voltage of the operational amplifier. The offset of the operational amplifier is mainly caused by the non-symmetry of the internal devices of the operational amplifier, the deviation of the integrated circuit manufacturing process, and the temperature and humidity gradient and stress gradient of the working environment, which will cause the electrical characteristics of the semiconductor devices to mismatch, thereby causing the offset of the operational amplifier.

[0003] At present, the main methods to reduce the offset of the operational amplifier are: 1) improving the semiconductor manufacturing process, improving the processing precision, and reducing the device mismatch, which is the most essential solution, but the process iteration period is long and the cost is high; 2) correcting and compensating the offset from the perspective of circuit design, which has high flexibility and low cost, so it is widely used in the field of circuits, for example: CN106656081A proposes a method of introducing a trimming current I_trim to compensate for the offset of the operational amplifier, but the matching precision of the current mirror and the leakage will restrict the precision of the offset compensation; CN107370463A proposes a method of compensating for the offset of the operational amplifier by adjusting the substrate voltage of the load tube and the common-mode level of the output stage, but when the power supply voltage is reduced, the adjustable voltage range is very narrow, which is not suitable for low power supply voltage application scenarios; CN107769737A proposes a method of using a comparator to form a feedback loop to adjust the substrate voltage of the input differential transistor of the operational amplifier to reduce the offset voltage of the operational amplifier, but an additional comparator and filter circuit are needed to assist in correction, which increases the complexity and cost of the circuit. SUMMARY

[0004] The present application provides an operational amplifier offset voltage automatic correction circuit and method, which aims to at least solve one of the technical problems existing in the prior art.

[0005] The technical scheme of the present application is an operational amplifier offset voltage automatic correction circuit, which comprises:

[0006] An operational amplifier main circuit, the operational amplifier main circuit comprises an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, and the operational amplifier main circuit at least comprises a non-inverting input end Vi+, an inverting input end Vi- and an output end Vout;

[0007] The automatic correction circuit comprises a correction control circuit and a correction flag generation circuit connected in sequence, the first transistor array, the second transistor array, the third transistor array and the fourth transistor array are electrically connected with the output end of the correction control circuit respectively, and the correction flag generation circuit is electrically connected with the output end Vout of the operational amplifier main circuit.

[0008] Further, the operational amplifier basic circuit comprises an input differential pair tube and an operational amplifier output stage, and the input differential pair tube comprises a PMOS differential pair tube and an NMOS differential pair tube.

[0009] The PMOS differential pair tube comprises an operational amplifier co-directional input end PMOS transistor pm0 and an operational amplifier reverse input end PMOS transistor pm0', the source of the operational amplifier co-directional input end PMOS transistor pm0 is connected with the output end of the first current source Ip, the drain of the operational amplifier co-directional input end PMOS transistor pm0 is connected with the first input end of the operational amplifier output stage, and the gate of the operational amplifier co-directional input end PMOS transistor pm0 is connected with the first transistor array of the input offset correction transistor array; the source of the operational amplifier reverse input end PMOS transistor pm0' is connected with the output end of the first current source Ip, the drain of the operational amplifier reverse input end PMOS transistor pm0' is connected with the second input end of the operational amplifier output stage, and the gate of the operational amplifier reverse input end PMOS transistor pm0' is connected with the second transistor array of the input offset correction transistor array.

[0010] The NMOS differential pair tube comprises an operational amplifier co-directional input end NMOS transistor nm0 and an operational amplifier reverse input end NMOS transistor nm0', the source of the operational amplifier co-directional input end NMOS transistor nm0 is connected with the output end of the second current source In, the drain of the operational amplifier co-directional input end NMOS transistor nm0 is connected with the third input end of the operational amplifier output stage, and the gate of the operational amplifier co-directional input end NMOS transistor nm0 is connected with the third transistor array of the input offset correction transistor array; the source of the operational amplifier reverse input end NMOS transistor nm0' is connected with the output end of the second current source In, the drain of the operational amplifier reverse input end NMOS transistor nm0' is connected with the fourth input end of the operational amplifier output stage, and the gate of the operational amplifier reverse input end NMOS transistor nm0' is connected with the fourth transistor array of the input offset correction transistor array.

[0011] Further, the input offset correction transistor array comprises a first transistor array, a second transistor array, a third transistor array and a fourth transistor array,

[0012] The first transistor array is a same-direction input PMOS offset correction transistor array, the first transistor array includes k PMOS offset correction transistors pm1-pmk, the gate of each PMOS offset correction transistor pm1-pmk is connected with the gate of the same-direction input PMOS transistor pm0 of the operational amplifier respectively, the source of each PMOS offset correction transistor pm1-pmk is connected with the output end of the first current source Ip respectively, the drain of each PMOS offset correction transistor pm1-pmk is connected with the corresponding control end of the correction control circuit respectively, whether the same-direction input PMOS transistor pm0 of the operational amplifier is connected in parallel is controlled by the switch control signal cal_p+[k:1] of the corresponding control end;

[0013] The second transistor array is a reverse-direction input PMOS offset correction transistor array, the second transistor array includes k PMOS offset correction transistors pm1'-pmk', the gate of each PMOS offset correction transistor pm1'-pmk' is connected with the gate of the reverse-direction input PMOS transistor pm0' of the operational amplifier respectively, the source of each PMOS offset correction transistor pm1'-pmk' is connected with the output end of the first current source Ip respectively, the drain of each PMOS offset correction transistor pm1'-pmk' is connected with the corresponding control end of the correction control circuit respectively, whether the reverse-direction input PMOS transistor pm0' of the operational amplifier is connected in parallel is controlled by the switch control signal cal_p-[k:1] of the corresponding control end;

[0014] The third transistor array is a same-direction input NMOS offset correction transistor array, the third transistor array includes k NMOS offset correction transistors nm1-nmk, the gate of each NMOS offset correction transistor nm1-nmk is connected with the gate of the same-direction input NMOS transistor nm0 of the operational amplifier respectively, the source of each NMOS offset correction transistor nm1-nmk is connected with the input end of the second current source In respectively, the drain of each NMOS offset correction transistor nm1-nmk is connected with the corresponding control end of the correction control circuit respectively, whether the same-direction input NMOS transistor nm0 of the operational amplifier is connected in parallel is controlled by the switch control signal cal_n+[k:1] of the corresponding control end;

[0015] The fourth transistor array is an inverted input NMOS offset correction transistor array, the fourth transistor array comprises k NMOS offset correction transistors nm1'~nmk', the gate of each NMOS offset correction transistor nm1'~nmk' is connected with the gate of the inverting input NMOS transistor nm0' of the operational amplifier respectively, the source of each NMOS offset correction transistor nm1'~nmk' is connected with the input end of the second current source In respectively, the drain of each NMOS offset correction transistor nm1'~nmk' is connected with the corresponding control end of the correction control circuit respectively, whether the inverting input NMOS transistor nm0' of the operational amplifier is connected in parallel is controlled by the switch control signal cal_n-[k:1] of the corresponding control end.

[0016] Further, the sizes of the operational amplifier co-directional input PMOS transistor pm0 and the operational amplifier inverted input PMOS transistor pm0' of the PMOS differential pair are equal, the sizes of the PMOS offset correction transistors with the same serial number in the k PMOS offset correction transistors pm1~pmk and the k PMOS offset correction transistors pm1'~pmk' are equal, and the sizes of the k PMOS offset correction transistors pm1~pmk and the k PMOS offset correction transistors pm1'~pmk' used for compensation are set to be much smaller than the sizes of the PMOS differential pair operational amplifier co-directional input PMOS transistor pm0 and the operational amplifier inverted input PMOS transistor pm0', and the sizes of the k PMOS offset correction transistors are set in proportion from small to large;

[0017] The sizes of the operational amplifier co-directional input NMOS transistor nm0 and the operational amplifier inverted input NMOS transistor nm0' of the NMOS differential pair are equal, the sizes of the NMOS offset correction transistors with the same serial number in the k NMOS offset correction transistors nm1~nmk and the k NMOS offset correction transistors nm1'~nmk' are equal, and the sizes of the k NMOS offset correction transistors nm1~nmk and the k NMOS offset correction transistors nm1'~nmk' used for compensation are set to be much smaller than the sizes of the NMOS differential pair operational amplifier co-directional input NMOS transistor nm0 and the operational amplifier inverted input NMOS transistor nm0', and the sizes of the k NMOS offset correction transistors are set in proportion from small to large.

[0018] Further, the correction control circuit comprises a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit;

[0019] The output end of the k-bit P counter is connected with the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends the cal_p+[k:1] control signal to the first transistor array, the output end of the P decoding latch circuit sends the cal_p-[k:1] control signal to the second transistor array,

[0020] The output end of the k-bit N counter is connected with the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends cal_n-[k:1] control signal to the fourth transistor array.

[0021] Further, the correction control circuit further comprises a reset signal end cal_pen of the k-bit P counter, the reset signal end cal_pen of the k-bit P counter is connected with the input end of the k-bit P counter,

[0022] The correction control circuit further comprises a reset signal end cal_nen of the k-bit N counter, the reset signal end cal_nen of the k-bit N counter is connected with the input end of the k-bit N counter;

[0023] The correction control circuit further comprises a clock driving signal end cal_clk, the counting result is added 1 at the rising edge of each clock, and the input end of the k-bit P counter and the input end of the k-bit N counter are connected with the clock driving signal end cal_clk respectively;

[0024] The correction control circuit further comprises a latch control signal end cal_end, the input end of the k-bit P counter, the input end of the P decoding latch circuit, the input end of the k-bit N counter and the input end of the N decoding latch circuit are connected with the latch control signal end cal_end respectively;

[0025] The correction control circuit further comprises a decoding circuit control signal end cal_dir, the input end of the P decoding latch circuit and the input end of the N decoding latch circuit are connected with the decoding circuit control signal end cal_dir respectively.

[0026] Further, the correction flag generation circuit comprises an output signal adjusting circuit, a correction end detection circuit and a correction direction judgment circuit, the input of the output signal adjusting circuit is connected with the output end Vout of the operational amplifier main circuit, the input of the correction end detection circuit and the input of the correction direction judgment circuit are connected with the output of the output signal adjusting circuit respectively, the output of the correction end detection circuit is connected with the correction control circuit through the latch control signal end cal_end, and the output of the correction direction judgment circuit is connected with the correction control circuit through the decoding circuit control signal end cal_dir.

[0027] Further, the application further provides an operation method of the operational amplifier offset voltage automatic correction circuit, applied to the operational amplifier offset voltage automatic correction circuit, and comprising the following steps:

[0028] S100, if the PMOS differential pair transistor is in an offset state, correcting the PMOS differential pair transistor offset;

[0029] S200, if the NMOS differential pair transistor is in an offset state, correcting the NMOS differential pair transistor offset;

[0030] S300, latching the correction result, so that the offsets of the PMOS differential pair transistor and the NMOS differential pair transistor are corrected and compensated to be less than one offset correction step in the whole input range.

[0031] Further, the step S100 comprises:

[0032] S110, setting the reset signal end cal_pen of the k-bit P counter to 0, clearing the output of the k-bit P counter of the correction control circuit and the P decoding latch circuit, and resetting the PMOS transistor correction;

[0033] S120, setting the reset signal end cal_pen of the k-bit P counter to 1, at this time, the level selection switches s1, s2 and s3 are closed, the non-inverting input end Vi+ and the inverting input end Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, and the PMOS correction is enabled;

[0034] S130, based on the level state of the output end Vout of the operational amplifier main circuit, obtaining the correction direction, if the output end Vout is high, setting the control signal end cal_dir of the decoding circuit to 0, and needing to do negative compensation, connecting the compensation transistor to the operational amplifier inverting input end PMOS transistor pm0' of the inverting input end Vi- of the operational amplifier main circuit, if the output end Vout is low, setting the control signal end cal_dir of the decoding circuit to 1, and needing to do positive compensation, connecting the compensation transistor to the operational amplifier non-inverting input end PMOS transistor pm0 of the non-inverting input end Vi+ of the operational amplifier main circuit;

[0035] S140, under the driving of the clock driving signal end cal_clk, the k-bit P counter starts to accumulate counting from 0;

[0036] S150, based on the accumulation result of the k-bit P counter, control the number of offset correction tubes incorporated into the same direction input or reverse input of the PMOS differential pair tube, if the control signal end cal_dir of the decoding circuit is 0, the control signal cal_p+[k:1] of the PMOS offset correction tube of the same direction input is set to 0, and the control signal cal_p-[k:1] of the PMOS offset correction tube of the reverse input is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of PMOS differential pair reverse input offset correction tubes is increased in real time according to the counting result, and vice versa, if the control signal end cal_dir of the decoding circuit is 1, the control signal cal_p-[k:1] of the PMOS offset correction tube of the reverse input is set to 0, and the control signal cal_p+[k:1] of the PMOS offset correction tube of the same direction input is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of PMOS differential pair same direction input offset correction tubes is increased in real time according to the counting result;

[0037] S160, determine whether the offset correction is completed based on the change of the output result of the operational amplifier main circuit, the correction flag generation circuit detects the level state of the output end Vout of the operational amplifier main circuit in real time, if it is detected that the output level of the operational amplifier main circuit flips, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latching circuit is latched, so that the number of compensation transistors connected remains unchanged, if it is detected that the output level of the operational amplifier main circuit does not flip, the latching control signal end cal_end remains 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latching circuit continue to accumulate and increase the number of offset correction tubes incorporated into the PMOS differential pair.

[0038] Further, the step S200 comprises:

[0039] S210, the reset signal end cal_nen of the k-bit N counter is set to 0, the output of the k-bit N counter of the correction control circuit and the N decoding latching circuit is cleared to 0, and the NMOS transistor correction is reset;

[0040] S220, the reset signal end cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2 and s4 are closed, the non-inverting input end Vi+ and the reverse input end Vi- of the operational amplifier main circuit are shorted to the NMOS correction common mode level Vcm_n, and the NMOS correction is enabled;

[0041] S230, based on the level state of the output end Vout of the operational amplifier main circuit, a correction direction is obtained, if the output end Vout is high level, the control signal end cal_dir of the decoding circuit is set to 0, negative compensation is needed, the compensation transistor is connected to the NMOS transistor nm0' of the reverse input end of the operational amplifier main circuit, if the output end Vout is low level, the control signal end cal_dir of the decoding circuit is set to 1, positive compensation is needed, the compensation transistor is connected to the NMOS transistor nm0 of the same direction input end of the operational amplifier main circuit;

[0042] S240, under the driving of the clock driving signal end cal_clk, the k-bit N counter starts to accumulate counting from 0;

[0043] S250, based on the accumulation result of the k-bit N counter, the number of offset correction tubes connected to the same direction input end or reverse input end of the NMOS differential pair tube is controlled, if the control signal end cal_dir of the decoding circuit is 0, the control signal cal_n+[k:1] of the same direction input end NMOS offset correction tube is set to 0, the control signal cal_n-[k:1] of the reverse input end NMOS offset correction tube is equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of offset correction tubes of the reverse input end of the NMOS differential pair is increased in real time according to the counting result, on the contrary, if the control signal end cal_dir of the decoding circuit is 1, the control signal cal_n-[k:1] of the reverse input end NMOS offset correction tube is set to 0, the control signal cal_n+[k:1] of the same direction input end NMOS offset correction tube is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes of the same direction input end of the NMOS differential pair is increased in real time according to the counting result;

[0044] S260, based on the change of the output result of the operational amplifier main circuit, it is judged whether the offset correction is completed, the correction flag generation circuit detects the level state of the output end Vout of the operational amplifier main circuit in real time, if it is detected that the output level of the operational amplifier main circuit is flipped, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and the output result of the N decoding latching circuit is latched, so that the number of compensation transistors connected remains unchanged, if it is detected that the output level of the operational amplifier main circuit is not flipped, the latching control signal end cal_end remains 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latching circuit continue to accumulate, and the number of offset correction tubes connected to the NMOS differential pair is increased.

[0045] The beneficial effects of the present application are:

[0046] The operation amplifier offset voltage automatic correction circuit and method can adapt to a wide power voltage range, has high offset correction precision, and does not need additional comparators and filters and other analog circuits, but only uses digital logic to complete automatic correction control, thereby reducing circuit complexity and cost. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 Fig. 1 shows a whole circuit schematic diagram of an operation amplifier offset voltage automatic correction circuit according to the present application.

[0048] Figure 2 Fig. 2 shows a circuit schematic diagram of one embodiment of an operation amplifier main circuit in the operation amplifier offset voltage automatic correction circuit according to the present application.

[0049] Figure 3 Fig. 3 shows a circuit schematic diagram of one embodiment of a correction control circuit in the operation amplifier offset voltage automatic correction circuit according to the present application.

[0050] Figure 4 Fig. 4 shows a circuit schematic diagram of one embodiment of a correction flag generation circuit in the operation amplifier offset voltage automatic correction circuit according to the present application.

[0051] Figure 5 Fig. 5 shows a flow chart of an operation method of the operation amplifier offset voltage automatic correction circuit according to the present application.

[0052] Figure 6 Fig. 6 shows a flow chart of correcting PMOS differential pair transistor offset in the operation method of the operation amplifier offset voltage automatic correction circuit according to the present application.

[0053] Figure 7 Fig. 7 shows a flow chart of correcting NMOS differential pair transistor offset in the operation method of the operation amplifier offset voltage automatic correction circuit according to the present application. DETAILED DESCRIPTION

[0054] The concept, specific structure and generated technical effects of the present application will be described clearly and completely in combination with embodiments and drawings, so as to fully understand the purpose, scheme and effects of the present application. It should be noted that the embodiments and features in the embodiments in the present application can be combined with each other without conflict.

[0055] It should be noted that, unless otherwise specified, when a certain feature is referred to as being "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. In addition, the up, down, left, right, top, bottom and other descriptions used in the present application are only relative to the relative positions of the components of the present application in the drawings.

[0056] Further, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this technology belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0057] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish one element from another. For example, a first element could also be termed a second element, and, similarly, a second element could also be termed a first element, without departing from the scope of the present disclosure.

[0058] Referring to Figures 1 to 7 In some embodiments, the present application provides an operational amplifier offset voltage automatic correction circuit, referring to Figure 1 , the operational amplifier offset voltage automatic correction circuit comprises:

[0059] An operational amplifier main circuit, comprising an operational amplifier basic circuit and an input offset correction transistor array connected in sequence, the operational amplifier main circuit comprising at least a non-inverting input terminal Vi+, an inverting input terminal Vi- and an output terminal Vout;

[0060] An automatic correction circuit, comprising a correction control circuit and a correction flag generation circuit connected in sequence, the first transistor array, the second transistor array, the third transistor array and the fourth transistor array are electrically connected with the output terminal of the correction control circuit, and the correction flag generation circuit is electrically connected with the output terminal Vout of the operational amplifier main circuit.

[0061] The present application has the following advantages:

[0062] The operational amplifier offset voltage automatic correction circuit and method can adapt to a wide range of power supply voltage, and has high offset correction precision. The proposed offset voltage automatic correction circuit does not need additional comparators and filters and other analog circuits, but only uses digital logic to complete automatic correction control, which reduces the circuit complexity and cost.

[0063] Specifically, referring to Figure 1 , the signal names are explained as follows:

[0064] 1) Vi+, Vi- are a set of differential input signal terminals of the operational amplifier;

[0065] 2) Vout is the output signal of the operational amplifier;

[0066] 3) Vcm_p is the common mode level of PMOS differential pair for offset correction;

[0067] 4) Vcm_n is the common mode level of NMOS differential pair for offset correction;

[0068] 5) cal_pen is the enable signal of PMOS differential pair for offset correction;

[0069] 6) cal_nen is the enable signal of NMOS differential pair for offset correction;

[0070] 7) cal_en is the enable signal of differential pair for offset correction, which is obtained by OR logic of cal_pen and cal_nen, that is, whether PMOS differential pair or NMOS differential pair is enabled for correction, cal_en will be set to 1;

[0071] 8) cal_clk is the clock signal of offset correction;

[0072] 9) cal_dir is the flag signal of offset correction direction;

[0073] 10) cal_end is the flag signal of offset correction completion;

[0074] 11) cal_p+[k:1] is the control signal of k-bit operational amplifier same direction input end PMOS offset correction tube;

[0075] 12) cal_p-[k:1] is the control signal of k-bit operational amplifier reverse input end PMOS offset correction tube;

[0076] 13) cal_n+[k:1] is the control signal of k-bit operational amplifier same direction input end NMOS offset correction tube;

[0077] 14) cal_n-[k:1] is the control signal of k-bit operational amplifier reverse input end NPMOS offset correction tube.

[0078] Wherein, the size of Vcm_p is set to be less than the threshold voltage Vthn of NMOS tube, so that only PMOS differential pair is enabled, and NMOS differential pair is disabled; the size of Vcm_n is set to be less than the power supply voltage VDD, and greater than the absolute value difference between VDD and the threshold voltage Vthp of PMOS tube, so that only NMOS differential pair is enabled, and PMOS differential pair is disabled.

[0079] Further, referring to Figure 2 , the operational amplifier basic circuit comprises an input differential pair tube and an operational amplifier output stage, and the input differential pair tube comprises a PMOS differential pair tube and an NMOS differential pair tube; wherein,

[0080] The PMOS differential pair tube comprises a PMOS transistor pm0 of a same direction input end of an operational amplifier and a PMOS transistor pm0' of an opposite direction input end of the operational amplifier, a source of the PMOS transistor pm0 of the same direction input end of the operational amplifier is connected with an output end of a first current source Ip, a drain of the PMOS transistor pm0 of the same direction input end of the operational amplifier is connected with a first input end of an output stage of the operational amplifier, and a gate of the PMOS transistor pm0 of the same direction input end of the operational amplifier is connected with a first transistor array of the input offset correction transistor array; a source of the PMOS transistor pm0' of the opposite direction input end of the operational amplifier is connected with the output end of the first current source Ip, a drain of the PMOS transistor pm0' of the opposite direction input end of the operational amplifier is connected with a second input end of the output stage of the operational amplifier, and a gate of the PMOS transistor pm0' of the opposite direction input end of the operational amplifier is connected with a second transistor array of the input offset correction transistor array.

[0081] The NMOS differential pair tube comprises an NMOS transistor nm0 of a same direction input end of an operational amplifier and an NMOS transistor nm0' of an opposite direction input end of the operational amplifier, a source of the NMOS transistor nm0 of the same direction input end of the operational amplifier is connected with an output end of a second current source In, a drain of the NMOS transistor nm0 of the same direction input end of the operational amplifier is connected with a third input end of an output stage of the operational amplifier, and a gate of the NMOS transistor nm0 of the same direction input end of the operational amplifier is connected with a third transistor array of the input offset correction transistor array; a source of the NMOS transistor nm0' of the opposite direction input end of the operational amplifier is connected with the output end of the second current source In, a drain of the NMOS transistor nm0' of the opposite direction input end of the operational amplifier is connected with a fourth input end of the output stage of the operational amplifier, and a gate of the NMOS transistor nm0' of the opposite direction input end of the operational amplifier is connected with a fourth transistor array of the input offset correction transistor array.

[0082] Specifically, referring to Figure 2 , the operational amplifier basic circuit comprises an input differential pair and an output stage, wherein the input differential pair is composed of a group of PMOS differential pairs pm0 and pm0' and a group of NMOS differential pairs nm0 and nm0', the PMOS differential pair pm0 is a PMOS transistor of a same direction input end of an operational amplifier, the PMOS differential pair pm0' is a PMOS transistor of an opposite direction input end of the operational amplifier, the NMOS differential pair nm0 is an NMOS transistor of the same direction input end of the operational amplifier, and the NMOS differential pair nm0' is an NMOS transistor of the opposite direction input end of the operational amplifier.

[0083] Further, referring to Figure 2 , the input offset correction transistor array comprises a first transistor array, a second transistor array, a third transistor array and a fourth transistor array,

[0084] The first transistor array is a same-direction input PMOS offset correction transistor array, the first transistor array includes k PMOS offset correction transistors pm1-pmk, the gate of each PMOS offset correction transistor pm1-pmk is connected with the gate of the same-direction input PMOS transistor pm0 of the operational amplifier respectively, the source of each PMOS offset correction transistor pm1-pmk is connected with the output end of the first current source Ip respectively, the drain of each PMOS offset correction transistor pm1-pmk is connected with the corresponding control end of the correction control circuit respectively, whether the same-direction input PMOS transistor pm0 of the operational amplifier is connected in parallel is controlled by the switch control signal cal_p+[k:1] of the corresponding control end;

[0085] The second transistor array is a reverse-direction input PMOS offset correction transistor array, the second transistor array includes k PMOS offset correction transistors pm1'-pmk', the gate of each PMOS offset correction transistor pm1'-pmk' is connected with the gate of the reverse-direction input PMOS transistor pm0' of the operational amplifier respectively, the source of each PMOS offset correction transistor pm1'-pmk' is connected with the output end of the first current source Ip respectively, the drain of each PMOS offset correction transistor pm1'-pmk' is connected with the corresponding control end of the correction control circuit respectively, whether the reverse-direction input PMOS transistor pm0' of the operational amplifier is connected in parallel is controlled by the switch control signal cal_p-[k:1] of the corresponding control end;

[0086] The third transistor array is a same-direction input NMOS offset correction transistor array, the third transistor array includes k NMOS offset correction transistors nm1-nmk, the gate of each NMOS offset correction transistor nm1-nmk is connected with the gate of the same-direction input NMOS transistor nm0 of the operational amplifier respectively, the source of each NMOS offset correction transistor nm1-nmk is connected with the input end of the second current source In respectively, the drain of each NMOS offset correction transistor nm1-nmk is connected with the corresponding control end of the correction control circuit respectively, whether the same-direction input NMOS transistor nm0 of the operational amplifier is connected in parallel is controlled by the switch control signal cal_n+[k:1] of the corresponding control end;

[0087] The fourth transistor array is an inverted input NMOS offset correction transistor array, and the fourth transistor array comprises k NMOS offset correction transistors nm1' to nmk'. The gate of each NMOS offset correction transistor nm1' to nmk' is connected with the gate of the inverting input NMOS transistor nm0' of the operational amplifier, the source of each NMOS offset correction transistor nm1' to nmk' is connected with the input end of the second current source In, and the drain of each NMOS offset correction transistor nm1' to nmk' is connected with a corresponding control end of the correction control circuit. Whether the inverting input NMOS transistor nm0' of the operational amplifier is connected in parallel is controlled by the switch control signal cal_n-[k:1] of the corresponding control end.

[0088] Specifically, referring to Figure 2 , the input offset correction transistor array comprises four transistor arrays:

[0089] The first transistor array is a same-direction input PMOS offset correction transistor array, and pmk to pm1 are k offset correction transistors of the same-direction input PMOS pm0. Whether pm0 is connected in parallel is controlled by the switch control signal cal_p+[k:1].

[0090] Specifically, cal_p+[k:1] is a k-bit control signal of the same-direction input PMOS offset correction transistor of the operational amplifier. If a certain bit cal_p+[i] = 1, the corresponding switch is closed, and the i-th P-type offset correction transistor pmi of the first transistor array is connected in parallel to the input transistor pm0 of the same-phase input end. If cal_p+[i] = 0, the corresponding switch is opened, and the i-th P-type offset correction transistor pmi of the first transistor array is disconnected from the input transistor pm0 of the same-phase input end. Wherein i = 1, 2, …, k.

[0091] The second transistor array is an inverted input PMOS offset correction transistor array, and pmk' to pm1' are k offset correction transistors of the inverted input PMOS pm0'. Whether pm0' is connected in parallel is controlled by the switch control signal cal_p-[k:1].

[0092] Specifically, cal_p-[k:1] is a k-bit control signal of the inverted input PMOS offset correction transistor of the operational amplifier. If a certain bit cal_p-[i] = 1, the corresponding switch is closed, and the i-th P-type offset correction transistor pmi' of the second transistor array is connected in parallel to the input transistor pm0' of the inverted input end. If cal_p-[i] = 0, the corresponding switch is opened, and the i-th P-type offset correction transistor pmi' of the second transistor array is disconnected from the input transistor pm0' of the inverted input end. Wherein i = 1, 2, …, k.

[0093] The third transistor array is a same-direction input NMOS offset correction tube array, nmk~nm1 is k offset correction tubes of the same-direction input NMOS nm0, and whether to be connected in parallel to nm0 is controlled by the switch control signal cal_n+[k:1].

[0094] Specifically, cal_n+[k:1] is a k-bit control signal of the same-direction input NMOS offset correction tube of the operational amplifier, if a certain bit cal_n+[i]=1, the corresponding switch is closed, and the i-th N-type offset correction tube nmi of the third transistor array is connected in parallel to the same-phase input tube nm0; if cal_n+[i]=0, the corresponding switch is opened, and the i-th N-type offset correction tube nmi of the third transistor array is disconnected from the same-phase input tube nm0; wherein i=1, 2, …, k.

[0095] The fourth transistor array is a reverse input NMOS offset correction tube array, nmk'~nm1' is k offset correction tubes of the reverse input NMOS nm0', and whether to be connected in parallel to nm0' is controlled by the switch control signal cal_n-[k:1].

[0096] Specifically, cal_n-[k:1] is a k-bit control signal of the reverse input NMOS offset correction tube of the operational amplifier, if a certain bit cal_n-[i]=1, the corresponding switch is closed, and the i-th N-type offset correction tube nmi' of the fourth transistor array is connected in parallel to the inverse-phase input tube nm0'; if cal_n-[i]=0, the corresponding switch is opened, and the i-th N-type offset correction tube nmi' of the fourth transistor array is disconnected from the inverse-phase input tube nm0'; wherein i=1, 2, …, k.

[0097] Further, with reference to Figure 2 , the size of the same-direction input PMOS transistor pm0 of the PMOS differential pair tube and the size of the reverse input PMOS transistor pm0' of the operational amplifier are equal, among the k PMOS offset correction tubes pm1~pmk and the k PMOS offset correction tubes pm1'~pmk', the PMOS offset correction tubes with the same serial number are equal in size, and the size of the k PMOS offset correction tubes pm1~pmk and the k PMOS offset correction tubes pm1'~pmk' used for compensation are set to be much smaller than the size of the same-direction input PMOS transistor pm0 of the PMOS differential pair tube and the size of the reverse input PMOS transistor pm0' of the operational amplifier, and the sizes of the k PMOS offset correction tubes are set in proportion from small to large;

[0098] The NMOS differential pair tube has an NMOS transistor nm0 at the same direction input end of the operational amplifier and an NMOS transistor nm0' at the opposite direction input end of the operational amplifier, and the sizes of the NMOS transistor nm0 and the NMOS transistor nm0' are equal. In the k NMOS offset correction tubes nm1-nmk and the k NMOS offset correction tubes nm1'-nmk', the sizes of the offset correction tubes with the same serial number are equal, and the sizes of the k NMOS offset correction tubes nm1-nmk and the k NMOS offset correction tubes nm1'-nmk' used for compensation are set to be much smaller than the sizes of the NMOS transistor nm0 and the NMOS transistor nm0' of the NMOS differential pair tube, and the sizes of the k NMOS offset correction tubes are set in proportion from small to large.

[0099] Specifically, the PMOS differential pair tube pm0 and pm0' have equal sizes, the PMOS offset correction tubes pmk-pm1 and pmk'-pm1' with the same serial number have equal sizes, and the sizes of the offset correction tubes pmk-pm1 and pmk'-pm1' used for compensation are set to be much smaller than the sizes of the PMOS differential pair tube pm0 and pm0'. The sizes of the offset correction tubes can be set in proportion from small to large. The NMOS differential pair tube nm0 and nm0' have equal sizes, the NMOS offset correction tubes nmk-nm1 and nmk'-nm1' with the same serial number have equal sizes, and the sizes of the offset correction tubes nmk-nm1 and nmk'-nm1' used for compensation are set to be much smaller than the sizes of the NMOS differential pair tube nm0 and nm0'. The sizes of the offset correction tubes can be set in proportion from small to large.

[0100] Further, referring to Figure 3 , the correction control circuit comprises a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit;

[0101] The output end of the k-bit P counter is connected with the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends a cal_p+[k:1] control signal to the first transistor array, the output end of the P decoding latch circuit sends a cal_p-[k:1] control signal to the second transistor array,

[0102] The output end of the k-bit N counter is connected with the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends a cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends a cal_n-[k:1] control signal to the fourth transistor array.

[0103] Further, referring to Figure 3 , the correction control circuit further comprises a reset signal end cal_pen of the k-bit P counter, the reset signal end cal_pen of the k-bit P counter is connected with the input end of the k-bit P counter,

[0104] The correction control circuit further comprises a reset signal end cal_nen of the k-bit N counter, which is connected with the input end of the k-bit N counter;

[0105] The correction control circuit further comprises a clock driving signal end cal_clk, which adds 1 to the counting result at the rising edge of each clock, and the input end of the k-bit P counter and the input end of the k-bit N counter are connected with the clock driving signal end cal_clk respectively;

[0106] The correction control circuit further comprises a latch control signal end cal_end, and the input end of the k-bit P counter, the input end of the P decode latch circuit, the input end of the k-bit N counter and the input end of the N decode latch circuit are connected with the latch control signal end cal_end respectively;

[0107] The correction control circuit further comprises a control signal end cal_dir of the decode circuit, and the input end of the P decode latch circuit and the input end of the N decode latch circuit are connected with the control signal end cal_dir of the decode circuit respectively.

[0108] Specifically, referring to Figure 3 ,

[0109] cal_clk is the clock driving signal of the two counters, and adds 1 to the counting result at the rising edge of each clock.

[0110] cal_pen is the reset signal of the k-bit P counter, cal_pen=0, the PMOS differential pair correction is closed, and the output result cal_pi[k:1] of the k-bit P counter is reset to 0; cal_pen=1, the counting function of the k-bit P counter is opened.

[0111] cal_nen is the reset signal of the k-bit N counter, cal_nen=0, the NMOS differential pair correction is closed, and the output result cal_ni[k:1] of the k-bit N counter is reset to 0; cal_nen=1, the counting function of the k-bit N counter is opened.

[0112] cal_end is the control signal of the counter and the latch control signal of the decode latch circuit, cal_end=0 when the correction is not completed, the counter normally counts; cal_end is 1 when the correction is completed, the counter stops counting, the counting result is kept, and the correction result is latched.

[0113] cal_dir as two decoding circuit control signal, if cal_dir = 0, it is indicated that the current operational amplifier exists positive offset voltage, and negative compensation is needed, therefore cal_p + [k:1] and cal_n + [k:1] are set to 0, and encoding control cal_p - [k:1] = cal_pi [k:1], cal_n - [k:1] = cal_ni [k:1]; on the contrary, if cal_dir = 1, it is indicated that the current operational amplifier exists negative offset voltage, and positive compensation is needed, therefore cal_p - [k:1] and cal_n - [k:1] are set to 0, and encoding control cal_p + [k:1] = cal_pi [k:1], cal_n + [k:1] = cal_ni [k:1].

[0114] Further, with reference to Figure 4 , the correction flag generation circuit includes an output signal adjustment circuit, a correction end detection circuit and a correction direction judgment circuit, the input of the output signal adjustment circuit is connected with the output Vout of the operational amplifier main circuit, the output of the output signal adjustment circuit is connected with the input of the correction end detection circuit and the input of the correction direction judgment circuit respectively, the output of the correction end detection circuit is connected with the correction control circuit through the latch control signal end cal_end, and the output of the correction direction judgment circuit is connected with the correction control circuit through the control signal end cal_dir of the decoding circuit.

[0115] Specifically, with reference to Figure 4 , the correction end detection circuit is used for detecting the edge flip of the operational amplifier output Vout in the correction process, if the edge flip of Vout does not occur in the correction process, cal_end = 0, indicating that the correction is not completed, and the correction continues, if the level high-low jump of Vout occurs in the correction process, cal_end will be set to 1, indicating that the correction is completed, and the correction stops. The correction direction judgment circuit is used for obtaining the correction direction. Define the offset voltage Vos = Vi+-Vi-, if Vout is high when the correction just starts, it indicates that Vos = Vi+-Vi->0, indicating that the current operational amplifier exists positive offset voltage, and negative compensation is needed, cal_dir is set to 0, and the correction control circuit is controlled to generate negative compensation control signal; on the contrary, if Vout is low when the correction just starts, it indicates that Vos = Vi+-Vi-<0, indicating that the current operational amplifier exists negative offset voltage, and positive compensation is needed, cal_dir is set to 1, and the correction control circuit is controlled to generate positive compensation control signal.

[0116] The offset correction direction flag signal cal_dir is used to control the correction direction, which can reduce the correction steps and improve the correction efficiency.

[0117] In the output signal adjusting circuit, Vout is an analog signal which needs to be shaped and level converted by the output signal adjusting circuit, and then connected to the following two digital circuits (detection circuit and judgment circuit). Two-stage inverters are used here to achieve this purpose.

[0118] Further, with reference to Figure 5 The application further provides an operation method of the operational amplifier offset voltage automatic correction circuit, which is applied to the operational amplifier offset voltage automatic correction circuit, and includes the following steps:

[0119] S100, if the PMOS differential pair transistor is in an offset state, correcting the PMOS differential pair transistor offset;

[0120] S200, if the NMOS differential pair transistor is in an offset state, correcting the NMOS differential pair transistor offset;

[0121] S300, latching the correction result, so that the offsets of the PMOS differential pair transistor and the NMOS differential pair transistor are corrected and compensated to be less than one offset correction step in the whole input range.

[0122] Specifically, as to the step S100 and the step S200, in engineering practice, the chip is tested in a large quantity in a machine, and it will not increase the cost to determine whether the PMOS transistor is offset or the NMOS transistor is offset, but the offsets of the PMOS and the NMOS are corrected at one time.

[0123] Further, with reference to Figure 6 The step S100 includes:

[0124] S110, setting the reset signal end cal_pen of the k-bit P counter to 0, so that the output of the k-bit P counter of the correction control circuit and the P decoding latch circuit is cleared to 0, and the PMOS transistor is corrected and reset;

[0125] S120, setting the reset signal end cal_pen of the k-bit P counter to 1, at this time, the level selection switches s1, s2 and s3 are closed, the non-inverting input end Vi+ and the inverting input end Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, and the PMOS correction is enabled;

[0126] S130, based on the level state of the output terminal Vout of the operational amplifier main circuit, obtaining a correction direction, if the output terminal Vout is high, setting the control signal end cal_dir of the decoding circuit to 0, needing to do negative compensation, connecting a compensation transistor on the PMOS transistor pm0' of the reverse input end of the operational amplifier main circuit, if the output terminal Vout is low, setting the control signal end cal_dir of the decoding circuit to 1, needing to do positive compensation, connecting a compensation transistor on the PMOS transistor pm0 of the same direction input end of the operational amplifier main circuit;

[0127] S140, under the driving of the clock driving signal end cal_clk, the k-bit P counter starts to accumulate from 0;

[0128] S150, based on the accumulation result of the k-bit P counter, controlling the number of offset correction tubes connected to the same direction input end or reverse input end of the PMOS differential pair tube, if the control signal end cal_dir of the decoding circuit is 0, setting the control signal cal_p+[k:1] of the same direction input end PMOS offset correction tube to 0, and the control signal cal_p-[k:1] of the reverse input end PMOS offset correction tube is equal to the output cal_pi[k:1] of the k-bit P counter, that is, according to the counting result, the number of PMOS differential pair reverse input end offset correction tubes is increased in real time, on the contrary, if the control signal end cal_dir of the decoding circuit is 1, setting the control signal cal_p-[k:1] of the reverse input end PMOS offset correction tube to 0, and the control signal cal_p+[k:1] of the same direction input end PMOS offset correction tube is equal to the output cal_pi[k:1] of the k-bit P counter, that is, according to the counting result, the number of PMOS differential pair same direction input end offset correction tubes is increased in real time;

[0129] S160, judging whether the offset correction is completed based on the change of the output result of the operational amplifier main circuit, the correction flag generation circuit detects the level state of the output terminal Vout of the operational amplifier main circuit in real time, if it is detected that the output level of the operational amplifier main circuit is flipped, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latching circuit is latched, so that the number of compensation transistors connected remains unchanged, if it is detected that the output level of the operational amplifier main circuit is not flipped, the latching control signal end cal_end remains 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latching circuit continue to accumulate, and the number of offset correction tubes connected to the PMOS differential pair is increased.

[0130] Further, with reference to Figure 7 , the step S200 comprises:

[0131] S210, the reset signal end cal_nen of the k-bit N counter is set to 0, so that the output of the k-bit N counter of the correction control circuit and the N decoding latch circuit is cleared, and the NMOS transistor correction reset is enabled;

[0132] S220, the reset signal end cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2 and s4 are closed, the non-inverting input end Vi+ and the inverting input end Vi- of the operational amplifier main circuit are shorted to the NMOS correction common mode level Vcm_n, and the NMOS correction is enabled;

[0133] S230, based on the level state of the output end Vout of the operational amplifier main circuit, the correction direction is obtained, if the output end Vout is high, the control signal end cal_dir of the decoding circuit is set to 0, negative compensation is needed, the compensation transistor is connected to the operational amplifier inverting input end NMOS transistor nm0' of the inverting input end Vi- of the operational amplifier main circuit, if the output end Vout is low, the control signal end cal_dir of the decoding circuit is set to 1, positive compensation is needed, and the compensation transistor is connected to the operational amplifier same input end NMOS transistor nm0 of the same input end Vi+ of the operational amplifier main circuit;

[0134] S240, under the driving of the clock driving signal end cal_clk, the k-bit N counter starts to accumulate count from 0;

[0135] S250, based on the accumulation result of the k-bit N counter, the number of offset correction tubes connected to the same input end or the inverting input end of the NMOS differential pair tube is controlled, if the control signal end cal_dir of the decoding circuit is 0, the control signal cal_n+[k:1] of the same input end NMOS offset correction tube is set to 0, and the control signal cal_n-[k:1] of the inverting input end NMOS offset correction tube is equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of offset correction tubes connected to the inverting input end of the NMOS differential pair is increased in real time according to the counting result, on the contrary, if the control signal end cal_dir of the decoding circuit is 1, the control signal cal_n-[k:1] of the inverting input end NMOS offset correction tube is set to 0, and the control signal cal_n+[k:1] of the same input end NMOS offset correction tube is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of offset correction tubes connected to the same input end of the NMOS differential pair is increased in real time according to the counting result;

[0136] S260, judging whether the offset correction is completed based on the change of the output result of the operational amplifier main circuit, the correction flag generation circuit detects the level state of the output end Vout of the operational amplifier main circuit in real time, if the output level of the operational amplifier main circuit is detected to be flipped, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and the output result of the N decoding latch circuit is latched, so that the number of the compensation transistors is kept unchanged, if the output level of the operational amplifier main circuit is detected not to be flipped, the latching control signal end cal_end is kept as 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latch circuit continue to accumulate, and the number of the offset correction tubes of the NMOS differential pair is increased.

[0137] Specifically, s1, s2, s3 and s4 are level selection switches, wherein the control end of s1 and s2 is connected with cal_en, the control end of s3 is connected with cal_pen, and the control end of s4 is connected with cal_nen. When the level of the control end of the switch is 1, the switch is turned on, and vice versa.

[0138] In a specific embodiment, the control signals cal_p+[k:1], cal_p-[k:1], cal_n+[k:1] and cal_n-[k:1] of the offset correction tubes when the correction is completed are latched and loaded to the input offset correction transistor array in the step S300.

[0139] At this time, the offset of the PMOS differential pair tube and the NMOS differential pair tube is corrected and compensated, and the offset of the operational amplifier in the entire input range during normal operation will be less than one offset correction step. The size of the correction step determines the size of the offset voltage after the final correction. By setting the size of the offset correction tube to be smaller and increasing the correction bit number k, the correction can be more precise.

[0140] In addition, in the steps S100 and S200, the PMOS differential pair tube offset correction and the NMOS differential pair tube offset correction have no sequence, but must be performed separately, and after one of them is corrected, the other one is corrected.

[0141] Normally, the chip only needs to be corrected once when it is shipped, and the correction result is saved. When used subsequently, the operational amplifier can be kept in the compensated low offset state by loading the factory correction result.

[0142] The above merely describes preferred embodiments of the present application, and the present application is not limited to the above-described embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure. All shall belong to the protection scope of the present application. The technical solutions and / or embodiments within the protection scope of the present application can have various modifications and changes.

Claims

1. An automatic offset voltage correction circuit for an operational amplifier, characterized by The operation amplifier main circuit comprises an operation amplifier basic circuit and an input offset correction transistor array, The operation amplifier main circuit comprises a non-inverting input terminal Vi+, an inverting input terminal Vi-, and an output terminal Vout, the operation amplifier basic circuit comprises an input differential pair and an operation amplifier output stage, and the input differential pair comprises a PMOS differential pair and an NMOS differential pair; wherein, The input offset correction transistor array comprises a first transistor array, a second transistor array, a third transistor array, and a fourth transistor array, The first transistor array comprises a plurality of PMOS offset correction tubes, the gate of each PMOS offset correction tube is connected with the gate of the PMOS transistor of the operation amplifier non-inverting input terminal of the PMOS differential pair, the source is connected with the output terminal of the first current source Ip, and the drain is connected with the corresponding control terminal of the correction control circuit; The second transistor array comprises a plurality of PMOS offset correction tubes, the gate of each PMOS offset correction tube is connected with the gate of the PMOS transistor of the operation amplifier inverting input terminal of the PMOS differential pair, the source is connected with the output terminal of the first current source Ip, and the drain is connected with the corresponding control terminal of the correction control circuit; The third transistor array comprises a plurality of NMOS offset correction tubes, the gate of each NMOS offset correction tube is connected with the gate of the NMOS transistor of the operation amplifier non-inverting input terminal of the NMOS differential pair, the source is connected with the input terminal of the second current source In, and the drain is connected with the corresponding control terminal of the correction control circuit; The fourth transistor array comprises a plurality of NMOS offset correction tubes, the gate of each NMOS offset correction tube is connected with the gate of the NMOS transistor of the operation amplifier inverting input terminal of the NMOS differential pair, the source is connected with the input terminal of the second current source In, and the drain is connected with the corresponding control terminal of the correction control circuit; an automatic correction circuit, the automatic correction circuit comprises a correction control circuit and a correction flag generation circuit connected in sequence, the first transistor array, the second transistor array, the third transistor array, and the fourth transistor array are electrically connected with the output terminal of the correction control circuit, and the correction flag generation circuit is electrically connected with the output terminal Vout of the operation amplifier main circuit.

2. The operation amplifier offset voltage automatic correction circuit according to claim 1, wherein, ​ The first transistor array is a same-direction input PMOS offset correction transistor array, the first transistor array comprises k PMOS offset correction transistors pm1-pmk, the gate of each PMOS offset correction transistor pm1-pmk is connected with the gate of an operational amplifier same-direction input PMOS transistor pm0 respectively, the source of each PMOS offset correction transistor pm1-pmk is connected with the output of a first current source Ip respectively, the drain of each PMOS offset correction transistor pm1-pmk is connected with a corresponding control end of a correction control circuit respectively, whether to be connected in parallel with the operational amplifier same-direction input PMOS transistor pm0 is controlled by a switch control signal cal_p+[k:1] of the corresponding control end; The second transistor array is a reverse-direction input PMOS offset correction transistor array, the second transistor array comprises k PMOS offset correction transistors pm1'-pmk', the gate of each PMOS offset correction transistor pm1'-pmk' is connected with the gate of an operational amplifier reverse-direction input PMOS transistor pm0' respectively, the source of each PMOS offset correction transistor pm1'-pmk' is connected with the output of the first current source Ip respectively, the drain of each PMOS offset correction transistor pm1'-pmk' is connected with a corresponding control end of the correction control circuit respectively, whether to be connected in parallel with the operational amplifier reverse-direction input PMOS transistor pm0' is controlled by a switch control signal cal_p-[k:1] of the corresponding control end; The third transistor array is a same-direction input NMOS offset correction transistor array, the third transistor array comprises k NMOS offset correction transistors nm1-nmk, the gate of each NMOS offset correction transistor nm1-nmk is connected with the gate of an operational amplifier same-direction input NMOS transistor nm0 respectively, the source of each NMOS offset correction transistor nm1-nmk is connected with the input of a second current source In respectively, the drain of each NMOS offset correction transistor nm1-nmk is connected with a corresponding control end of the correction control circuit respectively, whether to be connected in parallel with the operational amplifier same-direction input NMOS transistor nm0 is controlled by a switch control signal cal_n+[k:1] of the corresponding control end; The fourth transistor array is a reverse-direction input NMOS offset correction transistor array, the fourth transistor array comprises k NMOS offset correction transistors nm1'-nmk', the gate of each NMOS offset correction transistor nm1'-nmk' is connected with the gate of an operational amplifier reverse-direction input NMOS transistor nm0' respectively, the source of each NMOS offset correction transistor nm1'-nmk' is connected with the input of the second current source In respectively, the drain of each NMOS offset correction transistor nm1'-nmk' is connected with a corresponding control end of the correction control circuit respectively, whether to be connected in parallel with the operational amplifier reverse-direction input NMOS transistor nm0' is controlled by a switch control signal cal_n-[k:1] of the corresponding control end. The PMOS differential pair tube comprises a PMOS transistor pm0 of a same direction input of an operational amplifier and a PMOS transistor pm0' of an opposite direction input of the operational amplifier, the source of the PMOS transistor pm0 of the same direction input of the operational amplifier is connected with an output end of a first current source Ip, the drain of the PMOS transistor pm0 of the same direction input of the operational amplifier is connected with a first input end of an output stage of the operational amplifier, and the gate of the PMOS transistor pm0 of the same direction input of the operational amplifier is connected with a first transistor array of an input offset correction transistor array; the source of the PMOS transistor pm0' of the opposite direction input of the operational amplifier is connected with the output end of the first current source Ip, the drain of the PMOS transistor pm0' of the opposite direction input of the operational amplifier is connected with a second input end of the output stage of the operational amplifier, and the gate of the PMOS transistor pm0' of the opposite direction input of the operational amplifier is connected with a second transistor array of the input offset correction transistor array; The NMOS differential pair tube comprises an NMOS transistor nm0 of a same direction input of an operational amplifier and an NMOS transistor nm0' of an opposite direction input of the operational amplifier, the source of the NMOS transistor nm0 of the same direction input of the operational amplifier is connected with an output end of a second current source In, the drain of the NMOS transistor nm0 of the same direction input of the operational amplifier is connected with a third input end of an output stage of the operational amplifier, and the gate of the NMOS transistor nm0 of the same direction input of the operational amplifier is connected with a third transistor array of an input offset correction transistor array; the source of the NMOS transistor nm0' of the opposite direction input of the operational amplifier is connected with the output end of the second current source In, the drain of the NMOS transistor nm0' of the opposite direction input of the operational amplifier is connected with a fourth input end of the output stage of the operational amplifier, and the gate of the NMOS transistor nm0' of the opposite direction input of the operational amplifier is connected with a fourth transistor array of the input offset correction transistor array.

3. The automatic offset voltage correction circuit of the operational amplifier according to claim 1, wherein The PMOS transistor pm0 of the same direction input of the operational amplifier and the PMOS transistor pm0' of the opposite direction input of the operational amplifier of the PMOS differential pair tube are equal in size, the PMOS offset correction tubes pm1~pmk and the PMOS offset correction tubes pm1'~pmk' are equal in size, the PMOS offset correction tubes pm1~pmk and the PMOS offset correction tubes pm1'~pmk' are set to be much smaller than the PMOS transistor pm0 of the same direction input of the operational amplifier and the PMOS transistor pm0' of the opposite direction input of the operational amplifier in size, and the sizes of the PMOS offset correction tubes are set in proportion from small to large. The NMOS differential pair transistor of the operational amplifier has a same size of NMOS transistor nm0 at the same direction input end and a same size of NMOS transistor nm0' at the opposite direction input end, the same serial number of NMOS offset correction transistor in the k NMOS offset correction transistors nm1-nmk and the k NMOS offset correction transistors nm1'-nmk' has a same size, and the size of the k NMOS offset correction transistors nm1-nmk and the k NMOS offset correction transistors nm1'-nmk' is set to be much smaller than the size of the NMOS differential pair transistor of the operational amplifier, and the size of the k NMOS offset correction transistors is set in proportion from small to large.

4. The automatic correction circuit for the offset voltage of the operational amplifier according to claim 1, characterized in that, the correction control circuit comprises a k-bit P counter, a k-bit N counter, a P decoding latch circuit and an N decoding latch circuit; the output end of the k-bit P counter is connected with the input end of the P decoding latch circuit, the output end of the P decoding latch circuit sends a cal_p+[k:1] control signal to the first transistor array, the output end of the P decoding latch circuit sends a cal_p-[k:1] control signal to the second transistor array, the output end of the k-bit N counter is connected with the input end of the N decoding latch circuit, the output end of the N decoding latch circuit sends a cal_n+[k:1] control signal to the third transistor array, and the output end of the N decoding latch circuit sends a cal_n-[k:1] control signal to the fourth transistor array.

5. The automatic correction circuit for the offset voltage of the operational amplifier according to claim 4, characterized in that, the correction control circuit further comprises a reset signal end cal_pen of the k-bit P counter, the reset signal end cal_pen of the k-bit P counter is connected with the input end of the k-bit P counter, the correction control circuit further comprises a reset signal end cal_nen of the k-bit N counter, the reset signal end cal_nen of the k-bit N counter is connected with the input end of the k-bit N counter, the correction control circuit further comprises a clock driving signal end cal_clk, the clock driving signal end cal_clk counts the result by 1 at the rising edge of each clock, and the input end of the k-bit P counter and the input end of the k-bit N counter are respectively connected with the clock driving signal end cal_clk; the correction control circuit further comprises a latch control signal end cal_end, the input end of the k-bit P counter, the input end of the P decoding latch circuit, the input end of the k-bit N counter and the input end of the N decoding latch circuit are respectively connected with the latch control signal end cal_end; the correction control circuit further comprises a control signal end cal_dir of the decoding circuit, and the input end of the P decoding latch circuit and the input end of the N decoding latch circuit are respectively connected with the control signal end cal_dir of the decoding circuit.

6. The automatic correction circuit for the offset voltage of an operational amplifier according to claim 1, characterized in that, the correction flag generating circuit comprises an output signal adjusting circuit, a correction end detection circuit and a correction direction judging circuit, the input of the output signal adjusting circuit is connected with the output Vout of the operational amplifier main circuit, the input of the correction end detection circuit and the input of the correction direction judging circuit are respectively connected with the output of the output signal adjusting circuit, the output of the correction end detection circuit is connected with the correction control circuit through the latch control signal end cal_end, and the output of the correction direction judging circuit is connected with the correction control circuit through the control signal end cal_dir of the decoding circuit.

7. A method of operating an operational amplifier offset voltage auto-correction circuit, the method comprising: The method for operating the automatic correction circuit for the offset voltage of an operational amplifier according to any one of claims 1 to 6 comprises the following steps: S100, if the PMOS differential pair is in an offset state, correcting the offset of the PMOS differential pair; S200, if the NMOS differential pair is in an offset state, correcting the offset of the NMOS differential pair; S300, latching the correction result, so that the offsets of the PMOS differential pair and the NMOS differential pair of the operational amplifier are all corrected and compensated to be less than an offset correction step within the entire input range.

8. The method of claim 7, wherein: The step S100 comprises: S110, setting the reset signal end cal_pen of the k-bit P counter to 0, so that the output of the k-bit P counter of the correction control circuit and the P decoding latch circuit is cleared to 0, and the PMOS transistor is reset; S120, setting the reset signal end cal_pen of the k-bit P counter to 1, at this time, the level selection switches s1, s2 and s3 are closed, the non-inverting input end Vi+ and the inverting input end Vi- of the operational amplifier main circuit are shorted to the PMOS correction common mode level Vcm_p, and the PMOS correction is enabled; S130, based on the level state of the output end Vout of the operational amplifier main circuit, the correction direction is obtained, if the output end Vout is high, the control signal end cal_dir of the decoding circuit is set to 0, negative compensation is needed, a compensation transistor is connected to the operational amplifier inverting input end PMOS transistor pm0' of the inverting input end Vi- of the operational amplifier main circuit, if the output end Vout is low, the control signal end cal_dir of the decoding circuit is set to 1, positive compensation is needed, and a compensation transistor is connected to the operational amplifier non-inverting input end PMOS transistor pm0 of the non-inverting input end Vi+ of the operational amplifier main circuit; S140, under the driving of the clock driving signal end cal_clk, the k-bit P counter starts to accumulate counting from 0; S150, based on the accumulation result of the k-bit P counter, control the number of offset correction tubes connected to the same direction input or reverse input of the PMOS differential pair tube, if the control signal end cal_dir of the decoding circuit is 0, the control signal cal_p+[k:1] of the PMOS offset correction tube of the same direction input is set to 0, and the control signal cal_p-[k:1] of the PMOS offset correction tube of the reverse input is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of PMOS differential pair reverse input offset correction tubes is increased in real time according to the counting result, and vice versa, if the control signal end cal_dir of the decoding circuit is 1, the control signal cal_p-[k:1] of the PMOS offset correction tube of the reverse input is set to 0, and the control signal cal_p+[k:1] of the PMOS offset correction tube of the same direction input is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of PMOS differential pair same direction input offset correction tubes is increased in real time according to the counting result; S160, judge whether the offset correction is completed based on the change of the output result of the operational amplifier main circuit, the correction flag generation circuit detects the level state of the output end Vout of the operational amplifier main circuit in real time, if it is detected that the output level of the operational amplifier main circuit is flipped, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit P counter stops counting, and the output result of the P decoding latch circuit is latched, so that the number of compensation transistors connected remains unchanged, if it is detected that the output level of the operational amplifier main circuit is not flipped, the latching control signal end cal_end remains 0, indicating that the correction is not completed, the k-bit P counter and the P decoding latch circuit continue to accumulate, and the number of offset correction tubes connected to the PMOS differential pair is increased.

9. The method of claim 7, wherein: The step S200 comprises: S210, the reset signal end cal_nen of the k-bit N counter is set to 0, so that the output of the k-bit N counter of the correction control circuit and the N decoding latch circuit is cleared, and the NMOS transistor correction is reset; S220, the reset signal end cal_nen of the k-bit N counter is set to 1, at this time, the level selection switches s1, s2 and s4 are closed, the non-inverting input end Vi+ and the reverse input end Vi- of the operational amplifier main circuit are short-circuited to the NMOS correction common mode level Vcm_n, so that the NMOS correction is enabled; S230, based on the level state of the output end Vout of the operational amplifier main circuit, the correction direction is obtained, if the output end Vout is high, the control signal end cal_dir of the decoding circuit is set to 0, negative compensation is needed, and compensation transistors are connected to the operational amplifier reverse input end NMOS transistor nm0' of the operational amplifier main circuit, if the output end Vout is low, the control signal end cal_dir of the decoding circuit is set to 1, positive compensation is needed, and compensation transistors are connected to the operational amplifier same direction input end NMOS transistor nm0 of the operational amplifier main circuit; S240, under the drive of the clock drive signal end cal_clk, the k-bit N counter starts to accumulate count from 0; S250, based on the accumulation result of the k-bit N counter, the number of the offset correction tubes connected to the same direction input end or the reverse input end of the NMOS differential pair tube is controlled, if the control signal end cal_dir of the decoding circuit is 0, the control signal cal_n+[k:1] of the NMOS offset correction tube of the same direction input end is set to 0, the control signal cal_n-[k:1] of the NMOS offset correction tube of the reverse input end is equal to the output cal_ni[k:1] of the k-bit N counter, that is, the number of the NMOS differential pair reverse input end offset correction tubes is increased in real time according to the counting result, on the contrary, if the control signal end cal_dir of the decoding circuit is 1, the control signal cal_n-[k:1] of the NMOS offset correction tube of the reverse input end is set to 0, the control signal cal_n+[k:1] of the NMOS offset correction tube of the same direction input end is equal to the output cal_pi[k:1] of the k-bit P counter, that is, the number of the NMOS differential pair same direction input end offset correction tubes is increased in real time according to the counting result; S260, based on the change of the output result of the operational amplifier main circuit, it is judged whether the offset correction is completed, the correction flag generation circuit detects the level state of the output end Vout of the operational amplifier main circuit in real time, if it is detected that the output level of the operational amplifier main circuit is flipped, the latching control signal end cal_end is set to 1, indicating that the correction is completed, the k-bit N counter stops counting, and the output result of the N decoding latching circuit is latched, so that the number of the compensation transistors connected remains unchanged, if it is detected that the output level of the operational amplifier main circuit is not flipped, the latching control signal end cal_end remains 0, indicating that the correction is not completed, the k-bit N counter and the N decoding latching circuit continue to accumulate, and the number of the offset correction tubes connected to the NMOS differential pair is increased.

Images