A high-gain DC amplifier circuit

Abstract

This invention discloses a high-gain DC amplifier circuit, belonging to the field of precision amplification in high-precision DC voltage measurement. It solves the problem that the higher the amplification factor of an amplifier circuit, the more difficult it is to guarantee accuracy. The invention includes an input stage, an intermediate stage, and an output stage circuit. The intermediate stage circuit includes a mirror current source and a bias current source. The input stage circuit is used to adjust the input voltage signal V according to a programmable proportional signal. i The primary stage amplification is performed; a bias current source provides quiescent current to the input stage circuit, and a mirror current source serves as the active load for the input stage circuit; the output stage circuit performs secondary amplification on the voltage signal after primary amplification. This invention is mainly used for voltage amplification.

Description

Technical Field

[0001] This invention belongs to the field of precision amplification in high-precision DC voltage measurement. Background Technology

[0002] As societal demands for measurement expand and accuracy increases, measurement is gradually becoming a crucial support for the development of high-tech industries. In recent years, the manufacturing industry has been booming at an astonishing pace. Simultaneously, this has placed higher demands on measurement. The rapid development of electronic technology and digital signal processing technology in recent years has laid the foundation for the rapid popularization of nanovolt-level voltage measurement technology, but it also faces interference and influences from various complex factors such as noise and input-output nonlinearity. The primary goal of nanovolt-level voltage measurement research is to improve measurement accuracy, but traditional voltage measurement methods are prone to errors due to system noise and other interference.

[0003] In a high-precision nanovoltmeter, the primary parameter measured is DC voltage. Other parameters, including DC current, AC current, AC voltage, and resistance, all undergo their respective signal conditioning circuits and are ultimately converted into DC voltage signals, which are then amplified by a high-precision signal amplification system. As the core module of the high-precision test instrument, the performance of the high-precision signal amplification system determines the overall performance of the instrument system.

[0004] The main factors limiting the development of signal amplification circuits in existing high-precision voltage measurement systems include suboptimal hardware circuit design, high noise levels, and reduced overall accuracy and stability. Furthermore, because the measurement system has a wide range, the corresponding amplification factor of the amplifier circuit is larger, leading to the problem that the higher the amplification factor, the more difficult it is to guarantee accuracy; and low open-loop gain results in insufficient feedback depth. Summary of the Invention

[0005] The purpose of this invention is to solve the problem that the higher the amplification factor of an amplifier circuit, the more difficult it is to guarantee accuracy, and to provide a high-gain DC amplifier circuit.

[0006] A high-gain DC amplifier circuit includes an input stage, an intermediate stage, and an output stage, wherein the intermediate stage includes a mirror current source and a bias current source.

[0007] The input stage circuit is used to adjust the input voltage signal V according to the programmable proportional signal. i Perform primary amplification;

[0008] The bias current source is used to provide quiescent current to the input stage circuit, while the mirror current source serves as the active load of the input stage circuit.

[0009] The output stage circuit is used to perform secondary amplification on the voltage signal after primary amplification.

[0010] Preferably, the input stage circuit includes JFETs T1 to T2, BJTs T3 to T6, resistors R1 to R2, capacitor C1, and Zener diode D1;

[0011] The gate of JFET T1 serves as the voltage input terminal of the input stage circuit, receiving the voltage signal V. i ;

[0012] After the source of JFET T1 is connected to the source of JFET T2 and the anode of Zener diode D1, it serves as the current input terminal of the input stage circuit to receive the quiescent current.

[0013] The drain of JFET T1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of BJT T3. The other end of capacitor C1 is connected to the other end of resistor R1, the base of BJT T3, and the emitter of BJT T5. The collector of BJT T3 is connected to the collector of BJT T5, serving as the output terminal on one side of the input stage circuit. The base of BJT T5 is connected to the base of BJT T6 and the cathode of Zener diode D1, serving as the control input terminal of the input stage circuit and connected to the control output terminal of the mirror current source.

[0014] After the collector of BJT T6 is connected to the collector of BJT T4, it serves as the output terminal on the other side of the input stage circuit.

[0015] The output terminals on both sides of the input stage circuit are connected to the reference current output terminal and the mirror current output terminal of the current mirror source, respectively, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively.

[0016] The emitter of BJT transistor T6 is connected to the base of BJT transistor T4 and one end of resistor R2. The other end of resistor R2 is connected to the emitter of BJT transistor T4 and the drain of JFET transistor T2.

[0017] The gate of JFET T2 serves as the programmable proportional input terminal of the input stage circuit.

[0018] Preferably, the mirrored current source includes BJT transistors T7 to T9, resistors R4 to R6, and power supply V. CC ;

[0019] Power supply V CC The power supply terminal is connected to one end of resistors R4 to R6 simultaneously, and the other end of resistor R4 is connected to the emitter of BJT transistor T7. The collector of BJT transistor T7 serves as the reference current output terminal of the mirror current source.

[0020] The base of BJT transistor T7 is connected to the other end of resistor R5, the emitter of BJT transistor T8, and the base of BJT transistor T9. The collector of BJT transistor T8 is connected to the control output terminal of the input stage circuit as a mirror current source.

[0021] After the base of BJT T8 is connected to the collector of BJT T9, it serves as the mirror current output terminal of the mirror current source.

[0022] The emitter of BJT transistor T9 is connected to the other end of resistor R6;

[0023] The reference current output terminal and the mirror current output terminal of the mirror current source are connected to the output terminals on both sides of the input stage circuit, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively.

[0024] Preferably, the bias current source includes operational amplifier A1, resistor R3, and BJT transistor T. 10 Power supply V EE1 and power supply V EE2 ;

[0025] BJT tube T 10 The collector serves as the output terminal of the static current of the bias current source;

[0026] BJT tube T 10 The emitter of the resistor is connected to one end of the resistor R3 and the inverting input of the operational amplifier A1, while the other end of the resistor R3 is connected to the power supply V. EE1 connect;

[0027] The non-inverting input of operational amplifier A1 is connected to power supply V. EE2 connect.

[0028] Preferably, the output stage circuit includes operational amplifier A2 and capacitor C2;

[0029] The inverting input terminal of operational amplifier A2 is connected to one end of capacitor C2, serving as the inverting input terminal of the output stage circuit; the other end of capacitor C2 is connected to the output terminal of operational amplifier A2.

[0030] The non-inverting input of operational amplifier A2 is used as the non-inverting input of the output stage circuit;

[0031] The non-inverting and inverting input terminals of the output stage circuit are connected to the output terminals on both sides of the input stage circuit, and are also connected to the reference current output terminal and the mirror current output terminal of the mirror current source, respectively.

[0032] Preferably, the high-gain DC amplifier circuit further includes a programmable current compensation circuit, which is used to compensate for the voltage signal V received by the input stage circuit. i Perform current compensation.

[0033] Preferably, the programmable current compensation circuit includes a first D / A converter and an operational amplifier A4;

[0034] The analog signal output terminal of the first D / A converter is connected to the non-inverting input terminal of operational amplifier A4, the inverting input terminal of operational amplifier A4 is connected to the power supply ground, and the output terminal of operational amplifier A4 serves as the compensation current output terminal of the programmable current compensation circuit.

[0035] Preferably, the high-gain DC amplifier circuit further includes a programmable voltage compensation circuit, which is used to eliminate the offset voltage of the input stage circuit.

[0036] Preferably, the programmable voltage compensation circuit includes a second D / A converter, an operational amplifier A5, and a resistor R9;

[0037] The analog signal output terminal of the second D / A converter is connected to the inverting input terminal of operational amplifier A5, the non-inverting input terminal of operational amplifier A5 is connected to the power supply ground, the output terminal of operational amplifier A5 is connected to one end of resistor R9, and the other end of resistor R9 serves as the compensation voltage output terminal of the programmable voltage compensation circuit.

[0038] Preferably, the high-gain DC amplifier circuit further includes a programmable proportional circuit for generating a corresponding programmable proportional signal to control the voltage signal V. i Magnification;

[0039] The programmable proportional circuit includes a resistor R 71 To R 73 The resistor array R7 is composed of resistor R. 81 To R 83 The resistor array R8 is composed of analog switches SW1 to SW3, the first set of selector switches is composed of analog switches SW4 to SW6, and the follower A3.

[0040] resistor R 71 To resistor R 73 The first end of the series-connected resistor array R7 is used to receive the voltage signal output by the output stage circuit, and the last end of the resistor array R7 is connected to the power supply ground.

[0041] One end of analog switches SW1 to SW3 is connected to resistor R respectively 71 To resistor R 73 The first end of the analog switch SW1 to SW3 is connected to the other end of the analog switch SW1 to SW3, and the non-inverting input of the follower A3 is connected to the output of the follower A3.

[0042] resistor R 81 To R 83The first end of the series resistor array R8 formed after the series connection is connected to the output terminal of the follower A3, and the last end of the series resistor array R8 is connected to the power supply ground.

[0043] One end of analog switches SW4 to SW6 is connected to resistor R respectively 81 To resistor R 83 The first end is connected, and the other end of analog switches SW4 to SW6 is connected to serve as the programmable proportional signal output terminal of the programmable proportional circuit.

[0044] Advantages of this invention:

[0045] This invention includes an input stage, an intermediate stage, and an output stage circuit, wherein the intermediate stage circuit includes a mirror current source and a bias current source; the input stage circuit is used to adjust the input voltage signal V according to a programmable proportional signal. i The primary amplification is performed; the output stage circuit, as the second stage amplification, can further amplify the primary signal. At the same time, the bias current source is used to provide static current to the input stage circuit, giving the overall amplifier circuit a strong common-mode signal rejection capability and providing a stable current output to the branch. The mirror current source, as the active load of the input stage circuit, provides greater amplification capability to the overall amplifier circuit, thus ensuring both high amplification factor and accuracy.

[0046] This invention innovates the topology of the input, intermediate, and output stages, achieving an amplifier gain of up to 10,000 times using discrete components such as JFETs, BJTs, and resistors. The constructed input stage circuit is a common-source, common-base circuit, which effectively combines the high input impedance of a common-source amplifier with the excellent frequency characteristics of a common-base amplifier, aiming to increase input impedance and ensure low-noise performance. Furthermore, the open-loop gain of the amplifier circuit comprised of the input, intermediate, and output stages reaches tens of millions of times, effectively mitigating the problem of decreased accuracy with higher amplifier gain caused by insufficient open-loop gain. Attached Figure Description

[0047] Figure 1 This is a schematic diagram of the overall structure of a high-gain DC amplifier circuit according to the present invention;

[0048] Figure 2 The equivalent circuit diagram of a high-gain DC amplifier circuit formed by the input stage, intermediate stage, and output stage circuits. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0051] Detailed Implementation Method 1, see [link / reference] Figure 1 This embodiment describes a high-gain DC amplifier circuit, which includes an input stage, an intermediate stage, and an output stage circuit, wherein the intermediate stage circuit includes a mirror current source and a bias current source.

[0052] The input stage circuit is used to adjust the input voltage signal V according to the programmable proportional signal. i Perform primary amplification;

[0053] The bias current source is used to provide quiescent current to the input stage circuit, while the mirror current source serves as the active load of the input stage circuit.

[0054] The output stage circuit is used to perform secondary amplification on the voltage signal after primary amplification.

[0055] In this preferred embodiment, the input stage circuit is used to perform primary amplification of the input voltage signal, provide differential input, suppress common-mode interference, and provide a high input impedance; the bias current source is used to provide quiescent current to the input stage circuit to ensure that the input stage circuit has a suitable quiescent operating point, and the mirror current source serves as the active load of the input stage circuit; the output stage circuit is used to perform secondary amplification of the voltage signal after primary amplification and can isolate the active load.

[0056] See Figure 1 The input stage circuit includes JFETs T1 to T2, BJTs T3 to T6, resistors R1 to R2, capacitor C1, and Zener diode D1.

[0057] The gate of JFET T1 serves as the voltage input terminal of the input stage circuit, receiving the voltage signal V. i ;

[0058] After the source of JFET T1 is connected to the source of JFET T2 and the anode of Zener diode D1, it serves as the current input terminal of the input stage circuit to receive the quiescent current.

[0059] The drain of JFET T1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of BJT T3. The other end of capacitor C1 is connected to the other end of resistor R1, the base of BJT T3, and the emitter of BJT T5. The collector of BJT T3 is connected to the collector of BJT T5, serving as the output terminal on one side of the input stage circuit. The base of BJT T5 is connected to the base of BJT T6 and the cathode of Zener diode D1, serving as the control input terminal of the input stage circuit and connected to the control output terminal of the mirror current source.

[0060] After the collector of BJT T6 is connected to the collector of BJT T4, it serves as the output terminal on the other side of the input stage circuit.

[0061] The output terminals on both sides of the input stage circuit are connected to the reference current output terminal and the mirror current output terminal of the current mirror source, respectively, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively.

[0062] The emitter of BJT transistor T6 is connected to the base of BJT transistor T4 and one end of resistor R2. The other end of resistor R2 is connected to the emitter of BJT transistor T4 and the drain of JFET transistor T2.

[0063] The gate of JFET T2 serves as the programmable proportional input terminal of the input stage circuit.

[0064] In this preferred embodiment, the only input devices in the amplifier circuit are BJTs, JFETs, and MOSFETs. JFETs have good noise performance and high input impedance. Compared to BJTs and MOSFETs, JFETs are more suitable for weak signal detection and precision instruments. Therefore, a pair of JFETs is used to construct the input stage circuit. The input stage circuit receives the input signal, conditions and amplifies it accordingly, and then inputs the processed signal to the intermediate stage circuit for further amplification.

[0065] Furthermore, to achieve signal amplification without distortion in the intermediate stage circuit composed of BJTs, a bias circuit needs to be designed to ensure that the JFETs operate in the saturation region. In the amplifier circuit, the bias circuit mainly includes a DC bias structure that functions as a load and a bias current source. The DC bias structure uses a mirror current source circuit with the emitter output, effectively improving the amplification factor. The bias current source circuit is composed of a source-coupled differential amplifier circuit, whose main function is to provide bias current to the input stage circuit, ensuring a suitable quiescent operating point and providing a high common-mode rejection ratio (CMRR) to the input stage circuit. Therefore, a specific structure for the mirror current source and bias current source in the intermediate stage circuit is given, as follows:

[0066] See Figure 1The mirrored current source includes BJT transistors T7 to T9, resistors R4 to R6, and power supply V. CC ;

[0067] Power supply V CC The power supply terminal is connected to one end of resistors R4 to R6 simultaneously, and the other end of resistor R4 is connected to the emitter of BJT transistor T7. The collector of BJT transistor T7 serves as the reference current output terminal of the mirror current source.

[0068] The base of BJT transistor T7 is connected to the other end of resistor R5, the emitter of BJT transistor T8, and the base of BJT transistor T9. The collector of BJT transistor T8 is connected to the control output terminal of the input stage circuit as a mirror current source.

[0069] After the base of BJT T8 is connected to the collector of BJT T9, it serves as the mirror current output terminal of the mirror current source.

[0070] The emitter of BJT transistor T9 is connected to the other end of resistor R6;

[0071] The reference current output terminal and the mirror current output terminal of the mirror current source are connected to the output terminals on both sides of the input stage circuit, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively.

[0072] In this preferred embodiment, an improved mirror current source is used, and an emitter follower is added. The current amplification effect of BJT T8 is utilized to reduce the shunting of the reference current by the base currents of BJTs T7 and T9. In the actual circuit, the resistor R5 between the bases of BJTs T7 and T9 and ground is used to increase the operating current of T8, thereby improving the amplification factor of T8.

[0073] A mirrored current source increases the output resistance, thus increasing the voltage gain. However, to achieve the full advantage of the higher output resistance of an active load, an active load uses a common-source, common-base circuit, i.e., an input stage circuit consisting of JFETs T1 to T2, BJTs T3 to T6, resistors R1 to R2, capacitor C1, and Zener diode D1.

[0074] See Figure 1 The bias current source includes operational amplifier A1, resistor R3, and BJT transistor T. 10 Power supply V EE1 and power supply V EE2 ;

[0075] BJT tube T 10 The collector serves as the output terminal of the static current of the bias current source;

[0076] BJT tube T 10The emitter of the resistor is connected to one end of the resistor R3 and the inverting input of the operational amplifier A1, while the other end of the resistor R3 is connected to the power supply V. EE1 connect;

[0077] The non-inverting input of operational amplifier A1 is connected to the power supply.

[0078] Furthermore, the output stage circuit, also known as the second-stage amplifier circuit, converts the voltage signal into a current signal in the input stage. The intermediate stage amplifies the current signal a second time, increasing the circuit gain. The output stage circuit structure is primarily used to isolate the load, preventing a decrease in amplifier gain when a small resistive load is connected to the amplifier. For the output stage circuit design, integrated operational amplifiers can fully provide the parameters and performance required for both the intermediate and output stage circuits, and integrated op-amps are easier to implement than discrete components. Therefore, a specific structure of the output stage circuit is provided; see [link to documentation]. Figure 1 The output stage circuit includes operational amplifier A2 and capacitor C2;

[0079] The inverting input terminal of operational amplifier A2 is connected to one end of capacitor C2, serving as the inverting input terminal of the output stage circuit; the other end of capacitor C2 is connected to the output terminal of operational amplifier A2.

[0080] The non-inverting input of operational amplifier A2 is used as the non-inverting input of the output stage circuit;

[0081] The non-inverting and inverting input terminals of the output stage circuit are connected to the output terminals on both sides of the input stage circuit, and are also connected to the reference current output terminal and the mirror current output terminal of the mirror current source, respectively.

[0082] Furthermore, to address nonlinear issues such as offset voltage and current in amplifier circuits, corresponding compensation circuits need to be designed. The main function of the programmable current compensation circuit is to eliminate the amplifier's input bias current, while the main function of the programmable voltage compensation circuit is to provide programmable voltage offset adjustment, ensuring the input bias voltage is zero. Therefore, the following design is implemented:

[0083] The high-gain DC amplifier circuit further includes a programmable current compensation circuit, which is used to compensate for the voltage signal V received by the input stage circuit. i Perform current compensation; and provide a specific structure of a programmable current compensation circuit, see [link to details]. Figure 1 The programmable current compensation circuit includes a first D / A converter and an operational amplifier A4;

[0084] The analog signal output terminal of the first D / A converter is connected to the non-inverting input terminal of operational amplifier A4, the inverting input terminal of operational amplifier A4 is connected to the power supply ground, and the output terminal of operational amplifier A4 serves as the compensation current output terminal of the programmable current compensation circuit.

[0085] The high-gain DC amplifier circuit further includes a programmable voltage compensation circuit, which is used to eliminate the offset voltage of the input stage circuit. A specific structure of the programmable voltage compensation circuit is given; see [link to details]. Figure 1 The programmable voltage compensation circuit includes a second D / A converter, operational amplifier A5, and resistor R9;

[0086] The analog signal output terminal of the second D / A converter is connected to the inverting input terminal of operational amplifier A5, the non-inverting input terminal of operational amplifier A5 is connected to the power supply ground, the output terminal of operational amplifier A5 is connected to one end of resistor R9, and the other end of resistor R9 serves as the compensation voltage output terminal of the programmable voltage compensation circuit.

[0087] In this preferred embodiment, both the programmable current compensation circuit and the programmable voltage compensation circuit are controlled by the microcontroller through IIC output to the input terminal of the D / A converter, and then converted into analog output, thereby achieving the purpose of programmable control, so that the gain of the high-precision signal amplification system circuit remains consistent over a wide range.

[0088] See further Figure 1 The high-gain DC amplifier circuit further includes a programmable proportional circuit, which is used to generate a corresponding programmable proportional signal to control the voltage signal V. i Magnification;

[0089] Specifically, the programmable proportional circuit includes a resistor R 71 To R 73 The resistor array R7 is composed of resistor R. 81 To R 83 The resistor array R8 is composed of analog switches SW1 to SW3, the first set of selector switches is composed of analog switches SW4 to SW6, and the follower A3.

[0090] resistor R 71 To resistor R 73 The first end of the series-connected resistor array R7 is used to receive the voltage signal output by the output stage circuit, and the last end of the resistor array R7 is connected to the power supply ground.

[0091] One end of analog switches SW1 to SW3 is connected to resistor R respectively 71 To resistor R 73 The first end of the analog switch SW1 to SW3 is connected to the other end of the analog switch SW1 to SW3, and the non-inverting input of the follower A3 is connected to the output of the follower A3.

[0092] resistor R 81 To R 83The first end of the series resistor array R8 formed after the series connection is connected to the output terminal of the follower A3, and the last end of the series resistor array R8 is connected to the power supply ground.

[0093] One end of analog switches SW4 to SW6 is connected to resistor R respectively 81 To resistor R 83 The first end is connected, and the other end of analog switches SW4 to SW6 is connected to serve as the programmable proportional signal output terminal of the programmable proportional circuit.

[0094] In this preferred embodiment, the amplifier gain switching is determined by two precision resistor arrays and isolated by an operational amplifier. Each resistor array provides gains of 1, 10, and 100, and the resistor R... 71 To resistor R 73 The resistance values ​​are 180kΩ, 18kΩ, and 2kΩ respectively, and the resistance R is... 81 To R 83 The resistance values ​​are 4.5kΩ, 450Ω, and 50Ω respectively. The cascaded two attenuation networks (i.e., the network composed of resistor arrays and analog switches) will form a 10,000-fold amplification factor. These gains can be transmitted from the host computer to the slave computer via commands. After parsing, the slave computer controls the two sets of analog switches through IIC to select and switch them, finally forming a negative feedback input to the differential pair transistors of the input stage circuit.

[0095] Principle Analysis:

[0096] Figure 2 This is an equivalent circuit diagram of a high-gain DC amplifier circuit of the present invention, which is formed by input stage, intermediate stage and output stage circuits. The high-gain DC amplifier circuit is an improved differential amplifier circuit with active load.

[0097] The output resistance R of the high-gain DC amplifier circuit described in this invention o This is the parallel resistance of the output resistances of JFET T4 and JFET T9. Assuming that the Darlington transistors composed of T3 and T5, and T4 and T6, are common-base connected, then first derive the output resistance R of T4. o4 The expression is:

[0098] R o4 =r o [1+g m (R e ||r π )](1);

[0099] Among them, R e =r e =r o2 r o =V A / I(V A(where R is the Early voltage), and substituting it into formula (1), we get formula (2), R e r is the internal resistance of the signal source. e For the emitter resistance, r o2 Where I is the output resistance of JFET T2, I is the collector current, and g m For transconductance, r π This is the input resistance.

[0100] R o4 =r o4 +(g m4 r o4 )(r o2 ||r π4 (2);

[0101] In the above formula, r o4 g is the output resistance of T4. m4 For the transconductance of T4, r π4 This is the input resistance of T4;

[0102] If g m4 (r o2 ||r π4 If )>>1, then equation (2) simplifies to:

[0103] R o4 ≈(g m4 r o4 )(r o2 ||r π4 (3); Due to the limited β of the BJT, where β is the current amplification factor of the BJT, we have r π4 With r o2 Parallel appearance. (r) o2 ||r π4 ) is always less than r π4 Therefore, the maximum value is:

[0104] R o4 | max =g m4 r o4 r π4

[0105] =(g m4 r π4 )r o4 (4);

[0106] =β4r o4

[0107] β4 is the current amplification factor of BJT transistor T4;

[0108] Since T4 is designed with a Darlington connection, its output resistance is:

[0109] R o4 =β4 2 r o4 (5);

[0110] Since the base of T9 may not be zero, but the base voltage signal is small enough, it can also be calculated using formula (1), r π9 This is the input resistance of T9.

[0111] After calculation and simplification, the formula for the differential gain with active load (i.e., the gain of the high-gain DC amplifier circuit of this invention) is as follows:

[0112]

[0113] In equation (6), β9 is the current amplification factor of BJT transistor T9, and r o9 β4 is the output resistance of T9, β4 is the current amplification factor of BJT T4, and r o4 The output resistance of T4;

[0114] The T4 transistor uses the MMBT6429. Here, β4 = 800 (500-1250) and β9 = 100. Therefore, the amplification factor is:

[0115]

[0116] Substituting the values ​​of β4 and β9, A d =14000, which, when cascaded with the output stage op-amp A2 (gain 80000), can achieve an open-loop gain of tens of millions of times.

[0117] Verification experiment:

[0118] The technical effects of this invention are illustrated through the following verification experiments, as detailed below:

[0119] The nanovolt-level measurement system is implemented using a high-gain DC amplifier circuit as described in this invention. Different range tests were conducted on the nanovolt-level measurement system corresponding to the DC amplifier circuit of this invention at different amplification factors. The test results are shown in Table 1.

[0120] Table 1. Uncertainty Test of Amplifier Circuit at Different Amplification Factors in Nanovolt Measurement System

[0121]

[0122] Table 1 shows the uncertainty of the amplifier circuit at different amplification factors, with the effective values ​​for each range input. The ranges from 1 to 10000 correspond to the 1mV-10V range of the nanovolt measurement system. The table shows that when the nanovolt measurement system is in the 0mV-1mV range (i.e., with an amplification factor of 10000), the overall test uncertainty is less than 50ppm. Currently, most existing integrated operational amplifiers exhibit output distortion at high amplification factors; only a few precision amplifiers can guarantee output accuracy, but with uncertainties of several hundred ppm. However, this invention maintains a low uncertainty even at an amplification factor of 10000. This demonstrates that the invention achieves high amplification factor while maintaining amplification accuracy, proving its effectiveness.

[0123] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features described herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other described embodiments.

Claims

1. A high-gain DC amplifier circuit, comprising an input stage, an intermediate stage, and an output stage, wherein the intermediate stage circuit includes a mirror current source and a bias current source; The input stage circuit is used to perform primary amplification of the input voltage signal according to the programmable proportional signal; The bias current source is used to provide quiescent current to the input stage circuit, and the mirror current source serves as the active load of the input stage circuit; the output stage circuit is used to amplify the voltage signal after primary amplification. The input stage circuit includes JFETs T1 to T2, BJTs T3 to T6, resistors R1 to R2, capacitor C1, and Zener diode D1; The gate of JFET T1 serves as the voltage input terminal of the input stage circuit, receiving the voltage signal. After the source of JFET T1 is connected to the source of JFET T2 and the anode of Zener diode D1, it serves as the current input terminal of the input stage circuit to receive the quiescent current. The drain of JFET T1 is connected to one end of capacitor C1, one end of resistor R1, and the emitter of BJT T3. The other end of capacitor C1 is connected to the other end of resistor R1, the base of BJT T3, and the emitter of BJT T5. The collector of BJT T3 is connected to the collector of BJT T5, serving as the output terminal on one side of the input stage circuit. The base of BJT T5 is connected to the base of BJT T6 and the cathode of Zener diode D1, serving as the control input terminal of the input stage circuit and connected to the control output terminal of the mirror current source. After the collector of BJT T6 is connected to the collector of BJT T4, it serves as the output terminal on the other side of the input stage circuit. The output terminals on both sides of the input stage circuit are connected to the reference current output terminal and the mirror current output terminal of the current mirror source, respectively, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively. The emitter of BJT transistor T6 is connected to the base of BJT transistor T4 and one end of resistor R2. The other end of resistor R2 is connected to the emitter of BJT transistor T4 and the drain of JFET transistor T2. The gate of JFET T2 serves as the programmable proportional input terminal of the input stage circuit. The feature is that the mirror current source includes BJT transistors T7 to T9, resistors R4 to R6, and a power supply; The power supply terminal is connected to one end of resistors R4 to R6 simultaneously, and the other end of resistor R4 is connected to the emitter of BJT transistor T7. The collector of BJT transistor T7 serves as the reference current output terminal of the mirror current source. The base of BJT transistor T7 is connected to the other end of resistor R5, the emitter of BJT transistor T8, and the base of BJT transistor T9. The collector of BJT transistor T8 is connected to the control output terminal of the input stage circuit as a mirror current source. After the base of BJT T8 is connected to the collector of BJT T9, it serves as the mirror current output terminal of the mirror current source. The emitter of BJT transistor T9 is connected to the other end of resistor R6; The reference current output terminal and the mirror current output terminal of the mirror current source are connected to the output terminals on both sides of the input stage circuit, and are also connected to the non-inverting and inverting input terminals of the output stage circuit, respectively. The output stage circuit includes operational amplifier A2 and capacitor C2; The inverting input terminal of operational amplifier A2 is connected to one end of capacitor C2, serving as the inverting input terminal of the output stage circuit; the other end of capacitor C2 is connected to the output terminal of operational amplifier A2. The non-inverting input of operational amplifier A2 is used as the non-inverting input of the output stage circuit; The non-inverting and inverting input terminals of the output stage circuit are connected to the output terminals on both sides of the input stage circuit, and are also connected to the reference current output terminal and the mirror current output terminal of the mirror current source, respectively.

2. The high-gain DC amplifier circuit according to claim 1, characterized in that, The bias current source includes operational amplifier A1, resistor R3, BJT transistor T10, power supply, and power supply; The collector of BJT transistor T10 serves as the output terminal of the static current of the bias current source. The emitter of BJT transistor T10 is connected to one end of resistor R3 and the inverting input of operational amplifier A1, while the other end of resistor R3 is connected to the power supply. The non-inverting input of operational amplifier A1 is connected to the power supply.

3. The high-gain DC amplifier circuit according to claim 1, characterized in that, It also includes a programmable current compensation circuit, which is used to compensate the voltage signal received by the input stage circuit for current.

4. A high-gain DC amplifier circuit according to claim 3, characterized in that, The programmable current compensation circuit includes a first D / A converter and an operational amplifier A4; The analog signal output terminal of the first D / A converter is connected to the non-inverting input terminal of operational amplifier A4, the inverting input terminal of operational amplifier A4 is connected to the power supply ground, and the output terminal of operational amplifier A4 serves as the compensation current output terminal of the programmable current compensation circuit.

5. A high-gain DC amplifier circuit according to claim 1, characterized in that, It also includes a programmable voltage compensation circuit, which is used to eliminate the offset voltage of the input stage circuit.

6. A high-gain DC amplifier circuit according to claim 5, characterized in that, The programmable voltage compensation circuit includes a second D / A converter, operational amplifier A5, and resistor R9; The analog signal output terminal of the second D / A converter is connected to the inverting input terminal of operational amplifier A5, the non-inverting input terminal of operational amplifier A5 is connected to the power supply ground, the output terminal of operational amplifier A5 is connected to one end of resistor R9, and the other end of resistor R9 serves as the compensation voltage output terminal of the programmable voltage compensation circuit.

7. A high-gain DC amplifier circuit according to claim 1, characterized in that, It also includes a programmable proportional circuit, which is used to generate a corresponding programmable proportional signal to control the amplification factor of the voltage signal; The programmable proportional circuit includes a resistor array R7 consisting of resistors R71 to R73, a resistor array R8 consisting of resistors R81 to R83, a first set of selection switches consisting of analog switches SW1 to SW3, a second set of selection switches consisting of analog switches SW4 to SW6, and a follower A3. The first end of the resistor array R7 formed by the series connection of resistors R71 to R73 is used to receive the voltage signal output by the output stage circuit, and the last end of the resistor array R7 is connected to the power supply ground. One end of analog switches SW1 to SW3 is connected to the first end of resistors R71 to R73 respectively, and the other end of analog switches SW1 to SW3 is connected to the non-inverting input of follower A3. The inverting input of follower A3 is connected to the output of follower A3. The first end of the series resistor array R8 formed by connecting resistors R81 to R83 is connected to the output terminal of follower A3, and the last end of the series resistor array R8 is connected to the power supply ground. One end of analog switches SW4 to SW6 is connected to the first end of resistors R81 to R83 respectively. The other end of analog switches SW4 to SW6 is connected and serves as the output terminal of the programmable proportional signal of the programmable proportional circuit.

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