Clock control device, method, controller, and system-level chip

Abstract

The present invention discloses a clock control device, method, controller, and system-level chip. When receiving a low-power request signal sent by a digital logic device, the device delays the first preset clock to stop inputting a digital clock signal to the digital logic device based on the analog clock signal input by the analog clock generating device, and then delays the second preset clock to turn off the analog clock signal output by the analog clock generating device; when receiving a wake-up input signal input by an external wake-up source, the device delays the first preset clock to input a high-level digital clock gating signal to a digital clock gating unit in the clock control device, and then delays the third preset clock to control the analog clock generating device to output an analog clock signal. The digital clock gating unit inputs a digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal. The device can completely avoid glitches that occur when the clock signal is turned on and off.

Description

Technical Field

[0001] The present invention relates to the technical field of system-on-chip, and in particular to a clock control device, method and controller, and a system-on-chip. Background Art

[0002] In a system on chip (SoC), analog clock generators such as oscillators (OSC) and phase-locked loops (PLL) are usually integrated to generate clock signals to drive digital logic. Based on the need to reduce power consumption, SoCs are generally designed with low-power modes. When the system enters low-power mode, the analog clock generator must be allowed to be turned off to further reduce power consumption; when the system exits low-power mode, the analog clock generator must be allowed to be turned on again so that the system can resume operation in the previous state.

[0003] Since digital logic has high requirements for timing, especially when the operating frequency is high, if the clock signal has glitches, it will cause the digital logic to violate the timing and enter the metastable state, which will lead to the risk of system crash. The traditional method is to add a deglitch circuit to the analog design, but the deglitch circuit can only eliminate glitches of a certain width, and the consistency is poor due to process deviation, and it cannot completely purify the clock signal. In addition, when the process platform is migrated, redesign and verification must be carried out, which has high hidden costs. Summary of the invention

[0004] The present invention aims to solve one of the technical problems in the related art at least to a certain extent. To this end, one object of the present invention is to provide a clock control device that completely avoids glitches when an analog clock generating device is turned on and off, and is based on timing control, independent of the process, and has excellent consistency.

[0005] The second objective of the present invention is to provide a clock control method.

[0006] The third object of the present invention is to provide a controller.

[0007] A fourth objective of the present invention is to provide a system-on-chip.

[0008] To achieve the above-mentioned purpose, a first aspect of the present invention proposes a clock control device, wherein an analog clock input terminal of the clock control device is connected to a clock output terminal of an analog clock generating device, a digital clock output terminal of the clock control device is connected to a clock input terminal of a digital logic device, a low power request input terminal of the clock control device is connected to a low power request output terminal of the digital logic device, an analog circuit enable terminal of the clock control device is connected to an enable control terminal of the analog clock generating device, and a wake-up signal input terminal of the clock control device is connected to an output terminal of an external wake-up source, and is used for: upon receiving a low power request signal sent by the digital logic device, based on the The analog clock signal input by the analog clock generating device is delayed by a first preset clock to stop inputting the digital clock signal to the digital logic device, and then the analog clock signal output by the analog clock generating device is delayed by a second preset clock to turn off the analog clock signal; when receiving the wake-up input signal input by the external wake-up source, the digital clock gating unit in the clock control device is delayed by a first preset clock to input a high-level digital clock gating signal, and then the analog clock generating device is delayed by a third preset clock to output the analog clock signal, and the digital clock gating unit inputs the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0009] According to the clock control device of the embodiment of the present invention, when the clock is turned off, the timing control is introduced to turn off the digital clock output first, and then turn off the analog clock generating device, to ensure that the digital clock signal has no glitches. When the clock is turned on, the asynchronous control is introduced to ensure that when there is no clock, the analog clock generating device is turned on, and the digital clock signal is turned on before the analog clock generating device is turned on, to avoid glitches in the output digital clock signal.

[0010] In addition, the clock control device according to the above embodiment of the present invention may also have the following additional technical features:

[0011] According to one embodiment of the present invention, the clock control device includes: a low-power control circuit, wherein a first input end of the low-power control circuit is connected to a low-power request input end of the clock control device, and is used to generate a low-level clock enable signal when receiving the low-power request signal; a clock output control unit, wherein a first input end of the clock output control unit is connected to a first output end of the low-power control circuit, and a second input end of the clock output control unit is connected to an analog clock input end of the clock control device, and is used to delay the first preset clock to output a low-level digital clock gating signal and a low-level analog circuit enable signal when receiving the low-level clock enable signal and the analog clock signal; and a digital clock gating unit, wherein a first input end of the digital clock gating unit is connected to a first output end of the clock output control unit, and a second input end of the digital clock gating unit is connected to an analog clock input end of the clock control device. The second input end is connected to the analog clock input end of the clock control device, and the output end of the digital clock gating unit is connected to the digital clock output end of the clock control device, which is used to stop outputting the digital clock signal when receiving the low-level digital clock gating signal and the analog clock signal; an analog circuit enable control unit, the first input end of the analog circuit enable control unit is connected to the second output end of the clock output control unit, the second output end of the analog circuit enable control unit is connected to the analog clock input end of the clock control device, and the output end of the analog circuit enable control unit is connected to the analog circuit enable end of the clock control device, which is used to delay the second preset clock to output a low-level analog circuit enable signal when receiving the low-level analog circuit enable signal and the analog clock signal, so as to turn off the analog clock signal output by the analog clock generating device.

[0012] According to one embodiment of the present invention, the clock control device further includes: a wake-up control circuit, wherein a first input terminal of the wake-up control circuit is connected to a wake-up signal input terminal of the clock control device, and a first output terminal of the wake-up control circuit is connected to a second input terminal of the low-power control circuit, for outputting a wake-up signal upon receiving the wake-up input signal; the low-power control circuit, wherein a second input signal of the low-power control circuit is connected to an output terminal of the wake-up control circuit, for generating a high-level clock enable signal upon receiving the wake-up signal; the clock output control unit, for delaying the first preset clock to output a high-level digital clock gating signal and a low-level analog circuit enable signal upon receiving the high-level clock enable signal and the analog clock signal; an analog circuit enable delay unit, wherein the analog circuit enable delay unit The input end of the analog circuit enable delay unit is connected to the first output end of the clock output control unit, and is used to delay the fourth preset clock to output a high-level analog circuit start signal when receiving the high-level digital clock gating signal; the analog circuit enable control unit, the third input end of the analog circuit enable control unit is connected to the output end of the analog circuit enable delay unit, and is used to delay the second preset clock to output a high-level analog circuit enable signal when receiving the high-level analog circuit start signal, so as to control the analog clock generating device to output an analog clock signal, wherein the sum of the fourth preset clock and the second preset clock is equal to the third preset clock; the digital clock gating unit is used to output the digital clock signal when receiving the high-level digital clock gating signal and the analog clock signal.

[0013] According to one embodiment of the present invention, the clock output control unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a first OR logic gate, the data input terminal of the first D flip-flop and the input terminal of the first OR logic gate are both connected to the first input terminal of the clock output control unit, the clock input terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are all connected to the second input terminal of the clock output control unit, the positive output terminal of the first D flip-flop is connected to the data input terminal of the second D flip-flop, the positive output terminal of the second D flip-flop is connected to the data input terminal of the third D flip-flop, the positive output terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are connected to the input terminal of the first OR logic gate, the output terminal of the first OR logic gate is connected to the first output terminal of the clock output control unit, and the positive output terminal of the third D flip-flop is connected to the second output terminal of the clock output control unit.

[0014] According to one embodiment of the present invention, the analog circuit enable control unit includes a fourth D flip-flop, a fifth D flip-flop and a second OR logic gate, the data input terminal of the fourth D flip-flop is connected to the first input terminal of the analog circuit enable control unit, the clock input terminals of the fourth D flip-flop and the fifth D flip-flop are connected to the second input terminal of the analog circuit enable control unit, the positive output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop, the input terminal of the second OR logic gate is connected to the third input terminal of the analog circuit enable control unit, and the input terminal of the second OR logic gate is also connected to the positive output terminals of the fourth D flip-flop and the fifth D flip-flop, and the output terminal of the second OR logic gate is connected to the output terminal of the analog circuit enable control unit.

[0015] According to an embodiment of the present invention, the wake-up control circuit is used to output the wake-up signal when it is determined that the wake-up input signal input by the external wake-up source is a valid signal.

[0016] According to one embodiment of the present invention, the second output terminal of the low-power control circuit is connected to the second input terminal of the wake-up control circuit, and the first output terminal of the low-power control circuit outputs the low-level clock enable signal while the second output terminal outputs a low-power indication signal, wherein the wake-up control circuit is used to output the wake-up signal when receiving a valid wake-up input signal and having the input of the low-power indication signal.

[0017] To achieve the above-mentioned purpose, the second aspect of the embodiment of the present invention proposes a clock control method, which includes: when receiving a low-power request signal issued by a digital logic device, based on the analog clock signal input by the analog clock generating device, delaying the first preset clock to stop inputting the digital clock signal to the digital logic device, and then delaying the second preset clock to turn off the analog clock signal output by the analog clock generating device; when receiving a wake-up input signal input by an external wake-up source, delaying the first preset clock to generate a high-level digital clock gating signal, and then delaying the third preset clock to control the analog clock generating device to output the analog clock signal, and inputting the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0018] To achieve the above-mentioned purpose, the third aspect of the present invention proposes a controller, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the clock control method proposed in the second aspect of the present invention is implemented.

[0019] To achieve the above-mentioned purpose, the fourth aspect embodiment of the present invention proposes a system-level chip, comprising an analog clock generating device, a digital logic device and a clock control device as proposed in the first aspect embodiment of the present invention, wherein the analog clock input terminal of the clock control device is connected to the clock output terminal of the analog clock generating device, the digital clock output terminal of the clock control device is connected to the clock input terminal of the digital logic device, the low power request input terminal of the clock control device is connected to the low power request output terminal of the digital logic device, the analog circuit enable terminal of the clock control device is connected to the enable control terminal of the analog clock generating device, and the wake-up signal input terminal of the clock control device is connected to the output terminal of an external wake-up source.

[0020] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic diagram of a clock control device according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a clock control device according to a specific embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a clock control device according to another specific embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a timing closing sequence of an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of the timing sequence of the timing start of an embodiment of the present invention;

[0026] Figure 6 is a flow chart of a clock control method according to an embodiment of the present invention;

[0027] Figure 7 is a structural block diagram of a controller according to an embodiment of the present invention;

[0028] Figure 8 FIG. 1 is a schematic diagram of a system-on-chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0030] The clock control device, method, controller, and system-on-chip of the embodiments of the present invention are described in detail below with reference to the accompanying drawings and specific implementation modes.

[0031] Figure 1 FIG. 1 is a schematic diagram of a clock control device according to an embodiment of the present invention. Figure 1 As shown, the analog clock input terminal of the clock control device is connected to the clock output terminal of the analog clock generating device, the digital clock output terminal of the clock control device is connected to the clock input terminal of the digital logic device, the low power request input terminal of the clock control device is connected to the low power request output terminal of the digital logic device, the analog circuit enable terminal of the clock control device is connected to the enable control terminal of the analog clock generating device, and the wake-up signal input terminal of the clock control device is connected to the output terminal of the external wake-up source, for:

[0032] Upon receiving a low power request signal from the digital logic device, based on the analog clock signal input from the analog clock generating device, after delaying the first preset clock to stop inputting the digital clock signal to the digital logic device, delaying the second preset clock to turn off the analog clock signal output from the analog clock generating device;

[0033] When receiving the wake-up input signal input by the external wake-up source, the first preset clock is delayed to input a high-level digital clock gating signal to the digital clock gating unit in the clock control device, and then the third preset clock is delayed to control the analog clock generating device to output the analog clock signal. The digital clock gating unit inputs the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0034] Specifically, the system-level chip may include an analog clock generating device and a digital logic device, wherein the analog clock generating device is used to generate a clock signal required for the operation of the digital logic device, and the digital logic device is used to implement various functions defined by the system-level chip.

[0035] In order to solve the problem that the clock signal glitch elimination is incomplete and the consistency is poor due to the influence of the process when the analog clock generating device is turned on and off, the embodiment of the present invention sets a clock control device between the analog clock generating device and the digital logic device, and uses the clock control device to control the turning on and off of the analog clock signal and the digital clock signal when the analog clock generating device is turned on and off, so as to eliminate the glitch of the clock signal.

[0036] Specifically, when the system-level chip enters the low-power mode, the analog clock generating device needs to be allowed to be turned off to further reduce power consumption. Therefore, when the system-level chip enters the low-power mode, a low-power request signal can be sent to the clock control device through the digital logic device. When the clock control device receives the low-power request signal sent by the digital logic device, based on the analog clock signal input by the analog clock generating device, it delays the first preset clock to stop inputting the digital clock signal to the digital logic device. After stopping inputting the digital clock signal to the digital logic device, it delays the second preset clock to turn off the analog clock signal output by the analog clock generating device, so as to first turn off the digital clock signal input to the digital logic device, and then turn off the analog clock signal output by the analog clock generating device.

[0037] Specifically, when the system-level chip exits the low power consumption mode, an external wake-up source can be used to input a wake-up input signal to the clock control device to turn on the analog clock generation device, so that the analog clock generation device outputs an analog clock signal. Therefore, when the clock control device receives the wake-up input signal input by the external wake-up source, it delays the first preset clock to input a high-level digital clock gating signal to the digital clock gating unit in the clock control device, and after inputting a high-level digital clock gating signal to the digital clock gating unit, it delays the third preset clock to control the analog clock generation device to output the analog clock signal, so as to ensure that the digital clock gating unit is turned on before the analog clock generation device, and avoid glitches in the digital clock signal. After the analog clock generation device outputs the analog clock signal, the digital clock gating unit inputs the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0038] The embodiment of the present invention utilizes a clock control device, and when the clock is turned off, a timing control is introduced to first turn off the digital clock output, and then turn off the analog clock generating device, to ensure that the digital clock signal is completely free of glitches. When the clock is turned on, an asynchronous control is introduced to ensure that when there is no clock, the analog clock generating device is turned on, and the digital clock signal is turned on before the analog clock generating device is turned on, to avoid glitches in the output digital clock signal.

[0039] In one embodiment of the present invention, Figure 2 As shown, the clock control device includes:

[0040] A low power consumption control circuit, wherein a first input terminal of the low power consumption control circuit is connected to a low power consumption request input terminal of the clock control device, and is used to generate a low level clock enable signal when receiving a low power consumption request signal;

[0041] A clock output control unit, wherein a first input terminal of the clock output control unit is connected to a first output terminal of the low power consumption control circuit, and a second input terminal of the clock output control unit is connected to an analog clock input terminal of the clock control device, and is used for delaying a first preset clock to output a low-level digital clock gating signal and a low-level analog circuit enable signal when receiving a low-level clock enable signal and an analog clock signal;

[0042] A digital clock gating unit, wherein a first input end of the digital clock gating unit is connected to a first output end of the clock output control unit, a second input end of the digital clock gating unit is connected to an analog clock input end of a clock control device, and an output end of the digital clock gating unit is connected to a digital clock output end of the clock control device, and is used to stop outputting a digital clock signal when receiving a low-level digital clock gating signal and an analog clock signal;

[0043] An analog circuit enable control unit, wherein the first input terminal of the analog circuit enable control unit is connected to the second output terminal of the clock output control unit, the second output terminal of the analog circuit enable control unit is connected to the analog clock input terminal of the clock control device, and the output terminal of the analog circuit enable control unit is connected to the analog circuit enable terminal of the clock control device, and is used for delaying the second preset clock to output a low-level analog circuit enable signal when receiving a low-level analog circuit enable signal and an analog clock signal, so as to shut down the analog clock signal output by the analog clock generating device.

[0044] Specifically, when receiving the low power request signal, the low power control circuit generates a low level clock enable signal and outputs it through the first output terminal of the low power control circuit.

[0045] When receiving the low-level clock enable signal output by the low-power control circuit, the clock output control unit delays the first preset clock to generate a low-level digital clock gating signal and a low-level analog circuit enable signal based on the analog clock signal input by the analog clock generating device, and sends the low-level digital clock gating signal to the digital clock gating unit through its first output terminal, and sends the low-level analog circuit enable signal to the analog circuit enable control unit through its second output terminal.

[0046] When receiving a low-level digital clock gating signal, the digital clock gating unit stops outputting the digital clock signal based on the analog clock signal, so that the clock control device stops inputting the digital clock signal to the digital logic device. After receiving a low-level analog circuit enable signal, the analog circuit enable control unit delays the second preset clock and outputs a low-level analog circuit enable signal (analog circuit shutdown signal) based on the analog clock signal, so as to shut down the analog clock generating device and stop the analog clock generating device from outputting the analog clock signal.

[0047] The clock control device of the embodiment of the present invention ensures that the digital clock signal has no glitches at all by first shutting down the digital clock and then shutting down the analog clock.

[0048] In one embodiment of the present invention, Figure 2 As shown, the clock control device also includes:

[0049] A wake-up control circuit, wherein a first input terminal of the wake-up control circuit is connected to a wake-up signal input terminal of the clock control device, and a first output terminal of the wake-up control circuit is connected to a second input terminal of the low power consumption control circuit, and is used to output a wake-up signal when receiving a wake-up input signal;

[0050] A low power consumption control circuit, wherein a second input signal of the low power consumption control circuit is connected to an output terminal of the wake-up control circuit, and is used to generate a high-level clock enable signal when receiving a wake-up signal;

[0051] A clock output control unit, configured to delay a first preset clock to output a high-level digital clock gating signal and a low-level analog circuit enable signal when receiving a high-level clock enable signal and an analog clock signal;

[0052] an analog circuit enabling delay unit, wherein the input end of the analog circuit enabling delay unit is connected to the first output end of the clock output control unit, and is used for delaying the fourth preset clock to output a high-level analog circuit start signal when receiving a high-level digital clock gating signal;

[0053] an analog circuit enable control unit, wherein a third input terminal of the analog circuit enable control unit is connected to an output terminal of the analog circuit enable delay unit, and is used to delay the second preset clock to output a high-level analog circuit enable signal when receiving a high-level analog circuit start signal, so as to control the analog clock generating device to output an analog clock signal, wherein the sum of the fourth preset clock and the second preset clock is equal to the third preset clock;

[0054] The digital clock gating unit is used to output a digital clock signal when receiving a high-level digital clock gating signal and an analog clock signal.

[0055] Specifically, when the wake-up control circuit receives the wake-up input signal, the output terminal outputs the wake-up signal. When the low-power control circuit receives the wake-up signal, it generates a high-level clock enable signal and outputs it through the first output terminal of the low-power control circuit. When the clock output control unit receives the high-level clock enable signal, based on the analog clock signal input by the analog clock generating device, it delays the first preset clock to generate a high-level digital clock gating signal and a low-level analog circuit enable signal, and sends the high-level digital clock gating signal to the digital clock gating unit through its first output terminal, and sends the low-level analog circuit enable signal to the analog circuit enable control unit through its second output terminal.

[0056] When the clock output control unit receives a high-level digital clock gating signal, the clock output control unit is enabled. Since the analog circuit enable control unit receives a low-level analog circuit enable signal, the analog clock generating device cannot be controlled to output an analog clock signal at this time. An analog circuit enable delay unit is provided in an embodiment of the present invention. The analog circuit enable delay unit receives the digital clock gating signal output by the clock output control unit, and when the digital clock gating signal is high, delays the fourth preset clock to output a high-level analog circuit start signal, and sends the high-level analog circuit start signal to the analog circuit enable control unit. When the analog circuit enable control unit receives a high-level analog circuit start signal, it delays the second preset clock to output a high-level analog circuit enable signal to control the analog clock generating device to output an analog clock signal. After the analog clock generating device outputs the analog clock signal, the digital clock gating unit outputs a digital clock signal based on the received high-level digital clock gating signal and the analog clock signal.

[0057] It should be noted that the digital clock gating signal in the embodiment of the present invention is a switch signal, which is used to turn on or off the digital clock gating unit, a high level is turned on, and a low level is turned off. When the digital clock gating unit is turned on, whether there is a clock output depends on whether an analog clock signal is received; when the digital clock gating unit is turned off, no matter whether an analog clock signal is received, the gating unit will not have a clock output.

[0058] The clock control device of the embodiment of the present invention introduces asynchronous control to ensure that the analog clock generating device is turned on when there is no clock, and by adding a delay, it is ensured that the digital clock gating unit is turned on before the analog clock generating device, thereby avoiding glitches in the digital clock signal.

[0059] It should be noted that, in the embodiment of the present invention, there is no limitation on the time lengths corresponding to the first preset clock, the second preset clock, and the fourth preset clock, and they can be set according to actual needs.

[0060] In one embodiment of the present invention, Figure 3 As shown, the clock output control unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a first OR logic gate, the data input terminal D of the first D flip-flop and the input terminal of the first OR logic gate are both connected to the first input terminal of the clock output control unit, the clock input terminals Clk of the first D flip-flop, the second D flip-flop and the third D flip-flop are all connected to the second input terminal of the clock output control unit, the positive output terminal Q of the first D flip-flop is connected to the data input terminal D of the second D flip-flop, the positive output terminal Q of the second D flip-flop is connected to the data input terminal D of the third D flip-flop, the positive output terminals Q of the first D flip-flop, the second D flip-flop and the third D flip-flop are connected to the input terminal of the first OR logic gate, the output terminal of the first OR logic gate is connected to the first output terminal of the clock output control unit, and the positive output terminal Q of the third D flip-flop is connected to the second output terminal of the clock output control unit.

[0061] Specifically, the clock output control unit receives the clock enable signal, and the analog clock output by the analog clock generating device is used as the driving clock of the D flip-flop (D Flip-Flop, DFF) inside the clock output control unit. The clock enable signal is passed through multiple levels of DFF. The output of each level of DFF and the clock enable signal itself are subjected to an OR logic operation to generate a digital clock gating signal. The output of the last level of DFF is used as the analog circuit enable signal.

[0062] In one embodiment of the present invention, Figure 3 As shown, the analog circuit enable control unit includes a fourth D flip-flop, a fifth D flip-flop and a second OR logic gate, the data input terminal D of the fourth D flip-flop is connected to the first input terminal of the analog circuit enable control unit, the clock input terminals Clk of the fourth D flip-flop and the fifth D flip-flop are connected to the second input terminal of the analog circuit enable control unit, the positive output terminal Q of the fourth D flip-flop is connected to the data input terminal D of the fifth D flip-flop, the input terminal of the second OR logic gate is connected to the third input terminal of the analog circuit enable control unit, and the input terminal of the second OR logic gate is also connected to the positive output terminals Q of the fourth D flip-flop and the fifth D flip-flop, and the output terminal of the second OR logic gate is connected to the output terminal of the analog circuit enable control unit.

[0063] Specifically, the analog circuit enable control unit receives the analog circuit shutdown signal (low-level analog circuit enable signal) and the analog circuit delay start signal, and the analog clock is used as the driving clock of the internal DFF. The analog circuit shutdown signal passes through two levels of DFF and is beat by the falling edge of the analog clock. The output of each level of DFF and the analog circuit delay start signal are ORed to generate the analog circuit enable output signal.

[0064] It should be noted that Figure 3 In Represents the inverting output terminal of the D flip-flop.

[0065] In one embodiment of the present invention, Figure 3 As shown, the enable input terminal EN of the digital clock gating unit is connected to the first output terminal of the clock output control unit, the clock input terminal Clk of the digital clock gating unit is connected to the analog clock input terminal of the clock control device, and the clock output terminal GCK of the digital clock gating unit is connected to the output terminal of the digital clock gating unit.

[0066] Specifically, the digital clock gating unit receives a digital clock gating signal and an analog clock input. If the digital clock gating signal is 0 (low level), the digital clock output is turned off. If the digital clock gating signal is 1 (high level), the analog clock is output to the digital clock.

[0067] In one embodiment of the present invention, Figure 3 As shown, the wake-up control circuit is used to output a wake-up signal when it is determined that the wake-up input signal input by the external wake-up source is a valid signal.

[0068] Specifically, when the wake-up control circuit receives a wake-up input signal input from an external wake-up source, it determines whether the wake-up input signal is a valid wake-up input signal. If it is a valid wake-up input signal, it outputs a wake-up signal and a low power consumption indication signal.

[0069] In one embodiment of the present invention, Figure 3 As shown, the second output end of the low-power control circuit is connected to the second input end of the wake-up control circuit, and the first output end of the low-power control circuit outputs a low-level clock enable signal while the second output end outputs a low-power indication signal, wherein the wake-up control circuit is used to output a wake-up signal when a valid wake-up input signal is received and there is an input of a low-power indication signal.

[0070] Specifically, when the low power control circuit receives the low power request signal, it outputs a low level clock enable signal and a high level low power indication signal at the same time, to indicate that the system-level chip enters the low power mode.

[0071] To prevent the wake-up input signal from affecting the analog clock signal output by the analog clock generating device when the system-level chip is not in low power consumption mode, the wake-up control circuit generates a wake-up signal only when it receives a valid wake-up input signal from an external wake-up source and a low power consumption indication signal is input at the same time.

[0072] When the clock control device according to the embodiment of the present invention is used to turn off the digital clock signal and the analog clock, the clock turn-off timing diagram is as follows: Figure 4As shown. Specifically, a low-power request signal is received, and after the low-power request signal is processed by the low-power control circuit, the clock enable signal becomes low level in the T1 cycle, and after the low-level clock enable signal passes through the multiple DFFs in the clock output control unit and beats at the rising edges of T2, T3 and T4, the digital clock gating signal and the analog circuit enable signal become low level in the T4 cycle, and the digital clock gating unit turns off the digital clock output in the T5 cycle. After the analog circuit enable signal passes through the falling edges of the T5 and T7 cycles, the analog circuit enable output signal becomes low level in the T7 cycle, and the analog clock generating device is turned off at T7, and no longer outputs the clock signal. It should be noted that the T5, T6 and T7 cycles are all half cycles of the analog clock. Since the analog clock is in a low level state in the T7 cycle, and the analog clock generating device outputs a low level when it is turned off, turning off the analog clock generating device at this time can avoid glitches in the analog clock.

[0073] When the clock control device according to the embodiment of the present invention is used to start the digital clock signal and the analog clock, the clock start timing diagram is as follows: Figure 5 As shown. Specifically, when the system-level chip is in low power mode, if the external wake-up source has a valid wake-up input signal input at time t1, after being processed by the wake-up control circuit, a wake-up signal is sent to the low power control circuit, and the clock enable signal becomes high at time t2. After the clock enable signal passes through the OR logic (the second OR logic gate), the digital clock gating signal also becomes high at time t2 (ignoring the OR logic delay), and the digital clock gating unit is turned on at time t2. However, since the analog clock generating device has not been turned on at this time, the analog clock signal is in a low level state, and the digital clock output also continues to maintain a low level state. After the digital clock gating signal is delayed by the analog circuit enable delay unit, the analog circuit delay start signal becomes high at time t3. After the analog circuit delay start signal passes through the OR logic, the analog circuit enable output also becomes high at time t3 (ignoring the OR logic delay), and the analog clock generating device starts to output the analog clock input signal. Since the digital clock gating unit has been turned on in advance, the analog clock can pass through the gating unit to directly drive the digital clock output.

[0074] The clock control devices in the embodiments of the present invention are all designed with pure digital logic, and have relatively small hardware overhead, and are easy to implement in circuit design.

[0075] The clock control device in the embodiment of the present invention can completely avoid glitches when the analog clock generating device is turned on and off.

[0076] The clock control device in the embodiment of the present invention is based on timing control when turning on and off the analog clock output by the analog clock generating device, is independent of the process, and has excellent consistency. Moreover, by decoupling from the process, it avoids re-development when the process platform is migrated, and has high economic efficiency.

[0077] The invention provides a clock control method.

[0078] Figure 6 FIG. 1 is a flow chart of a clock control method according to an embodiment of the present invention. Figure 6 As shown, the clock control method may include:

[0079] S101, upon receiving a low power consumption request signal sent by a digital logic device, based on an analog clock signal input by an analog clock generating device, delaying a first preset clock to stop inputting a digital clock signal to the digital logic device, and then delaying a second preset clock to turn off an analog clock signal output by the analog clock generating device;

[0080] S102, when receiving the wake-up input signal input by the external wake-up source, delay the first preset clock to generate a high-level digital clock gating signal, delay the third preset clock to control the analog clock generating device to output the analog clock signal, and input the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0081] Specifically, when the system-level chip enters the low-power mode, the analog clock generation device needs to be allowed to be turned off to further reduce power consumption. Therefore, when the system-level chip enters the low-power mode, a low-power request signal can be sent to the clock control device through the digital logic device. When the clock control device receives the low-power request signal sent by the digital logic device, based on the analog clock signal input by the analog clock generation device, it delays the first preset clock to stop inputting the digital clock signal to the digital logic device. After stopping inputting the digital clock signal to the digital logic device, it delays the second preset clock to turn off the analog clock signal output by the analog clock generation device.

[0082] Specifically, when the system-level chip exits the low power consumption mode, an external wake-up source can be used to input a wake-up input signal to the clock control device to turn on the analog clock generation device. Therefore, when the clock control device receives the wake-up input signal input by the external wake-up source, it delays the first preset clock to input a high-level digital clock gating signal to the digital clock gating unit in the clock control device, and after inputting a high-level digital clock gating signal to the digital clock gating unit, it delays the third preset clock to control the analog clock generation device to output an analog clock signal, so as to ensure that the digital clock gating unit is turned on before the analog clock generation device, and avoid glitches in the digital clock signal. After the analog clock generation device outputs the analog clock signal, the digital clock gating unit inputs a digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

[0083] It should be noted that, for other specific implementations of the clock control method provided in the embodiment of the present invention, reference may be made to other specific implementations of the clock control device in the above embodiment of the present invention.

[0084] The embodiment of the present invention utilizes a clock control method. When the clock is turned off, timing control is introduced to first turn off the digital clock output and then turn off the analog clock generating device, thereby ensuring that the digital clock signal is completely free of glitches. When the clock is turned on, asynchronous control is introduced to ensure that when there is no clock, the analog clock generating device is turned on, and the digital clock signal is turned on before the analog clock generating device is turned on, thereby avoiding glitches in the output digital clock signal.

[0085] The invention provides a controller.

[0086] In this embodiment, the controller may include a memory and a processor. The memory stores a computer program. When the computer program is executed by the processor, the clock control method as described above is implemented.

[0087] Figure 7 4 is a structural block diagram of a controller according to an embodiment of the present invention.

[0088] like Figure 7 As shown, the controller 500 includes: a processor 501 and a memory 503. The processor 501 and the memory 503 are connected, such as through a bus 502. Optionally, the controller 500 may also include a transceiver 504. It should be noted that in actual applications, the transceiver 504 is not limited to one, and the structure of the controller 500 does not constitute a limitation on the embodiments of the present invention.

[0089] The processor 501 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of the present invention. The processor 501 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0090] The bus 502 may include a path to transmit information between the above components. The bus 502 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 502 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0091] The memory 503 is used to store a computer program corresponding to the asynchronous serial communication method of the above embodiment of the present invention, and the computer program is controlled and executed by the processor 501. The processor 501 is used to execute the computer program stored in the memory 503 to implement the contents shown in the above method embodiment.

[0092] Among them, the controller 500 includes but is not limited to: mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The controller 500 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present invention.

[0093] The controller of the embodiment of the present invention, based on the above clock control method, introduces timing control when the clock is turned off, first turns off the digital clock output, and then turns off the analog clock generating device, to ensure that the digital clock signal has no glitches. When the clock is turned on, asynchronous control is introduced to ensure that when there is no clock, the analog clock generating device is turned on, and the digital clock signal is turned on before the analog clock generating device is turned on, to avoid glitches in the output digital clock signal.

[0094] The invention provides a system-level chip.

[0095] Figure 8 FIG. 1 is a schematic diagram of a system-on-chip according to an embodiment of the present invention. Figure 8 As shown, the system-level chip 1000 includes an analog clock generating device 100, a digital logic device 200 and a clock control device 300 as described above, wherein the analog clock input terminal of the clock control device 300 is connected to the clock output terminal of the analog clock generating device 100, the digital clock output terminal of the clock control device 300 is connected to the clock input terminal of the digital logic device 200, the low power request input terminal of the clock control device 300 is connected to the low power request output terminal of the digital logic device 200, the analog circuit enable terminal of the clock control device 300 is connected to the enable control terminal of the analog clock generating device 100, and the wake-up signal input terminal of the clock control device 300 is connected to the output terminal of the external wake-up source.

[0096] Specifically, the system-level chip may include: an analog clock generating device 100, a digital logic device 200, and a clock control device 300. The analog clock generating device 100 is used to generate the clock signal required for the operation of the digital logic device 200, and the digital logic device 200 is used to implement various functions defined by the system-level chip. The clock control device 300 is used to realize the closing and opening of the analog clock circuit and the digital clock signal.

[0097] The system-level chip of the embodiment of the present invention can completely avoid glitches when the analog clock generating device 100 is turned on and off. When the analog clock output by the analog clock generating device 100 is turned on and off, it is based on timing control and does not depend on the process, and has excellent consistency. And by decoupling from the process, it avoids re-development when the process platform is migrated, and the economy is high.

[0098] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0099] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0100] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0101] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0102] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0103] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0104] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0105] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A clock control device, characterized in that: The analog clock input terminal of the clock control device is connected to the clock output terminal of the analog clock generating device, the digital clock output terminal of the clock control device is connected to the clock input terminal of the digital logic device, the low power request input terminal of the clock control device is connected to the low power request output terminal of the digital logic device, the analog circuit enable terminal of the clock control device is connected to the enable control terminal of the analog clock generating device, and the wake-up signal input terminal of the clock control device is connected to the output terminal of the external wake-up source, for: Upon receiving the low power request signal sent by the digital logic device, based on the analog clock signal input by the analog clock generating device, after delaying the first preset clock to stop inputting the digital clock signal to the digital logic device, delaying the second preset clock to turn off the analog clock signal output by the analog clock generating device; When receiving the wake-up input signal input by the external wake-up source, after delaying the first preset clock to input a high-level digital clock gating signal to the digital clock gating unit in the clock control device, delaying the third preset clock to control the analog clock generating device to output the analog clock signal, the digital clock gating unit inputs the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal; wherein the clock control device comprises: A low power consumption control circuit, wherein a first input terminal of the low power consumption control circuit is connected to a low power consumption request input terminal of the clock control device, and is used to generate a low level clock enable signal when receiving the low power consumption request signal; A clock output control unit, wherein a first input terminal of the clock output control unit is connected to a first output terminal of the low power consumption control circuit, and a second input terminal of the clock output control unit is connected to an analog clock input terminal of the clock control device, and is used for delaying the first preset clock to output a low-level digital clock gating signal and a low-level analog circuit enable signal when receiving the low-level clock enable signal and the analog clock signal; The digital clock gating unit, wherein the first input end of the digital clock gating unit is connected to the first output end of the clock output control unit, the second input end of the digital clock gating unit is connected to the analog clock input end of the clock control device, and the output end of the digital clock gating unit is connected to the digital clock output end of the clock control device, and is used to stop outputting the digital clock signal when receiving the low-level digital clock gating signal and the analog clock signal; An analog circuit enable control unit, wherein the first input terminal of the analog circuit enable control unit is connected to the second output terminal of the clock output control unit, the second input terminal of the analog circuit enable control unit is connected to the analog clock input terminal of the clock control device, and the output terminal of the analog circuit enable control unit is connected to the analog circuit enable terminal of the clock control device, and is used for delaying the second preset clock to output a low-level analog circuit enable signal when receiving the low-level analog circuit enable signal and the analog clock signal, so as to shut down the analog clock signal output by the analog clock generating device.

2. The clock control device according to claim 1, characterized in that: The clock control device also includes: A wake-up control circuit, wherein a first input terminal of the wake-up control circuit is connected to a wake-up signal input terminal of the clock control device, and a first output terminal of the wake-up control circuit is connected to a second input terminal of the low power consumption control circuit, and is configured to output a wake-up signal upon receiving the wake-up input signal; The low power consumption control circuit, wherein the second input signal of the low power consumption control circuit is connected to the output end of the wake-up control circuit, is used to generate a high-level clock enable signal when receiving the wake-up signal; The clock output control unit is used to delay the first preset clock to output a high-level digital clock gating signal and a low-level analog circuit enable signal when receiving the high-level clock enable signal and the analog clock signal; an analog circuit enabling delay unit, wherein the input end of the analog circuit enabling delay unit is connected to the first output end of the clock output control unit, and is used for delaying the fourth preset clock to output a high-level analog circuit start signal when receiving the high-level digital clock gating signal; The analog circuit enable control unit, the third input terminal of the analog circuit enable control unit is connected to the output terminal of the analog circuit enable delay unit, and is used to delay the second preset clock to output a high-level analog circuit enable signal when receiving the high-level analog circuit start signal, so as to control the analog clock generating device to output an analog clock signal, wherein the sum of the fourth preset clock and the second preset clock is equal to the third preset clock; The digital clock gating unit is used to output the digital clock signal when receiving the high-level digital clock gating signal and the analog clock signal.

3. The clock control device according to claim 1, characterized in that: The clock output control unit includes a first D flip-flop, a second D flip-flop, a third D flip-flop and a first OR logic gate, wherein a data input terminal of the first D flip-flop and an input terminal of the first OR logic gate are both connected to a first input terminal of the clock output control unit, clock input terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are all connected to a second input terminal of the clock output control unit, a positive output terminal of the first D flip-flop is connected to a data input terminal of the second D flip-flop, a positive output terminal of the second D flip-flop is connected to a data input terminal of the third D flip-flop, positive output terminals of the first D flip-flop, the second D flip-flop and the third D flip-flop are connected to an input terminal of the first OR logic gate, an output terminal of the first OR logic gate is connected to a first output terminal of the clock output control unit, and a positive output terminal of the third D flip-flop is connected to a second output terminal of the clock output control unit.

4. The clock control device according to claim 2, characterized in that: The analog circuit enable control unit includes a fourth D flip-flop, a fifth D flip-flop and a second OR logic gate, the data input terminal of the fourth D flip-flop is connected to the first input terminal of the analog circuit enable control unit, the clock input terminals of the fourth D flip-flop and the fifth D flip-flop are connected to the second input terminal of the analog circuit enable control unit, the positive output terminal of the fourth D flip-flop is connected to the data input terminal of the fifth D flip-flop, the input terminal of the second OR logic gate is connected to the third input terminal of the analog circuit enable control unit, and the input terminal of the second OR logic gate is also connected to the positive output terminals of the fourth D flip-flop and the fifth D flip-flop, and the output terminal of the second OR logic gate is connected to the output terminal of the analog circuit enable control unit.

5. The clock control device according to claim 2, characterized in that: The wake-up control circuit is used to output the wake-up signal when it is determined that the wake-up input signal input by the external wake-up source is a valid signal.

6. The clock control device according to claim 2 or 5, characterized in that: The second output end of the low-power control circuit is connected to the second input end of the wake-up control circuit, and the first output end of the low-power control circuit outputs the low-level clock enable signal while the second output end outputs a low-power indication signal, wherein the wake-up control circuit is used to output the wake-up signal when receiving a valid wake-up input signal and having the input of the low-power indication signal.

7. A clock control method, characterized in that: The method comprises: Upon receiving a low power request signal sent by a digital logic device, based on an analog clock signal input by an analog clock generating device, after delaying a first preset clock to stop inputting a digital clock signal to the digital logic device, delaying a second preset clock to turn off the analog clock signal output by the analog clock generating device, wherein, based on the analog clock signal input by the analog clock generating device, after delaying a first preset clock to stop inputting a digital clock signal to the digital logic device, delaying a second preset clock to turn off the analog clock signal output by the analog clock generating device, comprises: upon receiving the low power request signal, generating a low-level clock enable signal; upon receiving the low-level clock enable signal and the analog clock signal, delaying the first preset clock to output a low-level digital clock gating signal and a low-level analog circuit enable signal; upon receiving the low-level digital clock gating signal and the analog clock signal, stopping outputting the digital clock signal; upon receiving the low-level analog circuit enable signal and the analog clock signal, delaying the second preset clock to output a low-level analog circuit enable signal to turn off the analog clock signal output by the analog clock generating device; When receiving a wake-up input signal from an external wake-up source, after delaying the first preset clock to generate a high-level digital clock gating signal, delaying the third preset clock to control the analog clock generating device to output the analog clock signal, and inputting the digital clock signal to the digital logic device based on the high-level digital clock gating signal and the analog clock signal.

8. A controller, comprising a memory and a processor, wherein a computer program is stored in the memory, characterized in that: When the computer program is executed by the processor, the clock control method according to claim 7 is implemented.

9. A system-on-chip, characterized in that: It comprises an analog clock generating device, a digital logic device and a clock control device as described in any one of claims 1 to 6, wherein the analog clock input terminal of the clock control device is connected to the clock output terminal of the analog clock generating device, the digital clock output terminal of the clock control device is connected to the clock input terminal of the digital logic device, the low power request input terminal of the clock control device is connected to the low power request output terminal of the digital logic device, the analog circuit enable terminal of the clock control device is connected to the enable control terminal of the analog clock generating device, and the wake-up signal input terminal of the clock control device is connected to the output terminal of an external wake-up source.

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