Method for canceling sampling noise of two-stage analog-to-digital converter and analog-to-digital converter

Abstract

The present invention discloses a method for offsetting sampling noise of a two-stage analog-to-digital converter and an analog-to-digital converter. The two-stage analog-to-digital converter includes: a multi-bit SAR ADC as the first stage, an incremental type Noise Shaping SAR ADC that supports multiple conversions and has a configurable multi-bit order as the second stage, and a configurable floating voltage domain amplifier as an interstage amplifier; wherein the interstage amplifier is placed between the first stage and the second stage, the input end of the interstage amplifier is connected to the top plate of the CDAC in the first stage, and the output end of the interstage amplifier is connected to the top plate of the CDAC in the second stage. By designing a method for offsetting sampling noise, a method for enhancing the linearity of interstage amplification based on two-step conversion, and a method for digitally calibrating the gain of the interstage amplifier based on dithering, the conversion speed and accuracy of the analog-to-digital converter are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to analog-to-digital converter integrated circuit design technology, and specifically relates to a method for offsetting sampling noise for a two-stage analog-to-digital converter, a two-stage analog-to-digital converter structure capable of efficiently offsetting sampling noise, and an implementation method thereof. Background Art

[0002] Many data acquisition systems for edge applications require high precision, low latency, and high energy efficiency for analog-to-digital converters (ADCs). Sigma-Delta ADCs are often used to achieve high-precision analog-to-digital conversion through noise shaping and oversampling techniques. Incremental Sigma-Delta ADCs that use incremental operation can effectively reduce the design complexity and data latency of the back-end digital filter, making it easier to integrate the system. However, the traditional Incremental Sigma-Delta ADC is limited by the low quantization bit number of the quantizer, requiring more conversion cycles to achieve the expected accuracy, which in turn limits its conversion speed. The noise shaping successive approximation analog-to-digital converter (Noise Shaping SAR ADC) can significantly reduce the number of conversion cycles required to achieve the expected accuracy and improve the conversion speed by utilizing the multi-bit quantization characteristics of the SAR ADC and combining it with a high-order loop filter design. However, high-precision, low-latency, high-order NoiseShaping SAR ADCs still face new challenges.

[0003] First, at low conversion cycles, the accuracy of the system is usually limited by the sampling noise because the noise introduced by the input signal sampling cannot be effectively averaged. To reduce the sampling noise, traditional design solutions usually rely on large sampling capacitors, which makes it difficult for the input and reference power supply of the ADC to provide sufficient driving capabilities. In addition, designing independent input and reference power supply drivers consumes a lot of energy, significantly increasing the power consumption of the data acquisition system. To solve this problem, sampling noise cancellation technology is used. This technology amplifies the sampling noise during the sampling stage and stores it in the noise cancellation capacitor, thereby achieving noise cancellation in the subsequent conversion stage and improving the sampling accuracy. However, traditional sampling noise cancellation technology not only requires the amplifier to work during the sampling stage, but also must continue to amplify during the conversion stage, so a static amplifier or a continuously triggered dynamic amplifier is required, which not only increases time consumption, but also significantly increases power consumption, thereby limiting the conversion speed and energy efficiency of the ADC.

[0004] In addition, designing a high-order loop filter will significantly increase the hardware overhead and design complexity of the Noise Shaping SAR ADC. To reduce this overhead, designers embed the Noise Shaping SAR ADC into a zoom structure as a fine quantizer, using the additional quantization accuracy provided by the coarse quantizer to reduce the number of loop filter orders required to achieve high accuracy. However, although coarse quantization can reduce the filter order, it will extend the conversion cycle, thereby reducing the conversion speed.

[0005] In summary, it is difficult to design a high-precision, low-latency, high-energy-efficiency and easy-to-drive ADC suitable for edge applications using existing technologies. Summary of the invention

[0006] In view of the problem that it is difficult to strike a balance between ADC energy efficiency and ease of driving in the above-mentioned existing analog-to-digital converter (ADC) design technology, the present invention provides a method for offsetting sampling noise for a two-stage analog-to-digital converter and a two-stage ADC that can efficiently offset sampling noise and an implementation method thereof, including a method for offsetting sampling noise, a method for enhancing inter-stage amplification linearity based on two-step conversion, and a method for digitally calibrating inter-stage amplifier gain based on dithering, so as to improve the conversion speed and accuracy of the ADC.

[0007] For convenience, the present invention defines the following terms and their corresponding English names:

[0008] Analog-to-digital converter (ADC);

[0009] Incremental analog-to-digital converter (IncrementalADC);

[0010] Successive approximation analog-to-digital converter (SARADC);

[0011] Noise Shaping SAR ADC;

[0012] Capacitive digital-to-analog converter (CDAC);

[0013] Infinite impulse response (IIR);

[0014] MSB (MostSignificantBit, most significant bit);

[0015] LSB (Least Significant Bit).

[0016] The present invention designs a sampling noise cancellation technology, that is, a method for canceling the sampling noise of an analog-to-digital converter ADC, which can be applied to a two-stage analog-to-digital converter, specifically: in the sampling stage of the two-stage analog-to-digital converter, the sampling noise of the first stage is amplified and stored on the noise cancellation capacitor of the second stage; in the inter-stage amplification stage, the sampling noise of the first stage and the residual voltage after quantization are amplified and stored on the capacitive digital-to-analog converter CDAC of the second stage. By connecting the second-stage CDAC and the noise cancellation capacitor in series, the first-stage sampling noise can be canceled in the critical second-stage conversion process, thereby allowing the use of a small sampling capacitor to achieve high sampling accuracy, making the ADC easy to drive, and significantly reducing the burden of the ADC on the peripheral driving circuit. Compared with other sampling noise cancellation technologies, the sampling noise cancellation technology designed by the present invention is different in that: first, within a sampling cycle, the amplifier only needs to work twice in the sampling stage and the inter-stage amplification stage, and the amplifier can be turned off in other stages, so a high-efficiency dynamic amplifier can be used, which greatly reduces the extra time and energy overhead introduced by the amplifier in the sampling noise cancellation technology, and improves the conversion speed and energy efficiency of the ADC. Second, by dividing the sampling noise cancellation capacitor of the second stage into two, one of which is used to collect the sampling noise of the first stage, and the other is used to cancel the sampling noise during the second stage conversion process, the sampling noise cancellation technology can support the parallel execution of the first stage conversion and the second stage conversion, thereby improving the conversion speed of the ADC and can be suitable for pipeline ADC design.

[0017] The first stage of the two-stage analog-to-digital converter ADC provided by the present invention is a multi-bit SAR ADC; the second stage is an incremental type Noise Shaping SAR ADC supporting multiple conversions and configurable multi-bit orders; and the inter-stage amplifier is a configurable floating voltage domain amplifier.

[0018] In order to further improve the conversion speed and energy efficiency of ADC, the present invention provides an incremental Noise Shaping SAR ADC that supports multiple conversions and has a configurable multi-bit order as the second stage of a two-stage analog-to-digital converter system, which includes a comparator, a CDAC, two sets of noise cancellation capacitors, a configurable order loop filter, and digital logic. The filter designed by the present invention is a first-order / second-order configurable loop filter structure, which is used in an incremental ADC. A complete data readout includes N conversions. In the first N1 conversions, it is configured as a low-order working mode to save power consumption; in the next N2 (N2=N-N1) conversions, it is configured as a high-order working mode to improve conversion accuracy. By designing the values ​​of N1 and N2, a compromise between the power consumption of the loop filter and the quantization accuracy can be achieved: the smaller the N1 value, the higher the system quantization accuracy and the greater the power consumption of the loop filter; the larger the N1 value, the lower the system quantization accuracy and the lower the power consumption of the loop filter. By using the additional quantization accuracy provided by the first-stage coarse quantization, the order required for the second-stage loop filter can be reduced. In this design, combined with incremental operation, the loop filter of the first several conversion cycles is configured as a lower-order working mode to reduce power consumption; the loop filter of the subsequent conversion cycles is configured as a higher-order working mode to improve quantization accuracy. By adjusting the number of conversion cycles in low-order and high-order working modes, lower power consumption can be achieved while meeting the quantization accuracy requirements. In addition, since the working process of the loop filter does not destroy the charge stored in the second-stage CDAC, the second stage (Noise Shaping SAR ADC) can perform multiple conversions continuously without repeated inter-stage amplification, thereby reducing additional amplification time and power consumption.

[0019] In order to ensure the accuracy of ADC, the present invention provides an inter-stage amplification linearity enhancement technology based on two-step conversion. After the first-stage conversion of the ADC is completed, the comparator after the amplifier is used to perform several additional conversions, thereby reducing the quantization error of the first stage and the influence of the comparator mismatch on the residual voltage size, so that the amplifier has a smaller input signal swing in the inter-stage amplification stage, and the linearity of the inter-stage amplification is improved. In this design, a configurable floating voltage domain amplifier is used as an inter-stage amplifier. In the second-step conversion process of the first stage, the amplifier acts as a pre-amplifier of the comparator, and its gain hardly affects the conversion accuracy. Therefore, it can be configured as a low-power working mode, thereby improving the linearity of the inter-stage amplification with a smaller power consumption overhead, ensuring the accuracy of the ADC.

[0020] In addition, the present invention also adopts a dither-based inter-stage amplifier gain digital calibration technology for accurately obtaining the gain value of the inter-stage amplifier under different environmental conditions, thereby ensuring the quantization accuracy of the ADC under various environments.

[0021] The technical solution of the present invention is:

[0022] A sampling noise cancellation method for a two-stage analog-to-digital converter and a two-stage analog-to-digital converter implementation method including the sampling noise cancellation technology. The two-stage analog-to-digital converter mainly includes: a multi-bit SAR ADC as the first stage, an incremental type Noise ShapingSAR ADC that supports multiple conversions and has a configurable multi-bit order as the second stage, and a configurable floating voltage domain amplifier as an interstage amplifier. The connection relationship is: the interstage amplifier is placed between the first stage and the second stage, the input end of the interstage amplifier is connected to the top plate of the CDAC in the first stage ADC, and the output end of the interstage amplifier is connected to the top plate of the CDAC in the second stage ADC.

[0023] The components in the two-stage analog-to-digital converter system proposed by the present invention are described in detail below:

[0024] A. Multi-bit SAR ADC

[0025] In specific implementation, the present invention designs and adopts an 8-bit SAR ADC. The multi-bit SAR ADC includes a sampling circuit, two comparators, a CDAC, a capacitor for generating jitter and a control logic. The input end of one of the comparators is connected to the top plate of the CDAC for the first step conversion of the first stage, and the input end of the other comparator is connected to the output end of the amplifier for the second step conversion of the first stage, so as to improve the linearity of inter-stage amplification. The conversion results of the two steps are used to control the switching of the bottom plate switch of the CDAC. The capacitor for generating jitter is connected in parallel with the CDAC, and a digital calibration method for the gain of the inter-stage amplifier based on jitter is adopted. After the first stage conversion is completed, the bottom plate switches to inject a jitter voltage into the top plate of the CDAC. After the jitter voltage is amplified by the inter-stage amplifier, it will be quantized by the second stage of the ADC. By performing autocorrelation operation on the jitter voltage and the quantization result of the second stage, the gain of the inter-stage amplifier can be extracted and calibrated in the digital domain, which is used to calibrate the inter-stage gain under different environments.

[0026] The working process of the first-stage ADC is as follows: in the sampling stage, it is divided into two steps. The first step is to connect the input signal to the bottom plate of CDAC, and the top plate is connected to the common mode level; the second step is to disconnect the switch of the top plate, trigger the interstage amplifier to work, amplify the sampling noise on CDAC and the change of the input signal during the second-step sampling process, and save it to the noise cancellation capacitor of the second stage. In the first-stage conversion stage, it is divided into two steps. The first step is to trigger the comparator connected to the top plate of CDAC to work, and switch the MSB part of CDAC according to the comparison result; the second step is to trigger the amplifier and the comparator connected to the output end of the amplifier to work, amplify and compare the voltage on the top plate of CDAC, and switch the LSB part of CDAC according to the comparison result. Through the second-step conversion, not only can the quantization error after the first-step conversion be further reduced, but also the influence of the mismatch between the comparator and the amplifier on the output swing of the amplifier in the interstage amplification stage can be reduced, and the output swing of the amplifier can be reduced to improve the linearity of the interstage amplification.

[0027] B. Configurable floating voltage domain amplifier

[0028] In specific implementation, the present invention improves the floating voltage domain amplifier, designs and adopts a floating voltage domain amplifier that is configurable in low power consumption / high power consumption mode. The amplifier comprises an amplifier tube, a power supply capacitor and the like. The amplifier works in three stages during the operation of the ADC, namely: the second step of the sampling stage, the second step of the first stage conversion stage and the inter-stage amplification stage. When the amplifier is working, the power supply end of the amplifier tube is connected to the power supply capacitor to perform the amplification function; in other stages, the amplifier does not work, the power supply end of the amplifier tube floats, and the power supply capacitor is reset.

[0029] In the second step of the first-stage conversion phase, since the conversion accuracy of this stage is not sensitive to the gain value of the amplifier, the amplifier can be configured to a low-power mode by reducing its power supply capacitor. The load capacitor is the parasitic capacitor at the input of the comparator, which reduces the energy consumption of the system. In the second step of the sampling phase and the inter-stage amplification phase, the amplifier is connected to all power supply capacitors to work. The load capacitors are the noise cancellation capacitors of the second stage and the CDAC of the second stage. By designing the power supply capacitors and load capacitors of these two stages to be consistent, the consistency of the amplifier gain of these two stages is guaranteed. At the same time, larger power supply capacitors and load capacitors can also reduce the thermal noise of the amplifiers in these two stages and improve the system accuracy.

[0030] C. Incremental type supports multiple conversions and configurable Noise Shaping SAR ADC with multiple bit levels

[0031] In specific implementation, the present invention designs and adopts an incremental 7-bit first-order / second-order configurable Noise Shaping SAR ADC. The incremental multi-bit order configurable Noise Shaping SAR ADC includes a comparator, a CDAC, two groups of noise cancellation capacitors, a loop filter with configurable order and digital logic. The connection relationship is: the noise cancellation capacitor is placed between the CDAC top plate and the loop filter, and the input end of the comparator is connected to the output end of the loop filter. In a conversion cycle, the switching of the second-stage CDAC bottom plate switch is first controlled according to the comparison result of the comparator. After all bits are compared and switched, the loop filter is triggered to work and the output of the loop filter is updated.

[0032] The loop filter in the incremental multi-bit order-configurable Noise Shaping SAR ADC of the present invention is an order-configurable IIR (Infinite Impulse Response) filter, and a first-order / second-order configurable IIR filter can be used. The first-order working mode is implemented as follows: by connecting the capacitor that stores the residual voltage after the second-level quantization is completed in series with the integration capacitor 1a that stores the integration result of the previous conversion cycle, signal addition is achieved, and the addition result is stored on the integration capacitor 1b using a dynamic buffer to obtain the integration result of the current conversion cycle. In the next conversion cycle, the integration capacitor 1b is used to replace the integration capacitor 1a, and the integral value of the current cycle is added to the residual voltage of the next cycle, and then the integration result of the new cycle is saved to the integration capacitor 1a through the dynamic buffer. By alternately using the integration capacitor 1a and the integration capacitor 1b in each conversion cycle, continuous first-order integration of the residual voltage can be achieved. The second-order working mode is implemented as follows: add integral capacitor 2a and integral capacitor 2b to be cascaded after integral capacitor 1a or integral capacitor 1b, and add a dynamic buffer to update the values ​​of integral capacitor 2a and integral capacitor 2b. The updating method is the same as above, and the double integration function can be realized. In the working process of the incremental NoiseShaping SAR ADC, if a complete data readout contains N conversion cycles, in the first N1 conversion cycles, the loop filter is configured to the first-order working mode, and only one dynamic buffer works to reduce the power consumption of the ADC loop filter; in the next N2 (N2=N-N1) conversion cycles, the loop filter is configured to the second-order working mode, and two dynamic buffers work simultaneously to improve the quantization accuracy of the ADC. By configuring the size of N1 and N2, the power consumption of the loop filter can be reduced while meeting the target quantization accuracy requirements, thereby improving the energy efficiency of the ADC system.

[0033] During the loop filter update process, the dynamic buffer has a high input impedance, which can avoid destroying the residual voltage value stored on the second-stage CDAC. Therefore, after the loop filter update is completed, the second-stage input signal can be rebuilt by simply resetting the second-stage CDAC for the next conversion cycle. This enables multiple consecutive conversions in the second-stage conversion stage without re-amplifying the interstage. In a specific implementation, after one interstage amplification, the second stage performs three consecutive conversions, which greatly reduces the time and power consumption of the interstage amplification and improves the conversion speed and energy efficiency of the ADC system.

[0034] To support the parallel operation of the first stage and the second stage, the present invention introduces two groups of noise cancellation capacitors in the second stage design, which are respectively called noise cancellation capacitor E and noise cancellation capacitor O. During the second stage conversion process, if the noise cancellation capacitor E is connected in series with the second stage CDAC and connected in series with the integral capacitor of the loop filter to complete the second stage conversion, the first stage sampling will amplify the sampling noise and store it in the noise cancellation capacitor O. In the next second stage conversion, the noise cancellation capacitor O is connected in series with the second stage CDAC for conversion, and the new sampling noise is stored in the noise cancellation capacitor E. By alternately using the noise cancellation capacitor E and the noise cancellation capacitor O in different sampling cycles, the sampling noise cancellation is achieved while allowing the first stage and the second stage to work in parallel, thereby improving the accuracy and conversion speed of the ADC system.

[0035] The above two-stage analog-to-digital converter implementation method of the present invention comprises the following steps:

[0036] 1) Design and prepare a configurable floating voltage domain amplifier, and improve the existing floating voltage domain amplifier. Structurally, the configurable floating voltage domain amplifier is used to extract sampling noise in the sampling stage and the inter-stage amplification stage, and is used to reduce the residual voltage of the first stage in the first stage quantization stage. By splitting the power supply capacitor of the floating voltage domain amplifier into a large capacitor and a small capacitor, and adding a control element to control the connection between the power supply capacitor and the amplifier tube, dynamically configurable power supply is achieved during the operation of the two-stage ADC. In the first stage of quantization, only the small power supply capacitor is used to power the amplifier tube to reduce power consumption; in other stages, all power supply capacitors are enabled to power the amplifier tube, thereby ensuring the accuracy of the analog-to-digital converter.

[0037] 2) Prepare a multi-bit SAR ADC, which includes five parts: a sampling circuit, a CDAC, a capacitor for generating jitter, two comparators, and digital logic. Structurally, the multi-bit SAR ADC is used for sampling and first-stage conversion. The sampling circuit is connected to the bottom plate of the CDAC, and the capacitor for generating jitter is connected to the top plate of the CDAC. After the first-stage conversion is completed, the bottom plate voltage of the capacitor for generating jitter is switched to inject the jitter voltage into the top plate of the CDAC, which is used to calibrate the inter-stage amplifier gain under different environments. The input of one of the comparators is connected to the top plate of the CDAC, and the input of the other comparator is connected to the output port of the above-mentioned floating voltage domain amplifier. In the first-stage conversion stage, the comparison results of the two comparators are used to control the switching of the CDAC bottom plate switch through digital logic.

[0038] 3) Prepare a multi-bit order configurable Noise Shaping SAR ADC, which includes five parts: CDAC, two groups of noise cancellation capacitors, a loop filter with configurable order, a comparator and digital logic. The multi-bit order configurable NoiseShaping SAR ADC is used for the second-stage conversion, and the sampling noise of the first stage is saved during the sampling stage, and the sampling noise is canceled during the second-stage conversion process. In terms of design, one end of the two groups of noise cancellation capacitors is connected to the top plate of the CDAC, and the other end is connected to the loop filter, and the other end of the loop filter is connected to the input of the comparator. During the second-stage conversion process, according to the comparison result of the comparator, the switching of the CDAC bottom plate switch is controlled by digital logic to complete the analog-to-digital conversion. The sampling noise cancellation technology adopts the sampling noise cancellation technology implementation method proposed in the present invention, and the loop filter adopts the order configurable IIR loop filter implementation method designed by the present invention.

[0039] 4) Use a multi-bit SAR ADC as the first-stage ADC and a multi-bit configurable Noise Shaping SAR ADC as the second-stage ADC. The first-stage ADC and the second-stage ADC are connected via a configurable floating voltage domain amplifier. The input of the amplifier is connected to the CDAC top plate of the first-stage SAR ADC, and the output is connected to the CDAC top plate of the second-stage Noise Shaping SAR ADC. In terms of working mode, the first-stage ADC and the second-stage ADC are configured in a pipelined manner. The residual voltage after the first-stage quantization is transferred to the second-stage ADC through an inter-stage amplifier, and the second-stage ADC is configured to achieve continuous multiple conversions after an inter-stage amplification, and the second-stage ADC loop filter is reset every several conversion cycles, so that the two-stage analog-to-digital converter designed by the present invention can be obtained.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention provides a two-stage analog-to-digital converter design, which includes a more efficient sampling noise cancellation technology, by amplifying the sampling noise of the first stage on the noise cancellation capacitor of the second stage during the sampling stage, and amplifying the sampling noise again on the CDAC of the second stage during the inter-stage amplification stage, and connecting the CDAC and the noise cancellation capacitor in series, the sampling noise can be cancelled in the critical second-stage conversion process. The ADC designed using the sampling noise cancellation technology can achieve high sampling accuracy using a small sampling capacitor value, greatly reducing the burden of the ADC on the peripheral driving circuit.

[0042] Compared with other sampling noise cancellation technologies, the sampling noise cancellation technology provided by the present invention has the following advantages: 1. In one sampling cycle, the amplifier only needs to work twice, in the sampling stage and the inter-stage amplification stage, and the amplifier can be turned off in other stages, so a high-efficiency dynamic amplifier can be used, which greatly reduces the extra time and energy overhead introduced by the amplifier in the sampling noise cancellation technology, and improves the conversion speed and energy efficiency of the ADC. 2. By introducing a set of additional noise cancellation capacitors, the sampling noise cancellation technology supports the parallel execution of the first-stage conversion and the second-stage conversion, thereby improving the conversion speed of the ADC, and is suitable for the design of pipelined ADCs.

[0043] The present invention provides an incremental type Noise Shaping SAR ADC with configurable multi-bit order that supports multiple conversions as the second stage. Through incremental operation, the digital filter at the output end of the Noise Shaping SAR ADC has lower hardware overhead and output delay, which facilitates the system integration of the digital output end; through configurable order, the Noise Shaping SAR ADC can optimize its power consumption while meeting the quantization accuracy requirements, thereby improving the energy efficiency of the ADC system; through multiple conversions, the Noise Shaping SAR ADC can significantly reduce the number of inter-stage amplifications, thereby improving the conversion speed and energy efficiency of the ADC.

[0044] The present invention provides a configurable floating voltage domain amplifier and an amplifier linearity enhancement technology. By configuring the amplifier to a low power consumption mode and performing several additional first-stage conversions at the output end of the amplifier, the output swing of the inter-stage amplification can be effectively reduced with very low power consumption, thereby improving the linearity of the inter-stage amplification. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 The structure of the two-stage analog-to-digital converter and a simplified timing diagram of the present invention;

[0046] in, is the input signal; It is the first step sampling signal. When it is set high, the input signal is sampled in the first step. It is the second step sampling signal, and the second step sampling is performed when it is set high; It is the first-level conversion signal, and the first-level conversion is performed when it is set high; It is the second-level conversion signal, and the second-level conversion is performed when it is set high; To amplify the signal, inter-stage amplification is performed when set high.

[0047] Figure 2 It is a schematic diagram of the working process of the efficient sampling noise elimination technology of the present invention.

[0048] Figure 3 Schematic diagram of a circuit of a two-stage analog-to-digital converter of the present invention.

[0049] Figure 4 Detailed timing diagram of the two-stage analog-to-digital converter of the present invention.

[0050] Figure 5 The present invention provides a schematic diagram of the working principle of the linearity enhancement technology for the inter-stage amplifier in the two-stage analog-to-digital converter and a circuit diagram of a configurable floating voltage domain amplifier.

[0051] Figure 6 The figure is a schematic diagram of the working principle of the loop filter in the two-stage analog-to-digital converter of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described below through specific implementation modes in conjunction with the accompanying drawings, but the scope of the present invention is not limited in any way.

[0053] like Figure 1 As shown, the two-stage analog-to-digital converter proposed in the present invention includes a first-stage ADC, a second-stage ADC and an inter-stage amplifier. In a specific implementation, the first-stage ADC is an 8-bit SAR ADC, which adopts bottom plate sampling, and the second-stage ADC is an incremental 7-bit first-order / second-order configurable Noise Shaping SAR ADC, which adopts top plate sampling, and the inter-stage amplifier is a configurable floating voltage domain amplifier. Two sets of noise elimination capacitors are embedded in the second-stage ADC to eliminate the noise of the first-stage C DAC1 The sampling noise on the circuit is reduced, the sampling capacitance value of the first stage is lowered, the designed ADC is easy to drive, and the burden on the peripheral driving circuit is greatly reduced.

[0054] The working principle of the efficient sampling noise elimination technology proposed by the present invention is as follows: Figure 2 As shown. S1 When high, the input signal V IN Receive the sample to C DAC1 The bottom plate and top plate of the MOSFET are equivalently grounded. S1 When the falling edge arrives, the input signal and sampling noise are fixed to C DAC1 In odd sampling periods, at ΦS1 For low S2 When it is high, the trigger amplifier amplifies and collects the first-stage sampling noise and the change of the input signal to the noise elimination capacitor C NCE In the inter-stage amplification stage, the amplifier converts C DAC1 The residual voltage and sampling noise on C are amplified again DAC2 In the next even-numbered cycle, C DAC2 With C NCE The second stage conversion is performed in series, thereby achieving the cancellation of sampling noise in the critical second stage conversion. At the same time, the sampling noise of the even cycle is extracted by the amplifier to C NCO On. By C NCE and C NCO The sampling noise cancellation technology only requires the amplifier to work twice, in the sampling stage and the inter-stage amplification stage, to achieve the cancellation of the sampling noise within one sampling cycle. Compared with other sampling noise elimination technologies, the number of amplifier amplifications is greatly reduced. At the same time, the sampling noise cancellation technology supports the parallel execution of the first-stage conversion and the second-stage conversion, so it can significantly improve the conversion speed and energy efficiency of the ADC system.

[0055] The two-stage analog-to-digital converter circuit and timing diagram provided by the present invention are shown in FIG. Figure 3 and Figure 4 As shown in Figure 1, a complete data readout includes 10 samplings, and the loop filter is reset after completing a data readout. In a complete data readout process, the first-stage SAR ADC samples the input signal and amplifies the sampling noise to the noise elimination capacitor, followed by the first-stage conversion.

[0056] The first level conversion consists of two steps, such as Figure 5 As shown, the first step is to convert the trigger connection to C DAC1 The comparator on the top plate works to obtain the conversion result D of the first step. 1a , the digital logic switches the corresponding C DAC1 The bottom plate switches. After completing the 5-bit comparison, the second conversion begins. The second conversion triggers the amplifier and the comparator connected to the amplifier output to work, and performs an additional 3 comparisons to obtain the second conversion result D. 1b , the digital logic switches the corresponding C DAC1 The bottom plate switch. The conversion result D1 of the first stage is D 1a and D 1bThe second conversion not only further reduces the quantization error of the first stage, but also reduces the influence of the mismatch between the two comparators and the amplifier on the residual voltage of the first stage, greatly reducing the output swing of the amplifier in the inter-stage amplification stage, thereby improving the linearity of the inter-stage amplification. In addition, during the second conversion, the configurable floating voltage domain amplifier designed by the present invention is configured to a low power consumption mode, using only a small capacitor C Small As the power supply capacitor of the amplifier tube, it reduces the additional power consumption of the amplifier.

[0057] Before the inter-stage amplification stage, according to the digital code PN generated by the random number generator, switch C Dither The bottom plate of C DAC1 A random disturbance voltage is injected into the top plate, which will be amplified by the inter-stage amplifier and quantized by the second-stage ADC. By correlating the random disturbance with the quantization result of the second-stage ADC, the gain of the inter-stage amplifier can be extracted, and the gain calibration is performed in the digital domain, so that the ADC can work in different environments.

[0058] In the interstage amplification stage, the residual voltage and sampling noise of the first stage are amplified to CDAC2 for the conversion of the second stage. In this implementation, after one interstage amplification, the ADC of the second stage performs three consecutive conversions. Therefore, a complete data readout in this implementation includes 30 conversion cycles, and the conversion result D2 of the second stage is reset after each conversion. In each conversion cycle, the comparator first performs a 7-bit comparison, and after the comparison is completed, the loop filter is triggered to update once.

[0059] The loop filter adopts a first-order / second-order configurable loop filter structure. Its working principle is as follows: Figure 6 In the 1st to 24th conversion cycles of the second stage, the loop filter is configured in the first-order operation mode, C INT1a and C INT1b It is used alternately to extract the output of the buffer and to feed back the integration result in series with other capacitors in the second stage to realize the first-order integration function. In this mode, only one buffer works, so it has smaller power consumption. In the 25th to 30th conversion cycle, an additional C INT2a and C INT2b Works alternately and with C INT1a and C INT1b Cascading can realize the second-order integration function and obtain higher quantization accuracy. The first-order / second-order configurable loop filter structure can take into account the power consumption of the loop filter and the quantization accuracy of the ADC, and reduce the power consumption of the loop filter as much as possible while meeting the accuracy requirements.

[0060] It should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A sampling noise cancellation method for a two-stage analog-to-digital converter, characterized in that: The first stage and the second stage of the two-stage analog-to-digital converter are connected through a configurable floating voltage domain amplifier, that is, the interstage amplifier of the two-stage analog-to-digital converter is a configurable floating voltage domain amplifier; the input end of the configurable floating voltage domain amplifier is connected to the top plate of the capacitive analog-to-digital converter CDAC of the first stage, and the output end is connected to the top plate of the capacitive analog-to-digital converter CDAC of the second stage; the configurable floating voltage domain amplifier is used to extract sampling noise in the sampling stage and the interstage amplification stage of the two-stage analog-to-digital converter; in the sampling stage of the two-stage analog-to-digital converter, the sampling noise of the first stage of the two-stage analog-to-digital converter is amplified and stored in the noise cancellation capacitor of the second stage; In the inter-stage amplification stage, the sampling noise of the first stage and the quantized residual voltage are amplified and stored in the capacitive digital-to-analog converter of the second stage; the capacitive digital-to-analog converter of the second stage and the noise cancellation capacitor are connected in series to cancel the sampling noise of the first stage during the second stage conversion process.

2. A method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise, characterized in that: The sampling noise cancellation method of claim 1 is used; the first stage of the two-stage analog-to-digital converter is a multi-bit SAR ADC; the second stage is an incremental type Noise Shaping SAR ADC that supports multiple conversions and has a configurable multi-bit order; the inter-stage amplifier is a configurable floating voltage domain amplifier; and the following steps are included: 1) Design and prepare a configurable floating voltage domain amplifier, including an amplifier tube and a power supply capacitor; The power supply capacitor of the floating voltage domain amplifier is split into a large capacitor and a small capacitor, and a control element is added to control the connection between the power supply capacitor and the amplifier tube, so as to realize dynamically configurable power supply during the operation of the analog-to-digital converter; the configurable floating voltage domain amplifier is used to extract sampling noise in the sampling stage and the inter-stage amplification stage, and is used to reduce the residual voltage of the first stage in the first stage quantization stage; 2) Prepare a multi-bit SAR ADC, including a sampling circuit, a capacitive analog-to-digital converter CDAC, a capacitor for generating jitter, two comparators and a digital logic part; the sampling circuit is connected to the bottom plate of the CDAC; the capacitor for generating jitter is connected to the top plate of the CDAC; the multi-bit SAR ADC is used for sampling and first-stage conversion; after the first-stage conversion is completed, the bottom plate voltage of the capacitor for generating jitter is switched to inject the jitter voltage into the top plate of the CDAC to calibrate the gain of the inter-stage amplifier; the input end of one of the comparators is connected to the top plate of the CDAC, and the input end of the other comparator is connected to the output port of the above amplifier; in the first-stage conversion stage, the comparison results of the two comparators are both controlled by digital logic to switch the bottom plate switch of the CDAC; 3) Prepare an incremental Noise Shaping SAR ADC that supports multiple conversions and has a configurable multi-bit order, including CDAC, two sets of noise cancellation capacitors, a loop filter with a configurable order, a comparator, and a digital logic section; Among them, the loop filter with configurable order is used in the incremental ADC. In the N conversion processes included in the data readout, it is configured as a low-order working mode in the first N1 conversions; and configured as a high-order working mode in the next N2 conversions; N2=N-N1; One end of the noise cancellation capacitor is connected to the top plate of the CDAC, and the other end is connected to the loop filter, and the other end of the loop filter is connected to the input of the comparator; in the second-stage conversion process, the switching of the CDAC bottom plate switch is controlled by digital logic to complete the analog-to-digital conversion; the multi-bit configurable Noise Shaping SAR ADC is used for the second-stage conversion, and the sampling noise of the first stage is saved in the sampling stage, and the sampling noise is canceled in the second-stage conversion process; 4) A multi-bit SAR ADC is used as the first stage, and a multi-bit order configurable Noise Shaping SAR ADC is used as the second stage; the first stage and the second stage are connected through a configurable floating voltage domain amplifier; the input end of the amplifier is connected to the CDAC top plate of the first stage, and the output end is connected to the CDAC top plate of the second stage; when working, the first stage and the second stage are configured in a pipeline; the residual voltage after quantization of the first stage is transmitted to the second stage through the interstage amplifier, and the second stage is configured to realize continuous multiple conversions after one interstage amplification, and the loop filter in the second stage ADC is reset after a complete data readout.

3. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 2, characterized in that: In the configurable floating voltage domain amplifier, in the first quantization stage, only a small power supply capacitor is used to power the amplifier tube; in other stages, all power supply capacitors are enabled to power the amplifier tube.

4. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 2, characterized in that: When the sampling noise cancellation method is adopted, within one sampling cycle, the amplifier only needs to work twice, in the sampling stage and the inter-stage amplification stage, and the amplifier is turned off in other stages; and a dynamic amplifier is used.

5. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 4, characterized in that: The two-stage analog-to-digital converter uses two sampling noise elimination capacitors, that is, the sampling noise cancellation capacitors of the second stage include two, one of which is used to collect the sampling noise of the first stage, and the other capacitor cancels the sampling noise during the second stage conversion process, so that the first stage conversion and the second stage conversion are performed in parallel, thereby improving the conversion speed of the two-stage analog-to-digital converter; The first stage of the two-stage analog-to-digital converter works as follows: The sampling phase is divided into two steps. The first step of sampling connects the input signal to the bottom plate of CDAC and the top plate to the common mode level. The second step of sampling disconnects the switch of the top plate, triggers the interstage amplifier to work, amplifies the sampling noise on CDAC and the change of the input signal during the second step of sampling, and stores them on the noise cancellation capacitor of the second stage. In the first-stage conversion stage, it is divided into two steps. The first step conversion triggers the comparator connected to the top plate of CDAC to work, and the most significant bit part of CDAC is switched according to the comparison result; an inter-stage amplification linearity enhancement technology based on two-step conversion is designed. After the first-stage conversion of the analog-to-digital converter is completed, the comparator after the amplifier is used to perform several additional conversions as the second-step conversion, so that the amplifier has a small input signal swing in the inter-stage amplification stage, thereby improving the linearity of the inter-stage amplification; the second-step conversion is used to reduce the quantization error after the first-step conversion and reduce the output swing of the amplifier.

6. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 5, characterized in that: The working process of the configurable floating voltage domain amplifier includes three stages, namely: the second step of the sampling stage, the second step of the first stage conversion stage and the inter-stage amplification stage; When the amplifier is working, the amplifier tube is powered by the power supply capacitor to perform the amplification function; in other stages, the amplifier is not working, and the power supply end of the amplifier tube is floating to reset the power supply capacitor; In the second step of the first conversion stage, the amplifier is configured in a low-power mode by reducing the power supply capacitance of the amplifier, and the load capacitance is the parasitic capacitance of the comparator input, thereby reducing the energy consumption of the system; In the second step of the sampling phase and the inter-stage amplification phase, the amplifier is connected to all power supply capacitors to work, and the load capacitors are the second-stage noise cancellation capacitor and the second-stage CDAC respectively. The capacitance values ​​of the power supply capacitors and load capacitors in the two stages are consistent.

7. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 2, characterized in that: The incremental type in step 3) supports multiple conversions and the multi-bit order configurable Noise Shaping SAR ADC is specifically a 7-bit first-order or second-order. In one conversion cycle, the switching of the second-stage CDAC bottom plate switch is controlled according to the comparison result of the comparator. After all bits are compared and switched, the loop filter is triggered to work and the output of the loop filter is updated.

8. The method for realizing a two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 7, characterized in that: The loop filter is an infinite impulse response filter with configurable order; The first-order working mode is: by connecting the capacitor storing the residual voltage after the second-level quantization is completed in series with the integration capacitor 1a storing the integration result of the previous conversion cycle, the signal is added, and the addition result is stored on the integration capacitor 1b using the dynamic buffer to obtain the integration result of the current conversion cycle; in the next conversion cycle, the integration capacitor 1b is used to replace the integration capacitor 1a, the integration value of the current cycle is added to the residual voltage of the next cycle, and then the integration result of the new cycle is saved to the integration capacitor 1a through the dynamic buffer; By alternately using the integration capacitor 1a and the integration capacitor 1b in each conversion cycle, a continuous first-order integration of the residual voltage is achieved; The second-order working mode is: adding an integral capacitor 2a and an integral capacitor 2b in cascade connection after the integral capacitor 1a or the integral capacitor 1b, and adding a dynamic buffer to update the values ​​of the integral capacitor 2a and the integral capacitor 2b to realize the double integration function; During the loop filter update process, after the loop filter update is completed, the second-stage input signal is rebuilt by resetting the second-stage CDAC for conversion in the next conversion cycle; so that multiple consecutive conversions can be achieved in the second-stage conversion stage without re-amplification between stages; The two groups of noise cancellation capacitors in the second stage are called noise cancellation capacitor E and noise cancellation capacitor O respectively; during the second stage conversion process, if the noise cancellation capacitor E is connected in series with the second stage CDAC and connected in series with the integral capacitor of the loop filter to complete the second stage conversion, the first stage sampling will amplify the sampling noise and store it in the noise cancellation capacitor O; in the next second stage conversion, the noise cancellation capacitor O is connected in series with the second stage CDAC for conversion, and the new sampling noise is stored in the noise cancellation capacitor E; the noise cancellation capacitor E and the noise cancellation capacitor O are used alternately in different sampling cycles; the first stage and the second stage work in parallel.

9. A two-stage analog-to-digital converter that efficiently cancels sampling noise using the method of claim 2, characterized in that: include: A multi-bit SAR ADC is used as the first stage, an incremental type Noise Shaping SAR ADC supporting multiple conversions and configurable multi-bit order is used as the second stage, and a configurable floating voltage domain amplifier is used as an interstage amplifier; wherein the interstage amplifier is placed between the first stage and the second stage, an input end of the interstage amplifier is connected to the top plate of the CDAC in the first stage, and an output end of the interstage amplifier is connected to the top plate of the CDAC in the second stage.

10. The two-stage analog-to-digital converter for efficiently canceling sampling noise as claimed in claim 9, characterized in that: The multi-bit SARADC is 8 bits.

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