DPU-based UDP report system and method, electronic equipment and medium

Abstract

The invention provides a UDP report system and method based on a DPU, electronic equipment and a medium. The system comprises an initialization module, a software report data receiving module, a hardware report data receiving module, an arbitration module, a UDP packing module and a sending module. The initialization module is used for performing initialization configuration on the received static data; the static data is used for representing header information of a current transaction report; the arbitration module is used for sequentially transmitting the report data received by the software report data receiving module and the report data received by the hardware report data receiving module to the UDP packaging module according to the transmission priority; the report data is business data transmitted by each transaction report; the UDP packaging module is used for packaging the static data and the report data to obtain a UDP data packet when the report data is received; and the sending module is used for sending the UDP data packet to a transaction network port.

Description

Technical Field

[0001] The present disclosure relates to the technical field of order submission in financial trading systems such as securities and stocks, and in particular to a UDP order submission system, method, electronic device, and medium based on DPU. Background Art

[0002] High-frequency trading in the financial trading field is an important application field of ultra-low latency, and it is also the field that pursues the most extreme performance. Financial institutions and exchanges need to trade at the level of subtle or even nanoseconds to gain market advantages. Therefore, it is crucial for trading platforms and network infrastructure to achieve ultra-low latency. In the field of high-frequency trading, with the popularization of ultra-low latency technology of DPU (Data Processing Unit), the development of ultra-low latency and high-speed trading systems based on DPU has become a consensus among financial institutions.

[0003] In the related art, the CPU (Central Processing Unit) side assembles the received data into UDP data packets that conform to the exchange order format, and sends the UDP data packets to the DPU through the universal serial connection standard PCIe (Peripheral Component Interconnect Express). Since the complete UDP data packet needs to be assembled on the CPU, and the assembly is performed after the complete UDP data packet is received, it will cause high transmission delay. Therefore, in the trading scenario, how to send the trading order to the exchange faster is an urgent problem to be solved. Summary of the invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a DPU-based UDP order system, method, electronic device, and medium, which can send transaction orders to the exchange more quickly in a trading scenario.

[0005] In order to achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present disclosure provides a DPU-based UDP order system, the DPU-based UDP order system comprising: an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP package assembly module, and a sending module;

[0007] The initialization module is used to initialize and configure the received static data; the static data is used to represent the header information of the current transaction order;

[0008] The arbitration module is used to transmit the order data received by the software order data receiving module and the order data received by the hardware order data receiving module to the UDP packet assembly module in sequence according to the transmission priority; the order data is the business data transmitted for each transaction order;

[0009] The UDP packet assembly module is used to, when receiving the order data, perform packet assembly processing on the static data and the order data to obtain a UDP data packet;

[0010] The sending module is used to send the UDP data packet to the transaction network port.

[0011] As an optional implementation of the embodiment of the present disclosure, the software order data receiving module is used to receive the order data based on direct memory access DMA transmission through the software order data interface.

[0012] As an optional implementation of the embodiment of the present disclosure, the hardware order data receiving module is used to receive the order data sent by the trading strategy module through the hardware order data interface; the trading strategy module is used to store the order data.

[0013] As an optional implementation of the embodiment of the present disclosure, the arbitration module is specifically used to first read the order data from the first-in-first-out queue of the hardware order data receiving module and transmit the order data to the UDP packet assembly module when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module.

[0014] As an optional implementation of the embodiment of the present disclosure, the arbitration module is specifically used to first read the order data from the first-in-first-out queue of the software order data receiving module and transmit the order data to the UDP packet assembly module when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module.

[0015] As an optional implementation of the embodiment of the present disclosure, the UDP packet assembly module is also used to switch the working state of the UDP packet assembly module from an idle state to a start state when it is monitored that the initialization module has static data input.

[0016] As an optional implementation of the embodiment of the present disclosure, the UDP packet assembly module is further used to, when the working state of the UDP packet assembly module is the start state, when it is monitored that the first-in-first-out queue of the arbitration module is not empty, read the order data from the first-in-first-out queue of the arbitration module, perform packet assembly processing on the static data and the order data, and obtain a UDP data packet;

[0017] When it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has an end information input, the working state of the UDP packet assembly module is switched from the start state to the idle state.

[0018] In a second aspect, the embodiment of the present disclosure provides a UDP order reporting method based on DPU, including:

[0019] Initializing and configuring the received static data; the static data is used to represent the header information of the current transaction order;

[0020] According to the transmission priority, the order data received through the software order data interface and the order data received through the hardware order data interface are transmitted in sequence;

[0021] When the order data is received, the static data and the order data are packaged to obtain a UDP data packet;

[0022] The UDP data packet is sent to the transaction network port.

[0023] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0024] The order data based on direct memory access DMA transmission is received through the software order data interface.

[0025] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0026] The order data sent by the trading strategy module is received through the hardware order data interface; the trading strategy module is used to store the order data.

[0027] As an optional implementation of the embodiment of the present disclosure, the order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted according to the transmission priority, including:

[0028] When the priority of the software order data receiving module is lower than that of the hardware order data receiving module, the order data is first read from the first-in-first-out queue of the hardware order data receiving module, and the order data is transmitted to the UDP packet assembly module.

[0029] As an optional implementation of the embodiment of the present disclosure, the order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted according to the transmission priority, including:

[0030] When the priority of the software order data receiving module is higher than that of the hardware order data receiving module, the order data is first read from the first-in-first-out queue of the software order data receiving module, and the order data is transmitted to the UDP packet assembly module.

[0031] As an optional implementation of the embodiment of the present disclosure, when the order data is received, the static data and the order data are packaged together, and before the UDP data packet is obtained, the method further includes:

[0032] When it is monitored that the initialization module has static data input, the working state of the UDP packet assembly module is switched from the idle state to the start state.

[0033] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0034] When the working state of the UDP packet assembly module is the start state, when it is monitored that the first-in-first-out queue of the arbitration module is not empty, the order data is read from the first-in-first-out queue of the arbitration module, the static data and the order data are packaged, and a UDP data packet is obtained;

[0035] When it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has an end information input, the working state of the UDP packet assembly module is switched from the start state to the idle state.

[0036] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the DPU-based UDP reporting method described in the second aspect or any embodiment of the second aspect is implemented.

[0037] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the DPU-based UDP order reporting method described in the second aspect or any implementation scheme of the second aspect is implemented.

[0038] The DPU-based UDP order system provided by the present disclosure includes an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembly module and a sending module. The received static data is initialized and configured by the initialization module. The order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted to the UDP packet assembly module by the arbitration module according to the transmission priority. When the order data is received, the UDP packet assembly module performs packet assembly processing on the static data and the order data to obtain a UDP data packet. Finally, the sending module sends the UDP data packet to the transaction network port. The DPU-based UDP order system of the present application realizes simultaneous software and hardware ordering, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the static data is sent to the DPU card for pre-storage through the pre-configured architecture of the packet header information. Each subsequent order only transmits necessary transaction information (i.e., order data) to reduce the data transmission volume of PCIe, thereby reducing system latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0041] Figure 1 The following is a schematic diagram of an application scenario of a UDP order system based on DPU in one embodiment;

[0042] Figure 2 It is a structural diagram of a UDP order system based on DPU in one embodiment;

[0043] Figure 3 It is a flowchart of a UDP order system based on DPU in one embodiment;

[0044] Figure 4 It is a schematic diagram of the structure of the electronic device described in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0046] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0047] In the embodiments of the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present disclosure should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way. In addition, in the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "multiple" refers to two or more.

[0048] Glossary:

[0049] High-frequency trading (HFT) is an automated trading method that uses high-speed computer algorithms and network technology to conduct a large number of transactions in a very short period of time. This trading strategy relies on small market changes, such as small fluctuations in stock prices or price differences between different exchanges, to achieve profits. Characteristics of high-frequency trading include fast execution of trading orders, low-latency trading systems, and rapid response to market data. High-frequency trading (HFT) systems may use automated algorithms to quickly generate and execute trade orders to take advantage of small market fluctuations to profit.

[0050] DPU is a processor designed specifically for data centers to efficiently handle large-scale data workloads, including data transmission, protocol, protection, compression, analysis and encryption. Compared with traditional CPUs and GPUs, DPU focuses on data-centric workloads such as network, storage and security operations in data centers.

[0051] UDP is a connectionless network protocol used to transmit data in IP networks. It belongs to the transport layer protocol and is parallel to TCP (Transmission Control Protocol), but the main difference from the TCP protocol is that UDP is stateless and does not guarantee the order, integrity and reliability of data packets. UDP provides a simple way to send encapsulated IP data packets, but does not sort the data or ensure that they reach their destination.

[0052] Trading orders usually refer to instructions issued by investors or traders in the financial market to buy or sell securities, stocks, futures, foreign exchange and other financial products. These instructions contain detailed information about the transaction, such as the financial product code, transaction direction (buy or sell), transaction quantity, price, etc. The execution of trading orders is usually carried out through the trading system of the exchange, which determines the execution method of the order based on the type and duration of the order. The basic types of trading orders include: market order, limit order, stop loss order, take profit order, iceberg order and other types. Among them, market order refers to an instruction to buy or sell immediately at the current market price. Limit order refers to setting a specific price, and the buy or sell will only be executed when the market price reaches or exceeds this price. Stop loss order means that when the market price reaches a certain level, the stop loss order will be triggered, usually used to limit losses. Take profit order is similar to stop loss order, but is used to lock in profits and is triggered when the price reaches a preset level. Iceberg order refers to a large transaction order, which only displays a small part of the transaction volume and hides the rest to avoid excessive impact on the market price.

[0053] Trading strategy refers to a set of rules and methods developed in the financial market to achieve profit goals. Different traders adopt different trading strategies based on their risk preferences, market analysis, fund management capabilities and other factors. Some common types of trading strategies are: technical analysis strategy, fundamental analysis strategy, quantitative trading strategy, trend tracking strategy, hedging strategy, arbitrage strategy, value investment strategy, etc. Among them, technical analysis strategy relies on icons and historical price data to predict future market trends. Fundamental analysis strategy: Make trading decisions based on information such as the company's financial situation, industry conditions, and macroeconomic indicators. Quantitative trading strategy refers to the use of mathematical models and algorithms to identify trading opportunities. Trend tracking strategy refers to following market trends, buying stocks in an upward trend, and selling stocks in a downward trend. Hedging strategy refers to reducing market risk by holding positions in multiple related assets at the same time. Arbitrage strategy refers to using price differences in different markets or at different points in time to obtain risk-free profits. Value investment strategy refers to finding stocks whose market prices are lower than their intrinsic value and holding them for a long time.

[0054] RAM (Random Access Memory) is hardware used in computers and other electronic devices to temporarily store data and programs. It is the computer's primary memory, used to store data and instructions currently in use while the computer is running. RAM is usually volatile, meaning that when the power is turned off, the data stored in RAM is lost. RAM allows data to be read and written quickly, which allows computers to quickly access and process information.

[0055] PCIE is a computer bus and expansion card standard for connections between computer hardware devices. PCIe uses high-speed serial connections and supports different data transfer rates.

[0056] In the related art, the received data is assembled into a UDP data packet that conforms to the exchange order format on the CPU (Central Processing Unit) side, and the UDP data packet is sent to the DPU through the universal serial connection standard PCIe (Peripheral Component Interconnect Express). Since the complete UDP data packet needs to be assembled on the CPU, transmitting the complete UDP data packet to the low-latency network card DPU through the universal serial connection standard PCIe will result in high transmission delay. In addition, when the trading strategy itself is implemented on the DPU low-latency network card, it is necessary to upload the data content of the order to the CPU (Central Processing Unit) through the universal serial connection standard PCIe (Peripheral Component Interconnect Express), and then the CPU sends it to the low-latency network card DPU through PCIe. The two PCIe transmissions increase the delay. Therefore, in the trading scenario, how to send the trading order to the exchange faster is an urgent problem to be solved.

[0057] In order to solve the above problems, the present disclosure proposes a UDP order system based on DPU. The UDP order system based on DPU provided by the present disclosure includes an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembly module and a sending module. The received static data is initialized and configured by the initialization module. The order data received through the software order data interface and the order data received through the hardware order data interface are transmitted to the UDP packet assembly module in sequence according to the transmission priority by using the arbitration module. When the order data is received, the UDP packet assembly module performs packet assembly processing on the static data and the order data to obtain a UDP data packet. Finally, the sending module sends the UDP data packet to the transaction network port. The UDP order system based on DPU of the present application realizes simultaneous ordering of software and hardware, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the static data is sent to the DPU card for pre-storage through the pre-configured architecture of the packet header information. Each subsequent order only transmits the necessary transaction information (i.e., order data) to reduce the data transmission volume of PCIe, thereby reducing the system delay.

[0058] Reference Figure 1 As shown, Figure 1The schematic diagram of the application scenario of the DPU-based UDP order system in the embodiment of the present disclosure shows that the system is composed of 6 modules, namely: initialization module, software order data receiving module, hardware order data receiving module, arbitration module, UDP package module and sending module. Each module is connected through FIFO. When the input FIFO of each module is not empty, data is read from the FIFO, the calculation of this module is completed, and the result is written to the output FIFO of this module.

[0059] The following is a detailed introduction to the DPU-based UDP order reporting system of an embodiment of the present disclosure.

[0060] Reference Figure 2 As shown, Figure 2 A structural diagram of a DPU-based UDP order reporting system according to an embodiment of the present disclosure includes:

[0061] The initialization module 210 is used to initialize and configure the received static data; the static data is used to represent the header information of the current transaction order.

[0062] In the disclosed embodiment, when the UDP protocol is used for data transmission, the data packet will be encapsulated in turn by the Ethernet frame, IP (Internet Protocol) header and UDP header. The header information of the current transaction order includes the source MAC, destination MAC, source port, destination port, message format, message length and the like. Since the header information of the current transaction order does not change with the specific transaction order, it can be pre-configured and issued in the form of initialization parameters in the initialization module. Static data includes: Ethernet frame header data, IP header data, the preset order protocol header data and message header data. Among them, the Ethernet frame header data includes: Ethernet type, source MAC address, destination MAC address. IP header data includes: IP protocol version, IP header length, service type, total length, identifier, source IP address, destination IP address and the like. UDP header data includes: source port, destination port, length, checksum and the like. The message header part is used to distinguish different types of message information, such as stop loss order, stop profit order, iceberg order and the like. The initialization module initiates DMA transmission of the public information (i.e. static data) in the exchange order format that is not related to specific transaction information in a pre-configured manner by the initialization process on the CPU, and sends these static data to the DPU card for pre-storage. Each subsequent order only transmits necessary transaction information (i.e. order data) to reduce the data transmission volume of PCIe, thereby reducing system latency.

[0063] The arbitration module 220 is used to transmit the order data received by the software order data receiving module 230 and the order data received by the hardware order data receiving module 240 to the UDP packet assembly module in sequence according to the transmission priority; the order data is the business data transmitted for each transaction order.

[0064] In the disclosed embodiment, the order data is used to describe the detailed information of the transaction, and the order data includes, for example, the financial product code of the transaction, the transaction direction, the transaction quantity, the price, etc. The transmission priority can be set according to the actual application scenario. For example, the order data received by the software order data receiving module 230 can be set to be transmitted first, and the order data received by the hardware order data receiving module 240 can also be set to be transmitted first.

[0065] Optionally, the software order data receiving module 230 is used to receive order data transmitted based on direct memory access (DMA) through a software order data interface.

[0066] In the disclosed embodiment, the software order data receiving module receives the message content data transmitted based on DMA from the order process of the CPU through the software order data receiving interface when the transaction order is initiated by the software.

[0067] Optionally, the hardware order data receiving module 240 is used to receive the order data sent by the trading strategy module through the hardware order data interface; the trading strategy module is used to store the order data.

[0068] In the disclosed embodiment, the hardware order data receiving module, when a transaction order is initiated from within the DPU (i.e., the transaction strategy module is implemented on the DPU), receives the message content data sent from the transaction strategy module through the hardware order data receiving interface.

[0069] In an optional embodiment, the arbitration module 220 is specifically used to first read the order data from the first-in-first-out queue of the hardware order data receiving module and transmit the order data to the UDP packet assembly module when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module.

[0070] In the embodiment of the present disclosure, for the arbitration module, since the software order data is cached in the software FIFO and the hardware order data is cached in the hardware FIFO, the arbitration switch is used to first determine whether the hardware FIFO is empty in each clock cycle. When the hardware FIFO is not empty, the order data is read from the hardware FIFO and transmitted to the UDP packet assembly module; when the hardware FIFO is empty, it is further determined whether the software FIFO is empty. When the software FIFO is not empty, the order data is read from the software FIFO and transmitted to the UDP packet assembly module.

[0071] In an optional embodiment, the arbitration module 220 is specifically used to first read the order data from the first-in-first-out queue of the software order data receiving module and transmit the order data to the UDP packet assembly module when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module.

[0072] In the embodiment of the present disclosure, for the arbitration module, since the software order data is cached in the software FIFO and the hardware order data is cached in the hardware FIFO, the arbitration switch is used to first determine whether the software FIFO is empty in each clock cycle. When the software FIFO is not empty, the order data is read from the software FIFO and transmitted to the UDP packet assembly module; when the software FIFO is empty, it is further determined whether the hardware FIFO is empty. When the hardware FIFO is not empty, the order data is read from the hardware FIFO and transmitted to the UDP packet assembly module.

[0073] In addition, it should be noted that when both the hardware FIFO and the software FIFO are empty, no data is transmitted.

[0074] The UDP packet assembly module 250 is used to, when receiving the order data, perform packet assembly processing on the static data and the order data to obtain a UDP data packet.

[0075] In the disclosed embodiment, when the UDP packet assembly module receives the order data sent by the arbitration module, the static data stored in the initialization module is assembled with the order data sent by the arbitration module to obtain a complete UDP data packet.

[0076] In an optional implementation, the UDP packet assembly module 250 is further configured to switch the working state of the UDP packet assembly module from an idle state to a start state when it is detected that the initialization module has static data input.

[0077] In the disclosed embodiment, the working state of the UDP packet assembly module includes: an idle state and a start state. The initial working state of the UDP packet assembly module is an idle state, which monitors the FIFO queue data of the initialization module: when the initialization module sends the initialization configuration information, the initialization configuration information is cached in the on-chip RAM of the initialization module, and the working state of the UDP packet assembly module is switched from the idle state to the start state.

[0078] In an optional embodiment, the UDP packet assembly module 250 is also used to, when the working state of the UDP packet assembly module is the starting state, when it is monitored that the first-in-first-out queue of the arbitration module is not empty, read the order data from the first-in-first-out queue of the arbitration module, and perform packet assembly on the static data and the order data to obtain a UDP data packet; when it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has end information input, the working state of the UDP packet assembly module is switched from the starting state to the idle state.

[0079] In the embodiment of the present disclosure, when the working state of the UDP packet assembly module is the starting state, the FIFO queue of the arbitration module is monitored to see whether there is order data: when it is monitored that the first-in-first-out queue of the arbitration module is not empty, the order data is read from the first-in-first-out queue of the arbitration module, the static data and the order data are packaged, and a UDP data packet is obtained; when it is monitored that the first-in-first-out queue of the arbitration module is empty, if the initialization module is monitored to have end information input, the working state of the UDP packet assembly module is switched from the starting state to the idle state.

[0080] The sending module 260 is used to send the UDP data packet to the transaction network port.

[0081] In the disclosed embodiment, a complete UDP data packet is sent to the transaction network port for transaction.

[0082] The DPU-based UDP order system provided by the present disclosure includes an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembly module and a sending module. The received static data is initialized and configured by the initialization module. The order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted to the UDP packet assembly module by the arbitration module according to the transmission priority. When the order data is received, the UDP packet assembly module performs packet assembly processing on the static data and the order data to obtain a UDP data packet. Finally, the sending module sends the UDP data packet to the transaction network port. The DPU-based UDP order system of the present application realizes simultaneous software and hardware ordering, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the static data is sent to the DPU card for pre-storage through the pre-configured architecture of the packet header information. Each subsequent order only transmits necessary transaction information (i.e., order data) to reduce the data transmission volume of PCIe, thereby reducing system latency.

[0083] Corresponding to the above system embodiment, the present disclosure embodiment also provides a UDP order method based on DPU, referring to Figure 3 As shown, Figure 3 It is a flowchart of a UDP order reporting method based on DPU, and the method includes the following steps S31-S34.

[0084] S31. Initialize and configure the received static data.

[0085] The static data is used to represent the header information of the current transaction order.

[0086] S32. According to the transmission priority, the order data received through the software order data interface and the order data received through the hardware order data interface are transmitted in sequence.

[0087] S33. When the order data is received, the static data and the order data are packaged together to obtain a UDP data packet.

[0088] S34, sending the UDP data packet to the transaction network port.

[0089] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0090] The order data based on direct memory access DMA transmission is received through the software order data interface.

[0091] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0092] The order data sent by the trading strategy module is received through the hardware order data interface; the trading strategy module is used to store the order data.

[0093] As an optional implementation of the embodiment of the present disclosure, the order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted according to the transmission priority, including:

[0094] When the priority of the software order data receiving module is lower than that of the hardware order data receiving module, the order data is first read from the first-in-first-out queue of the hardware order data receiving module, and the order data is transmitted to the UDP packet assembly module.

[0095] As an optional implementation of the embodiment of the present disclosure, the order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted according to the transmission priority, including:

[0096] When the priority of the software order data receiving module is higher than that of the hardware order data receiving module, the order data is first read from the first-in-first-out queue of the software order data receiving module, and the order data is transmitted to the UDP packet assembly module.

[0097] As an optional implementation of the embodiment of the present disclosure, when the order data is received, the static data and the order data are packaged together, and before the UDP data packet is obtained, the method further includes:

[0098] When it is monitored that the initialization module has static data input, the working state of the UDP packet assembly module is switched from the idle state to the start state.

[0099] As an optional implementation of the embodiment of the present disclosure, the method further includes:

[0100] When the working state of the UDP packet assembly module is the start state, when it is monitored that the first-in-first-out queue of the arbitration module is not empty, the order data is read from the first-in-first-out queue of the arbitration module, the static data and the order data are packaged, and a UDP data packet is obtained;

[0101] When it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has an end information input, the working state of the UDP packet assembly module is switched from the start state to the idle state.

[0102] The DPU-based UDP order reporting method provided by the present disclosure performs initialization configuration on the received static data, and transmits the order data received through the software order data interface and the order data received through the hardware order data interface in sequence according to the transmission priority. When the order data is received, the UDP packet assembly module performs packet assembly processing on the static data and the order data to obtain a UDP data packet, and finally, sends the UDP data packet to the transaction network port. The DPU-based UDP order reporting method of the present application realizes simultaneous software and hardware order reporting, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the static data is sent to the DPU card for pre-storage through the pre-configured architecture of the packet header information, and each subsequent order only transmits the necessary transaction information (i.e., order data) to reduce the data transmission volume of PCIe, thereby reducing system latency.

[0103] For the specific limitations on the DPU-based UDP order reporting method, please refer to the limitations on the DPU-based UDP order reporting system mentioned above, which will not be repeated here.

[0104] The present disclosure also provides an electronic device, Figure 4This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 4 As shown, the electronic device provided in this embodiment includes: a memory 41 and a processor 42, the memory 41 is used to store a computer program; the processor 42 is used to execute the steps performed by any embodiment of the DPU-based UDP order method provided in the above method embodiment when calling the computer program. The electronic device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. Among them, the processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. When the computer program is executed by the processor, a UDP order method based on DPU is implemented. The display screen of the electronic device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the housing of the computer device, or an external keyboard, touchpad or mouse.

[0105] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0106] In one embodiment, the DPU-based UDP order system provided by the present disclosure can be implemented in the form of a computer, and the computer program can be used in Figure 4 The electronic device shown in the figure is run. The memory of the electronic device can store various program modules constituting the DPU-based UDP order system of the electronic device.

[0107] An embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the DPU-based UDP order reporting method provided in the above method embodiment is implemented.

[0108] Those skilled in the art will appreciate that the embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0109] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0110] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0111] Computer readable media include permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0112] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0113] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A UDP order reporting system based on DPU, characterized in that: The DPU-based UDP order system includes: an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP package module and a sending module; The initialization module is used to initialize and configure the received static data; the static data is used to represent the header information of the current transaction order; The arbitration module is used to transmit the order data received by the software order data receiving module and the order data received by the hardware order data receiving module to the UDP packet assembly module in sequence according to the transmission priority; the order data is the business data transmitted for each transaction order; The UDP packet assembly module is used to, when receiving the order data, perform packet assembly processing on the static data and the order data to obtain a UDP data packet; The sending module is used to send the UDP data packet to the transaction network port.

2. The system according to claim 1, characterized in that The software order data receiving module is used to receive the order data based on direct memory access DMA transmission through the software order data interface.

3. The system according to claim 1, characterized in that The hardware order data receiving module is used to receive the order data sent by the trading strategy module through the hardware order data interface; the trading strategy module is used to store the order data.

4. The system according to claim 1, characterized in that The arbitration module is specifically used to read the order data from the first-in-first-out queue of the hardware order data receiving module when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module, and transmit the order data to the UDP packet assembly module.

5. The system according to claim 1, characterized in that The arbitration module is specifically used to first read the order data from the first-in-first-out queue of the software order data receiving module and transmit the order data to the UDP packet assembly module when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module.

6. The system according to claim 1, characterized in that The UDP packet assembly module is also used to switch the working state of the UDP packet assembly module from an idle state to a start state when it is monitored that the initialization module has static data input.

7. The system according to claim 6, characterized in that The UDP packet assembly module is further configured to, when the working state of the UDP packet assembly module is the start state, read the order data from the first-in-first-out queue of the arbitration module when it is monitored that the first-in-first-out queue of the arbitration module is not empty, perform packet assembly processing on the static data and the order data, and obtain a UDP data packet; When it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has an end information input, the working state of the UDP packet assembly module is switched from the start state to the idle state.

8. A UDP order reporting method based on DPU, characterized in that: include: Initialize the configuration of the received static data; The static data is used to represent the header information of the current transaction order; According to the transmission priority, the order data received through the software order data interface and the order data received through the hardware order data interface are transmitted in sequence; When the order data is received, the static data and the order data are packaged to obtain a UDP data packet; The UDP data packet is sent to the transaction network port.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the DPU-based UDP reporting method described in claim 8 is implemented.

10. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the DPU-based UDP order reporting method described in claim 8 is implemented.

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