Manufacturing method of ETOX Nor flash memory

Abstract

The present application relates to the field of semiconductor integrated circuit manufacturing technology, and specifically to a method for manufacturing an ETOX Nor flash memory. The method comprises: providing a shaped semiconductor substrate, the semiconductor substrate comprising a flash memory cell region and a peripheral circuit region; forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region; etching the second polysilicon layer, the inter-polysilicon dielectric layer, and the second polysilicon layer in the storage cell region to form flash memory cells, each of which has a source region lead-out space; etching the second polysilicon layer in the peripheral circuit region to form logic device polysilicon; and, based on the thickness of the inter-polysilicon dielectric layer, implanting impurity ions at a dose matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at the location of the source region lead-out space to form a flash memory cell source region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing an ETOX Nor flash memory. Background Art

[0002] ETOX Nor flash memory boasts fast read speeds and is used as a primary code storage device in a wide range of intelligent applications, including automotive electronics, IoT, and wearable devices. These applications place extremely high demands on product reliability, with DRB (data retention) being one of the most critical performance indicators, requiring a minimum of 20 years. As capacity increases and process nodes shrink, the challenges posed by DRB become even greater, leading to the risk of failure.

[0003] The DRB tailing rate (Vt ≤ 7V percentage) is an important measure of DRB performance. Big data analysis has found a strong correlation between the data tailing rate and the inter-polysilicon dielectric layer. Specifically, the thickness of the inter-polysilicon dielectric layer significantly influences the data tailing rate, with thinner layers increasing the apparent data tailing rate. However, the thickness of the inter-polysilicon dielectric layer in related technologies fluctuates, making it difficult to adjust the thickness to mitigate its impact on the DRB tailing rate. Summary of the Invention

[0004] The present application provides a method for manufacturing an ETOX NOR flash memory, which can solve the problem of data tailing rate in the related art.

[0005] In order to solve the technical problems in the background technology, the present application provides a method for manufacturing an ETOX NOR flash memory, the method comprising the following steps:

[0006] Providing a shaped semiconductor substrate, the semiconductor substrate comprising a flash memory cell region and a peripheral circuit region;

[0007] forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region;

[0008] Sequentially etching the second polysilicon layer, the inter-polysilicon dielectric layer, and the second polysilicon layer in the storage cell region to form flash memory cells, wherein a source region lead-out space is formed in each of the flash memory cells;

[0009] Etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon;

[0010] According to the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position where the source region is drawn out, to form a flash memory cell source region.

[0011] Optionally, the step of implanting impurity ions having a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at a spatial position where the source region is led out, to form a flash memory cell source region, includes:

[0012] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, implanting impurity ions into the semiconductor substrate at a position where the source region is drawn out of the space with a first implantation dose to form a flash memory cell source region;

[0013] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region;

[0014] When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region;

[0015] The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

[0016] Optionally, the first target thickness is 176A, and the first implantation dose range is 2.8E14 atoms / cm 2 to 2.2E14 atoms / cm 2 ;

[0017] The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, comprises:

[0018] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 to 2.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0019] Optionally, the first target thickness is 176A, the second target thickness is 174A, and the second implantation dose is in the range of 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 ;

[0020] The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises:

[0021] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the thickness of the dielectric layer is 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0022] Optionally, the second target thickness is 174A, and the third implant dose is in the range of 2.6E14 atoms / cm 2 to 3.2E14 atoms / cm 2 ;

[0023] The step of implanting impurity ions into the semiconductor substrate at the source region extraction space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises:

[0024] When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 to 3.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0025] Optionally, the step of forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region includes:

[0026] forming a plurality of first shallow trench isolation structures in a semiconductor substrate of a memory cell region, wherein the first shallow trench isolation structures extend in a longitudinal direction to divide the memory cell region into a plurality of columns of memory cells;

[0027] forming a tunneling oxide layer on the semiconductor substrate by a thermal oxidation process;

[0028] Depositing a first polysilicon layer on the tunneling oxide layer, and etching away the first polysilicon layer covering the first shallow trench isolation structure, so that the remaining first polysilicon layer in the storage cell area is floating gate polysilicon of the flash memory, and the floating gate polysilicon extends in the longitudinal direction;

[0029] forming a second shallow trench isolation structure in the peripheral circuit region;

[0030] forming a dielectric layer between polysilicon layers;

[0031] Etching and removing the inter-polysilicon dielectric layer and the first polysilicon layer at the position of the peripheral circuit area;

[0032] A second polysilicon layer is formed by deposition, and the second polysilicon layer fills the gap between two adjacent columns of memory cells.

[0033] Optionally, after the step of forming a source region lead-out space in each of the flash memory cells by sequentially etching a second polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer in the memory cell region is completed, and before the step of etching the second polysilicon layer in the peripheral circuit region to form polysilicon of a logic device is performed, the following steps are further performed:

[0034] Impurities are implanted into the drain region of the flash memory unit through an ion implantation process to form a lightly doped drain region.

[0035] Optionally, after the step of etching the second polysilicon layer in the peripheral circuit area to form polysilicon for logic devices is completed, the following steps are further performed before the step of forming the flash memory cell source region is performed, based on the thickness of the inter-polysilicon dielectric layer, implanting impurity ions at a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at a spatial position where the source region is drawn out:

[0036] Impurities are implanted into the source and drain regions on both sides of the high-voltage device of the logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

[0037] The technical solution of the present application includes at least the following advantages: the present application implants impurity ions at a dose matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at a spatial position where the source region is drawn out, based on the thickness of the inter-polysilicon dielectric layer, to form a flash memory cell source region. The dose implanted in the source region is adjusted to match polysilicon dielectric layers of different thicknesses, that is, the implanted dose in the source region is increased when the polysilicon dielectric layer is relatively thin, thereby compensating for the data tailing problem caused by the thin polysilicon dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 A flow chart of a method for manufacturing an ETOX Nor flash memory provided in one embodiment of the present application is shown;

[0040] Figure 2 A schematic cross-sectional structural diagram of a provided semiconductor substrate is shown;

[0041] Figure 3 shows a schematic diagram of the cross-sectional structure of the device after the tunneling oxide layer is formed;

[0042] Figure 4 shows a schematic diagram of the cross-sectional structure of the device after the inter-polysilicon dielectric layer is formed;

[0043] Figure 5 FIG. 4 shows a schematic diagram of a cross-sectional structure of the device after step S5 is completed. DETAILED DESCRIPTION

[0044] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0045] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0046] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0047] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0048] Figure 1 The flowchart of the manufacturing method of ETOX Nor flash memory provided by an embodiment of the present application is shown. Figure 1 As can be seen, the manufacturing method of the ETOX Nor flash memory includes the following steps:

[0049] Step S1: providing a semiconductor substrate, wherein the semiconductor substrate includes a memory cell region and a peripheral circuit region.

[0050] Reference Figure 2 , which shows a schematic cross-sectional view of the semiconductor substrate provided. Figure 2 As can be seen in the figure, the semiconductor substrate 100 includes a memory cell region 110 and a peripheral circuit region 120. The peripheral circuit region 120 includes a high-voltage device region and a low-voltage device region. The high-voltage device region includes an N-type high-voltage device region HVNMOS and a P-type high-voltage device region HVPMOS, while the low-voltage device region includes an N-type low-voltage device region LVNMOS and a P-type low-voltage device region LVPMOS. Figure 2 The memory cell region 110 shown includes two different cross-sectional directions, namely a Y-direction cross-sectional direction and an X-direction cross-sectional direction.

[0051] Deep N-type well regions 111 are formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110 and in the semiconductor substrate 100 at the location of the high-voltage device region 120. A first high-voltage P-type well region 112 is also formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110. The depth of the first high-voltage P-type well region 112 is less than that of the deep N-type well region 111. A threshold voltage adjustment region 113 is also formed by doping in the semiconductor substrate 100 at the location of the storage cell region 110. The threshold voltage adjustment region 113 extends downward from the surface of the semiconductor substrate 100 and is less deep than the first high-voltage P-type well region 112.

[0052] A high-voltage N-type well region 121 is further formed by doping in the semiconductor substrate 100 at the location of the P-type high-voltage device region HVPMOS, and a high-voltage P-type well region 122 is further formed by doping in the semiconductor substrate 100 of the N-type high-voltage device region HVNMOS. The depths of the high-voltage N-type well region 121 and the high-voltage P-type well region 122 are both smaller than the deep N-type well region 111.

[0053] Step S2: forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer and a second polysilicon layer stacked in sequence from bottom to top on the semiconductor substrate at the location of the storage cell region.

[0054] This step S2 can be implemented by the following steps:

[0055] First, a plurality of first shallow trench isolation structures are formed in the semiconductor substrate of the memory cell region. The first shallow trench isolation structures extend in a longitudinal direction to divide the memory cell region into a plurality of columns of memory cells.

[0056] Then, a tunneling oxide layer is formed on the semiconductor substrate by a thermal oxidation process, wherein the material of the tunneling oxide layer is silicon oxide. Figure 3 , which shows a schematic diagram of the cross-sectional structure of the device after the tunneling oxide layer is formed. Figure 3 It can be seen from FIG. 1 that a plurality of first shallow trench isolation structures 310 are formed in the semiconductor substrate 100 , and a tunneling oxide layer 210 is formed on the semiconductor substrate 100 .

[0057] A first polysilicon layer is then deposited on the tunneling oxide layer, and the first polysilicon layer covering the first shallow trench isolation structure is removed by etching, so that the remaining first polysilicon layer in the storage cell area is the floating gate polysilicon of the flash memory, and the floating gate polysilicon extends longitudinally.

[0058] A second shallow trench isolation structure is formed in the peripheral circuit area. The second shallow trench isolation structure in the peripheral circuit area isolates the adjacent high-voltage device area and the low-voltage device area, and isolates the adjacent N-type high-voltage device area and the P-type high-voltage device area in the high-voltage device area, and isolates the adjacent N-type low-voltage device area and the P-type low-voltage device area in the low-voltage device area. The second shallow trench isolation structure in the peripheral circuit area extends downward from the upper surface of the first polysilicon layer into the semiconductor substrate.

[0059] A polysilicon interlayer dielectric layer is formed. The polysilicon interlayer dielectric layer may be made of an ONO material, i.e., silicon oxide, silicon nitride, and silicon oxide stacked sequentially from bottom to top. The polysilicon interlayer dielectric layer covers the surface of the first polysilicon layer according to the surface morphology of the first polysilicon layer.

[0060] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after the polysilicon inter-dielectric layer is formed. Figure 4 As can be seen in the figure, the floating gate polysilicon of the flash memory formed by the remaining first polysilicon layer 220 in the memory cell region 110 is separated by gaps 300. The floating gate polysilicon extends in the longitudinal direction, i.e., the Y direction. An inter-polysilicon dielectric layer 230 covers the surface of the first polysilicon layer 220 according to the surface morphology of the first polysilicon layer 220. A second shallow trench isolation structure 320 is formed in the peripheral circuit region 120. The second shallow trench isolation structure 320 in the peripheral circuit region 120 isolates the adjacent high-voltage device region from the low-voltage device region. It also isolates the adjacent N-type high-voltage device region HVNMOS and P-type high-voltage device region HVPMOS in the high-voltage device region, and isolates the adjacent N-type low-voltage device region LVNMOS and P-type low-voltage device region LVPMOS in the low-voltage device region. The second shallow trench isolation structure 320 in the peripheral circuit region 120 extends downward from the upper surface of the first polysilicon layer 220 into the semiconductor substrate 100.

[0061] A low-voltage N-type well region is formed in the semiconductor substrate at the location of the P-type low-voltage device region through an ion implantation process, and the low-voltage N-type well region extends downward from the upper surface of the semiconductor substrate at the location of the P-type low-voltage device region. A low-voltage P-type well region is formed in the semiconductor substrate at the location of the N-type low-voltage device region, and the low-voltage P-type well region extends downward from the upper surface of the semiconductor substrate at the location of the N-type low-voltage device region.

[0062] The inter-polysilicon dielectric layer and the first polysilicon layer at the location of the peripheral circuit area are removed by etching.

[0063] A second polysilicon layer is deposited to fill the gap between two adjacent columns of memory cells.

[0064] Step S3: etching the second polysilicon layer, the inter-polysilicon dielectric layer and the second polysilicon layer in sequence in the storage cell region to form flash memory cells, and forming a source region lead-out space in each of the flash memory cells.

[0065] After step S3 is completed and before step S4 is performed, impurities are implanted into the drain region of the flash memory cell through an ion implantation process to form a lightly doped drain region.

[0066] Step S4: etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon.

[0067] The logic device polysilicon includes N-type high-voltage device polysilicon located in the N-type high-voltage device area, P-type high-voltage device polysilicon located in the P-type high-voltage device area, N-type low-voltage device polysilicon located in the N-type low-voltage device area, and P-type low-voltage device polysilicon located in the P-type low-voltage device area.

[0068] After step S4 is completed and before step S5 is performed, impurities are implanted into the source and drain regions on both sides of the polysilicon of the high-voltage logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

[0069] Step S5: Based on the thickness of the inter-polysilicon dielectric layer, impurity ions with a dosage matching the thickness of the inter-polysilicon dielectric layer are implanted into the semiconductor substrate at the spatial position where the source region is drawn out, to form a flash memory cell source region.

[0070] Reference Figure 5 , which shows a schematic diagram of the cross-sectional structure of the device after step S5 is completed, Figure 5It can be seen that a source region lead-out space 400 is formed in the flash memory cell, impurities are injected into the drain region of the flash memory cell 110 to form a lightly doped drain 510, and the second polysilicon layer 240 is etched in the peripheral circuit region 120 to form logic device polysilicon. The logic device polysilicon includes an N-type high-voltage device polysilicon 610 located in the N-type high-voltage device region HVNMOS, a P-type high-voltage device polysilicon 320 located in the P-type high-voltage device region HVPMOS, an N-type low-voltage device polysilicon 630 located in the N-type low-voltage device region LVNMOS, and a P-type low-voltage device polysilicon 640 located in the P-type low-voltage device region LVPMOS.

[0071] A low-voltage N-type well region 123 is formed in the semiconductor substrate 100 at the location of the P-type low-voltage device region LVPMOS. The low-voltage N-type well region 123 extends downward from the upper surface of the semiconductor substrate 100 at the location of the P-type low-voltage device region LVPMOS. A low-voltage P-type well region 124 is formed in the semiconductor substrate 100 at the location of the N-type low-voltage device region LVNMOS. The low-voltage P-type well region 124 extends downward from the upper surface of the semiconductor substrate 100 at the location of the N-type low-voltage device region LVNMOS.

[0072] When performing step S5, the present application can be implemented by the following steps:

[0073] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, implanting impurity ions into the semiconductor substrate at a position where the source region is drawn out of the space with a first implantation dose to form a flash memory cell source region;

[0074] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region;

[0075] When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region;

[0076] The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

[0077] The first target thickness is 176A, and the first implant dose range is 2.8E14 atoms / cm 2 to 2.2E14 atoms / cm 2 ;

[0078] The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, comprises:

[0079] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 to 2.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0080] The first target thickness is 176A, the second target thickness is 174A, and the second implant dose range is 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 ;

[0081] The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises:

[0082] When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the thickness of the dielectric layer is 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0083] The second target thickness is 174A, and the third implant dose is in the range of 2.6E14 atoms / cm 2 to 3.2E14 atoms / cm 2 ;

[0084] The step of implanting impurity ions into the semiconductor substrate at the source region extraction space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises:

[0085] When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 to 3.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

[0086] The present application forms a flash memory cell source region by implanting impurity ions at a dose matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at a spatial position leading out of the source region, based on the thickness of the inter-polysilicon dielectric layer. The dose implanted in the source region is adjusted to match polysilicon dielectric layers of different thicknesses, that is, the implanted dose in the source region is increased when the polysilicon dielectric layer is relatively thin, thereby compensating for the data tailing problem caused by the thin polysilicon dielectric layer.

[0087] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for manufacturing an ETOX Nor flash memory, characterized in that: The manufacturing method of the ETOX Nor flash memory comprises the following steps: Providing a shaped semiconductor substrate, the semiconductor substrate comprising a storage cell region and a peripheral circuit region; forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region; Sequentially etching the second polysilicon layer, the inter-polysilicon dielectric layer, and the second polysilicon layer in the storage cell region to form flash memory cells, wherein a source region lead-out space is formed in each of the flash memory cells; Etching the second polysilicon layer in the peripheral circuit area to form logic device polysilicon; When the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, implanting impurity ions into the semiconductor substrate at a position where the source region is drawn out of the space with a first implantation dose to form a flash memory cell source region; When the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a second implantation dose to form a flash memory cell source region; When the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, implanting impurity ions into the semiconductor substrate at the source region lead-out space position with a third implantation dose to form a flash memory cell source region; The first target thickness is greater than the second target thickness, the first implantation dose is less than the second implantation dose, and the second implantation dose is less than the third implantation dose.

2. The method for manufacturing the ETOX Nor flash memory according to claim 1, wherein: The first target thickness is 176A, and the first implant dose range is 2.8E14 atoms / cm 2 to 2.2E14 atoms / cm 2 ; The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a first implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to a first target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 176A, the 2 to 2.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

3. The method for manufacturing the ETOX NOR flash memory according to claim 1, wherein: The first target thickness is 176A, the second target thickness is 174A, and the second implant dose range is 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 ; The step of implanting impurity ions into the semiconductor substrate at a position where the source region is led out of the semiconductor substrate at a second implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is greater than or equal to the second target thickness and less than the first target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is greater than or equal to 174A and less than 176A, the thickness of the dielectric layer is 2.4E14 atoms / cm 2 to 3.0E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

4. The method for manufacturing the ETOX Nor flash memory according to claim 1, wherein: The second target thickness is 174A, and the third implant dose is in the range of 2.6E14 atoms / cm 2 to 3.2E14 atoms / cm 2 ; The step of implanting impurity ions into the semiconductor substrate at the source region extraction space position with a third implantation dose to form a flash memory cell source region when the thickness of the inter-polysilicon dielectric layer is less than the second target thickness, comprises: When the thickness of the inter-polysilicon dielectric layer is less than 174A, the 2 to 3.2E14 atoms / cm 2 The impurity ions are implanted into the semiconductor substrate at the spatial position where the source region is led out of the source region to form a flash memory cell source region.

5. The method for manufacturing the ETOX Nor flash memory according to claim 1, wherein: The step of forming a tunneling oxide layer, a first polysilicon layer, an inter-polysilicon dielectric layer, and a second polysilicon layer stacked sequentially from bottom to top on the semiconductor substrate at the location of the storage cell region includes: forming a plurality of first shallow trench isolation structures in a semiconductor substrate of a memory cell region, wherein the first shallow trench isolation structures extend in a longitudinal direction to divide the memory cell region into a plurality of columns of memory cells; forming a tunneling oxide layer on the semiconductor substrate by a thermal oxidation process; Depositing a first polysilicon layer on the tunneling oxide layer, and etching away the first polysilicon layer covering the first shallow trench isolation structure, so that the remaining first polysilicon layer in the storage cell area is floating gate polysilicon of the flash memory, and the floating gate polysilicon extends in the longitudinal direction; forming a second shallow trench isolation structure in the peripheral circuit region; forming a dielectric layer between polysilicon layers; Etching and removing the inter-polysilicon dielectric layer and the first polysilicon layer at the position of the peripheral circuit area; A second polysilicon layer is formed by deposition, and the second polysilicon layer fills the gap between two adjacent columns of memory cells.

6. The method for manufacturing the ETOX Nor flash memory according to claim 1, wherein: The second polysilicon layer, the inter-polysilicon dielectric layer, and the second polysilicon layer are sequentially etched in the memory cell region to form a flash memory unit. After the step of forming a source region lead-out space in each of the flash memory units is completed, the following steps are further performed before the step of etching the second polysilicon layer in the peripheral circuit region to form polysilicon of a logic device is performed: Impurities are implanted into the drain region of the flash memory unit through an ion implantation process to form a lightly doped drain region.

7. The method for manufacturing the ETOX Nor flash memory according to claim 1, wherein: After the step of etching the second polysilicon layer in the peripheral circuit region to form polysilicon for the logic device is completed, the following steps are further performed before the step of forming the flash memory cell source region by implanting impurity ions at a dosage matching the thickness of the inter-polysilicon dielectric layer into the semiconductor substrate at a spatial position where the source region is drawn out, based on the thickness of the inter-polysilicon dielectric layer: Impurities are implanted into the source and drain regions on both sides of the high-voltage device of the logic device through an ion implantation process to form low-doped source and drain regions of the high-voltage device.

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