Semiconductor device including transistor

Abstract

The invention relates to a semiconductor device including a transistor. A semiconductor device includes: a substrate; the first electrode layer is arranged on the substrate; an interlayer insulating layer having an opening exposing the first electrode layer; an oxide semiconductor layer formed along a surface of the opening and connected to the first electrode layer; a gate insulating layer formed along a surface of the oxide semiconductor layer; a stacked structure including a first gate electrode layer, a first insulating layer, a second gate electrode layer, and a second insulating layer stacked in a vertical direction, and filling a remaining space of an opening in which the oxide semiconductor layer and the gate insulating layer are formed; and a second electrode layer disposed over the stacked structure and the oxide semiconductor layer and connected to the oxide semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0118970, filed on September 7, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to a semiconductor technology, and more particularly, to a semiconductor device including a transistor. Background Art

[0004] With the development of the electronics industry, electronic products are becoming increasingly miniaturized, high-performance and integrated, and at the same time, the operating speed of electronic products is required to be improved.

[0005] In order to meet these demands, it is necessary to develop a technology that can maintain and / or improve the characteristics of unit elements constituting electronic products (such as transistors) while reducing their size. In addition, a technology using an oxide semiconductor as a channel of a transistor is also under development. Summary of the invention

[0006] In an embodiment of the present disclosure, a semiconductor device may include: a substrate; a first electrode layer disposed on the substrate; an interlayer insulating layer having an opening exposing the first electrode layer; an oxide semiconductor layer formed along a surface of the opening and connected to the first electrode layer; a gate insulating layer formed along a surface of the oxide semiconductor layer; a stacked structure including a first gate electrode layer, a first insulating layer, a second gate electrode layer, and a second insulating layer stacked in a vertical direction and filling a remaining space of the opening formed with the oxide semiconductor layer and the gate insulating layer; and a second electrode layer disposed on the stacked structure and the oxide semiconductor layer and connected to the oxide semiconductor layer.

[0007] In another embodiment of the present disclosure, a semiconductor device may include: a substrate; a first electrode layer disposed on the substrate; a stacked structure disposed on the first electrode layer and including a first insulating layer, a first gate electrode layer, a second insulating layer and a second gate electrode layer stacked in a vertical direction; a gate insulating layer formed along the side walls of the first gate electrode layer and the side walls and upper surface of the second gate electrode layer; an oxide semiconductor layer formed along the surface of the stacked structure on which the gate insulating layer is formed and the surface of the first electrode layer; and a second electrode layer connected to the oxide semiconductor layer above the oxide semiconductor layer.

[0008] These and other features and advantages of the present invention will become apparent from the detailed description of the embodiments of the present disclosure and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1A to 5Bis a diagram illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure.

[0010] Figure 6 is a time-voltage graph illustrating the operation of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 7 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0012] FIG. 8A to FIG. 11B is a diagram illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure.

[0013] Fig.12 is a cross-sectional view illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] The drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may be enlarged to clearly illustrate certain features of the described embodiments. When presenting a specific example in a drawing or description of two or more layers in a multilayer structure, the relative positioning relationship of these layers or the order of the arrangement layers shown reflects the specific implementation of the described or shown example, and different relative positioning relationships or the order of the arrangement layers are possible. In addition, the example of the multilayer structure described or shown may not reflect all the layers present in the specific multilayer structure (for example, one or more additional layers may exist between the two shown layers). As a specific example, when the first layer in the multilayer structure described or shown is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be directly formed on the second layer or the substrate, but it may also represent a structure in which one or more other intermediate layers may exist between the first layer and the second layer or between the first layer and the substrate.

[0016] Figures 1A to 5B is a diagram illustrating a semiconductor device and a method of manufacturing the same according to an embodiment of the present disclosure. Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5A shows a plan view, Figure 1B , Figure 2B , Figure 3B , Figure 4B and Figure 5B Shown are Figure 1A , Figure 2A , Figure 3A , Figure 4A and Figure 5AA cross-sectional view taken along line AA'.

[0017] Next, the manufacturing method will be described first.

[0018] Reference Figure 1A and Figure 1B , a substrate 100 may be provided. The substrate 100 may include a semiconductor material such as silicon. In addition, a desired lower structure may be formed in the substrate 100.

[0019] Subsequently, a first electrode layer 110 and a first interlayer insulating layer 105 may be formed over the substrate 100 .

[0020] The first electrode layer 110 may correspond to one of the source electrode and the drain electrode connected to both ends of the transistor, respectively. For example, the first electrode layer 110 may correspond to the source electrode. The first electrode layer 110 may have an island shape in a plan view. In an embodiment, the first electrode layer 110 has a circular shape in a plan view, but the present disclosure is not limited thereto, and the planar shape of the first electrode layer 110 may be modified in a variety of ways. In a plan view, a plurality of first electrode layers 110 may be arranged in a matrix form along a first direction parallel to the line A-A' and a second direction intersecting the line A-A'. For reference, the first direction and the second direction may correspond to a horizontal direction substantially parallel to the upper surface of the substrate 100. The direction substantially perpendicular to the upper surface of the substrate 100 will be referred to as a vertical direction hereinafter. The first electrode layer 110 may include at least one of a plurality of conductive materials. For example, the first electrode layer 110 may include a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru) or molybdenum (Mo), and an oxide, nitride, or alloy containing at least one of these metals.

[0021] The first interlayer insulating layer 105 may be formed to fill spaces between the plurality of first electrode layers 110. The first interlayer insulating layer 105 may include at least one of various insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0022] Reference Figure 2A and Figure 2B , a second interlayer insulating layer 120 may be formed over the first electrode layer 110 and the first interlayer insulating layer 105. The second interlayer insulating layer 120 may have a line-shaped opening OP1 extending along the second direction and exposing a row of the first electrode layer 110 arranged along the second direction. The second interlayer insulating layer 120 may include at least one of a plurality of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0023] The second interlayer insulating layer 120 can be formed by depositing an insulating material on the first electrode layer 110 and the first interlayer insulating layer 105, and selectively etching the insulating material to expose the rows of the first electrode layer 110 arranged along the second direction. The etching of the insulating material can be performed by anisotropic etching (such as dry etching). In the first direction, the second interlayer insulating layer 120 may have a width that increases from top to bottom. In the first direction, the width of the opening OP1 of the second interlayer insulating layer 120 can be reduced from top to bottom. This may be because the upper portion of the second interlayer insulating layer 120 is exposed to the etching process for a longer time than the lower portion of the second interlayer insulating layer 120.

[0024] Reference Figure 3A and Figure 3B The oxide semiconductor layer 130 and the gate insulating layer 140 may be formed on Figure 2A and Figure 2B The oxide semiconductor layer 130 and the gate insulating layer 140 can be formed by Figure 2A and Figure 2B The oxide semiconductor material and the gate insulating material are conformally deposited on the process result of the process of forming the first electrode layer 110 and patterned into a line shape to overlap with the row of the first electrode layer 110 arranged in the first direction. As a result, in a plan view, the oxide semiconductor layer 130 and the gate insulating layer 140 may have a line shape extending in the first direction, and a plurality of lines including the oxide semiconductor layer 130 and the gate insulating layer 140 may be separated from each other in the second direction. In an embodiment, the gate insulating layer 140 is patterned together with the oxide semiconductor layer 130, but the present disclosure is not limited thereto. In another embodiment, the gate insulating layer 140 may not be patterned. That is, the gate insulating layer 140 may be formed on Figure 2A and Figure 2B The process results over the entire surface.

[0025] The oxide semiconductor layer 130 may be a portion used as a channel of a transistor, and may include at least one of a plurality of oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), zinc tin oxide (ZTO), indium gallium oxide (IGO), or InO2. The oxide semiconductor layer 130 may be deposited using a plurality of deposition methods such as ALD (atomic layer deposition). The oxide semiconductor layer 130 may be conformally formed along the upper surface and sidewalls of the second interlayer insulating layer 120, the upper surface of the first electrode layer 110, and the upper surface of the first interlayer insulating layer 105. Therefore, the lowermost surface of the oxide semiconductor layer 130, that is, the portion of the lower surface of the oxide semiconductor layer 130 located at the lowest height in the vertical direction, may be in direct contact with the upper surface of the first electrode layer 110, and therefore, the oxide semiconductor layer 130 may be electrically connected to the first electrode layer 110.

[0026] The gate insulating layer 140 may be a portion of a gate insulating layer used as a transistor, and may include at least one of a plurality of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material having a dielectric constant higher than silicon oxide. The gate insulating layer 140 may be deposited using at least one of a plurality of deposition methods such as ALD. The gate insulating layer 140 may be conformally formed along the upper surface of the oxide semiconductor layer 130.

[0027] The oxide semiconductor layer 130 and the gate insulating layer 140 may be formed to a thickness that does not completely fill the opening OP1 of the second interlayer insulating layer 120. Therefore, a space may remain within the opening OP1.

[0028] Reference Figure 4A and 4B A stack structure 150, 160, 170, and 180 including a first gate electrode layer 150, a first insulating layer 160, a second gate electrode layer 170, and a second insulating layer 180 may be formed in the remaining space of the opening OP1. Sidewalls and lower surfaces of the stack structures 150, 160, 170, and 180 may be surrounded by a gate insulating layer 140.

[0029] The first gate electrode layer 150 may be used to reduce the Schottky barrier formed by the contact between the first electrode layer 110 and the oxide semiconductor layer 130. On the other hand, the second gate electrode layer 170 may be used to control the on / off of the transistor. This will be described in more detail when describing the operation of the semiconductor device described later. The first insulating layer 160 may be used to physically and electrically separate the first gate electrode layer 150 and the second gate electrode layer 170. The second insulating layer 180 may be used to physically and electrically separate the second gate electrode layer 170 and the second electrode layer (refer to Figure 5A and Figure 5B190 in), which will be described later. Each of the first gate electrode layer 150 and the second gate electrode layer 170 may include at least one of a plurality of conductive materials, for example, a metal such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru) or molybdenum (Mo), and an oxide, nitride or alloy containing at least one of these metals. The first gate electrode layer 150 and the second gate electrode layer 170 may be formed of the same material or may be formed of different materials. Each of the first insulating layer 160 and the second insulating layer 180 may include at least one of a plurality of insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. The first insulating layer 160 and the second insulating layer 180 may be formed of the same material or may be formed of different materials.

[0030] Since the stacked structures 150, 160, 170, and 180 are buried in the opening OP1, the stacked structures 150, 160, 170, and 180 may have a line shape extending in the second direction similar to the opening OP1, and thus, the stacked structures 150, 160, 170, and 180 may overlap with the plurality of first electrode layers 110 arranged along the second direction. The stacked structures 150, 160, 170, and 180 may be formed in the following manner. First, a conductive material for forming the first gate electrode layer 150 may be deposited on Figure 3A and Figure 3BThe conductive material may be deposited on the process result in which the first gate electrode layer 150 is formed to sufficiently fill the remaining space of the opening OP1, and then the conductive material may be recessed using an etch-back method or the like until a desired thickness is reached to form the first gate electrode layer 150. Next, an insulating material for forming the first insulating layer 160 may be deposited on the process result in which the first gate electrode layer 150 is formed to sufficiently fill the remaining space of the opening OP1 in which the first gate electrode layer 150 is formed, and then the insulating material may be recessed until a desired thickness is reached to form the first insulating layer 160. Next, a conductive material for forming the second gate electrode layer 170 may be deposited on the process result in which the first gate electrode layer 150 and the first insulating layer 160 are formed to sufficiently fill the remaining space of the opening OP1 in which the first gate electrode layer 150 and the first insulating layer 160 are formed, and then the conductive material may be recessed until a desired thickness is reached to form the second gate electrode layer 170. Next, an insulating material for forming the second insulating layer 180 may be deposited over the process result in which the first gate electrode layer 150, the first insulating layer 160, and the second gate electrode layer 170 are formed to sufficiently fill the remaining space of the opening OP1 in which the first gate electrode layer 150, the first insulating layer 160, and the second gate electrode layer 170 are formed, and then a planarization process such as CMP (chemical mechanical polishing) may be performed so that the oxide semiconductor layer 130 is exposed to form the second insulating layer 180. As a result, the upper surface of the second insulating layer 180 may be located at substantially the same height as the uppermost surface of the oxide semiconductor layer 130 and form a flat surface with the uppermost surface of the oxide semiconductor layer 130. In this process, the gate insulating layer 140 located above the uppermost surface of the oxide semiconductor layer 130 may be removed.

[0031] In an embodiment, when the second insulating layer 180 is formed, the oxide semiconductor layer 130 is formed on the upper surface of the second interlayer insulating layer 120 by performing a planarization process until the upper surface of the oxide semiconductor layer 130 is exposed, but the present disclosure is not limited thereto. In another embodiment, when the second insulating layer 180 is formed, a planarization process may be performed to expose the second interlayer insulating layer 120. For example, the planarization process may be performed until the line indicated by the dotted line ①. In this case, the uppermost surface of the oxide semiconductor layer 130 may be located at substantially the same height as the upper surfaces of the second insulating layer 180 and the second interlayer insulating layer 120 to form a flat surface. As long as the uppermost surface of the oxide semiconductor layer 130 is aligned with the second electrode layer (reference layer 120) to be described later, the uppermost surface of the oxide semiconductor layer 130 may be located at substantially the same height as the upper surfaces of the second insulating layer 180 and the second interlayer insulating layer 120 to form a flat surface. Figure 5A and Figure 5B 190) in contact and electrical connection, the height of the uppermost surface of the oxide semiconductor layer 130 can be modified in various ways.

[0032] Reference Figure 5A and Figure 5B, the second electrode layer 190 may be formed on Figure 4A and Figure 4B on the process results.

[0033] The second electrode layer 190 may correspond to one of the source electrode and the drain electrode connected to both ends of the transistor, respectively. For example, the second electrode layer 190 may correspond to the drain electrode. In a plan view, the second electrode layer 190 may have a linear shape extending in a first direction and may overlap with a plurality of first electrode layers 110 arranged in the first direction. A plurality of second electrode layers 190 may be arranged spaced apart from each other in the second direction. The second electrode layer 190 may include at least one of a plurality of conductive materials. For example, the second electrode layer 190 may include a metal (such as platinum (Pt), tungsten (W), aluminum (Al), copper (Cu), tantalum (Ta), titanium (Ti), ruthenium (Ru) or molybdenum (Mo)), and an oxide, nitride or alloy containing at least one of these metals.

[0034] The second electrode layer 190 may be electrically connected to the oxide semiconductor layer 130 by directly contacting the uppermost surface of the oxide semiconductor layer 130 .

[0035] As a result, semiconductor devices including transistors can be manufactured, such as Figure 5A and Figure 5B shown.

[0036] Refer again Figure 5A and Figure 5B , the semiconductor device may include: a substrate 100; a first electrode layer 110 disposed on the substrate 100; a second interlayer insulating layer 120, which is disposed on the first electrode layer 110 and has an opening OP1 exposing the first electrode layer 110; an oxide semiconductor layer 130, which is formed along the surface of the opening OP1 and is electrically connected to the first electrode layer 110; a gate insulating layer 140, which is formed along the surface of the oxide semiconductor layer 130; a stacked structure 150, 160, 170 and 180, which fills the remaining space of the opening OP1 in which the gate insulating layer 140 and the oxide semiconductor layer 130 are formed, and includes a first gate electrode layer 150, a first insulating layer 160, a second gate electrode layer 170 and a second insulating layer 180 stacked from bottom to top; and a second electrode layer 190, which is disposed on the oxide semiconductor layer 130 and the stacked structure 150, 160, 170 and 180 and is electrically connected to the oxide semiconductor layer 130.

[0037] The first electrode layer 110 may have an island shape, and a plurality of first electrode layers 110 may be arranged along the first direction and the second direction. The second electrode layer 190 may have a line shape extending along the first direction to overlap with the plurality of first electrode layers 110 arranged in the first direction. The plurality of second electrode layers 190 may be arranged spaced apart from each other in the second direction. The first electrode layer 110 and the second electrode layer 190 may correspond to a source electrode and a drain electrode of a transistor, respectively.

[0038] The stacked structures 150, 160, 170, and 180 may have a line shape extending in the second direction to overlap with the plurality of first electrode layers 110 arranged in the second direction. The second gate electrode layer 170 may be used to control the on / off of the transistor. That is, when a voltage equal to or higher than the threshold voltage of the transistor is applied to the second gate electrode layer 170, current flow may occur between the first electrode layer 110 and the second electrode layer 190 through the oxide semiconductor layer 130 (see Figure 5B ), that is, through the oxide semiconductor layer 130 formed along the sidewalls of the stacked structures 150, 160, 170 and 180, thereby turning on the transistor. On the other hand, when the voltage applied to the second gate electrode layer 170 is reduced to below the threshold voltage or is removed, the current flow through the oxide semiconductor layer 130 can disappear and the transistor can be turned off. Therefore, the oxide semiconductor layer 130 between the first electrode layer 110 and the second electrode layer 190 can be used as a channel of the transistor. The first gate electrode layer 150 can be used to reduce the Schottky barrier formed by the contact between the oxide semiconductor layer 130 and the first electrode layer 110. When a predetermined voltage is applied to the first gate electrode layer 150 and conductive carriers accumulate in the region of the oxide semiconductor layer 130 adjacent to the first gate electrode layer 150, the Schottky barrier between the oxide semiconductor layer 130 and the first electrode layer 110 can be reduced, thereby reducing the contact resistance between the oxide semiconductor layer 130 and the first electrode layer 110. As a result, the operating characteristics of the transistor can be improved. If the conductive carriers are electrons, the predetermined voltage may be a positive voltage. The accumulation region of the conductive carriers is defined by Figure 5B The reference symbol P1 in FIG. 1 represents a voltage applied to the first gate electrode layer 150 and a voltage applied to the second gate electrode layer 170 may be independent of each other.

[0039] Since components of the semiconductor device have been described in detail in the manufacturing method, a detailed description thereof will be omitted here.

[0040] According to the semiconductor device and the method for manufacturing the same, the following effects can be obtained.

[0041] First, since an oxide semiconductor is used as a channel of a transistor, various advantages resulting therefrom such as reduction in off-state current can be ensured.

[0042] In addition, since the oxide semiconductor channel extends in the vertical direction, problems due to a short channel effect, a floating body effect, or the like may not occur.

[0043] In addition, by using an additional gate electrode in addition to the gate electrode that controls the on / off of the transistor, the Schottky barrier that inevitably occurs between the source electrode and the oxide semiconductor channel can be reduced. That is, an ohmic contact between the source electrode and the oxide semiconductor channel can be formed. Therefore, the operating characteristics of the transistor can be improved.

[0044] In addition, since the oxide semiconductor channel is simply formed by a deposition method such as ALD without an etching process, attack on the oxide semiconductor channel can be reduced, thereby reducing degradation of characteristics of the oxide semiconductor channel.

[0045] In addition, since the gate insulating layer covering the oxide semiconductor channel is formed after the oxide semiconductor channel is formed, the phenomenon of oxygen escaping from the oxide semiconductor channel and the increase of oxygen vacancies in the oxide semiconductor channel and the problems caused thereby can be solved.

[0046] Figure 6 is a time-voltage graph illustrating the operation of a semiconductor device according to an embodiment of the present disclosure.

[0047] Reference Figure 6 as well as Figure 5A and Figure 5B , a voltage applied to the first gate electrode layer 150 is represented as a first voltage V1, and a voltage applied to the second gate electrode layer 170 is represented as a second voltage V2.

[0048] The second voltage V2 may be applied only in the on period Ton of the transistor, and may not be applied in the remaining periods. The second voltage V2 may have a magnitude greater than a threshold voltage of the transistor.

[0049] On the other hand, since the first voltage V1 is used to form an ohmic contact between the oxide semiconductor layer 130 and the first electrode layer 110, the first voltage V1 can be applied not only in the on period Ton of the transistor but also in the remaining periods (such as the off period of the transistor). That is, the first voltage V1 can be always applied regardless of the operation of the transistor.

[0050] In an embodiment, the amplitude of the first voltage V1 is shown to be smaller than the amplitude of the second voltage V2, but the present disclosure is not limited thereto. The amplitude of the first voltage V1 and the amplitude of the second voltage V2 can be adjusted independently of each other. Therefore, in another embodiment, the amplitude of the first voltage V1 and the amplitude of the second voltage V2 can be the same as each other, or the amplitude of the second voltage V2 can be smaller than the amplitude of the first voltage V1.

[0051] Figure 5A and Figure 5B The semiconductor device may further include a storage element connected to one end of the transistor. For example, the storage element may be connected to the source electrode. The storage element may store different data according to the voltage or current applied by the transistor. In an embodiment, for example, the storage element may include a capacitor including two electrodes and a dielectric material disposed between the two electrodes. Or, as another example, the storage element may include a variable resistance layer that stores different data by switching between different resistance states. The variable resistance layer may include at least one of a variety of materials used for resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), or magnetoresistive random access memory (MRAM), for example, a metal oxide (such as a transition metal oxide or a perovskite-based material), a phase change material (such as a chalcogenide-based material), a ferroelectric material, or a ferromagnetic material, and may have a single-layer structure or a multi-layer structure. Due to Figure 5A and Figure 5B The first electrode layer 110 corresponding to the source electrode in the semiconductor device is located at the bottom of the transistor component, so the storage element can be arranged under the first electrode layer 110. This will refer to Figure 7 Give a description.

[0052] Figure 7 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The description will focus on Figure 5A and Figure 5B The differences in semiconductor devices.

[0053] Reference Figure 7 ,Apart from Figure 5A and Figure 5B In addition to the components of the semiconductor device, the semiconductor device may further include capacitors 101 , 102 , and 103 , and the capacitors 101 , 102 , and 103 include a first capacitor electrode layer 101 , a second capacitor electrode layer 103 , and a capacitor insulating layer 102 .

[0054] The capacitors 101, 102, and 103 may be located between the substrate 100 and the first electrode layer 110 in the vertical direction. The first capacitor electrode layer 101 may have a columnar shape overlapping each of the plurality of first electrode layers 110, and may contact the lower surface of the first electrode layer 110 to be electrically connected to the first electrode layer 110. The second capacitor electrode layer 103 may have a shape surrounding the sidewalls and lower surfaces of the plurality of first capacitor electrode layers 101. The capacitor insulating layer 102 may be interposed between the first capacitor electrode layer 101 and the second capacitor electrode layer 103. In an embodiment, for example, the capacitor insulating layer 102 may be conformally formed along the sidewalls and lower surface of the first capacitor electrode layer 101. And, the capacitor insulating layer 102 may be conformally formed along the upper surface of the second capacitor electrode layer 103.

[0055] Capacitors 101, 102, and 103 may be formed by the following method. First, a conductive material for forming second capacitor electrode layer 103 may be deposited on substrate 100, and the conductive material may be selectively etched to form second capacitor electrode layer 103, which provides a space in which capacitor insulating layer 102 and first capacitor electrode layer 101 are to be buried. Subsequently, capacitor insulating layer 102 may be conformally formed along a lower contour over second capacitor electrode layer 103, and then the remaining portion of the space in which capacitor insulating layer 102 is formed may be filled with a conductive material to form first capacitor electrode layer 101. Subsequent processes after forming capacitors 101, 102, and 103 may be similar to those described above. Figures 1A to 5B The process described in is essentially the same.

[0056] In general, a capacitor can be formed using a high temperature process. Therefore, if the capacitor is formed after the oxide semiconductor channel is formed, the oxide semiconductor channel may be exposed to the high temperature process and its characteristics may deteriorate. However, in the present example, since the capacitors 101, 102, and 103 are formed before the oxide semiconductor layer 130 is formed, the exposure of the oxide semiconductor layer 130 to the high temperature process can be prevented and / or reduced. As a result, it is possible to help maintain the characteristics of the oxide semiconductor layer 130.

[0057] In this example, capacitors 101, 102, and 103 formed in the shape shown in the figure have been described, but the present disclosure is not limited thereto. As long as the capacitor is formed under the first electrode layer 110 and one of the two electrodes of the capacitor is connected to the first electrode layer 110, the shape of the capacitor can be modified in a variety of ways. Alternatively, another storage element such as a variable resistance layer can be formed under the first electrode layer 110 to replace the capacitors 101, 102, and 103. One end of the variable resistance layer can be electrically connected to the first electrode layer 110, and the other end of the variable resistance layer can be electrically connected to another conductive line.

[0058] FIG. 8A to FIG. 11B is a diagram illustrating a semiconductor device and a method of manufacturing the same according to another embodiment of the present disclosure. Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A is a plan view, and Figure 8B , Fig. 9B , Fig. 10B and Fig. 11B Along Fig. 8A , Fig. 9A , Fig. 10A and Fig.11A A cross-sectional view taken along line AA'.

[0059] Next, the manufacturing method will be described first.

[0060] Reference Fig. 8A and Figure 8B , a first electrode layer 210 may be formed on the substrate 200 .

[0061] The first electrode layer 210 may correspond to one of a source electrode and a drain electrode respectively connected to both ends of the transistor. For example, the first electrode layer 210 may correspond to a drain electrode. In a plan view, the first electrode layer 210 may have a line shape extending in a first direction, and a plurality of first electrode layers 210 may be arranged spaced apart from each other in a second direction. The spaces between the plurality of first electrode layers 210 may be filled with a first interlayer insulating layer.

[0062] Reference Fig. 9A and 9B A stacked structure 220 , 230 , 240 , 250 and 255 may be formed on the first electrode layer 210 and the first interlayer insulating layer, the stacked structure including a first insulating layer 220 , a first gate electrode layer 230 , a second insulating layer 240 , a second gate electrode layer 250 and a first gate insulating layer 255 .

[0063] The first gate electrode layer 230 can be used to control the on / off of the transistor. The second gate electrode layer 250 can be used to reduce the Schottky barrier between the second electrode layer and the oxide semiconductor layer, which will be described later. The first insulating layer 220 can be used to physically and electrically separate the first gate electrode layer 230 and the first electrode layer 210 from each other. The second insulating layer 240 can be used to physically and electrically separate the first gate electrode layer 230 and the second gate electrode layer 250 from each other. The first gate insulating layer 255 can be used as a gate insulating layer together with the second gate insulating layer, which will be described later.

[0064] The stacked structures 220, 230, 240, 250 and 255 may have a linear shape extending in the second direction. A plurality of stacked structures 220, 230, 240, 250 and 255 may be formed to be spaced apart from each other in the first direction. The stacked structures 220, 230, 240, 250 and 255 may be formed by sequentially depositing an insulating material for forming the first insulating layer 220, a conductive material for forming the first gate electrode layer 230, an insulating material for forming the second insulating layer 240, a conductive material for forming the second gate electrode layer 250 and an insulating material for forming the first gate insulating layer 255 on the first electrode layer 210 and the first interlayer insulating layer, and selectively etching them. In the first direction, the stacked structures 220, 230, 240, 250 and 255 may have a width that increases from top to bottom. This may be because the upper portions of the stack structures 220 , 230 , 240 , 250 , and 255 are exposed to the etching process for a longer time than the lower portions of the stack structures 220 , 230 , 240 , 250 , and 255 .

[0065] Reference Fig. 10A and Fig. 10B , a second gate insulating layer 260 may be formed on sidewalls of the stacked structures 220 , 230 , 240 , 250 , and 255 .

[0066] The second gate insulating layer 264 may be deposited on the substrate by using a method such as physical vapor deposition (PVD) or ALD. Fig. 9A and Fig. 9B The gate insulating material is deposited on the entire surface of the process result and a blanket etching process is performed. During the blanket etching process, the gate insulating material on the first gate insulating layer 255 and on the first electrode layer 210 can be removed to form a second gate insulating layer 260 located on the sidewalls of the stacked structures 220, 230, 240, 250 and 255.

[0067] Subsequently, the oxide semiconductor layer 270 may be conformally formed along the lower contour on the process result in which the second gate insulating layer 260 is formed, and may be patterned into a line shape to overlap the first electrode layer 210. As a result, in a plan view, the oxide semiconductor layer 270 may have a line shape extending in the first direction, and a plurality of oxide semiconductor layers 270 may be separated from each other in the second direction. The first gate electrode layer 230 and the oxide semiconductor layer 270 may be separated from each other by the second gate insulating layer 260. The second gate electrode layer 250 and the oxide semiconductor layer 270 may be separated from each other by the first gate insulating layer 255 and the second gate insulating layer 260. The lowermost surface of the oxide semiconductor layer 270 may contact the first electrode layer 210 and may be electrically connected to the first electrode layer 210. The oxide semiconductor layer 270 may be formed to a thickness that does not completely fill the space between the stacked structures 220, 230, 240, 250, and 255.

[0068] Reference Fig.11A and Fig. 11B , a second interlayer insulating layer 280 may be formed to fill remaining spaces between the stack structures 220 , 230 , 240 , 250 , and 255 .

[0069] The second interlayer insulating layer 280 may be formed by Fig. 10A and Fig. 10B The insulating material is deposited on the process result to sufficiently fill the remaining space between the stacked structures 220, 230, 240, 250 and 255, and a planarization process is performed to expose the oxide semiconductor layer 270. Therefore, the uppermost surface of the oxide semiconductor layer 270 and the upper surface of the second interlayer insulating layer 280 may be located at substantially the same height and form a flat surface.

[0070] Subsequently, a second electrode layer 290 may be formed over the oxide semiconductor layer 270. The second electrode layer 290 may have an island shape and may have a lower surface in contact with the oxide semiconductor layer 270 to be electrically connected to the oxide semiconductor layer 270. The second electrode layer 290 may correspond to one of a source electrode and a drain electrode respectively connected to both ends of the transistor. For example, the second electrode layer 290 may correspond to a source electrode. In a plan view, a plurality of second electrode layers 290 may be arranged in a matrix along a first direction and a second direction. A plurality of second electrode layers 290 arranged along the first direction may overlap with the first electrode layer 210 extending along the first direction, and a plurality of second electrode layers 290 arranged along the second direction may overlap with stacked structures 220, 230, 240, 250, and 255 extending along the second direction.

[0071] As a result, semiconductor devices including transistors can be manufactured, such as Fig.11A and Fig. 11B shown.

[0072] Refer again Fig.11A and Fig. 11B , the semiconductor device may include: a substrate 200; a first electrode layer 210 arranged on the substrate 200; a stacked structure 220, 230, 240, 250 and 255, which is arranged on the first electrode layer 210 and includes a first insulating layer 220, a first gate electrode layer 230, a second insulating layer 240, a second gate electrode layer 250 and a first gate insulating layer 255 stacked from bottom to top; a second gate insulating layer 260, which is formed along the sidewalls of the stacked structures 220, 230, 240, 250 and 255; an oxide semiconductor layer 270, which is formed along the surface of the stacked structures 220, 230, 240, 250 and 255 on which the gate insulating layer 260 is formed and the surface of the first electrode layer 210 to be connected to the first electrode layer 210; and a second electrode layer 290, which is formed on the oxide semiconductor layer 270 to be connected to the oxide semiconductor layer 270.

[0073] The second electrode layer 290 may have an island shape, and a plurality of second electrode layers 290 may be arranged along the first direction and the second direction. On the other hand, the first electrode layer 210 may have a line shape extending along the first direction to overlap with a plurality of second electrode layers 290 arranged in the first direction. A plurality of first electrode layers 210 may be arranged spaced apart from each other in the second direction. The first electrode layer 210 and the second electrode layer 290 may correspond to a drain electrode and a source electrode of a transistor, respectively.

[0074] The stacked structures 220, 230, 240, 250, and 255 may have a line shape extending in the second direction to overlap with the plurality of second electrode layers 290 arranged in the second direction. The first gate electrode layer 230 may be used to control the on / off of the transistor. That is, when a voltage equal to or higher than the threshold voltage of the transistor is applied to the first gate electrode layer 230, current flows (see Fig. 11BThe dashed arrow in the figure) may occur between the first electrode layer 210 and the second electrode layer 290 through the oxide semiconductor layer 270, thereby turning on the transistor. On the other hand, when the voltage applied to the first gate electrode layer 230 is reduced to below the threshold voltage or is removed, the current flow through the oxide semiconductor layer 270 may disappear and the transistor may be turned off. The second gate electrode layer 250 may be used to reduce the Schottky barrier formed by the contact between the oxide semiconductor layer 270 and the second electrode layer 290. When a predetermined voltage such as a positive voltage is applied to the second gate electrode layer 250 and conductive carriers such as electrons accumulate in a region of the oxide semiconductor layer 270 adjacent to the second gate electrode layer 250, the Schottky barrier between the oxide semiconductor layer 270 and the second electrode layer 290 may be reduced, thereby reducing the contact resistance between the oxide semiconductor layer 270 and the second electrode layer 290. As a result, the operating characteristics of the transistor may be improved. The accumulation region of the conductive carriers is formed by Fig. 11B Indicated by the reference symbol P2.

[0075] Since components of the semiconductor device have been described in detail in the manufacturing method, a detailed description thereof will be omitted here.

[0076] Fig.11A and Fig. 11B The semiconductor device may further include a storage element connected to one end of the transistor. For example, the storage element may be connected to the source electrode. The storage element may include a capacitor, a variable resistance layer, etc. Fig.11A and Fig. 11B The second electrode layer 290 corresponding to the source electrode in the semiconductor device is located on the top of the transistor component, so the storage element can be set on the second electrode layer 290. This will refer to Fig.12 Give a description.

[0077] Fig.12 is a cross-sectional view showing a semiconductor device and a method for manufacturing the same according to another embodiment of the present disclosure. The description will focus on Fig.11A and Fig. 11B The differences in semiconductor devices.

[0078] Reference Fig.12 ,Apart from Fig.11A and 11B In addition to the components of the semiconductor device, the semiconductor device may also include a third interlayer insulating layer 292 and capacitors 294, 296 and 298, the third interlayer insulating layer 292 fills the space between the second electrode layers 290, and the capacitors 294, 296 and 298 include a first capacitor electrode layer 294, a second capacitor electrode layer 298 and a capacitor insulating layer 296.

[0079] Capacitors 294, 296, and 298 may be disposed above the second electrode layer 290 in a vertical direction. In an embodiment, the first capacitor electrode layer 294 may have a columnar shape overlapping each of the plurality of second electrode layers 290, and may contact the upper surface of the second electrode layer 290 to be electrically connected to the second electrode layer 290. The second capacitor electrode layer 298 may have a shape surrounding the sidewalls and upper surfaces of the plurality of first capacitor electrode layers 294. The capacitor insulating layer 296 may be interposed between the first capacitor electrode layer 294 and the second capacitor electrode layer 298. In an embodiment, for example, the capacitor insulating layer 296 may be conformally formed along the sidewalls and upper surface of the first capacitor electrode layer 294.

[0080] Capacitors 294, 296, and 298 may be formed by the following method. First, a conductive material for forming first capacitor electrode layer 294 may be deposited on second electrode layer 290 and third interlayer insulating layer 292, and the conductive material may be selectively etched to form columnar first capacitor electrode layer 294. Then, capacitor insulating layer 296 may be conformally formed along the entire surface of the process result, and a conductive material may be deposited on capacitor insulating layer 296 to a thickness sufficient to cover first capacitor electrode layer 294 to form second capacitor electrode layer 298.

[0081] The case where capacitors 294, 296, and 298 are formed as shown in the figure has been described, but the present disclosure is not limited thereto. As long as the capacitor is formed on the second electrode layer 290 and one of the two electrodes of the capacitor is connected to the second electrode layer 290, the shape of the capacitor can be modified in a variety of ways. Alternatively, another storage element such as a variable resistance layer can be formed on the second electrode layer 290 to replace capacitors 294, 296, and 298. One end of the variable resistance layer can be electrically connected to the second electrode layer 290, and the other end of the variable resistance layer can be electrically connected to another conductive line.

[0082] According to the above-described embodiments of the present disclosure, it is possible to provide a semiconductor device which improves its operating characteristics and facilitates the manufacturing process.

[0083] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the present disclosure. In addition, these embodiments may be combined to form further embodiments.

Claims

1. A semiconductor device, comprising: substrate; A first electrode layer disposed on the substrate; an interlayer insulating layer having an opening exposing the first electrode layer; an oxide semiconductor layer formed along a surface of the opening and connected to the first electrode layer; a gate insulating layer formed along a surface of the oxide semiconductor layer; a stacked structure comprising a first gate electrode layer, a first insulating layer, a second gate electrode layer, and a second insulating layer stacked in a vertical direction and filling a remaining space of the opening in which the oxide semiconductor layer and the gate insulating layer are formed; as well as A second electrode layer is disposed on the stacked structure and the oxide semiconductor layer and connected to the oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein The first electrode layer and the oxide semiconductor layer are in direct contact with each other to form a Schottky barrier, and Wherein, the first gate electrode layer is used to reduce the Schottky barrier.

3. The semiconductor device according to claim 2, wherein: Conductive carriers are accumulated in a region of the oxide semiconductor layer adjacent to the first gate electrode layer according to a first voltage applied to the first gate electrode layer.

4. The semiconductor device according to claim 3, wherein: The first voltage is applied to the first gate electrode layer during an on period and an off period of the transistor.

5. The semiconductor device according to claim 1, wherein According to a second voltage applied to the second gate electrode layer, a current flows through the oxide semiconductor layer and is generated between the first electrode layer and the second electrode layer.

6. The semiconductor device according to claim 5, wherein: The second voltage is applied to the second gate electrode layer in an on period of the transistor.

7. The semiconductor device according to claim 1, wherein The first electrode layer has an island shape, The plurality of first electrode layers are arranged along a second direction and a first direction parallel to the upper surface of the substrate, and the second direction is parallel to the upper surface of the substrate and intersects with the first direction. wherein the stacked structure extends along the second direction to overlap with the plurality of first electrode layers arranged along the second direction, and The second electrode layer extends along the first direction to overlap with the plurality of first electrode layers arranged along the first direction.

8. The semiconductor device according to claim 1, wherein The stacked structure has a width that decreases from top to bottom.

9. The semiconductor device according to claim 1, further comprising: A storage element is between the first electrode layer and the substrate and is electrically connected to the first electrode layer.

10. A semiconductor device comprising: substrate; A first electrode layer disposed on the substrate; a stacked structure, which is disposed on the first electrode layer and includes a first insulating layer, a first gate electrode layer, a second insulating layer and a second gate electrode layer stacked in a vertical direction; a gate insulating layer formed along the sidewalls of the first gate electrode layer and the sidewalls and upper surface of the second gate electrode layer; an oxide semiconductor layer formed along a surface of the stacked structure on which the gate insulating layer is formed and a surface of the first electrode layer; as well as A second electrode layer is on the oxide semiconductor layer and connected to the oxide semiconductor layer.

11. The semiconductor device according to claim 10, wherein: The first electrode layer and the oxide semiconductor layer are in direct contact with each other to form a Schottky barrier, and Wherein, the second gate electrode layer is used to reduce the Schottky barrier.

12. The semiconductor device according to claim 11, wherein Conductive carriers are accumulated in a region of the oxide semiconductor layer adjacent to the second gate electrode layer according to a second voltage applied to the second gate electrode layer.

13. The semiconductor device according to claim 12, wherein: The second voltage is applied to the second gate electrode layer during an on period and an off period of the transistor.

14. The semiconductor device according to claim 10, wherein: According to a first voltage applied to the first gate electrode layer, a current flows through the oxide semiconductor layer and is generated between the first electrode layer and the second electrode layer.

15. The semiconductor device according to claim 14, wherein: The first voltage is applied to the first gate electrode layer in an on period of the transistor.

16. The semiconductor device according to claim 10, wherein: The second electrode layer has an island shape, The plurality of second electrode layers are arranged along a second direction and a first direction parallel to the upper surface of the substrate, the second direction is parallel to the upper surface of the substrate and intersects with the first direction, wherein the stacked structure extends along the second direction to overlap with the plurality of second electrode layers arranged along the second direction, and The first electrode layer extends along the first direction to overlap with the plurality of second electrode layers arranged along the first direction.

17. The semiconductor device according to claim 10, wherein: The stacked structure has a width that increases from top to bottom.

18. The semiconductor device according to claim 10, further comprising: A storage element is on the second electrode layer and electrically connected to the second electrode layer.

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