A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, the substrate has a first surface and a second surface, the substrate comprises an IGBT region and a diode region, and a drift region of a first conduction type is formed in the substrate; forming a diode anode of a second conduction type in the diode region; forming an oxide layer covering the diode anode on the first surface; forming a carrier injection blocking layer in the IGBT region; forming an active gate in the IGBT region; forming a body region of the second conduction type on the carrier injection blocking layer; and forming an emitter region of the first conduction type in the IGBT region. By forming the oxide layer on the diode anode and not forming the carrier injection blocking layer, the oxide layer is removed when a contact hole is formed, so that there is no carrier injection blocking layer between a metal layer and the diode anode, the hole extraction speed during reverse recovery is accelerated, the reverse recovery loss is reduced, the number of masks is saved, and the production cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In order to improve the power density of an Insulated Gate Bipolar Transistor (IGBT), the IGBT can be integrated with a diode (for example, a Fast Recovery Diode, FRD) in a chip, that is, an RCIGBT is formed.

[0003] In the related art, for an RCIGBT integrated with an FRD and an IGBT, there is a problem of poor reverse recovery performance of the FRD and the IGBT. Since the optimization directions of the IGBT and the FRD are opposite, if the lifetime of the FRD is controlled to reduce the turn-on loss and the reverse recovery loss, the turn-on loss of the IGBT is large, and if the anode concentration of the FRD is optimized, more masks are needed, resulting in an increase in cost. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the specific embodiment section. The summary section of the present application does not mean to attempt to limit the key features and necessary technical features of the claimed technical solution, nor to attempt to determine the protection scope of the claimed technical solution.

[0005] In view of the existing problems, the present application provides a manufacturing method of a semiconductor device, which comprises:

[0006] A substrate is provided, the substrate has opposite first and second surfaces, the substrate includes an IGBT region and a diode region, the diode region is located on a first side of the IGBT region, and a drift region of a first conductivity type is formed in the substrate;

[0007] A diode anode of a second conductivity type extending from the first surface into the drift region is formed in the diode region;

[0008] An oxide layer covering at least the diode anode is formed on the first surface;

[0009] A carrier injection blocking layer is formed on a side of the drift region in the IGBT region close to the first surface;

[0010] An active gate extending from the first surface into the drift region and away from the second surface is formed in the IGBT region;

[0011] forming a body region of a second conductivity type on a side of the carrier injection barrier layer proximate the first surface such that at least a portion of the body region is on the carrier injection barrier layer, wherein the body region is also on both sides of the active gate;

[0012] forming an emitter region of a first conductivity type in the IGBT region extending from the first surface into the body region, the emitter region being on both sides of the active gate.

[0013] In one embodiment, the substrate further comprises a termination region on a second side of the IGBT region, the manufacturing method further comprising forming at least one well region of the second conductivity type in the termination region at the same time as forming the diode anode of the second conductivity type.

[0014] In one embodiment, the termination region is formed with a field oxide layer, the field oxide layer of the termination region being formed at the same time as the oxide layer covering the diode anode.

[0015] In one embodiment, the manufacturing method further comprises:

[0016] forming an insulating layer covering the first surface and the oxide layer, and forming a contact hole and an opening exposing at least a portion of a surface of the diode anode in the insulating layer, the contact hole penetrating through the emitter region and exposing at least a portion of the body region;

[0017] forming a conductive connection structure electrically connected with the emitter region and the diode anode, the conductive connection structure covering the insulating layer and filling the contact hole and the opening.

[0018] In one embodiment, the diode anode has a doping concentration lower than a doping concentration of the body region.

[0019] In one embodiment, the manufacturing method further comprises:

[0020] forming a collector region of the second conductivity type in the IGBT region and the termination region extending from the second surface into the substrate;

[0021] forming an electrode layer of the first conductivity type in the diode region extending from the second surface into the substrate.

[0022] Another aspect of the present application provides a semiconductor device, comprising:

[0023] a substrate having opposite first and second surfaces, the substrate comprising an IGBT region and a diode region on a first side of the IGBT region, a drift region of a first conductivity type being formed in the substrate;

[0024] a diode anode of the second conductivity type in the diode region and extending from the first surface into the drift region and in direct contact with the drift region;

[0025] a carrier injection barrier layer on the drift region of the IGBT region near the first surface;

[0026] an active gate in the IGBT region, the active gate extending from the first surface into the drift region and away from the second surface;

[0027] a body region of the second conductivity type at least partially on the carrier injection barrier layer and on both sides of the active gate;

[0028] an emitter region of the first conductivity type extending from the first surface into the body region.

[0029] In one embodiment, the semiconductor device further comprises a termination region on the second side of the IGBT region, the termination region comprising at least one well region of the second conductivity type, the well region and the diode anode having the same doping concentration.

[0030] In one embodiment, the semiconductor device further comprises:

[0031] an insulating layer covering part of the first surface and having a contact hole extending through the emitter region and exposing at least part of the body region and an opening exposing at least part of the surface of the diode anode formed therein;

[0032] a conductive connection structure electrically connected with the emitter region and the diode anode, the conductive connection structure covering the insulating layer and filling the contact hole and the opening.

[0033] In one embodiment, the semiconductor device further comprises:

[0034] a collector region of the second conductivity type in the IGBT region and the termination region and extending from the second surface into the substrate;

[0035] an electrode layer of the first conductivity type in the diode region and extending from the second surface into the substrate.

[0036] The semiconductor device and the manufacturing method thereof according to the embodiments of the present application form an oxide layer on the diode anode to block the injection to the diode region when forming the carrier injection barrier layer before the carrier injection barrier layer, so that the carrier injection barrier layer is not formed in the diode region, thereby accelerating the hole extraction speed during the reverse recovery and reducing the reverse recovery loss. BRIEF DESCRIPTION OF DRAWINGS

[0037] The following drawings for the present application are hereby included for purposes of illustrating, explaining and

[0038] In the drawings:

[0039] Figure 1 A flow chart of a method of manufacturing a semiconductor device according to an embodiment of the present application is shown;

[0040] Figures 2A-2L Cross-sectional views of a semiconductor device obtained by sequentially performing the method of manufacturing a semiconductor device according to an embodiment of the present application are shown. DETAILED DESCRIPTION

[0041] The present application will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. This application may, however, be embodied in different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided as non-limiting examples so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0042] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0043] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is oriented "above" or "over" the other element or feature. Thus, the exemplary term "below" or "beneath" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0045] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implant formed by a continuous implantation process will not have a sharp boundary (dashed lines) between implanted and non-implanted regions. Thus, the regions illustrated in the figures are schematic representations for purposes of example only and are not intended to portray actual shapes or forms of the regions of a device. Additionally, the exemplary terms "over" and "under" are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "over" or "under" another element or feature is oriented "under" or "over", respectively, the other element or feature. Thus, the exemplary terms "over" and "under" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0047] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description in order to explain the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0048] IGBT devices are mainly developed towards higher cell density, larger wafer size, thinner chip thickness, i.e. higher working junction temperature. Currently, the performance has approached its theoretical limit. An important development trend of IGBT devices in the future is to develop towards multi-functional integration, for example, to integrate IGBT and diode (such as freewheeling diode FWD or fast recovery diode FRD) on chip to reduce the cost of power devices and improve power density, i.e. to form RCIGBT.

[0049] RCIGBT is a PIN diode structure formed by forming part of N+ region on the back P+ collector region of a conventional IGBT through one or two times of photolithography, thereby forming P well, N-drift region on the front of IGBT, and back N+ collector region, i.e. a diode structure composed of P-type semiconductor, intrinsic semiconductor (I-type, i.e. undoped semiconductor) and N-type semiconductor, forming a conduction channel from the emitter to the collector of IGBT. RCIGBT increases the area of a single chip, reduces the thermal resistance, and increases the power density.

[0050] In the current related art, for RCIGBT integrating FRD and IGBT, there is a problem of poor reverse recovery performance of FRD and IGBT. Since the optimization directions of IGBT and FRD are opposite, if the lifetime control is performed on FRD to reduce the turn-on loss and reverse recovery loss, the turn-on loss of IGBT is large, and if the anode concentration of FRD is optimized, more masks are needed, resulting in increased cost.

[0051] Therefore, in view of the existence of the foregoing technical problems, the present application proposes a manufacturing method of a semiconductor device, as shown in Figure 1 which mainly includes the following steps:

[0052] Step S110: providing a substrate having opposite first and second surfaces, the substrate including an IGBT region and a diode region located on a first side of the IGBT region, and forming a drift region having a first conductivity type in the substrate;

[0053] Step S120: forming a diode anode of a second conductivity type extending from the first surface into the drift region in the diode region;

[0054] Step S130: forming an oxide layer covering at least the diode anode on the first surface;

[0055] Step S140: A carrier injection barrier layer is formed on the side of the drift region within the IGBT region near the first surface;

[0056] Step S150: An active gate is formed in the IGBT region extending from the first surface into the drift region and away from the second surface;

[0057] Step S160: A body region of a second conductivity type is formed on the side of the carrier injection barrier layer near the first surface, such that at least a portion of the body region is located on the carrier injection barrier layer, wherein the body region is also located on both sides of the active gate;

[0058] Step S170: A first conductivity type emitter region is formed in the IGBT region, extending from the first surface into the body region, the emitter region being located on both sides of the active gate.

[0059] In this embodiment, before the carrier injection blocking layer, an oxide layer is formed on the diode anode to block the injection into the diode region when the carrier injection blocking layer is formed, so that the carrier injection blocking layer will not be formed in the diode region, thereby accelerating the hole extraction speed during reverse recovery and reducing reverse recovery loss.

[0060] Below, for reference Figure 1 , Figures 2A-2L The method for manufacturing the semiconductor device of the present invention will be described in detail, wherein, Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown; Figures 2A-2L A schematic cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. In the following description, N and P represent the conductivity type of the semiconductor. The first conductivity type will be defined as N-type and the second conductivity type as P-type.

[0061] Example 1

[0062] The method for manufacturing a semiconductor device according to this application includes the following steps:

[0063] First, such as Figure 1 As shown, perform step S110, as follows: Figure 2A As shown, a substrate 200 is provided, which has a first surface 201 and a second surface 202 opposite to each other. The substrate 200 includes an IGBT region, a diode region and a termination region. The diode region is located on the first side of the IGBT region and the termination region is located on the second side of the IGBT region. A drift region with a first conductivity type is formed in the substrate. For example, a drift region with a first conductivity type is formed between the first surface 201 and the second surface 202.

[0064] For example, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc.

[0065] Next, proceed to step S120, as follows: Figure 2B As shown, ions of a second conductivity type are implanted into the terminal region and diode region of the substrate 200 to form a diode anode 203 of the second conductivity type extending from the first surface 201 into the drift region of the substrate 200 in the diode region, and at least one well region 204 of the second conductivity type extending from the first surface 201 into the drift region in the terminal region, followed by annealing. It is worth noting that the well region 204 of the second conductivity type in the terminal region can serve as a protective ring for the terminal region, thereby improving the withstand voltage performance of the IGBT structure. Exemplarily, a plurality of well regions 204 spaced apart can be formed.

[0066] Next, proceed to step S130, such as... Figure 2C As shown, an oxide layer 205 is formed on the first surface 201, at least covering the diode anode 203. Simultaneously with the formation of the oxide layer 205, a field oxide layer is formed in the termination region, covering the first surface 201 between the well regions 204 in the termination region. Exemplarily, the process for forming the field oxide layer and the oxide layer includes, but is not limited to, Local Oxidation of Silicon (LOCOS) technology. By simultaneously forming the oxide layer 205 and the field oxide layer in the termination region, it is unnecessary to additionally form a mask on the diode anode 203 during the subsequent formation of the carrier injection barrier layer and the body region. Therefore, mask preparation is saved, costs are reduced, and the process is simplified.

[0067] Next, step S140 is executed, where a carrier injection barrier layer 206 is formed on the side of the drift region of the IGBT region near the first surface 201. The carrier injection barrier layer 206 can increase the emitter carrier concentration during IGBT operation, thereby reducing the on-state voltage drop. Exemplarily, the carrier injection barrier layer of the first conductivity type can be formed by deep ion implantation and / or diffusion. Since an oxide layer is formed on the diode anode surface of the diode region, a carrier injection barrier layer will not form in the diode region when the IGBT region is formed. Because of the presence of the oxide layer, no additional mask is needed to prevent the formation of a carrier injection barrier layer on the diode region, thus saving on mask requirements.

[0068] Next, proceed to step S150, as follows: Figure 2E As shown, a patterned mask layer (not shown) is formed on the first surface 201 of the IGBT region of the substrate 200. This patterned mask layer defines the position and size of the predetermined active gate trench 2071. Then, the substrate 200 is etched from the first surface 201 to form the active gate trench 2071. The active gate trench 2071 is located away from the second surface 202 and extends into the drift region. Exemplarily, the number of active gate trenches 2071 is at least one. When there are multiple active gate trenches 2071, the multiple active gate trenches 2071 are spaced apart in a direction parallel to the first surface 201. Next, a gate dielectric layer (not shown) is formed on the inner surface of the active gate trench 2071. The gate dielectric layer can be formed by any suitable method, such as chemical vapor deposition, physical vapor deposition, or thermal oxidation. Optionally, the material of the gate dielectric layer may include silicon oxide or other suitable insulating materials.

[0069] Next, as Figure 2F As shown, a gate material layer (e.g., a polysilicon layer) is deposited to fill the active gate trench 2071 to form an active gate 207.

[0070] Next, proceed to step S160, such as... Figure 2G As shown, a second conductivity type body region 208 is formed on the side of the carrier injection barrier layer 206 near the first surface 201, and a second conductivity type body region 208 is also formed on a portion of the second conductivity type well region 204 in the terminal region. The body regions 208 on the carrier injection barrier layer 206 are located on both sides of the active gate 207 and are annealed to obtain the desired result. Figure 2HThe structure is shown. Similarly, since an oxide layer is formed on the diode anode surface in the diode region, when forming the body region of the second conductivity type, the presence of the oxide layer means that no mask is needed to form the body region in the diode region, thus saving one mask. In some examples, the doping concentration of the diode anode is lower than that of the body region. That is, the doping concentration implanted when forming the well region of the second conductivity type in the terminal region and when forming the diode anode of the second conductivity type is lower than that when forming the body region of the second conductivity type. Therefore, it can be considered that low-concentration conductive ion implantation is used when forming the well region of the second conductivity type and the diode anode of the second conductivity type, thereby reducing the concentration of the diode anode and further reducing reverse recovery loss.

[0071] Next, proceed to step S170, as follows: Figure 2I As shown, a first conductivity type emitter region 209 extending from the first surface 201 into the body region 208 is formed by implanting and / or diffusing a first conductivity type dopant on the first surface 201 where the IGBT region is located. The emitter region 209 is located at one end of the body region 208 near the active gate 207. The first conductivity type emitter region 209 is also referred to as the first conductivity type source region. Exemplarily, the second conductivity type body region of the terminal region is not implanted with a first conductivity type dopant, thereby not forming an emitter region.

[0072] Next, as Figure 2J As shown, an insulating layer 210 is formed on the first surface 201 of the substrate 200 to cover the first surface 201. A patterned mask layer (not shown) is formed on the insulating layer 210. The patterned mask layer defines the position and size of the predetermined contact hole 211 and the position and size of the diode anode 203. Then, the substrate 200 is etched from the first surface 201 to form the contact hole 211 in the insulating layer 210. The contact hole 211 penetrates the emitter region 209 and exposes at least a portion of the body region 208. At the same time, at least a portion of the oxide layer 205 on the diode anode 203 is removed to form an opening that exposes at least a portion of the surface of the diode anode 203. The contact hole in the insulating layer allows the emitter region to be electrically connected to the emitter region metal layer (i.e., the metal layer in the electrical connection structure 212) to realize the electrical function of the semiconductor device.

[0073] Next, as Figure 2KAs shown, a conductive connection structure 212 is formed on the insulating layer 210, the first surface 201 of the diode anode 203, and in the contact hole 211. The conductive connection structure includes a conductive plug formed after filling the contact hole 211, a emitter metal layer in the IGBT region, and a metal layer on the diode anode 203. The conductive plug is electrically connected to the emitter metal layer. Since the emitter region 209 is on the side of the body region 208 near the first surface 201, the conductive plug can electrically connect the body region 208 and the emitter region 209 to the emitter metal layer, realizing the electrical function of the semiconductor device. The metal layer on the diode anode 203 is electrically connected to the diode anode. In some examples, a through-hole is also formed in the insulating layer 210, exposing at least a portion of the surface of the well region 204, and the electrical connection structure is also in contact with and electrically connected to the well region 204.

[0074] Next, as Figure 2L As shown, the second surface 202 of the substrate 200 is thinned, and then second conductivity type ion implantation is performed in the IGBT region and the terminal region to form a second conductivity type collector region 213 extending from the thinned second surface 202 into the substrate 200. First conductivity type ion implantation is performed in the diode region to form a first conductivity type electrode layer 214 extending from the thinned second surface 202 into the substrate 200. The contact point between the collector region 213 and the electrode layer 214 can be considered the boundary between the IGBT region and the diode region. For example, the collector region 213 and the electrode layer 214 have the same thickness, and the thickness direction is also the arrangement direction of the first and second surfaces. Next, a metal overlay is performed on the side of the collector region 213 and the electrode layer 214 facing away from the first surface of the substrate 200 (i.e., on the second surface of the substrate 200) to form a collector metal layer, thereby forming a collector in the IGBT region and a diode cathode in the diode region.

[0075] This concludes the description of the key steps in the semiconductor device manufacturing method of the present invention. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0076] In summary, the manufacturing method of the embodiment of the present application forms an oxide layer on the diode anode and does not form a carrier injection blocking layer on the diode anode, removes the oxide layer when forming the contact hole, so that there is no carrier injection blocking layer between the metal layer and the diode anode, thereby accelerating the hole extraction speed during reverse recovery, reducing the reverse recovery loss. In addition, the substrate is implanted to form the diode anode with a lower doping concentration than the body region, so that the diode anode concentration is reduced, further reducing the reverse recovery loss. At the same time, since the oxide layer is formed before the carrier injection blocking layer is formed, and the oxide layer is removed at the same time when the contact hole is formed, the oxide layer in the diode region can prevent the formation of the carrier injection blocking layer and the body region in the diode region when the carrier injection blocking layer and the body region are formed, thereby saving the number of masks, and further reducing the production cost.

[0077] Embodiment Two

[0078] The present application also provides a semiconductor device which can be prepared by the manufacturing method of the semiconductor device in the aforementioned embodiment one. Some details in the present embodiment can be referred to the relevant description of the method in the foregoing, which will not be repeated here.

[0079] Specifically, as Figure 2LAs shown, the semiconductor device comprises a substrate 200, a diode anode 203 of a second conductivity type, a carrier injection barrier layer 206, an active gate 207, a body region 208 of the second conductivity type, an emitter region 209 of a first conductivity type, an insulating layer 210 and a conductive connecting structure 212. The substrate 200 has opposite first and second surfaces 201 and 202, and a drift region of the first conductivity type is disposed between the first and second surfaces 201 and 202. The substrate 200 comprises a termination region comprising at least one well region 204 of the second conductivity type, an IGBT region and a diode region, wherein the diode region is on a first side of the IGBT region and the termination region is on a second side of the IGBT region; the diode anode 203 is in the diode region, the carrier injection barrier layer 206 and the active gate 207 are both in the IGBT region, the carrier injection barrier layer 206 is on a side of the drift region close to the first surface 201, the diode anode 203 and the active gate 207 both extend from the first surface 201 into the drift region, and the active gate 207 is away from the second surface 202, the diode anode 203 directly contacts the drift region; the body region 208 is between the carrier injection barrier layer 206 and the well region 204 of the termination region, and the body region 208 on the carrier injection barrier layer is on both sides of the active gate 207; the emitter region 209 is on the body region and extends from the first surface 201 to the body region 208; the insulating layer 210 is on the first surface 201 and covers the first surface 201, and a contact hole and an opening exposing at least part of a surface of the diode anode 203 are formed in the insulating layer 210. The conductive connecting structure 212 covers the insulating layer 210 and fills the contact hole and the opening, thereby realizing electrical connection with the emitter region 209 and the diode anode 203.

[0080] In some embodiments, the diode anode has a doping concentration lower than that of the body region.

[0081] In some embodiments, the semiconductor device further comprises a collector region 213 of the second conductivity type in the IGBT region and the termination region, and an electrode layer 214 of the first conductivity type in the diode region, wherein the collector region 213 and the electrode layer 214 both extend from the second surface 202 into the substrate 200. Figure 2L As shown, the semiconductor device further comprises a collector region 213 of the second conductivity type in the IGBT region and the termination region, and an electrode layer 214 of the first conductivity type in the diode region, wherein the collector region 213 and the electrode layer 214 both extend from the second surface 202 into the substrate 200.

[0082] While several embodiments have been described, it should be apparent that many modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosed concept. More specifically, it is intended that modifications and variations of the subject matter described herein will occur to those skilled in the art upon reading this disclosure, and such modifications and variations are intended to be included within the scope of the disclosure. Although specific arrangements were described herein, it will be appreciated that other arrangements can be utilized and the generic or specific components described herein can be arranged and combined in a wide variety of other ways. Other substitutions and modifications will occur to those skilled in the art, and are also intended to be within the scope of the application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided, the substrate having opposing first and second surfaces, the substrate including an IGBT region and a diode region, the diode region being located on a first side of the IGBT region, and a drift region of a first conductivity type being formed within the substrate; A diode anode of a second conductivity type is formed in the diode region, extending from the first surface into the drift region; An oxide layer is formed on the first surface that at least covers the diode anode; A carrier injection barrier layer is formed on the side of the drift region within the IGBT region near the first surface; An active gate is formed in the IGBT region, extending from the first surface into the drift region and away from the second surface; A body region of a second conductivity type is formed on the side of the carrier injection barrier layer near the first surface, such that at least a portion of the body region is located on the carrier injection barrier layer, wherein the body region is also located on both sides of the active gate; A first conductivity type emitter region is formed in the IGBT region, extending from the first surface into the body region, and the emitter region is located on both sides of the active gate.

2. The manufacturing method as described in claim 1, characterized in that, The substrate further includes a termination region located on the second side of the IGBT region, and the manufacturing method further includes forming at least one well region of the second conductivity type in the termination region while forming the diode anode of the second conductivity type.

3. The manufacturing method as described in claim 2, characterized in that, A field oxide layer is formed in the terminal region, and the field oxide layer in the terminal region is formed simultaneously with the oxide layer covering the diode anode.

4. The manufacturing method as described in claim 1, characterized in that, The manufacturing method further includes: An insulating layer is formed covering the first surface and the oxide layer, and a contact hole and an opening exposing at least a portion of the surface of the diode anode are formed in the insulating layer, the contact hole penetrating the emitter region and exposing at least a portion of the body region; A conductive connection structure is formed that is electrically connected to the emitter region and the diode anode, the conductive connection structure covering the insulating layer and filling the contact hole and the opening.

5. The manufacturing method as described in claim 1, characterized in that, The doping concentration of the diode anode is lower than that of the body region.

6. The manufacturing method as described in claim 2, characterized in that, The manufacturing method further includes: A collector region of a second conductivity type is formed in the IGBT region and the terminal region, extending from the second surface into the substrate; An electrode layer of a first conductivity type is formed in the diode region, extending from the second surface into the substrate.

7. A semiconductor device, characterized in that, include: A substrate having opposing first and second surfaces, the substrate including an IGBT region and a diode region, the diode region being located on a first side of the IGBT region, and a drift region of a first conductivity type being formed within the substrate; The anode of the diode of the second conductivity type is located in the diode region and extends from the first surface into the drift region and is in direct contact with the drift region; A carrier injection blocking layer is located on the side of the drift region within the IGBT region that is close to the first surface; An active gate is located in the IGBT region, and the active gate extends from the first surface into the drift region and away from the second surface; The second conductivity type of body region is located at least partially on the carrier injection blocking layer, and the body region is located on both sides of the active gate; The emitter region of the first conductivity type extends from the first surface into the body region.

8. The semiconductor device as claimed in claim 7, characterized in that, The substrate further includes a termination region located on the second side of the IGBT region. The termination region includes at least one well region of a second conductivity type, and the well region and the diode anode have the same doping concentration.

9. The semiconductor device as claimed in claim 7, characterized in that, The semiconductor device further includes: An insulating layer that covers a portion of the first surface, and having a contact hole and an opening that exposes at least a portion of the surface of the diode anode, the contact hole penetrating the emitter region and exposing at least a portion of the body region; A conductive connection structure is electrically connected to the emitter region and the diode anode, the conductive connection structure covering the insulating layer and filling the contact hole and the opening.

10. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor device further includes: The collector region of the second conductivity type is located in the IGBT region and the terminal region, and extends from the second surface into the substrate; An electrode layer of a first conductivity type is located in the diode region and extends from the second surface into the substrate.

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