A superjunction semiconductor device and a method for manufacturing the same

Abstract

The present invention provides a superjunction semiconductor device and a preparation method thereof, which are applied to the technical field of semiconductor devices. In the present invention, a superjunction structure is formed on a substrate, and the superjunction structure includes N layers of epitaxial layers stacked in sequence, and after each epitaxial layer is formed, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, wherein N≥2; since the first sacrificial layer in the present invention is an oxide material with transparent properties (such as silicon dioxide), therefore, during the formation of the selective second ion implantation region of the epitaxial layer using the alignment groove filled with the first sacrificial layer on each epitaxial layer, not only will there be no problem of photoresist residue in the alignment groove, but also there will be no problem of damage to the shape of the alignment groove of the subsequently formed epitaxial layer derived from the photoresist residue and the problem of the exposure device being unable to recognize the alignment mark.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a super junction semiconductor device and a preparation method thereof. Background Art

[0002] Super junction MOSFET (super junction metal oxide semiconductor field effect transistor) is an innovative voltage-resistant device that overcomes the "Silicon Limit" of traditional MOSFET and effectively solves the contradiction between on-resistance and breakdown voltage. Super junction structure is generally achieved by epitaxial layer growth and ion implantation.

[0003] When epitaxial growth is performed using a multi-layer epitaxial technology, the inside of a recessed alignment mark formed in a lower epitaxial layer is filled with the epitaxial layer above it, and therefore, the shape of the alignment mark newly formed in the upper epitaxial layer is severely damaged. Therefore, when patterning is performed during selective ion implantation for selectively forming a p-type region in an n-type epitaxial layer, an exposure device cannot recognize the alignment mark, and a problem occurs in which patterning positioning (alignment) cannot be performed. Summary of the invention

[0004] The object of the present invention is to provide a super junction semiconductor device and a method for preparing the same, so as to solve the problems of residual photoresist in the alignment groove during the formation of the super junction structure and the resulting destruction of the shape of the alignment groove of the subsequently formed epitaxial layer and the inability of the exposure equipment to recognize the alignment mark.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a method for preparing a super junction semiconductor device, which may specifically include the following steps: providing a substrate.

[0006] A super junction structure is formed on the substrate, the super junction structure comprising N epitaxial layers stacked in sequence, wherein after forming each epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, and N≥2.

[0007] In some optional examples, after forming the first sacrificial layer corresponding to each epitaxial layer in the super junction structure, the method may further include: performing first ion implantation on multiple first regions of each epitaxial layer to form multiple first ion implantation regions.

[0008] In some optional examples, before forming the first sacrificial layer corresponding to the first epitaxial layer in the super junction structure, the method may further include: forming a second sacrificial layer to cover the inner surface of the alignment groove in the first epitaxial layer.

[0009] In some optional examples, a top surface of the first sacrificial layer corresponding to each epitaxial layer is flush with a top surface of the corresponding epitaxial layer.

[0010] In some optional examples, after forming the first sacrificial layer corresponding to each epitaxial layer, it may also include: forming a patterned photoresist layer on the first sacrificial layer and a portion of the epitaxial layer; performing a second ion implantation on the second region of each epitaxial layer to form a plurality of second ion implantation regions, wherein the plurality of first ion implantation regions and the plurality of second ion implantation regions have opposite conductivity types and are alternately arranged in each epitaxial layer.

[0011] In some optional examples, the first ion implantation regions or the second ion implantation regions located in different epitaxial layers in the super junction structure are respectively aligned.

[0012] In some optional examples, the thickness of the second sacrificial layer may be 150Å~250Å.

[0013] In some optional examples, the step of forming the second sacrificial layer may specifically include: performing thermal oxidation treatment on the epitaxial layer.

[0014] In some optional examples, the material of the second sacrificial layer may include oxide, which may be silicon dioxide; the material of the first sacrificial layer may include insulating material, which may include TEOS oxide.

[0015] In the second aspect, based on the super junction semiconductor device as described above, the present invention also provides a super junction semiconductor device, which can be prepared by the preparation method of the super junction semiconductor device as described above. The specific steps are detailed in the steps of the above preparation method and will not be repeated here.

[0016] Wherein, the super junction semiconductor device may include: a substrate.

[0017] A super junction structure is arranged on the substrate, the super junction structure includes N layers of epitaxial layers stacked in sequence, wherein after each layer of the epitaxial layer is formed, an alignment groove is formed in the epitaxial layer, and a first sacrificial layer and a plurality of first ion implantation regions and a plurality of second ion implantation regions of conductive types are formed in the alignment groove, and are arranged alternately, wherein N≥2 and the plurality of first ion implantation regions and the plurality of second ion implantation regions of the N layers in the super junction structure are aligned with each other.

[0018] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0019] The method for preparing a super junction semiconductor device provided by the present invention comprises: providing a substrate, forming a super junction structure on the substrate, the super junction structure comprising N layers of epitaxial layers stacked in sequence, wherein after forming each layer of the epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, and N≥2.

[0020] In the present invention, the first sacrificial layer is filled in the corresponding alignment groove in each epitaxial layer, and an unexpected effect is obtained: the aspect ratio of the alignment groove is reduced, and the growth of the epitaxial layer subsequently formed in the process of forming the super junction structure is avoided in the alignment groove. Since the first sacrificial layer formed in the corresponding alignment groove in each epitaxial layer is a material with transparent properties (such as TEOS oxide), therefore, during the formation of the selective second ion implantation area of ​​the epitaxial layer using the alignment groove filled with the first sacrificial layer on each epitaxial layer, the exposure equipment can accurately identify the alignment groove through the first sacrificial layer, that is, the alignment accuracy of the alignment groove is improved, and the problem of residual photoresist in the alignment groove and the damage to the shape of the alignment groove of the subsequently formed epitaxial layer derived from the residual photoresist is reduced, that is, the product yield of the super junction structure is improved.

[0021] Furthermore, by forming a second sacrificial layer on the inner surface of the corresponding alignment groove in the first epitaxial layer, the problem of residual photoresist in the alignment groove and the resulting destruction of the shape of the alignment groove during the formation of the super junction structure is better avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0023] Figure 1 It is a schematic flow chart of a method for preparing a superjunction semiconductor device provided in an embodiment of the present invention.

[0024] Figure 2~Figure 10 It is a structural schematic diagram of the preparation method of the super junction semiconductor device provided in an embodiment of the present invention during the preparation process.

[0025] Wherein, the accompanying drawings are marked as follows:

[0026] 100-substrate, 110-N-type epitaxial layer, 120-first epitaxial layer, 121-alignment groove, 122-first ion implantation area, 123-second ion implantation area, 130-second sacrificial layer, 130'-second sacrificial layer remaining on the inner surface of the alignment groove after etching, 140-first sacrificial layer, 150-patterned photoresist layer, 160-second epitaxial layer, 161-alignment groove formed in the second epitaxial layer, 82-N-type column, 83-P-type column.

[0027] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0028] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0029] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0030] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.

[0031] According to the background technology, in the prior art, a super junction MOSFET includes a super junction structure, and the super junction structure can be formed by a multilayer epitaxial technology, for example, by repeatedly performing epitaxial growth of an n-type semiconductor layer for forming an n-type drift layer and selective ion implantation of p-type impurities for forming a p-type region (second ion implantation region) to form parallel pn layers.

[0032] Specifically, photoresist is required in the process of selective ion implantation of p-type impurities in the p-type region of each epitaxial layer, and is removed afterwards. However, in order to accurately realize the selective ion implantation of p-type impurities in each epitaxial layer, it is usually necessary to form at least one recessed alignment mark, such as an alignment groove, on the epitaxial layer. In the process of removing the photoresist, there will inevitably be a problem of uneven photoresist residue in the recessed alignment mark due to the aspect ratio of the recessed alignment mark and other issues. The uneven residue of the photoresist will further lead to morphological deformation of the subsequently formed recessed alignment mark, and the opaque photoresist will cause the selective ion implantation of p-type impurities in the subsequent epitaxial layer to be misplaced and the super junction structure to fail.

[0033] To this end, the present invention provides a super junction semiconductor device and a method for preparing the same, so that after each epitaxial layer and its corresponding alignment groove in the super junction structure are formed, at least one first sacrificial layer can be formed on the surface of the epitaxial layer and on the inner surface of the alignment groove, so as to reduce the aspect ratio of the alignment groove by utilizing the first sacrificial layer whose material has light-transmitting properties, thereby solving the problems of growth of the epitaxial layer subsequently formed in the alignment groove during the formation of the super junction structure, residual photoresist in the alignment groove and the resulting destruction of the shape of the alignment groove of the epitaxial layer subsequently formed, and inability of the exposure equipment to recognize the alignment mark.

[0034] Please refer to Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for preparing a superjunction semiconductor device provided in an embodiment of the present invention. Figure 1 As shown, the method for preparing the super junction semiconductor device may include at least the following steps:

[0035] Step S101, providing a substrate.

[0036] Step S102, forming a super junction structure on the substrate, the super junction structure comprising N epitaxial layers stacked in sequence, wherein after forming each epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, and N≥2.

[0037] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for preparing a super junction semiconductor device in an embodiment of the present invention, the method for preparing a super junction semiconductor device proposed in the present invention will be further described below in combination with various structural schematic diagrams of the preparation method during the preparation process.

[0038] Figure 2~Figure 10 It is a structural schematic diagram of the preparation method of the super junction semiconductor device provided in an embodiment of the present invention during the preparation process.

[0039] Execute the above step S101: Please refer to Figure 2 As shown, a substrate 100 is provided; wherein the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but it is not limited thereto. In one embodiment, the substrate 100 can be a doped semiconductor substrate, such as a low-resistance n+ type silicon substrate doped with arsenic (As) (hereinafter referred to as arsenic-doped substrate, not shown in the figure), and of course, the doped semiconductor substrate can also be a semiconductor substrate after any N-type ion implantation. In another embodiment, the substrate 100 can be an undoped semiconductor substrate, such as a silicon substrate, and at least one doped epitaxial layer, such as an N-type epitaxial layer 110, can also be formed on the substrate 100, but it is not limited thereto.

[0040] It should be understood that before performing the above step S101 to form the N-type epitaxial layer 110 on the substrate 100 , the surface of the substrate 100 may be pre-cleaned, but the present invention is not limited thereto.

[0041] Execute the above step S102: Please refer to Figure 3 As shown, an epitaxial process is then used to form a first epitaxial layer 120 of a preset thickness on the substrate 100, and an etching process, such as at least one of a dry etching process or a wet etching process, is used to form at least one alignment mark, such as an alignment groove 121, in a specific area, such as an edge area, of the first epitaxial layer 120. In one embodiment, the bottom surface profile of the alignment groove 121 may be a curved arc shape that is concave along a direction close to the surface of the substrate 100, such as a semicircular shape, or an irregular curved arc shape (not shown in the figure), but not limited thereto. In another embodiment, the bottom surface profile of the alignment groove 121 may be a planar structure that is concave along a direction close to the surface of the substrate 100, such as a rectangle (not shown in the figure), but not limited thereto.

[0042] Continue to execute the above step S102: Please refer to Figure 4As shown, the second sacrificial layer 130 can be uniformly and conformally covered on the surface of the first epitaxial layer 120 and on the inner surface (bottom and sidewall) of the alignment groove 121 formed therein. In one embodiment, a thermal oxidation process can be used to perform thermal oxidation treatment on a portion of the surface of the first epitaxial layer 120 to form the second sacrificial layer 130. In one embodiment, the thickness of the second sacrificial layer 130 in a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) can be in the range of 150Å to 250Å, for example, specifically 150Å, 160Å, 170Å, 180Å, 190Å, 200Å, 220Å, etc. Preferably, the thickness of the second sacrificial layer 130 in the embodiment of the present invention is 200Å; and the material of the second sacrificial layer 130 is an oxide, for example, preferably silicon dioxide, but not limited thereto.

[0043] Continue to execute the above step S102: Please refer to Figure 5 As shown, an N-type ion implantation is performed in a plurality of first regions of the first epitaxial layer 120 by an ion implantation process to form a plurality of first ion implantation regions 122 ( Figure 5 At this time, the conductivity type of each of the first ion implantation regions 122 is the same and is N-type.

[0044] Continue to execute the above step S102: Please refer to Figure 6 As shown, an insulating material, such as TEOS oxide, may be further deposited in the remaining space of the alignment groove 121 to form a first sacrificial layer 140 in the alignment groove 121 whose top surface is flush with the top surface of the second sacrificial layer 130 .

[0045] Continue to execute the above step S102: Please refer to Figure 7As shown, a patterned photoresist layer 150 is formed on the surface of the second sacrificial layer 130 and the first sacrificial layer 140 by using a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process. In one embodiment, a plurality of window patterns for forming a plurality of P-type columns of the super junction structure are defined in the patterned photoresist layer 150, and the window patterns expose the second region in the first epitaxial layer 120, so as to facilitate the use of an ion implantation process to perform P-type ion implantation on the plurality of second regions in the first epitaxial layer 120 exposed by the window patterns, that is, to form a plurality of second ion implantation regions 123 arranged alternately with the first ion implantation regions 122. In one embodiment, the P-type ions forming the second ion implantation regions 123 may be boron ions, and the ion implantation energy during the ion implantation process for forming the second ion implantation regions 123 may be about 500keV, and the ion implantation dose may be about 1e14cm -2 Around, but not limited to this.

[0046] Obviously, since the alignment groove 121 in the embodiment of the present invention is filled with the first sacrificial layer 140 and the second sacrificial layer 130, in the process of forming the second ion implantation area 123 of the first epitaxial layer 120, the patterned photoresist layer 150 will not be filled in the alignment groove 121. Therefore, the problem of residual photoresist in the alignment groove and the resulting destruction of the shape of the alignment groove during the formation of the super junction structure can be better avoided.

[0047] Continue to execute the above step S102: Please refer to Figure 8As shown, an etching process, such as a wet etching process, can be used to sequentially remove the patterned photoresist layer 150, the second sacrificial layer 130 on the surface of the first epitaxial layer 120, and the first sacrificial layer 140 in the alignment groove 121, and the second sacrificial layer remaining on the inner surface of the alignment groove 121 after etching is marked with a reference numeral 130'. In one embodiment, the thickness of the second sacrificial layer 130' remaining on the inner surface of the alignment groove 121 after etching can be controlled by controlling the over-etching time in the wet etching process in this step, for example, to about 10Å. Obviously, in an embodiment of the present invention, after forming the first epitaxial layer in the super junction structure, such as the first epitaxial layer 120, its corresponding alignment mark for photolithography alignment, such as a second sacrificial layer with a certain thickness and uniform coverage is retained on the inner surface of the alignment groove 121, and the first sacrificial layer 140 filling the alignment groove 121, and the second sacrificial layer with a certain thickness and uniform coverage and the first sacrificial layer 140 can reduce the aspect ratio of the alignment groove 121, thereby avoiding the growth of the epitaxial layer (such as the second epitaxial layer 160) subsequently formed in the super junction structure formation process in the alignment groove and the residue of photoresist in the alignment groove, and thus the corresponding alignment groove can be conformally formed in the subsequent epitaxial layer (such as the second epitaxial layer 160).

[0048] Continue to execute the above step S102: Please refer to Fig. 9As shown, the same process technology as that used to form the first epitaxial layer 120 and the alignment groove 121 therein as described above can be further used to form subsequent multiple epitaxial layers and the corresponding alignment grooves therein. For example, the second epitaxial layer 160 can be sequentially formed on the surface of the first epitaxial layer 120 exposed after removing part of the second sacrificial layer 130 by using an epitaxial process, and the alignment groove located at the edge of the second epitaxial layer 160 can be formed by using etching and other processes. For the sake of distinction, the alignment groove formed in the second epitaxial layer 160 in the embodiment of the present invention is named as the second alignment groove and is marked with the reference numeral 161. Similarly, the same process technology as that used to form the first sacrificial layer 140, the first ion implantation region 122 and the second ion implantation region 123 on the first epitaxial layer 120 can be used to form a plurality of N-type ion implantation regions and P-type ion implantation regions alternately arranged with the plurality of N-type ion implantation regions in the second epitaxial layer 160, and this cycle is repeated until an N-layer epitaxial layer is formed on the substrate 100. In one embodiment, since a plurality of N-type ion implantation regions and P-type ion implantation regions alternately arranged with the plurality of N-type ion implantation regions are formed in each epitaxial layer, and the N-type ion implantation regions and P-type ion implantation regions of the plurality of epitaxial layers are respectively aligned along the vertical direction, a plurality of N-type column columns 82 of the super junction structure and a plurality of P-type column columns 83 alternately arranged with the N-type column columns 82 are formed in the N-layer epitaxial layer.

[0049] In addition, based on the same inventive concept, an embodiment of the present invention may further provide a super junction semiconductor device, which may at least include:

[0050] A substrate 100 and a super junction structure disposed on the substrate 100, wherein the super junction structure includes a plurality of N-type columns 82 and a plurality of P-type columns 83 arranged alternately with the N-type columns 82. In one embodiment, the plurality of N-type columns 82 and the plurality of P-type columns 83 arranged alternately with the N-type columns 82 are formed in an epitaxial layer in which N layers are sequentially stacked, and N≥2.

[0051] To summarize, the method for preparing a super junction semiconductor device provided by the present invention includes: providing a substrate, forming a super junction structure on the substrate, the super junction structure including N layers of epitaxial layers stacked in sequence, wherein after forming each layer of the epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, and N≥2.

[0052] In the present invention, the first sacrificial layer is filled in the corresponding alignment groove in each epitaxial layer, and an unexpected effect is obtained: the aspect ratio of the alignment groove is reduced, and the growth of the epitaxial layer subsequently formed in the process of forming the super junction structure is avoided in the alignment groove. Since the first sacrificial layer formed in the corresponding alignment groove in each epitaxial layer is a material with transparent properties (such as TEOS oxide), therefore, during the formation of the selective second ion implantation area of ​​the epitaxial layer using the alignment groove filled with the first sacrificial layer on each epitaxial layer, the exposure equipment can accurately identify the alignment groove through the first sacrificial layer, that is, the alignment accuracy of the alignment groove is improved, and the problem of residual photoresist in the alignment groove and the destruction of the shape of the alignment groove of the subsequently formed epitaxial layer derived from the residual photoresist is reduced.

[0053] Furthermore, by forming a second sacrificial layer on the inner surface of the corresponding alignment groove in the first epitaxial layer, the problem of residual photoresist in the alignment groove and the resulting destruction of the shape of the alignment groove during the formation of the super junction structure is better avoided.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0055] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a superjunction semiconductor device, characterized in that: include: providing a substrate; A super junction structure is formed on the substrate, the super junction structure comprising N epitaxial layers stacked in sequence, wherein after forming each epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer is formed in the alignment groove, the N is greater than or equal to 2, and the top surface of the first sacrificial layer corresponding to each epitaxial layer is flush with the top surface of the corresponding epitaxial layer, and the material of the first sacrificial layer comprises an insulating material, and the insulating material comprises TEOS oxide.

2. The method for preparing a superjunction semiconductor device according to claim 1, characterized in that: After forming the first sacrificial layer corresponding to each epitaxial layer in the super junction structure, the method further includes: A first ion implantation is performed on the first regions of each of the epitaxial layers to form a plurality of first ion implantation regions.

3. The method for preparing a superjunction semiconductor device according to claim 2, characterized in that: Before forming the first sacrificial layer corresponding to the first epitaxial layer in the super junction structure, the method further includes: A second sacrificial layer is formed to cover the inner surface of the alignment groove in the first epitaxial layer.

4. The method for preparing a superjunction semiconductor device according to claim 3, characterized in that: After forming the first sacrificial layer corresponding to each epitaxial layer, the method further comprises: forming a patterned photoresist layer on the first sacrificial layer and a portion of the epitaxial layer; A second ion implantation is performed on the second region of each epitaxial layer to form a plurality of second ion implantation regions, wherein the plurality of first ion implantation regions and the plurality of second ion implantation regions have opposite conductivity types and are alternately arranged in each epitaxial layer.

5. The method for preparing a superjunction semiconductor device according to claim 4, characterized in that: The first ion implantation regions or the second ion implantation regions in the super junction structure that are located in different epitaxial layers are aligned with each other.

6. The method for preparing a superjunction semiconductor device according to claim 3, characterized in that: The thickness of the second sacrificial layer is 150Å~250Å.

7. The method for preparing a superjunction semiconductor device according to claim 3, characterized in that: The step of forming the second sacrificial layer includes: performing a thermal oxidation process on the epitaxial layer.

8. The method for preparing a superjunction semiconductor device according to claim 3, characterized in that: The material of the second sacrificial layer includes oxide, and the oxide is silicon dioxide.

9. A superjunction semiconductor device, characterized in that: include: substrate; A super junction structure is arranged on the substrate, the super junction structure includes N layers of epitaxial layers stacked in sequence, wherein after forming each epitaxial layer, an alignment groove is formed in the epitaxial layer and a first sacrificial layer and a plurality of first ion implantation regions and a plurality of second ion implantation regions with opposite conductivity types and arranged alternately are formed in the alignment groove, wherein N≥2 and the plurality of first ion implantation regions and a plurality of second ion implantation regions of the N layers in the super junction structure are respectively aligned, the top surface of the first sacrificial layer corresponding to each epitaxial layer is respectively flush with the top surface of the corresponding epitaxial layer, and the material of the first sacrificial layer includes an insulating material, and the insulating material includes TEOS oxide.

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