Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments relate to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes first to fourth electrodes, first to fourth semiconductor regions, and first and second insulating portions. The first semiconductor region is arranged on the first electrode. The second semiconductor region is arranged on the first semiconductor region. The third semiconductor region is arranged on the second semiconductor region. The second electrode is arranged on the third semiconductor region and is electrically connected with the third semiconductor region. The third electrode is parallel to the second semiconductor region. The first insulating portion is provided between the second semiconductor region and the third electrode. The fourth electrode is parallel to the first semiconductor region and the third electrode. The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode. The fourth semiconductor region is disposed under the third electrode and electrically connected to the second electrode.

Description

[0001] Related Application

[0002] The present application claims the priority of Japanese Patent Application No. 2023-143985 (filing date: September 5, 2023) as a basic application, and the present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used for power conversion, etc. It is desired that the on-resistance of the semiconductor device be low. Summary of the invention

[0005] A semiconductor device of an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a second electrode, a third electrode, a first insulating portion, a fourth electrode, a second insulating portion, and a fourth semiconductor region of the second conductivity type. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is selectively provided on the second semiconductor region. The second electrode is provided on the third semiconductor region. The second electrode is electrically connected to the third semiconductor region. The third electrode is parallel to the second semiconductor region in a second direction and a third direction. The second direction is perpendicular to a first direction from the first electrode toward the second electrode. The third direction is perpendicular to the first direction and the second direction. The first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction. The fourth electrode is parallel to the first semiconductor region and the third electrode in the second direction and the third direction. The second insulating portion is provided between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second direction and the third direction. The fourth semiconductor region is provided below the third electrode. The fourth semiconductor region is electrically connected to the second electrode.

[0006] The method for manufacturing a semiconductor device of the embodiment comprises a first step, a second step and a third step. In the first step, a column region of a second conductivity type is formed in a semiconductor region of a first conductivity type. In the second step, a first conductive portion is formed adjacent to the column region. In the third step, a second conductive portion is formed on the column region.

[0007] The method for manufacturing a semiconductor device of the embodiment comprises a first step, a second step and a third step. In the first step, a first conductive portion is formed in a semiconductor region of a first conductive type. In the second step, a column region of a second conductive type is formed adjacent to the first conductive portion. In the third step, a second conductive portion is formed on the column region.

[0008] According to the present embodiment, a semiconductor device capable of reducing on-resistance and a method for manufacturing the semiconductor device can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0010] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.

[0011] Figure 3 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0012] Figure 4 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0013] Figure 5 This is a graph showing simulation results of the semiconductor device according to the first embodiment.

[0014] Figure 6 It is a plan view showing a part of a semiconductor device according to a first modification example of the first embodiment.

[0015] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0016] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0017] Fig. 9 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.

[0018] Fig.10 It is a plan view showing a part of the semiconductor device according to the second embodiment.

[0019] Fig.11 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0020] Fig.12 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0021] Fig.13 It is a plan view showing a part of the semiconductor device according to the third embodiment.

[0022] Fig.14 It is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.

[0023] Fig.15 (a) to (d) are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment.

[0024] Fig.16 (a) to (c) are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to an embodiment.

[0025] Fig.17 (a) to (d) are cross-sectional views showing another example of the method for manufacturing the semiconductor device according to the embodiment.

[0026] Fig.18 (a) and (b) are cross-sectional views showing another example of the method for manufacturing the semiconductor device according to the embodiment.

[0027] Description of Reference Numerals

[0028] 11: Drain electrode (first electrode)

[0029] 12: Source electrode (second electrode)

[0030] 13: Gate electrode (third electrode)

[0031] 13a: First electrode region

[0032] 13b: Second electrode region

[0033] 14: FP electrode (fourth electrode)

[0034] 15: Gate pad

[0035] 21:n - Type drift region (first semiconductor region)

[0036] 22: p-type base region (second semiconductor region)

[0037] 22a: First Area

[0038] 22b: Second area

[0039] 23:n + Type source region (third semiconductor region)

[0040] 24: p-type column region (fourth semiconductor region)

[0041] 25: p + Type connection region (fifth semiconductor region)

[0042] 28:n + Type Drain Region

[0043] 31: Gate insulating portion (first insulating portion)

[0044] 32: FP insulating part (second insulating part)

[0045] 32a: First insulation area

[0046] 32b: Second insulation area

[0047] 60: Semiconductor area

[0048] 61: Groove

[0049] 62: Semiconductor layer

[0050] 63: Column area

[0051] 64: Semiconductor layer

[0052] 65: Groove

[0053] 66: Insulation layer

[0054] 67: First conductive part

[0055] 68: Groove

[0056] 69: Insulation layer

[0057] 70: Second conductive part

[0058] 71: Semiconductor area

[0059] 72: Semiconductor area

[0060] 75: Oxide film

[0061] 100, 100A, 100B, 200, 300: Semiconductor devices DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0063] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as in reality. Even when representing the same part, sometimes the size and ratio are different according to the drawings.

[0064] In the specification and each drawing of the present application, the same reference numerals are used for the same elements as those already described, and the detailed description thereof will be appropriately omitted.

[0065] In the following description and drawings, n + 、n - and p + , p These expressions indicate the relative highs and lows of the concentrations of each impurity. That is, the expression with "+" added indicates that the impurity concentration is relatively high compared to the expression without "+" or "-", and the expression with "-" added indicates that the impurity concentration is relatively low compared to the expression without either. These expressions indicate the relative highs and lows of the net impurity concentration after these impurities compensate for each other when both p-type impurities and n-type impurities are contained in each region.

[0066] Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0067] (First Embodiment)

[0068] Figure 1 It is a plan view showing the semiconductor device according to the first embodiment.

[0069] Figure 2 It is a plan view showing a part of the semiconductor device according to the first embodiment.

[0070] Figure 3 and Figure 4 This is a cross-sectional view showing a portion of the semiconductor device according to the first embodiment.

[0071] Figure 2 express Figure 1 Region II is shown.

[0072] Figure 3 yes Figure 2 The cross-sectional view at line III-III is shown.

[0073] Figure 4 yes Figure 2 A cross-sectional view taken along line IV-IV is shown.

[0074] The semiconductor device 100 of the first embodiment is a vertical MOSFET. The semiconductor device 100 is a MOSFET of a so-called dot-on-the-fly (DOTFP) structure.

[0075] like Figure 1 to Figure 4 As shown, the semiconductor device 100 includes a drain electrode 11 (first electrode), a source electrode 12 (second electrode), a gate electrode 13 (third electrode), an FP electrode 14 (fourth electrode), a gate pad 15, -type drift region 21 (first semiconductor region), p-type base region 22 (second semiconductor region), n + type source region 23 (third semiconductor region), p-type column region 24 (fourth semiconductor region), p + type connection region 25 (fifth semiconductor region), n + The first conductivity type is n-type and the second conductivity type is p-type. Figure 2 , the source electrode 12 is omitted.

[0076] In the description of the following embodiments, a first direction D1, a second direction D2, and a third direction D3 are used. The direction from the drain electrode 11 toward the source electrode 12 is set to the first direction D1. One of the directions perpendicular to the first direction D1 is set to the second direction D2. The direction perpendicular to the first direction D1 and the second direction D2 is set to the third direction D3. The direction perpendicular to the first direction D1 and intersecting the second direction D2 is set to the fourth direction D4. The fourth direction D4 may be the same as the third direction D3 or different from the third direction. In addition, in order to make the description easier to understand, the direction from the drain electrode 11 toward the source electrode 12 is set to the top, and the opposite direction is set to the bottom, but these directions have nothing to do with the direction of gravity. Observation from above is set to "looking down".

[0077] like Figure 1 As shown in FIG. 1 , a source electrode 12 and a gate pad 15 are provided on the upper surface of the semiconductor device 100. The source electrode 12 and the gate pad 15 are electrically isolated from each other.

[0078] like Figure 3 and Figure 4 As shown, a drain electrode 11 is provided on the lower surface of the semiconductor device 100. + The type drain region 28 has an n - Type drift region 21. - The drift region 21 is connected to n + The type drain region 28 is electrically connected to the drain electrode 11. - A p-type base region 22 is provided on the p-type drift region 21. An n-type base region 22 is selectively provided on the p-type base region 22. + Type source region 23 and p + In the p-type base region 22 and the n-type connection region 25. + The source electrode 12 is provided on the p-type source region 23. The source electrode 12 is connected to the p-type base region 22 and the n-type + The type source region 23 is electrically connected.

[0079] The gate electrode 13 is parallel to the p-type base region 22 in the second direction D2 and the third direction D3. In the semiconductor device 100, a portion of the gate electrode 13 is parallel to the n-type base region 22 in the second direction D2 and the third direction D3. - In the semiconductor device 100, a portion of the gate electrode 13 is parallel to a portion of the n-type drift region 21 in the second direction D2 and the third direction D3. + A portion of the type source region 23 is parallel.

[0080] The gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the second direction D2 and the third direction D3. In the semiconductor device 100, a portion of the gate insulating portion 31 is provided between the gate electrode 13 and the p-type base region 22 in the second direction D2 and the third direction D3. - A portion of the gate insulating portion 31 is provided between the gate electrode 13 and the n type drift region 21 in the second direction D2 and the third direction D3. + A portion of the gate insulating portion 31 is provided between the gate electrode 13 and the p-type column region 24 in the first direction D1. A portion of the gate insulating portion 31 is provided between the gate electrode 13 and the source electrode 12 in the first direction D1. In this way, the gate electrode 13 is surrounded by the gate insulating portion 31. The gate electrode 13 is provided inside the gate insulating portion 31.

[0081] The gate electrode 13 is electrically connected to the gate pad 15. The gate pad 15 is electrically isolated from the source electrode 12. The gate electrode 13 may be electrically connected to the gate pad 15 via a gate wiring layer (not shown).

[0082] The FP electrode 14 is connected to the n electrode in the second direction D2 and the third direction D3. - In the semiconductor device 100, a portion of the FP electrode 14 is parallel to the p-type base region 22 in the second direction D2 and the third direction D3. A portion of the FP electrode 14 is parallel to the n-type base region 22 in the second direction D2 and the third direction D3. + Type source regions 23 are arranged in parallel.

[0083] The FP insulating portion 32 is provided between the FP electrode 14 and the n electrode 14 in the second direction D2 and the third direction D3. - In the semiconductor device 100, a portion of the FP insulating portion 32 is provided between the FP electrode 14 and the p-type base region 22 in the second direction D2 and the third direction D3. A portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n-type base region 22 in the second direction D2 and the third direction D3. + A portion of the FP insulating portion 32 is provided between the FP electrode 14 and the n type source region 23 in the first direction D1. -The FP electrode 14 is surrounded by the FP insulating portion 32. The FP electrode 14 is provided inside the FP insulating portion 32. The FP electrode 14 is electrically connected to the source electrode 12.

[0084] A p-type column region 24 is provided under the gate electrode 13. The p-type column region 24 functions as a superjunction structure. The p-type column region 24 is aligned with the n-type column region 24 in the second direction D2 and the third direction D3. - The p-type drift region 21 is parallel to the FP electrode 14. The lower end of the p-type column region 24 is, for example, located below the lower end of the FP electrode 14. In the semiconductor device 100, the lower end of the p-type column region 24 is parallel to the lower end of the FP insulating portion 32 in the second direction D2 and the third direction D3.

[0085] The p-type column region 24 is electrically connected to the source electrode 12. In the semiconductor device 100, the p-type column region 24 is connected to the source electrode 12 via the p-type base region 22 and the p-type base region 22. + The p-type base region 22 includes a first region 22a and a second region 22b. The lower end of the first region 22a is located above the upper end of the p-type column region 24. The lower end of the second region 22b is located below the upper end of the p-type column region 24. The second region 22b is parallel to the p-type column region 24 in the second direction D2 and the third direction D3. + The type connection region 25 is provided on the second region 22b.

[0086] p + The type connection region 25 is parallel to the gate electrode 13 in the second direction D2 and the third direction D3. + The type connection region 25 is parallel to the FP electrode 14 in the second direction D2 and the third direction D3. + The p-type connection region 25 is connected to the first region 22a and the n-type base region 22 in the second direction D2 and the third direction D3. + Type source regions 23 are arranged in parallel.

[0087] like Figure 2 As shown, in the semiconductor device 100, a plurality of FP electrodes 14 and FP insulating portions 32 are provided in a plan view. The FP electrodes 14 are arranged in a regular triangle shape in a plan view. The FP electrodes 14 may also be arranged in a quadrilateral shape in a plan view. The gate electrode 13 is provided between the plurality of FP electrodes 14.

[0088] like Figure 2As shown in FIG. 1 , in the semiconductor device 100, the FP electrode 14 and the FP insulating portion 32 are hexagonal in shape when viewed from above. The FP electrode 14 and the FP insulating portion 32 may also be triangular, quadrilateral, etc. in shape when viewed from above. + The shape of the n-type source region 23 is a hexagon. + The shape of the source region 23 may be, for example, a triangle, a quadrilateral, or the like.

[0089] The operation of the semiconductor device 100 will be described.

[0090] In a state where a positive voltage is applied to the drain electrode 11 relative to the source electrode 12, a voltage above the threshold is applied to the gate electrode 13. As a result, a channel (inversion layer) is formed in the p-type base region 22, and the semiconductor device 100 becomes a conducting state. Electrons flow from the source electrode 12 to the drain electrode 11 through the channel. Thereafter, if the voltage applied to the gate electrode 13 is lower than the threshold, the channel in the p-type base region 22 disappears, and the semiconductor device 100 becomes a cut-off state.

[0091] When the semiconductor device 100 is switched to the off state, the positive voltage applied to the drain electrode 11 relative to the source electrode 12 increases. - The potential difference between the drift region 21 and the FP electrode 14 increases. Due to the increase in the potential difference, the depletion layer is formed from the FP insulating portion 32 and the n - The interface of the drift region 21 is n - The n type drift region 21 is expanded. By expanding the depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, the withstand voltage of the semiconductor device 100 can be increased while maintaining the same. - The concentration of the impurities that serve as donors in the drift region 21 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .

[0092] When the semiconductor device 100 is in the off state and a positive potential is applied to the drain electrode 11 relative to the potential of the source electrode 12, a depletion layer is formed between the p-type column region 24 and the n-type column region 24. - The pn junction surface of the type drift region 21 expands along the second direction D2 and the third direction D3. By expanding the depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, the withstand voltage of the semiconductor device 100 can be improved while maintaining the same. - The concentration of the impurities that serve as donors in the drift region 21 is reduced, thereby reducing the on-resistance of the semiconductor device 100 .

[0093] An example of the material of each component of the semiconductor device 100 is described.

[0094] The drain electrode 11 , the source electrode 12 , and the gate pad 15 include metal such as aluminum or copper.

[0095] n - type drift region 21, p-type base region 22, n + type source region 23, p-type column region 24, p + Type connection area 25 and n + The type drain region 28 includes silicon, silicon carbide, gallium nitride or gallium arsenide as a semiconductor material. When silicon is used as a semiconductor material, arsenic, phosphorus or antimony can be used as an impurity that serves as a donor, and boron can be used as an impurity that serves as an acceptor.

[0096] The gate electrode 13 and the FP electrode 14 are made of a conductive material such as polysilicon. Impurities may be added to the conductive material.

[0097] The gate insulating portion 31 and the FP insulating portion 32 include an insulating material. The gate insulating portion 31 and the FP insulating portion 32 include, for example, silicon oxide or silicon nitride.

[0098] The effects of the first embodiment will be described.

[0099] In the semiconductor device 100, a plurality of FP electrodes 14 are provided in the second direction D2 and the third direction D3. According to this structure, the number of n FP electrodes 14 that form the current path can be reduced compared to a case where the FP electrodes 14 extend continuously in one direction. - The volume of the type drift region 21 increases. As a result, the on-resistance of the semiconductor device 100 can be reduced. In addition, in the semiconductor device 100, a plurality of gate electrodes 13 are also provided in the second direction D2 and the third direction D3. According to this structure, compared with the case where the gate electrode 13 extends continuously in one direction, channels are formed in more areas. The channel density is increased, and the on-resistance of the semiconductor device 100 is further reduced. For example, if the on-resistance of the semiconductor device 100 is reduced, the current density flowing through the semiconductor device 100 can be increased. By increasing the current density, the miniaturization of the semiconductor device 100 can be achieved. Alternatively, the number of semiconductor devices 100 required to flow a specified current can be reduced.

[0100] In addition, in the semiconductor device 100, as Figure 3 and Figure 4 As shown, a p-type column region 24 is provided under the gate electrode 13. A potential difference is provided between the p-type column region 24 and the n-type column region so that when the semiconductor device 100 is turned off, for example, n -The potential of the region (hereinafter referred to as "n-type column region") in the type drift region 21 that is parallel to the p-type column region 24 in the second direction D2 and the third direction D3 is higher than that of the p-type column region 24. In addition, the impurity concentration of the n-type column region in the unit cell is substantially the same as the impurity amount of the p-type column region 24. Therefore, the depletion layer extends from the pn junction interface formed by the p-type column region 24 and the n-type column region to the p-type column region 24 side and the n-type column region side, respectively, and each p-type column region 24 and each n-type column region is depleted at a predetermined voltage. As a result, the n-type column region 24 can be improved. - By reducing the concentration of the impurities that serve as donors in the type drift region 21, the on-resistance of the semiconductor device 100 is reduced and the breakdown voltage is improved.

[0101] Furthermore, by providing the p-type column region 24 under the gate electrode 13 , the area where the gate electrode 13 and the drain electrode 11 face each other (overlap) can be reduced, and the capacitance ratio between the gate electrode 13 and the drain electrode 11 can be reduced.

[0102] In addition, in the semiconductor device 100, as Figure 3 and Figure 4 As shown in FIG. 1 , the lower end of the p-type column region 24 is located below the lower end of the FP electrode 14. Thus, the on-resistance of the semiconductor device 100 can be further reduced.

[0103] In addition, in the semiconductor device 100, as Figure 4 As shown, the p-type column region 24 is formed via the p-type base region 22 (second region 22b). + The type connection region 25 is electrically connected to the source electrode 12. Thus, the gate wiring does not need to be a multilayer wiring, so it is easy to manufacture the semiconductor device 100. In addition, since the volume of the gate electrode 13 is increased, the gate resistance can be reduced.

[0104] Figure 5 This is a graph showing simulation results of the semiconductor device according to the first embodiment.

[0105] exist Figure 5 In FIG. 1 , the ratio of the breakdown voltages at various impurity concentrations of the semiconductor device 100 is indicated by a solid line, and the ratio of the breakdown voltages at various impurity concentrations of a reference example in which the p-type column region 24 is not provided is indicated by a dotted line.

[0106] like Figure 5 As shown in the figure, it is shown that in the semiconductor device 100 provided with the p-type column region 24, compared with the reference example without the p-type column region 24, even if n - The concentration of the impurities that serve as donors in the drift region 21 increases, and the breakdown voltage is unlikely to decrease.

[0107] (First Modification)

[0108] Figure 6 It is a plan view showing a part of a semiconductor device according to a first modification example of the first embodiment.

[0109] Figure 7 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0110] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a first modification of the first embodiment.

[0111] Figure 6 Representation and Figure 1 The area corresponding to region II shown.

[0112] Figure 7 yes Figure 6 A cross-sectional view taken along line VII-VII is shown.

[0113] Figure 8 yes Figure 6 A cross-sectional view taken along line VIII-VIII is shown.

[0114] like Figure 6 to Figure 8 As shown, in the semiconductor device 100A according to the first modification of the first embodiment, the thickness of the FP insulating portion 32 and the thickness of the p-type column region 24 are different from those of the semiconductor device 100 . Other aspects are the same as those of the semiconductor device 100 .

[0115] The FP insulating portion 32 includes a first insulating region 32a and a second insulating region 32b. The first insulating region 32a extends along the second direction D2. The second insulating region 32b extends along the fourth direction D4. The thickness T1 of the first insulating region 32a is smaller than the thickness T2 of the second insulating region 32b. The thickness T1 is the thickness in a direction (third direction D3) perpendicular to the first direction D1 and the extension direction (second direction D2) of the first insulating region 32a. The thickness T2 is the thickness in a direction (fourth direction D4) perpendicular to the first direction D1 and the extension direction (fourth direction D4) of the second insulating region 32b.

[0116] The p-type column region 24 includes a first portion 24a and a second portion 24b. The first portion 24a extends along the second direction D2. The first portion 24a is along the first insulating region 32a. The second portion 24b extends along the fourth direction D4. The second portion 24b is along the second insulating region 32b. The thickness T11 of the first portion 24a is greater than the thickness T12 of the second portion 24b. The thickness T11 is the thickness in a direction (third direction D3) perpendicular to the first direction D1 and the extending direction (second direction D2) of the first portion 24a. The thickness T12 is the thickness in a direction (fourth direction D4) perpendicular to the first direction D1 and the extending direction (fourth direction D4) of the second portion 24b.

[0117] For example, in n - When the drift region 21 contains silicon, a difference in the oxidation rate of silicon is likely to occur in each plane orientation of the silicon crystal. Specifically, the oxidation rate on the (100) plane of the silicon crystal is likely to be slower than the oxidation rate on the plane inclined relative to the (100) plane. Therefore, the thickness of the FP insulating portion 32 along the (100) plane is likely to be smaller than the thickness of the FP insulating portion 32 on the plane inclined relative to the (100) plane. For example, when the (100) plane is along the second direction D2, the thickness T1 of the first insulating region 32a extending along the second direction D2 is likely to be smaller than the thickness T2 of the second insulating region 32b extending along the direction inclined relative to the second direction D2 (for example, the fourth direction D4).

[0118] In the semiconductor device 100A, when the thickness T1 of the first insulating region 32a is smaller than the thickness T2 of the second insulating region 32b, the thickness T11 of the first portion 24a is made larger than the thickness T12 of the second portion 24b. Thus, the thickness of the p-type column region 24 can be increased in the region where the FP insulating portion 32 is likely to be thin, thereby improving the withstand voltage.

[0119] (Second Modification)

[0120] Fig. 9 This is a cross-sectional view showing a portion of a semiconductor device according to a second modification of the first embodiment.

[0121] Fig. 9 Representation and Figure 6 The cross section at the position corresponding to the line VII-VII is shown.

[0122] like Fig. 9 As shown, in the semiconductor device 100B according to the second modification of the first embodiment, the thickness and the impurity concentration of the p-type column region 24 are different from those of the semiconductor device 100A. Other than that, the semiconductor device 100B is the same as the semiconductor device 100A.

[0123] In the semiconductor device 100B, the thickness T11 of the first portion 24a is the same as the thickness T12 of the second portion 24b. On the other hand, the concentration of the impurity that serves as a donor in the first portion 24a is higher than the concentration of the impurity that serves as a donor in the second portion 24b.

[0124] In the semiconductor device 100B, when the thickness T1 of the first insulating region 32a is smaller than the thickness T2 of the second insulating region 32b, the concentration of the impurity that becomes a donor in the first portion 24a is made higher than the concentration of the impurity that becomes a donor in the second portion 24b. Thus, in the region where the FP insulating portion 32 is likely to become thinner, the concentration of the impurity that becomes a donor in the p-type column region 24 can be increased, thereby improving the withstand voltage.

[0125] (Second Embodiment)

[0126] Fig.10 It is a plan view showing a part of the semiconductor device according to the second embodiment.

[0127] Fig.11 and Fig.12 It is a cross-sectional view showing a part of the semiconductor device according to the second embodiment.

[0128] Fig.10 Representation and Figure 1 The area corresponding to region II shown.

[0129] Fig.11 yes Fig.10 A cross-sectional view taken along line XI-XI is shown.

[0130] Fig.12 yes Fig.10 A cross-sectional view taken along line XII-XII is shown.

[0131] like Figure 10 to Figure 12 As shown, in the semiconductor device 200 of the second embodiment, p + The position of the type connection region 25 is different from that of the semiconductor device 100. Other than that, the semiconductor device 100 is the same as that of the semiconductor device 100.

[0132] In the semiconductor device 200, the p-type column region 24 is formed via the p + The type connection region 25 is electrically connected to the source electrode 12. + The p-type connection region 25 is provided on the p-type column region 24. + The type connection region 25 is parallel to the gate electrode 13 in the second direction D2 and the third direction D3. + The type connection region 25 is parallel to the FP electrode 14 in the second direction D2 and the third direction D3. + The p-type connection region 25 is connected to the p-type base region 22 and the n-type base region 23 in the second direction D2 and the third direction D3. + Type source regions 23 are arranged in parallel.

[0133] The gate electrode 13 includes a first electrode region 13a and a second electrode region 13b. The first electrode region 13a extends along the second direction D2. The second electrode region 13b extends along the fourth direction D4. + The type connection region 25 is parallel to the first electrode region 13a in the second direction D2. + The type connection region 25 is parallel to the second electrode region 13b in the fourth direction D4. + The type connection region 25 is provided at a position where the gate electrodes 13 intersect.

[0134] In the dot FP structure, at the position where the gate electrode 13 intersects, the gate electrode 13 does not intersect with the p-type base region 22 or the n-type base region 23. + Therefore, by setting a p type source region 23 at the intersection of the gate electrode 13 + The p-type connection region 25 can electrically connect the p-type column region 24 and the source electrode 12 using a region where a channel is not formed. Thus, holes can be extracted in a portion where a channel is not formed, and holes can be extracted in a low resistance region.

[0135] (Third Embodiment)

[0136] Fig.13 It is a plan view showing a part of the semiconductor device according to the third embodiment.

[0137] Fig.14 It is a cross-sectional view showing a part of the semiconductor device according to the third embodiment.

[0138] Fig.13 Representation and Figure 1 The area corresponding to region II shown.

[0139] Fig.14 yes Fig.13 A cross-sectional view taken along line XIV-XIV is shown.

[0140] like Fig.13 and Fig.14 As shown, in the semiconductor device 300 of the third embodiment, no p + The semiconductor device 100 is different from the semiconductor device 100 in that the type connection region 25 is included. Other points are the same as the semiconductor device 100.

[0141] In the semiconductor device 300, the p-type column region 24 is electrically connected to the source electrode 12 via the p-type base region 22. The p-type base region 22 includes a first region 22a and a second region 22b. The lower end of the first region 22a is located above the upper end of the p-type column region 24. The lower end of the second region 22b is located below the upper end of the p-type column region 24. The second region 22b is parallel to the p-type column region 24 in the second direction D2 and the third direction D3.

[0142] The gate electrode 13 is located between the first region 22a and the second region 22b in the second direction D2 and the third direction D3. The upper end of the p-type column region 24 is located between the second region 22b and the n-type column region 24 in the second direction D2 and the third direction D3. - The first region 22a functions as a channel.

[0143] The second region 22b does not function as a channel.

[0144] (First Manufacturing Method)

[0145] Fig.15 (a)~ Fig.15 (d) and Fig.16 (a)~ Fig.16 (c) is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment.

[0146] like Fig.15 (a)~ Fig.15 (d) and Fig.16 (a)~ Fig.16 As shown in (c), the first manufacturing method includes a first step, a second step, a third step, and a fourth step.

[0147] In the first step, a column region 63 of a second conductivity type (e.g., p-type) is formed in a semiconductor region 60 of a first conductivity type (e.g., n-type). In the second step, a first conductive portion 67 is formed adjacent to the column region 63. The second step is performed after the first step. In the third step, a second conductive portion 70 is formed on the column region 63. The third step is performed after the second step. In the fourth step, a diffusion layer is formed. The fourth step is performed after the third step. Fig.15 (a)~ Fig.15 (c) corresponds to the first step. Fig.15 (d) and Fig.16 (a) corresponds to the second step. Fig.16 (b) corresponds to the third step. Fig.16 (c) corresponds to the fourth step. Each step will be described below.

[0148] In the first step, first, Fig.15 As shown in (a) of FIG. 1 , a portion of the semiconductor region 60 is removed to form a trench 61 in the semiconductor region 60. The trench 61 is formed by, for example, etching.

[0149] In the first step, next, Fig.15 As shown in (b) of FIG. 6 , a semiconductor layer 62 is formed inside the trench 61 and on the semiconductor region 60. The semiconductor layer 62 is formed by, for example, CVD (Chemical Vapor Deposition) or the like.

[0150] In the first step, next, Fig.15 As shown in (c), the portion of the semiconductor layer 62 formed on the semiconductor region 60 is removed. As a result, the portion of the semiconductor layer 62 formed inside the trench 61 is left to form the pillar region 63. The semiconductor region 60 corresponds to the above-mentioned n -The p-type drift region 21. The pillar region 63 corresponds to the above-mentioned p-type pillar region 24. The portion of the semiconductor layer 62 formed on the semiconductor region 60 is removed by, for example, CMP (Chemical Mechanical Polishing).

[0151] In the second step, first, Fig.15 As shown in (d), a semiconductor layer 64 is formed on the pillar region 63 and on the semiconductor region 60. The semiconductor layer 64 may be an undoped semiconductor layer to which no impurities are added, a semiconductor layer to which p-type impurities are added, or a semiconductor layer to which n-type impurities are added. The semiconductor layer 64 may be formed by, for example, CVD.

[0152] In the second step, next, Fig.16 As shown in (a), a first conductive portion 67 is formed adjacent to the column region 63. More specifically, first, a portion of the semiconductor region 60 and a portion of the semiconductor layer 64 adjacent to the column region 63 are removed, and a trench 65 is formed adjacent to the column region 63. Next, an insulating layer 66 is formed inside the trench 65 along the sidewalls and bottom of the trench 65. Next, a first conductive portion 67 is formed inside the insulating layer 66 along the sidewalls and bottom of the insulating layer 66. The insulating layer 66 is equivalent to the above-mentioned FP insulating portion 32. The first conductive portion 67 is equivalent to the above-mentioned FP electrode 14. The formation of the trench 65 is performed, for example, by etching. The formation of the insulating layer 66 is performed, for example, by thermal oxidation. The formation of the first conductive portion 67 is performed, for example, by a combination of CVD and etching.

[0153] In the third step, Fig.16 As shown in (b), a second conductive portion 70 is formed on the pillar region 63. More specifically, first, a portion of the semiconductor layer 64 on the pillar region 63 is removed, and a trench 68 is formed on the pillar region 63. Next, an insulating layer 69 is formed inside the trench 68 along the sidewalls and bottom of the trench 68. Next, a second conductive portion 70 is formed inside the insulating layer 69 along the sidewalls and bottom of the insulating layer 69. The insulating layer 69 is equivalent to the above-mentioned gate insulating portion 31. The second conductive portion 70 is equivalent to the above-mentioned gate electrode 13. The formation of the trench 68 is performed, for example, by etching. The formation of the insulating layer 69 is performed, for example, by thermal oxidation. The formation of the second conductive portion 70 is performed, for example, by a combination of CVD and etching.

[0154] In the fourth step, if Fig.16As shown in (c), a diffusion layer is formed in the semiconductor layer 64. More specifically, the second conductivity type impurities are injected into the semiconductor layer 64 to form a semiconductor region 71, and the first conductivity type impurities are injected into a part of the semiconductor region 71 to form a semiconductor region 72. The semiconductor region 71 corresponds to the p-type base region 22 described above. The semiconductor region 72 corresponds to the n-type base region 22 described above. + Type source region 23.

[0155] When the semiconductor device is provided with the above-mentioned p + In the case of type connection area 25, p + The type connection region 25 is formed, for example, after the fourth step.

[0156] As described above, when the thickness of the p-type column region 24 is made different depending on the position, in the first step, when the trench 61 is formed in the semiconductor region 60, the trench 61 with different widths may be formed. In addition, as described above, when the concentration of the impurity that serves as a donor in the p-type column region 24 is made different depending on the position, in the first step, when the semiconductor layer 62 is formed inside the trench 61 and on the semiconductor region 60, the semiconductor layer 62 (column region 63) with different impurity concentrations may be formed in multiple times.

[0157] According to the first manufacturing method, a semiconductor device having a p-type column region 24 (column region 63 ) provided below the gate electrode 13 (second conductive portion 70 ) can be easily manufactured. Therefore, a semiconductor device capable of reducing on-resistance can be easily manufactured.

[0158] (Second Manufacturing Method)

[0159] Fig.17 (a)~ Fig.17 (d) Fig.18 (a) and Fig.18 (b) is a cross-sectional view showing another example of the method for manufacturing the semiconductor device according to the embodiment.

[0160] like Fig.17 (a)~ Fig.17 (d) Fig.18 (a) and Fig.18 As shown in (b), the second manufacturing method includes a first step, a second step, a third step, and a fourth step.

[0161] In the first step, a first conductive portion 67 is formed in a semiconductor region 60 of a first conductive type (e.g., n-type). In the second step, a column region 63 of a second conductive type (e.g., p-type) is formed adjacent to the first conductive portion 67. The second step is performed after the first step. In the third step, a second conductive portion 70 is formed on the column region 63. The third step is performed after the second step. In the fourth step, a diffusion layer is formed. The fourth step is performed after the third step. Fig.17 (a) corresponds to the first step. Fig.17 (b)~ Fig.17 (d) corresponds to the second step. Fig.18 (a) corresponds to the third step. Fig.18 (b) corresponds to the fourth step. Each step will be described below. In addition, the formation and removal of each part can be performed in the same manner as the first manufacturing method.

[0162] In the first step, Fig.17 As shown in (a), a first conductive portion 67 is formed in the semiconductor region 60. More specifically, first, a semiconductor layer 64 is formed on the semiconductor region 60. Next, a portion of the semiconductor region 60 and a portion of the semiconductor layer 64 are removed, and a trench 65 is formed in the semiconductor region 60 and the semiconductor layer 64. Next, an insulating layer 66 is formed inside the trench 65 along the sidewalls and bottom of the trench 65. Next, a first conductive portion 67 is formed inside the insulating layer 66 along the sidewalls and bottom of the insulating layer 66.

[0163] In the second step, first, Fig.17 As shown in (b), an oxide film 75 is formed on the semiconductor layer 64. Next, a portion of the semiconductor layer 64 and a portion of the oxide film 75 adjacent to the first conductive portion 67 are removed, and a trench 68 is formed adjacent to the first conductive portion 67. By forming the trench 68, the semiconductor region 60 is exposed.

[0164] In the second step, next, Fig.17 As shown in (c), the second conductivity type impurities are injected from the trench 68 into the semiconductor region 60. Furthermore, by performing activation annealing, as shown in FIG. Fig.17 As shown in (d) , the pillar region 63 is formed adjacent to the first conductive portion 67 .

[0165] In the third step, Fig.18 As shown in (a), the second conductive portion 70 is formed on the pillar region 63. More specifically, first, the oxide film 75 is removed. Next, the insulating layer 69 is formed inside the trench 68 along the sidewalls and bottom of the trench 68. Next, the second conductive portion 70 is formed inside the insulating layer 69 along the sidewalls and bottom of the insulating layer 69. The oxide film 75 is removed by, for example, etching.

[0166] In the fourth step, if Fig.18 As shown in (b), a diffusion layer is formed in the semiconductor layer 64. The fourth step can be performed in the same manner as the fourth step of the first manufacturing method.

[0167] When the semiconductor device is provided with the above-mentioned p + In the case of type connection area 25, p + The type connection region 25 is formed, for example, after the fourth step.

[0168] As described above, when the thickness of the p-type column region 24 is made different depending on the position, in the second step, when the trench 68 is formed adjacent to the first conductive portion 67, the trench 68 with different widths may be formed. In addition, as described above, when the concentration of the impurity that serves as a donor in the p-type column region 24 is made different depending on the position, in the second step, when the second conductive type impurity is injected into the semiconductor region 60 from the trench 68, the column region 63 with different impurity concentrations may be formed in multiple times.

[0169] According to the second manufacturing method, a semiconductor device having a p-type column region 24 (column region 63 ) provided below the gate electrode 13 (second conductive portion 70 ) can be easily manufactured. Therefore, a semiconductor device capable of reducing on-resistance can be easily manufactured.

[0170] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed using, for example, SCM (scanning electrostatic capacitance microscope). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the activated impurity concentration in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by SIMS (secondary ion mass spectrometry).

[0171] Embodiments may include the following structures.

[0172] (Structure 1)

[0173] A semiconductor device comprising:

[0174] a first electrode;

[0175] A first semiconductor region of a first conductivity type, disposed on the first electrode;

[0176] A second semiconductor region of a second conductivity type, disposed on the first semiconductor region;

[0177] The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region;

[0178] a second electrode disposed on the third semiconductor region and electrically connected to the third semiconductor region;

[0179] a third electrode arranged in parallel with the second semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the second electrode and in a third direction perpendicular to the first direction and the second direction;

[0180] A first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction;

[0181] a fourth electrode, arranged in parallel with the first semiconductor region and the third electrode in the second direction and the third direction;

[0182] a second insulating portion provided between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second direction and the third direction; and

[0183] The fourth semiconductor region of the second conductivity type is provided under the third electrode and is electrically connected to the second electrode.

[0184] (Structure 2)

[0185] The semiconductor device according to Structure 1, wherein:

[0186] The lower end of the fourth semiconductor region is located below the lower end of the fourth electrode.

[0187] (Structure 3)

[0188] The semiconductor device according to Structure 1 or 2, wherein:

[0189] The semiconductor device further includes a fifth semiconductor region of the second conductivity type provided on the second semiconductor region and arranged in parallel with the third electrode in the second direction and the third direction.

[0190] The fourth semiconductor region is electrically connected to the second electrode via the second semiconductor region and the fifth semiconductor region.

[0191] (Structure 4)

[0192] The semiconductor device according to Structure 1 or 2, wherein:

[0193] The semiconductor device further includes a fifth semiconductor region of the second conductivity type provided on the fourth semiconductor region and arranged in parallel with the third electrode in the second direction and the third direction.

[0194] The fourth semiconductor region is electrically connected to the second electrode via the fifth semiconductor region.

[0195] The third electrode includes a first electrode region extending along the second direction and a second electrode region extending along a fourth direction perpendicular to the first direction and intersecting the second direction.

[0196] The fifth semiconductor region is parallel to the first electrode region in the second direction, and is parallel to the second electrode region in the fourth direction.

[0197] (Structure 5)

[0198] The semiconductor device according to any one of Structures 1 to 4, wherein:

[0199] The second insulating portion includes a first insulating region extending along the second direction and a second insulating region extending along a fourth direction perpendicular to the first direction and intersecting the second direction.

[0200] The fourth semiconductor region includes a first portion extending along the second direction and a second portion extending along the fourth direction,

[0201] The thickness of the first insulating region is smaller than the thickness of the second insulating region,

[0202] The thickness of the first portion is greater than the thickness of the second portion.

[0203] (Structure 6)

[0204] The semiconductor device according to any one of Structures 1 to 5, wherein:

[0205] The second insulating portion includes a first insulating region extending along the second direction and a second insulating region extending along a fourth direction perpendicular to the first direction and intersecting the second direction.

[0206] The fourth semiconductor region includes a first portion extending along the second direction and a second portion extending along the fourth direction,

[0207] The thickness of the first insulating region is smaller than the thickness of the second insulating region,

[0208] The concentration of the second conductivity type impurity in the first portion is higher than the concentration of the second conductivity type impurity in the second portion.

[0209] (Structure 7)

[0210] A method for manufacturing a semiconductor device, comprising:

[0211] In a first step, a pillar region of a second conductivity type is formed in a semiconductor region of a first conductivity type;

[0212] A second step is to form a first conductive portion adjacent to the pillar region; and

[0213] In a third step, a second conductive portion is formed on the pillar region.

[0214] (Structure 8)

[0215] A method for manufacturing a semiconductor device, comprising:

[0216] In a first step, a first conductive portion is formed in a semiconductor region of a first conductivity type;

[0217] A second step is to form a pillar region of a second conductivity type adjacent to the first conductive portion; and

[0218] In a third step, a second conductive portion is formed on the pillar region.

[0219] As described above, according to the embodiments, a semiconductor device capable of reducing on-resistance and a method for manufacturing the semiconductor device can be provided.

[0220] The embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the scope of the invention and its equivalents recorded in the claims.

Claims

1. A semiconductor device, characterized in that: have: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A second semiconductor region of a second conductivity type, disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region; a second electrode disposed on the third semiconductor region and electrically connected to the third semiconductor region; a third electrode arranged in parallel with the second semiconductor region in a second direction perpendicular to the first direction from the first electrode toward the second electrode and in a third direction perpendicular to the first direction and the second direction; A first insulating portion is provided between the second semiconductor region and the third electrode in the second direction and the third direction; a fourth electrode, arranged in parallel with the first semiconductor region and the third electrode in the second direction and the third direction; a second insulating portion, provided between the first semiconductor region and the fourth electrode and between the third electrode and the fourth electrode in the second direction and the third direction; as well as The fourth semiconductor region of the second conductivity type is provided under the third electrode and is electrically connected to the second electrode.

2. The semiconductor device according to claim 1, wherein: The lower end of the fourth semiconductor region is located below the lower end of the fourth electrode.

3. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a fifth semiconductor region of the second conductivity type provided on the second semiconductor region and arranged in parallel with the third electrode in the second direction and the third direction. The fourth semiconductor region is electrically connected to the second electrode via the second semiconductor region and the fifth semiconductor region.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a fifth semiconductor region of the second conductivity type provided on the fourth semiconductor region and arranged in parallel with the third electrode in the second direction and the third direction. The fourth semiconductor region is electrically connected to the second electrode via the fifth semiconductor region. The third electrode includes a first electrode region extending along the second direction and a second electrode region extending along a fourth direction perpendicular to the first direction and intersecting the second direction. The fifth semiconductor region is parallel to the first electrode region in the second direction, and is parallel to the second electrode region in the fourth direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The second insulating portion includes a first insulating region extending along the second direction and a second insulating region extending along a fourth direction perpendicular to the first direction and intersecting the second direction. The fourth semiconductor region includes a first portion extending along the second direction and a second portion extending along the fourth direction, The thickness of the first insulating region is smaller than the thickness of the second insulating region, The thickness of the first portion is greater than the thickness of the second portion.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that The second insulating portion includes a first insulating region extending along the second direction and a second insulating region extending along a fourth direction perpendicular to the first direction and intersecting the second direction. The fourth semiconductor region includes a first portion extending along the second direction and a second portion extending along the fourth direction, The thickness of the first insulating region is smaller than the thickness of the second insulating region, The concentration of the second conductivity type impurity in the first portion is higher than the concentration of the second conductivity type impurity in the second portion.

7. A method for manufacturing a semiconductor device, characterized in that: have: In a first step, a pillar region of a second conductivity type is formed in a semiconductor region of a first conductivity type; A second step is to form a first conductive portion adjacent to the pillar region; as well as In a third step, a second conductive portion is formed on the pillar region.

8. A method for manufacturing a semiconductor device, characterized in that: have: In a first step, a first conductive portion is formed in a semiconductor region of a first conductivity type; a second step of forming a pillar region of a second conductivity type adjacent to the first conductive portion; as well as In a third step, a second conductive portion is formed on the pillar region.

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