IGBT with improved turn-off loss and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides an IGBT with improved turn-off loss, a preparation method thereof, and a chip thereof. The carrier storage layer is set to be a stepped structure, the bottom of the carrier storage layer covers an N-type drift region, a P-type base region is formed on the first step of the carrier storage layer, an N-type emitter doping region and a P-type emitter doping region are formed on the horizontal portion of the P-type base region of the L-shaped structure, an N-type doping region is formed in a groove of the top step of the carrier storage layer, a gate dielectric layer is formed on the top step of the carrier storage layer, the gate dielectric layer wraps the gate polysilicon layer and the gate polysilicon layer is opposite to the N-type doping region, a P-type well region is formed on the top step of the carrier storage layer and is parallel to the gate dielectric layer, thereby reducing the gate area, changing the capacitance between the collector and the emitter, and adding an additional current extraction channel, thereby further reducing the turn-off loss of the device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to an IGBT with improved turn-off loss, a preparation method thereof, and a chip. Background Art

[0002] Insulate-Gate Bipolar Transistor (IGBT) is a gate-controlled bipolar device. Due to the presence of minority carriers, a large number of holes are injected when it is turned on. Therefore, it has low operating loss, large current and high voltage resistance. It is widely used in medium-frequency and high-power fields such as electric vehicles and household appliances.

[0003] However, when the IGBT is turned off, it needs to extract a large number of holes generated when it is turned on. The hole extraction path and extraction speed will greatly affect the device's shutdown speed and shutdown loss. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide an IGBT with improved turn-off loss, a preparation method thereof, and a chip, aiming to reduce the turn-off loss of the IGBT device during hole extraction.

[0005] A first aspect of an embodiment of the present application provides an IGBT with improved turn-off loss, comprising:

[0006] A P-type substrate and an N-type buffer layer, wherein the N-type buffer layer is formed on the front side of the P-type substrate;

[0007] An N-type drift region, wherein the N-type drift region is formed on the N-type buffer layer;

[0008] A carrier storage layer is formed on the N-type drift region, the carrier storage layer is a stepped structure, and the bottom of the carrier storage layer covers the N-type drift region;

[0009] A P-type base region is formed on the first step of the carrier storage layer, and the P-type base region has an L-shaped structure;

[0010] An N-type emitter doping region and a P-type emitter doping region are formed on a horizontal portion of the P-type base region of the L-shaped structure and isolated from the carrier storage layer by a vertical portion of the P-type base region;

[0011] An N-type doped region formed in a groove of a top step of the carrier storage layer;

[0012] A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the top step of the carrier storage layer, the gate dielectric layer wraps the gate polysilicon layer, and the gate polysilicon layer is opposite to the N-type doped region;

[0013] A P-type well region is formed on a top step of the carrier storage layer and is in contact with a first side of the gate dielectric layer;

[0014] an emitter electrode, contacting the N-type emitter doping region and the P-type emitter doping region, and contacting the second side of the gate dielectric layer;

[0015] A collector is formed on the back side of the P-type substrate.

[0016] In some embodiments, the P-type well region has a stepped structure.

[0017] In some embodiments, the width of the P-type well region gradually increases in a direction away from the carrier storage layer.

[0018] In some embodiments, the doping concentration of the P-type well region is graded doping.

[0019] In some embodiments, the doping concentration of the P-type well region gradually decreases in a direction away from the carrier storage layer.

[0020] In some embodiments, the emitter contacts the gate dielectric layer.

[0021] In some embodiments, a PN junction is formed between the carrier storage layer and the P-type base region, and a PN junction is formed between the carrier storage layer and the P-type well region.

[0022] In some embodiments, the doping concentration of P-type doping ions in the P-type emitter doping region is greater than the doping concentration of P-type doping ions in the P-type base region, and a PN junction is formed between the P-type base region and the N-type emitter doping region.

[0023] The second aspect of the embodiment of the present application further provides a preparation method for preparing the IGBT with improved turn-off loss as described in the first aspect above, the preparation method comprising:

[0024] An N-type drift region is formed by epitaxy on the front side of the N-type substrate;

[0025] Epitaxially growing an N-type silicon material on the N-type drift region, and performing ion implantation to form a carrier storage layer and an N-type doped region; wherein the N-type doped region is formed in a groove of the carrier storage layer;

[0026] forming a gate dielectric layer and a gate polysilicon layer on the carrier storage layer, wherein the gate dielectric layer wraps the gate polysilicon layer, and the gate polysilicon layer is opposite to the N-type doping region;

[0027] epitaxially growing a P-type well region on the carrier storage layer, wherein the P-type well region contacts the first side of the gate dielectric layer;

[0028] Implanting N-type doping ions on the back side of the N-type substrate to form an N-type buffer layer, and implanting P-type doping ions on the back side of the N-type buffer layer to form a P-type substrate;

[0029] N-type doping ions and P-type doping ions are implanted into a partial area of ​​the carrier storage layer to form a P-type base region, an N-type emitter doping region and a P-type emitter doping region, so that the carrier storage layer has a stepped structure; wherein the P-type base region is formed on the first step of the carrier storage layer, and the P-type base region has an L-shaped structure; the N-type emitter doping region and the P-type emitter doping region are formed on the horizontal portion of the P-type base region of the L-shaped structure, and are isolated from the carrier storage layer by the vertical portion of the P-type base region;

[0030] forming an emitter electrode in contact with the N-type emitter doping region and the P-type emitter doping region; wherein the emitter electrode is in contact with the second side of the gate dielectric layer;

[0031] A collector electrode is formed on the back side of the P-type substrate.

[0032] A third aspect of the embodiments of the present application further provides a chip, comprising an IGBT with improved turn-off loss as described in any of the above embodiments.

[0033] The beneficial effects of the embodiments of the present application are as follows: by setting the carrier storage layer to be a stepped structure, the bottom of the carrier storage layer covers the N-type drift region, the P-type base region is formed on the first step of the carrier storage layer, the N-type emitter doped region and the P-type emitter doped region are formed on the horizontal portion of the P-type base region of the L-shaped structure, the N-type doped region is formed in the groove of the top step of the carrier storage layer, the gate dielectric layer is formed on the top step of the carrier storage layer, the gate dielectric layer wraps the gate polysilicon layer and the gate polysilicon layer is opposite to the N-type doped region, the P-type well region is formed on the top step of the carrier storage layer and is parallel to the gate dielectric layer, thereby reducing the gate area, changing the capacitance between the collector and the emitter, and adding an additional current extraction channel, thereby further reducing the turn-off loss of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of the structure of the IGBT with improved turn-off loss provided in the embodiment of the present application Figure 1 ;

[0035] Figure 2 Schematic diagram of the structure of the IGBT with improved turn-off loss provided in the embodiment of the present application Figure 2 ;

[0036] Figure 3a A simulation schematic diagram of a comparative structure provided in an embodiment of the present application;

[0037] Figure 3b A simulation schematic diagram of an improved structure provided in an embodiment of the present application;

[0038] Figure 4 A comparison diagram of device parameters of a comparative structure and an improved structure provided in an embodiment of the present application;

[0039] Figure 5 A comparison diagram of output characteristic curve simulation results of a comparative structure and an improved structure provided in an embodiment of the present application;

[0040] Figure 6 A comparison diagram of transfer characteristic curve simulation results of a comparative structure and an improved structure provided in an embodiment of the present application;

[0041] Figure 7 A comparison diagram of switching characteristic curve simulation results of a comparative structure and an improved structure provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram showing the effect of the width of the N-type doped region of the improved structure provided in an embodiment of the present application on the electrical parameters of the device;

[0043] Fig. 9 A schematic diagram showing the effect of the vertical distance between the lower surface of the P-type well region and the bottom of the gate oxide on the electrical parameters of the device in the improved structure provided in an embodiment of the present application;

[0044] Fig.10 It is a schematic flow chart of a method for preparing an IGBT with improved turn-off loss provided in an embodiment of the present application;

[0045] Fig.11 It is a schematic diagram of forming an N-type drift region, a carrier storage layer and an N-type doping region provided in an embodiment of the present application;

[0046] Fig.12 It is a schematic diagram of forming a gate dielectric layer, a gate polysilicon layer and a P-type well region provided by an embodiment of the present application;

[0047] Fig.13 It is a schematic diagram of forming an N-type buffer layer and a P-type substrate provided in an embodiment of the present application;

[0048] Fig.14 It is a schematic diagram of forming a P-type base region, an N-type emitter doping region, and a P-type emitter doping region provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0051] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0053] IGBT is a bipolar device. When it is turned on, a large number of holes will be generated. Its switching speed is inevitably affected by the minority carriers. At the same time, the switching speed of the device is also related to the capacitance of the device. By reducing the gate area, the capacitance can be reduced, but it will affect the other static parameters of the device to a certain extent.

[0054] In order to solve the above technical problems, the embodiment of the present application provides an IGBT with improved turn-off loss, see Figure 1 As shown, the IGBT with improved turn-off loss in this embodiment includes: a P-type substrate 110, an N-type buffer layer 120, an N-type drift region 130, a carrier storage layer 210, a P-type base region 220, an N-type emitter doping region 230, a P-type emitter doping region 240, an N-type doping region 211, a gate dielectric layer 250, a gate polysilicon layer 251, a P-type well region 260, a collector 310 and an emitter 320.

[0055] Among them, the N-type buffer layer 120 is formed on the front side of the P-type substrate 110, the N-type drift region 130 is formed on the N-type buffer layer 120, and the carrier storage layer 210 is formed on the N-type drift region 130. The carrier storage layer 210 is a stepped structure, and the bottom of the carrier storage layer 210 covers the N-type drift region 130. The P-type base region 220 is formed on the first step of the carrier storage layer 210, and the P-type base region 220 is an L-shaped structure; the N-type emitter doping region 230 and the P-type emitter doping region 240 are formed on the horizontal part of the P-type base region 220 of the L-shaped structure, and are isolated from the carrier storage layer 210 by the vertical part of the P-type base region 220. The N-type doping region 211 can be formed by injecting N-type doping ions into a part of the top step of the carrier storage layer 210, so that the top step of the carrier storage layer 210 forms at least one groove structure, the N-type doping region 211 is formed in the groove of the top step of the carrier storage layer 210, the gate dielectric layer 250 is formed on the top step of the carrier storage layer 210, the gate dielectric layer 250 wraps the gate polysilicon layer 251, and the gate polysilicon layer 251 is opposite to the N-type doping region 211. The P-type well region 260 is formed on the top step of the carrier storage layer 210 and contacts the first side of the gate dielectric layer 250. The emitter 320 contacts the N-type emitter doping region 230 and the P-type emitter doping region 240, and contacts the second side of the gate dielectric layer 250, and the collector 310 is formed on the back side of the P-type substrate 110.

[0056] In the embodiment of the present application, the carrier storage layer 210 is set to a stepped structure, the bottom of the carrier storage layer 210 covers the N-type drift region 130, the P-type base region of the L-shaped structure is formed on the first step of the carrier storage layer 210, the N-type emitter doping region 230 and the P-type emitter doping region 240 are formed on the horizontal portion of the P-type base region 220 of the L-shaped structure, the N-type doping region 211 is formed in the groove of the top step of the carrier storage layer 210, the gate dielectric layer 250 is formed on the top step of the carrier storage layer 210, the gate dielectric layer 250 wraps the gate polysilicon layer 251 and the gate polysilicon layer 251 is opposite to the N-type doping region 211, and the P-type well region 260 is formed on the top step of the carrier storage layer 210 and is parallel to the gate dielectric layer 250, thereby reducing the gate area, changing the capacitance between the collector and the emitter, and adding an additional current extraction channel, thereby further reducing the turn-off loss of the device.

[0057] In some embodiments, Figure 1As shown, the carrier storage layer 210 may include two steps, so that the carrier storage layer 210 has an L-shaped structure, and an L-shaped P-type base region 220 is formed on the horizontal portion of the L-shaped carrier storage layer 210, and an N-type emitter doping region 230 and a P-type emitter doping region 240 are formed on the horizontal portion of the L-shaped P-type base region 220. The N-type emitter doping region 230 is isolated from the carrier storage layer 210 by the vertical portion of the P-type base region 220, and an emitter 320 is formed on the N-type emitter doping region 230 and the P-type emitter doping region 240.

[0058] In some embodiments, the top step of the carrier storage layer 210 may be formed into a plurality of N-type doping regions 211 by doping a plurality of designated regions thereof, wherein the plurality of N-type doping regions 211 are arranged in sequence and contact the gate dielectric layer 250 .

[0059] In some embodiments, the P-type well region 260 has a stepped structure.

[0060] In this embodiment, the P-type well region 260 can be an inverted trapezoidal structure, which is wider at the top and narrower at the bottom. The depth of the P-type well region 260 gradually increases in the direction away from the carrier storage layer 210, which can facilitate better outflow of holes and reduce the impact of changes in the gate area on the device.

[0061] In some embodiments, for example, the P-type well region 260 may also be in an inverted triangle structure. The present application does not limit the specific structure of the P-type well region 260 .

[0062] In some embodiments, the interface between the P-type well region 260 and the gate dielectric layer 250 can be a trapezoidal interface. The P-type well region 260 is a stepped structure whose width gradually increases in the direction from the collector 310 to the emitter 320. The shape of the P-type well region 260 matches the shape of the gate dielectric layer 250, which can facilitate better outflow of holes while reducing the impact of changes in the gate area on the device.

[0063] In some embodiments, the doping concentration of the P-type well region 260 is graded doping.

[0064] In some embodiments, the doping concentration of the P-type well region 260 gradually decreases in a direction away from the carrier storage layer 210 .

[0065] In some embodiments, the width of the P-type well region 260 gradually increases in the direction from the collector 310 to the emitter 320, and the doping of the P-type well region 260 is gradient doping, with a low doping concentration at the top and a high doping concentration at the bottom, which can facilitate better outflow of holes and reduce the impact of changes in the gate area on the device.

[0066] In some embodiments, the emitter 320 is in contact with the gate dielectric layer 250 .

[0067] In some embodiments, the width of the top of the P-type well region 260 is at least twice the width of the contact surface between the P-type well region 260 and the carrier storage layer 210 .

[0068] In some embodiments, the doping concentration of the N-type doping ions in the N-type drift region 130 is less than the doping concentration of the N-type doping ions in the N-type buffer layer 120 .

[0069] In some embodiments, a PN junction is formed between the carrier storage layer 210 and the P-type base region 220 , and a PN junction is formed between the carrier storage layer 210 and the P-type well region 260 .

[0070] In some embodiments, the doping concentration of the P-type doping ions in the P-type emitter doping region 240 is greater than the doping concentration of the P-type doping ions in the P-type base region, and a PN junction is formed between the P-type base region 220 and the N-type emitter doping region 230 .

[0071] In order to better illustrate the improved structure proposed in the embodiment of the present application (ie, Figure 1 The innovation of the present application embodiment is that Figure 3a The comparative structure in FIG. 1 is used as a comparison, and the comparative structure does not include the N-type doping region 211 (N1) and the P-type well region 260 (P-well) in the improved structure. Figure 4 It can be seen from the characteristic parameter table in the embodiment of the present application that the improved structure ( Figure 1 Compared with the comparative structure, the gate and emitter voltage V GE is 0V, the collector current I CE When the current is 250uA, the collector-emitter breakdown voltage V CES Both are 841V; at the collector and emitter voltage V CE is 15V, collector current I CE When the gate voltage is 1A, the gate threshold voltage V GEth Both are 2.3V; at the collector and emitter voltage V GE is 15V, collector current I CE When the current is 1A, the on-state voltage V on Both are 0.87V. The collector and emitter voltage V GE is 300V, the maximum gate voltage V gmax When the voltage is 15V and the device on-resistance is 10Ω, the conduction loss E on The turn-off loss E is 10.2 mJ, which greatly improves the structure without affecting other electrical parameters. off , its turn-off loss E offReduced from 82mJ to 78mJ.

[0072] Combination Figure 5 The output characteristic curves in FIG. 1 show that the voltage V between the collector 310 and the emitter 320 of the comparison structure and the improved structure GE When the voltage V between the gate and the emitter 320 of the comparative structure and the improved structure is 15V, CE When the voltage increases from 0V to 15V, the output characteristic curve is consistent. Figure 5 Where Ic is the collector current and Vc is the collector voltage.

[0073] Combination Figure 6 It can be seen from the transfer characteristic curves in that when the voltage between the gate and the emitter 320 of the comparative structure and the improved structure is 15V, when the voltage between the collector 310 and the emitter 320 of the comparative structure and the improved structure increases from 0V to 15V, the transfer characteristic curves of the comparative structure and the improved structure are consistent. Figure 6 Where Ic is the collector current and Vg is the gate voltage.

[0074] Combination Figure 7 From the switching characteristic curve in the figure, we can see that the turn-off time of the improved structure is shorter and the turn-off loss is lower. Figure 7 Where Ic is the collector current, Vg is the gate voltage, and Vc is the collector voltage.

[0075] Figure 8 The influence of different widths of the N-type doping region 211 on the electrical parameters of the device is shown in FIG. Figure 8 As shown, the width of the N-type doping region 211 is reduced, which will reduce the collector current. When the width of the N-type doping region 211 is increased to 1um, its current basically matches the current of the comparative structure. Figure 8 Where Ic is the collector current and Vg is the gate voltage.

[0076] In some embodiments, the contact surface between the P-type well region 260 and the carrier storage layer 210 is located below the bottom of the gate oxide.

[0077] Specifically, the depth of the P-type well region 260 is related to the turn-off loss of the device, such as Fig. 9As shown, it is a schematic diagram of the influence of the vertical distance between the lower surface of the P-type well region 260 (i.e., the contact surface between the P-type well region 260 and the carrier storage layer 210) and the bottom of the gate oxide (i.e., the contact surface between the gate dielectric layer 250 and the carrier storage layer 210) on the electrical parameters of the device, wherein, when the lower surface of the P-type well region 260 is located below the bottom of the gate oxide (i.e., the lower surface of the P-type well region 260 penetrates into the carrier storage layer 210), the vertical distance between the lower surface of the P-type well region 260 and the bottom of the gate oxide is positive, when the lower surface of the P-type well region 260 is located above the bottom of the gate oxide, the vertical distance between the lower surface of the P-type well region 260 and the bottom of the gate oxide is negative, and when the lower surface of the P-type well region 260 is flush with the bottom of the gate oxide, the vertical distance between the lower surface of the P-type well region 260 and the bottom of the gate oxide is 0. Fig. 9 As shown, the deeper the lower surface of the P-type well region 260 penetrates into the carrier storage layer 210 and the closer it is to the N-type drift region 130, the faster the turn-off speed and the lower the turn-off loss. Fig. 9 Ic is the collector current, Vc is the collector voltage, Vg is the gate voltage, -0.1um-Ic means the collector current of the device when the lower surface of the P-type well region 260 is located 0.1um above the bottom of the gate oxide, -0.1um-Vc means the collector voltage of the device when the lower surface of the P-type well region 260 is located 0.1um above the bottom of the gate oxide; 0um-Ic means the collector current of the device when the lower surface of the P-type well region 260 is flush with the bottom of the gate oxide, 0um-Vc means the collector voltage of the device when the lower surface of the P-type well region 260 is flush with the bottom of the gate oxide; 0.5um-Ic means the collector current of the device when the lower surface of the P-type well region 260 is located 0.5um below the bottom of the gate oxide, 0.5um-Vc means the collector voltage of the device when the lower surface of the P-type well region 260 is located 0.5um below the bottom of the gate oxide.

[0078] In this embodiment, the width of the P-type well region 260 gradually increases in the direction from the collector 310 to the emitter 320. The shape of the P-type well region 260 matches the shape of the gate dielectric layer 250, which can facilitate better outflow of holes while reducing the impact of changes in the gate area on the device.

[0079] The present application also provides a method for preparing an IGBT with improved turn-off loss, see Fig.10 As shown, the preparation method in this embodiment includes steps S100 to S800.

[0080] In step S100 , an N-type drift region 130 is formed by epitaxial growth on the front side of an N-type substrate.

[0081] In this embodiment, an N-type drift region 130 may be formed on the front surface of the N-type substrate by an epitaxial process.

[0082] In one embodiment, the N-type substrate and the N-type drift region 130 have the same N-type doping ion doping concentration.

[0083] In step S200 , an N-type silicon material is epitaxially grown on the N-type drift region 130 , and ion implantation is performed to form a carrier storage layer 210 and an N-type doping region 211 .

[0084] In this embodiment, combined with Fig.11 As shown, N-type silicon material can continue to be epitaxially grown on the N-type drift region 130, and ion implantation can be performed to form a carrier storage layer 210 and an N-type doping region 211, and the doping concentration of the N-type doping region 211 is much greater than the doping concentration of the carrier storage layer 210. After the N-type doping region 211 is formed, the top step of the finally formed carrier storage layer 210 is made to have a concave-convex structure.

[0085] In some embodiments, when N-type doping ions are implanted into the upper portion of the carrier storage layer 210, the shape of the N-type doping region 211 can be adjusted by adjusting the ion implantation direction. For example, by adjusting the ion implantation direction, the N-type doping region 211 can be set to a shape that is narrow at the bottom and wide at the top, and its doping concentration can also be set to a lower doping concentration at the bottom and a higher doping concentration at the top.

[0086] In step S300 , a gate dielectric layer 250 and a gate polysilicon layer 251 are formed on the carrier storage layer 210 . The gate dielectric layer 250 wraps the gate polysilicon layer 251 , and the gate polysilicon layer 251 is opposite to the N-type doping region 211 .

[0087] See also Fig.12 As shown, in this embodiment, a gate dielectric material can be first deposited on the carrier storage layer 210, and then a groove can be formed by etching the gate dielectric material, and a gate polysilicon material can be deposited in the groove to form a gate polysilicon layer 251, and then the surface of the gate polysilicon layer 251 can be oxidized to obtain a gate dielectric layer 250 that wraps the gate polysilicon layer 251.

[0088] In step S400 , a P-type well region 260 is epitaxially grown on the carrier storage layer 210 , and the P-type well region 260 is in contact with the first side of the gate dielectric layer 250 .

[0089] See also Fig.12 As shown, in this embodiment, a P-type silicon material may be epitaxially grown on the first side of the gate dielectric layer 250 , and a P-type well region 260 contacting the first side of the gate dielectric layer 250 may be formed on the carrier storage layer 210 .

[0090] In some embodiments, a single crystal silicon material may be deposited on the first side of the gate dielectric layer 250 and P-type dopant ions may be implanted into the single crystal silicon material to form a P-type well region 260. The shape of the P-type well region 260 may be adjusted by adjusting the implantation direction of the P-type dopant ions.

[0091] In step S500 , N-type dopant ions are implanted on the back side of the N-type substrate to form an N-type buffer layer 120 , and P-type dopant ions are implanted on the back side of the N-type buffer layer 120 to form a P-type substrate.

[0092] In this embodiment, see Fig.13 As shown, N-type doping ions are injected into the back side of the N-type substrate to form an N-type buffer layer 120, the concentration of N-type doping ions in the N-type buffer layer 120 is greater than the concentration of N-type doping ions in the N-type drift region 130, and the N-type buffer layer 120 is in contact with the N-type drift region 130, and P-type doping ions are injected into the back side of the N-type buffer layer 120 to form a P-type substrate, and the injection depth of the P-type doping ions is less than the injection depth of the N-type doping ions.

[0093] In step S600, N-type doping ions and P-type doping ions are implanted into a portion of the carrier storage layer 210 to form a P-type base region, an N-type emitter doping region 230 and a P-type emitter doping region 240, so that the carrier storage layer 210 has a stepped structure.

[0094] In this embodiment, combined with Fig.14 As shown, P-type ion implantation can be performed on various regions of the carrier storage layer 210, and the depth of the P-type ion implantation is different, so that the carrier storage layer 210 has a stepped structure, wherein a P-type base region is formed on the first step of the carrier storage layer 210, and then N-type ion implantation and P-type ion implantation are performed on a portion of the P-type base region to form an N-type emitter doping region 230 and a P-type emitter doping region 240, and a PN junction is formed between the N-type emitter doping region 230 and the P-type emitter doping region 240.

[0095] In some embodiments, see Fig.14 As shown, the P-type base region 220 is in an L-shaped structure, and the N-type emitter doping region 230 and the P-type emitter doping region 240 are formed on the horizontal portion of the P-type base region 220 of the L-shaped structure and isolated from the carrier storage layer by the vertical portion of the P-type base region.

[0096] In some embodiments, see Fig.14 As shown, in this embodiment, the width of the N-type emitter doping region 230 is the same as the width of the P-type emitter doping region 240, and the thickness of the N-type emitter doping region 230 is the same as the thickness of the P-type emitter doping region 240. The sum of the width of the N-type emitter doping region 230 and the width of the P-type emitter doping region 240 is equal to the width of the horizontal portion of the P-type base region 220.

[0097] In step S700 , an emitter electrode contacting the N-type emitter doping region 230 and the P-type emitter doping region 240 is formed.

[0098] In this embodiment, combined with Figure 1 As shown, the emitter 320 contacts the second side of the gate dielectric layer 250 .

[0099] In step S800 , a collector electrode is formed on the back surface of the P-type substrate 110 .

[0100] In some embodiments, the doping concentration of the N-type doping ions in the N-type drift region 130 is less than the doping concentration of the N-type doping ions in the N-type buffer layer 120 .

[0101] In some embodiments, a PN junction is formed between the carrier storage layer 210 and the P-type base region 220 , and the doping concentration of the P-type doping ions in the P-type emitter doping region 240 is lower than the doping concentration of the P-type doping ions in the P-type base region 220 .

[0102] An embodiment of the present application also provides a chip, comprising an IGBT with improved turn-off loss as in any of the above embodiments.

[0103] In this embodiment, the chip includes a chip substrate, on which one or more IGBTs with improved turn-off loss are arranged. The IGBT with improved turn-off loss can be prepared by the preparation method in any of the above embodiments, or the IGBT with improved turn-off loss in any of the above embodiments can be arranged on the chip substrate.

[0104] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate and form an integrated circuit with an IGBT that improves turn-off loss.

[0105] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0106] The beneficial effects of the embodiments of the present application are as follows: by setting the carrier storage layer to be a stepped structure, the bottom of the carrier storage layer covers the N-type drift region, the P-type base region is formed on the first step of the carrier storage layer, the N-type emitter doped region and the P-type emitter doped region are formed on the horizontal portion of the P-type base region of the L-shaped structure, the N-type doped region is formed in the groove of the top step of the carrier storage layer, the gate dielectric layer is formed on the top step of the carrier storage layer, the gate dielectric layer wraps the gate polysilicon layer and the gate polysilicon layer is opposite to the N-type doped region, the P-type well region is formed on the top step of the carrier storage layer and is parallel to the gate dielectric layer, thereby reducing the gate area, changing the capacitance between the collector and the emitter, and adding an additional current extraction channel, thereby further reducing the turn-off loss of the device.

[0107] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0108] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0109] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0110] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0111] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An IGBT with improved turn-off loss, characterized in that: include: A P-type substrate and an N-type buffer layer, wherein the N-type buffer layer is formed on the front side of the P-type substrate; An N-type drift region, wherein the N-type drift region is formed on the N-type buffer layer; A carrier storage layer is formed on the N-type drift region, the carrier storage layer is a stepped structure, and the bottom of the carrier storage layer covers the N-type drift region; A P-type base region is formed on the first step of the carrier storage layer, and the P-type base region has an L-shaped structure; An N-type emitter doping region and a P-type emitter doping region are formed on a horizontal portion of the P-type base region of the L-shaped structure and isolated from the carrier storage layer by a vertical portion of the P-type base region; An N-type doped region is formed in a groove of a top step of the carrier storage layer; A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the top step of the carrier storage layer, the gate dielectric layer wraps the gate polysilicon layer, and the gate polysilicon layer is opposite to the N-type doped region; A P-type well region is formed on a top step of the carrier storage layer and is in contact with a first side of the gate dielectric layer; an emitter electrode, contacting the N-type emitter doping region and the P-type emitter doping region, and contacting the second side of the gate dielectric layer; The collector is formed on the back side of the P-type substrate; the interface between the P-type well region and the gate dielectric layer is a trapezoidal interface, and the P-type well region is a stepped structure whose width gradually increases in the direction from the collector to the emitter.

2. The IGBT with improved turn-off loss according to claim 1, characterized in that: The doping concentration of the P-type well region is graded doping.

3. The IGBT with improved turn-off loss according to claim 2, characterized in that: The doping concentration of the P-type well region gradually decreases in a direction away from the carrier storage layer.

4. The IGBT with improved turn-off loss according to claim 1, characterized in that: The emitter is in contact with the gate dielectric layer.

5. The IGBT with improved turn-off loss according to any one of claims 1 to 4, characterized in that: A PN junction is formed between the carrier storage layer and the P-type base region, and a PN junction is formed between the carrier storage layer and the P-type well region.

6. The IGBT with improved turn-off loss according to any one of claims 1 to 4, characterized in that: The doping concentration of the P-type doping ions in the P-type emitter doping region is greater than the doping concentration of the P-type doping ions in the P-type base region, and a PN junction is formed between the P-type base region and the N-type emitter doping region.

7. A preparation method for preparing an IGBT with improved turn-off loss as claimed in any one of claims 1 to 6, characterized in that: The preparation method comprises: An N-type drift region is formed by epitaxy on the front side of the N-type substrate; Epitaxially growing an N-type silicon material on the N-type drift region, and performing ion implantation to form a carrier storage layer and an N-type doped region; wherein the N-type doped region is formed in a groove of the carrier storage layer; forming a gate dielectric layer and a gate polysilicon layer on the carrier storage layer, wherein the gate dielectric layer wraps the gate polysilicon layer, and the gate polysilicon layer is opposite to the N-type doping region; epitaxially growing a P-type well region on the carrier storage layer, wherein the P-type well region contacts the first side of the gate dielectric layer; Implanting N-type doping ions on the back side of the N-type substrate to form an N-type buffer layer, and implanting P-type doping ions on the back side of the N-type buffer layer to form a P-type substrate; N-type doping ions and P-type doping ions are implanted into a partial area of ​​the carrier storage layer to form a P-type base region, an N-type emitter doping region and a P-type emitter doping region, so that the carrier storage layer has a stepped structure; wherein the P-type base region is formed on the first step of the carrier storage layer, and the P-type base region has an L-shaped structure; the N-type emitter doping region and the P-type emitter doping region are formed on the horizontal portion of the P-type base region of the L-shaped structure, and are isolated from the carrier storage layer by the vertical portion of the P-type base region; forming an emitter electrode in contact with the N-type emitter doping region and the P-type emitter doping region; wherein the emitter electrode is in contact with the second side of the gate dielectric layer; A collector is formed on the back side of the P-type substrate; the interface between the P-type well region and the gate dielectric layer is a trapezoidal interface, and the P-type well region is a stepped structure whose width gradually increases in the direction from the collector to the emitter.

8. A chip, characterized in that: An IGBT with improved turn-off loss comprising the IGBT as claimed in any one of claims 1 to 6.

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