Semiconductor packaging structure and manufacturing method thereof, power device, and electronic device

Abstract

The present disclosure relates to a semiconductor packaging structure and a manufacturing method thereof, a power device, and an electronic device. The semiconductor packaging structure includes a wafer, a first crimping assembly, and a second crimping assembly. The first crimping assembly includes a cathode located on the first side of the wafer and used for rigidly crimping the first side surface of the wafer. The second crimping assembly includes an anode located on the second side of the wafer and used for rigidly crimping the second side surface of the wafer. The second side surface is opposite to the first side surface. The thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3. The present disclosure is conducive to reducing the junction-to-shell thermal resistance of the device, so as to further improve the heat dissipation efficiency and the current carrying capacity of the device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure and a manufacturing method thereof, a power device, and an electronic device. Background Art

[0002] Power devices, also known as power electronic devices, refer to power semiconductor devices that are capable of handling high voltages and high currents. Power devices are mainly used in power conversion and control circuits of power equipment. As the heat generated per unit area of ​​power devices increases, in order to quickly dissipate the heat, higher requirements are placed on the heat dissipation performance of the semiconductor packaging structure in power devices. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor packaging structure and a manufacturing method thereof, a power device, and an electronic device, which are beneficial to reducing the device junction-shell thermal resistance to further improve the device heat dissipation efficiency and the device current flow capacity.

[0004] In order to achieve the above-mentioned objectives, in a first aspect, some embodiments of the present disclosure provide a semiconductor packaging structure, including: a wafer, a first crimping assembly, and a second crimping assembly. The first crimping assembly includes a cathode located on a first side of the wafer and used for rigidly crimping the first side surface of the wafer. The second crimping assembly includes an anode located on a second side of the wafer and used for rigidly crimping the second side surface of the wafer. Wherein, the second side surface is opposite to the first side surface. The thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3.

[0005] In some embodiments of the present disclosure, a ratio of a series thermal resistance of the first thermal resistor and the second thermal resistor to a parallel thermal resistance of the first thermal resistor and the second thermal resistor ranges from 4.3 to 20.

[0006] In some embodiments of the present disclosure, the thickness of one of the cathode and the anode is smaller than the thickness of the other; wherein the ratio of the smaller thickness to the larger thickness is less than or equal to 0.6.

[0007] In some embodiments of the present disclosure, the cathode and / or the anode are solid electrodes; or, the cathode and / or the anode are hollow electrodes.

[0008] In some examples, the cathode and / or the anode is a hollow electrode. For example, the hollow electrode includes an electrode body, a water inlet and a water outlet are provided on the crimping surface of the electrode body facing away from the wafer, a fluid channel connecting the water inlet and the water outlet is provided inside the electrode body, and the water inlet and the water outlet are used to connect to a radiator. Or, for example, the hollow electrode includes at least an electrode layer and a flow channel layer stacked in sequence in a direction close to the wafer; the electrode layer has a water inlet through hole and a water outlet through hole for connecting to the radiator; the flow channel layer has a fluid channel connecting the water inlet through hole and the water outlet through hole.

[0009] In some embodiments of the present disclosure, the hollow electrode includes: an electrode layer and a flow channel layer stacked in sequence along a direction close to the wafer. The flow channel layer includes: a manifold layer and a microchannel layer. The manifold layer is located on the side of the electrode layer close to the wafer, and includes a first hollow pattern and a second hollow pattern that are separated and arranged, the first hollow pattern is connected to the water inlet through hole, and the second hollow pattern is connected to the water outlet through hole. The microchannel layer is located on the side of the manifold layer close to the wafer, and includes a plurality of microchannels that are separated and arranged; the microchannels are connected to the first hollow pattern and the second hollow pattern. Wherein, the fluid channel is composed of the first hollow pattern, the microchannel and the second hollow pattern.

[0010] In some embodiments of the present disclosure, the electrode layer and the manifold layer are an integrated structure. Alternatively, the manifold layer and the microchannel layer are an integrated structure.

[0011] In some embodiments of the present disclosure, the first crimping assembly includes one or more first subassemblies; the first thermal resistance is the sum of the body thermal resistance of each first subassembly and the contact thermal resistance between each first subassembly and an adjacent first device, wherein the adjacent first device includes other first subassemblies or wafers in contact with the corresponding first subassembly. The second crimping assembly includes one or more second subassemblies; the second thermal resistance is the sum of the body thermal resistance of each second subassembly and the contact thermal resistance between each second subassembly and an adjacent second device, wherein the adjacent second device includes other second subassemblies or wafers in contact with the corresponding second subassembly. The series thermal resistance of the first thermal resistance and the second thermal resistance is: the sum of the first thermal resistance and the second thermal resistance. The parallel thermal resistance of the first thermal resistance and the second thermal resistance is: the product of the first thermal resistance and the second thermal resistance divided by the sum of the first thermal resistance and the second thermal resistance.

[0012] In some possible embodiments, the first crimping assembly includes a first subassembly, the first subassembly is a cathode. The second crimping assembly includes a second subassembly, the second subassembly is an anode. The cathode and the anode are both directly connected to the wafer. Accordingly, the first thermal resistance is the sum of the body thermal resistance of the cathode and the first contact thermal resistance between the cathode and the wafer. The second thermal resistance is the sum of the body thermal resistance of the anode and the second contact thermal resistance between the anode and the wafer.

[0013] Based on this, illustratively, both the cathode and the anode are thermally conductive composite electrodes.

[0014] In some other possible implementations, the semiconductor packaging structure further includes: a transition layer; wherein one of the cathode and the anode is directly connected to the wafer, and the other is connected to the wafer through the transition layer.

[0015] In some embodiments of the present disclosure, the first crimping assembly includes a cathode and a transition layer, and the transition layer is located between the wafer and the cathode. Accordingly, the first thermal resistance is the sum of the body thermal resistance of the transition layer, the third contact thermal resistance between the transition layer and the wafer, the body thermal resistance of the cathode, and the fourth contact thermal resistance between the cathode and the transition layer. The second thermal resistance is the sum of the body thermal resistance of the anode and the second contact thermal resistance between the anode and the wafer.

[0016] In some other embodiments of the present disclosure, the second crimping assembly includes an anode and a transition layer, and the transition layer is located between the wafer and the anode. Accordingly, the first thermal resistance is the sum of the body thermal resistance of the cathode and the first contact thermal resistance between the cathode and the wafer. The second thermal resistance is the sum of the body thermal resistance of the transition layer, the fifth contact thermal resistance between the transition layer and the wafer, the body thermal resistance of the anode, and the sixth contact thermal resistance between the anode and the transition layer.

[0017] Based on this, illustratively, the electrodes directly connected to the wafer in the cathode and the anode are thermally conductive composite electrodes, and the electrodes connected to the wafer through the transition layer in the cathode and the anode are metal electrodes.

[0018] In some other possible embodiments, the first crimping assembly includes a cathode and a first transition layer, the first transition layer is located between the cathode and the wafer and connects the cathode and the wafer. The second crimping assembly includes an anode and a second transition layer, the second transition layer is located between the anode and the wafer and connects the anode and the wafer. Accordingly, the first thermal resistance is the sum of the body thermal resistance of the first transition layer, the seventh contact thermal resistance between the first transition layer and the wafer, the body thermal resistance of the cathode, and the eighth contact thermal resistance between the cathode and the first transition layer. The second thermal resistance is the sum of the body thermal resistance of the second transition layer, the ninth contact thermal resistance between the second transition layer and the wafer, the body thermal resistance of the anode, and the tenth contact thermal resistance between the anode and the second transition layer.

[0019] Based on this, illustratively, both the cathode and the anode are metal electrodes.

[0020] In a second aspect, some embodiments of the present disclosure also provide a method for manufacturing a semiconductor packaging structure, which is used to prepare the semiconductor packaging structure described in any of the above embodiments. The manufacturing method includes: crimping a first crimping assembly on the first side of a wafer; crimping a second crimping assembly on the second side of the wafer; wherein the first crimping assembly includes a cathode for rigidly crimping the first side surface of the wafer. The second crimping assembly includes an anode for rigidly crimping the second side surface of the wafer. The second side surface is opposite to the first side surface. The thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3.

[0021] In a third aspect, some embodiments of the present disclosure further provide a power device, including a thyristor or a diode. The thyristor or the diode includes the semiconductor package structure as described in any of the above embodiments.

[0022] In a fourth aspect, some embodiments of the present disclosure further provide an electronic device, comprising a power device as described in any of the above embodiments.

[0023] The embodiments of the present disclosure may or at least have the following advantages:

[0024] In the embodiment of the present disclosure, the thermal resistance on the first side of the wafer is the first thermal resistance, and the thermal resistance on the second side of the wafer is the second thermal resistance. By setting the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance and their parallel thermal resistance to be greater than or equal to 4.3, the offset packaging of the wafer can be controlled, thereby utilizing the technical principle that the parallel thermal resistance of the first thermal resistance and the second thermal resistance will be smaller than the thermal resistance on either side when the wafer dissipates heat on both sides, and reducing the thermal resistance of the first side or the second side of the wafer as much as possible, thereby achieving a significant reduction in the parallel thermal resistance of the semiconductor packaging structure, thereby effectively reducing the junction-shell thermal resistance of the semiconductor packaging structure, and further effectively improving the heat dissipation efficiency and flow capacity of the semiconductor packaging structure.

[0025] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1is a schematic structural diagram of a semiconductor packaging structure provided in some embodiments;

[0028] Figure 2 A schematic diagram of a corresponding relationship between a series-parallel proportional coefficient β and an x ​​ratio provided in some embodiments; wherein the x ratio is a ratio of a single-side thermal resistance to a series thermal resistance;

[0029] Figure 3 is a schematic structural diagram of a solid electrode provided in some embodiments;

[0030] Figure 4 is a schematic structural diagram of another solid electrode provided in some embodiments;

[0031] Figure 5 A three-dimensional schematic diagram of a longitudinal section of a solid electrode provided in some embodiments;

[0032] Figure 6 A schematic cross-sectional view of a longitudinal section of a hollow electrode provided in some embodiments;

[0033] Figure 7 A three-dimensional schematic diagram of a longitudinal section of a hollow electrode provided in some embodiments;

[0034] Figure 8 is a schematic cross-sectional view of a longitudinal section of an electrode layer provided in some embodiments;

[0035] Fig. 9 A three-dimensional schematic diagram of a longitudinal section of an electrode layer provided in some embodiments;

[0036] Fig.10 A three-dimensional schematic diagram of a manifold layer provided in some embodiments;

[0037] Fig.11 is a schematic top view of a manifold layer provided in some embodiments;

[0038] Fig.12 A schematic cross-sectional view of a longitudinal section of a microchannel layer provided in some embodiments;

[0039] Fig.13 is a schematic top view of a microchannel layer provided in some embodiments;

[0040] Fig.14 A three-dimensional schematic diagram of a flow channel layer provided in some embodiments;

[0041] Fig.15 is a schematic top view of a flow channel layer provided in some embodiments;

[0042] Fig.16A three-dimensional schematic diagram of an electrode layer and a manifold layer as an integrated structure provided in some embodiments;

[0043] Fig.17 is a schematic structural diagram of another semiconductor packaging structure provided in some embodiments;

[0044] Fig.18 for Fig.17 A schematic cross-sectional view of a semiconductor packaging structure from a three-dimensional perspective is shown;

[0045] Fig.19 It is a structural schematic diagram of another semiconductor packaging structure provided in some embodiments.

[0046] Description of reference numerals:

[0047] 1-wafer, 2-cathode, 3-anode, 4-first flange, 5-tube shell, 6-second flange, 7-first transition layer, 8-second transition layer, 9-hollow electrode, 91-electrode layer, H1-water inlet through hole, H2-water outlet through hole, H3-positioning hole, 92-manifold layer, 921-partition, F1-first hollow pattern, F2-second hollow pattern, 93-microchannel layer, 931-microchannel, 10-diamond composite metal electrode, 101-diamond composite metal base layer, 102-first alloy layer, 103-second alloy layer, 104-conductive flange. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0051] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0052] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] In the related art, press-fit power semiconductor devices are usually designed as symmetrical structures, that is, the wafer is set at the center of the device, and the cathode and anode are roughly symmetrically set on both sides of the wafer. In this way, after the wafer is heated, the heat can be dissipated along two paths above and below the wafer to ensure the heat dissipation requirements of the power semiconductor device. However, it is difficult to further reduce the thermal resistance of the device and improve the current carrying capacity of the device by adopting the aforementioned symmetrical structure of the power semiconductor device.

[0054] Based on this, the embodiments of the present disclosure provide a semiconductor packaging structure and a manufacturing method thereof, a power device, and an electronic device, which can improve the heat transfer efficiency of the device electrode, reduce the device junction-shell thermal resistance, and make the wafer junction temperature lower when the device is working, so as to improve the rated current capacity of the device, thereby meeting the further heat dissipation requirements of the press-fit power semiconductor device.

[0055] See also Figure 1 Some embodiments of the present disclosure provide a semiconductor packaging structure, including: a wafer 1, a first crimping assembly, and a second crimping assembly. The first crimping assembly includes a cathode 2 located on a first side of the wafer 1 and used for rigidly crimping the first side surface of the wafer 1. The second crimping assembly includes an anode 3 located on a second side of the wafer 1 and used for rigidly crimping the second side surface of the wafer 1. The second side surface is opposite to the first side surface. The thermal resistance of the first side of the wafer 1 is a first thermal resistance R th-A , the thermal resistance of the second side of wafer 2 is the second thermal resistance R th-K ; The first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance and the first thermal resistance R th-A and the second thermal resistance R th-K The ratio of parallel thermal resistance is greater than or equal to 4.3.

[0056] Here, the cathode 2 is used for rigidly pressing the first side surface of the wafer 1, including direct pressing when the cathode 2 is adjacent to the wafer 1, and also including indirect pressing when other sub-components are provided between the cathode 2 and the wafer 1. Similarly, the anode 3 is used for rigidly pressing the second side surface of the wafer 1, including direct pressing when the anode 3 is adjacent to the wafer 1, and also including indirect pressing when other sub-components are provided between the anode 3 and the wafer 1.

[0057] It should be noted that the wafer 1 mentioned in the embodiment of the present disclosure is not a blank wafer, but a chip wafer formed based on the whole wafer; that is, a whole wafer is prepared as a chip, and the wafer 1 is a wafer chip. The semiconductor packaging structure provided in the embodiment of the present disclosure is a whole wafer press-fit packaging.

[0058] Furthermore, the semiconductor packaging structure provided by the embodiment of the present disclosure is a crimping type structure, which can be specifically manifested as follows: each crimping component in the semiconductor packaging structure is independently arranged, and can maintain a good contact state and produce good electrical and thermal conductivity through pressure; however, after the pressure is removed, the contact interface between each crimping component or some subcomponents in the crimping component can maintain a contact state or a separation state (that is, there can be a gap between adjacent components or adjacent subcomponents). In addition, in actual application, the semiconductor packaging structure needs to apply pressure to achieve rigid crimping (including indirect crimping) between the cathode 2 and / or the anode 3 and the wafer 1. The semiconductor packaging structure has the advantages of strong current flow capacity, easy series connection, and short circuit state after failure.

[0059] The rigid crimping mentioned in the embodiments of the present disclosure is relative to the elastic crimping, wherein the rigid crimping means that the compression deformation of the crimping assembly or crimping subassembly is mainly achieved by the elastic deformation of its material itself; the elastic crimping means that the compression deformation of the crimping assembly or crimping subassembly is mainly achieved by the structural deformation of the spring or disc spring. Furthermore, the essential difference between rigid crimping and elastic crimping is also reflected in: there is an order of magnitude difference in the amount of deformation under the same pressure, for example, the compression deformation amount in rigid crimping is usually at the μm level, and the compression deformation amount in elastic crimping is usually at the mm level.

[0060] What needs to be explained is that please combine Figure 2 Understanding, the applicant defines the first thermal resistance R th-A and the second thermal resistance R th-K The thermal resistance R th-series The parallel thermal resistance R th-paral The ratio of is the series-parallel connection number β, and the calculation formula of the series-parallel connection number β can be derived as follows:

[0061] The first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-seriesSatisfies formula (1): , (1).

[0062] The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-paral Satisfies formula (2): , (2).

[0063] The series-parallel connection number β satisfies formula (3): , (3).

[0064] Here, x is the single-side thermal resistance of the wafer (for example, the first thermal resistance R th-A Or the second thermal resistance R th-K ) and the series thermal resistance R th-series ratio.

[0065] The applicant has studied and calculated and found that if Figure 2 It can be seen that if the semiconductor packaging structure adopts a symmetrical or approximately symmetrical packaging structure, the upper and lower thermal resistances are the same, for example, the value of x is approximately 0.5, and the series-parallel ratio coefficient β is 4.0; if the series-parallel ratio coefficient β is increased, then according to the series-parallel ratio coefficient β and the first thermal resistance R th-A And the second thermal resistance R th-K The corresponding relationship between the design of semiconductor packaging structure and the design of asymmetric packaging structure (also called offset packaging structure) is that the wafer 1 can be designed to deviate by a preset size to either the cathode 2 or the anode 3 in a semiconductor packaging structure with a constant total height. In this way, when the total height of the semiconductor packaging structure is kept constant, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series can remain unchanged, but as the series-parallel ratio coefficient β increases, the first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-paral will decrease accordingly. And, according to Figure 2From the changing trend of the curve shown, it can be seen that in the process of the semiconductor packaging structure changing from a symmetrical or nearly symmetrical packaging structure to an asymmetrical packaging structure, the series-parallel proportional coefficient β gradually changes from a slow increase to a rapid increase; it can be seen that the effect of the offset degree of the semiconductor packaging structure on its parallel thermal resistance is nonlinear, that is, the effect is very small at the beginning and can be almost ignored, but as the offset degree increases, the parallel thermal resistance will decrease rapidly, so that the technical advantages of the offset packaging structure can be clearly manifested. In this way, the embodiment of the present disclosure can effectively design an offset packaging structure of the semiconductor packaging structure by adjusting the value range of the series-parallel proportional coefficient β to be greater than or equal to 4.3, for example, controlling it between 4.3 and 20, so as to achieve a significant reduction in the junction-to-shell thermal resistance of the semiconductor packaging structure and the power device.

[0066] The applicant matches the change of the series-parallel ratio coefficient β, and the junction-to-case thermal resistance R of the semiconductor packaging structure th The corresponding relationship between the series-parallel proportional coefficient β and the series-parallel proportional coefficient β was simulated and calculated: when the semiconductor packaging structure adopts a symmetrical packaging structure, the series-parallel proportional coefficient β is 4.0, and the junction-to-case thermal resistance of the semiconductor packaging structure at this time is 3.04K / kW; when the series-parallel proportional coefficient β of the semiconductor packaging structure is adjusted, for example, when the series-parallel proportional coefficient β is increased to 4.43, the junction-to-case thermal resistance of the semiconductor packaging structure will drop to 2.33K / kW, with a decrease of 23%; for example, when the series-parallel proportional coefficient β is increased to 5.77, the junction-to-case thermal resistance of the semiconductor packaging structure will drop to 1.78K / kW, with a decrease of 41%; for example, when the series-parallel proportional coefficient β is further increased to 7.88, the junction-to-case thermal resistance of the semiconductor packaging structure will drop to 1.56K / kW, with a decrease of 49%; and so on.

[0067] As described above, in the embodiment of the present disclosure, the thermal resistance of the first side of the wafer 1 is taken as the first thermal resistance R th-A , the thermal resistance of the second side of wafer 1 is the second thermal resistance R th-K and by setting the first thermal resistance R th-A and the second thermal resistance R th-K The thermal resistance R th-series The parallel thermal resistance R th-paral The ratio between them is greater than or equal to 4.3, which can control the offset packaging of the wafer 1, so that the first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-paral The technical principle is to reduce the thermal resistance of the first side or the second side of the wafer 1 as much as possible, thereby realizing the parallel thermal resistance R of the semiconductor packaging structure. th-paral The thermal resistance of the semiconductor package structure can be effectively reduced, thereby effectively improving the heat dissipation efficiency and flow capacity of the semiconductor package structure.

[0068] In some embodiments of the present disclosure, the first thermal resistance R th-A and the second thermal resistance R th-K The thermal resistance R th-series The parallel thermal resistance R th-paral The ratio ranges from 4.3 to 20.

[0069] In some preferred examples, the first thermal resistance R th-A and the second thermal resistance R th-K The thermal resistance R th-series The parallel thermal resistance R th-paral The ratio ranges from 4.3 to 8.

[0070] It should be added that, in some embodiments, please continue to refer to Figure 1 , the cathode 2 and the anode 3 both use tube shell electrodes. For example, the semiconductor packaging structure also includes a tube shell 5 sleeved on the wafer 1 and the cathode 2 and the anode 3. The cathode 2 can be used as a tube shell base, and the anode 3 can be used as a tube shell cover. The cathode 2 and the anode 3 are respectively welded and interconnected with the tube shell 5 through corresponding flanges (such as the first flange 4 and the second flange 6), thereby realizing the tube shell sealing of the wafer 1.

[0071] For example, the tube shell 5 includes but is not limited to an insulating ceramic ring, which can be used for high-voltage insulation, for example, to ensure that the creepage distance and electrical clearance meet the high-voltage requirements of 8.5 kV and above.

[0072] For example, the first flange 4 is located at the edge of the cathode 2 and can be interconnected with the cathode 2 by high temperature welding or be an integral structure.

[0073] For example, a high temperature welding process can also be used to interconnect gate components on the cathode 2; the gate components include, for example, a gate lead ring and a gate disc spring component. Among them, the gate disc spring component can be stacked by disc springs and gaskets. The gate disc spring component has a certain elasticity and will produce a certain displacement under pressure, and its main function is to realize the lead-out connection of the gate of the wafer 1.

[0074] For example, the second flange 6 is located at the edge of the anode 3 and can be interconnected with the anode 3 by high-temperature welding or be an integral structure.

[0075] In some embodiments, the wafer 1 is a power semiconductor chip, for example, a whole wafer of a gate commutated turn-off thyristor (GCT) silicon-based chip. The size of the wafer 1 can be 2 inches, 3 inches, 4 inches, 6 inches or 8 inches, etc. The thickness of the wafer 1 can range from 0.2 mm to 2 mm, for example.

[0076] By way of example, the wafer 1 includes an active area located in a central region and a terminal area located in an edge region, wherein the active area is a main current passing area and a heat generating area, and the terminal area is a main insulating area.

[0077] It is worth mentioning that the following embodiments of the present disclosure provide some possible implementation methods for adjusting the series-to-parallel ratio coefficient β, but are not limited thereto.

[0078] In some embodiments of the present disclosure, the thickness of the cathode 2 and the anode 3 are different. The embodiments of the present disclosure can adjust the series-parallel proportional coefficient β by adjusting the thickness of the cathode 2 and the anode 3. Specifically, the thickness of one of the cathode 2 and the anode 3 can be reduced while increasing the thickness of the other. In addition, the embodiments of the present disclosure can also adjust the thickness of the cathode 2 and the anode 3 while ensuring that the total height of the semiconductor packaging structure remains unchanged, so as to ensure the compatibility of the semiconductor packaging structure.

[0079] For example, the thickness of one of the cathode 2 and the anode 3 is smaller than the thickness of the other; wherein the ratio of the smaller thickness to the larger thickness is less than or equal to 0.6.

[0080] In other embodiments of the present disclosure, the structures of the cathode 2 and the anode 3 may be the same or similar, or different. For example, the cathode 2 and / or the anode 3 are solid electrodes. Alternatively, for example, the cathode 2 and / or the anode 3 are hollow electrodes.

[0081] In some embodiments, the thicker one of the cathode 2 and the anode 3 is a solid electrode, such as a thermally conductive composite material electrode, to achieve the corresponding regulation of its thermal resistance.

[0082] Optionally, the thermally conductive composite material electrodes include but are not limited to copper diamond composite materials electrodes, aluminum diamond composite materials electrodes, silver diamond composite materials electrodes, graphene metal composite materials electrodes, carbon nanotube metal composite materials electrodes, molybdenum copper alloy electrodes, tungsten copper alloy electrodes or iridium copper alloy electrodes and other composite materials electrodes with higher thermal conductivity.

[0083] In some embodiments of the present disclosure, please combine Figure 3~Figure 5 It is understood that the cathode 2 and / or the anode 3 adopts a diamond composite metal electrode 10. The structure of the diamond composite metal electrode 10 can be referred to the following description.

[0084] For example, Figure 3As shown in the figure, the diamond composite metal electrode 10 comprises: a diamond composite metal base layer 101 and a first alloy layer 102 and a second alloy layer 103 located on the upper and lower surfaces of the diamond composite metal base layer 101. The diamond composite metal base layer 101, the first alloy layer 102 and the second alloy layer 103 are an integrated structure. The surfaces of the first alloy layer 102 and the second alloy layer 103 facing away from the diamond composite metal base layer 101 are machined surfaces and can be used to directly contact the wafer 1.

[0085] For example, Figure 4 As shown, the diamond composite metal electrode 10 comprises: a diamond composite metal base layer 101, a first alloy layer 102 and a second alloy layer 103 located on the upper and lower surfaces of the diamond composite metal base layer 101, and a conductive flange 104 located on the side wall of the diamond composite metal base layer 101. The diamond composite metal base layer 101, the first alloy layer 102, the second alloy layer 103 and the conductive flange 104 are an integral structure. The surfaces of the first alloy layer 102 and the second alloy layer 103 facing away from the diamond composite metal base layer 101 are machined surfaces for directly contacting the wafer 1. The flange welding surface of the conductive flange 104 does not contain diamond components.

[0086] Illustratively, the flange welding surface of the conductive flange 104 is parallel to the machined surface of the first alloy layer 102 and / or the second alloy layer 103 .

[0087] Illustratively, the machined surface of first alloy layer 102 and / or second alloy layer 103 is a finely ground surface.

[0088] For example, the surface flatness of the machined surface of the first alloy layer 102 and / or the second alloy layer 103 is less than or equal to 10 μm, and the surface roughness Ra is less than or equal to 0.7 μm (eg, may be less than or equal to 0.5 μm).

[0089] In some examples, the thickness of the first alloy layer 102 and / or the second alloy layer 103 ranges from 0.1 mm to 0.2 mm, for example, 0.1 mm, 0.12 mm, 0.15 mm, 0.18 mm or 0.2 mm.

[0090] In some examples, the first alloy layer 102 and / or the second alloy layer 103 includes at least one of a molybdenum-copper alloy layer or a tungsten-copper alloy layer. Among them, the thermal expansion coefficient of molybdenum-copper / tungsten-copper is close to that of copper diamond, which is conducive to reducing thermal stress. Secondly, molybdenum-copper / tungsten-copper is easier to process and grind than diamond, so it is easy to process and obtain a machined surface for direct contact with the wafer, so as to keep the surface roughness and surface flatness of the package electrode to meet the design standards, and ensure that the uniformity of the pressure distribution of the package electrode can also meet the design requirements. In addition, it is also easy to process the required positioning holes on the outer shape of the package electrode.

[0091] In the disclosed embodiment, it is not only helpful to simplify the packaging structure of the semiconductor packaging device to avoid the failure of the wafer 1 due to large thermal stress, but also to take into account the performance requirements of the diamond composite metal electrode 10 in terms of high thermal conductivity and high electrical conductivity through the diamond composite metal base layer 101 and the first alloy layer 102 and the second alloy layer 103, so as to ensure that the diamond composite metal electrode 10 has good heat resistance, corrosion resistance, chemical stability and thermal and electrical conductivity, and effectively weld the flange through the flange welding surface of the conductive flange 104 without diamond components, so as to improve the welding strength and welding reliability of the flange, thereby effectively improving the molding quality and performance of the diamond composite metal electrode 10, and then effectively improving the packaging reliability of the semiconductor packaging device. In addition, in the disclosed embodiment, the diamond composite metal electrode 10 is also easy to have high compatibility, so as to be well compatible with various valve string press-fit structures.

[0092] For example, the thermal conductivity of the diamond composite metal electrode 10 is greater than 400 W / m·K. The thermal expansion coefficient of the diamond composite metal electrode 10 is less than 10e -6 / K, for example, less than 8e -6 / K.

[0093] In some embodiments of the present disclosure, the diamond composite metal base layer 101 includes: one or more layers of an aluminum diamond composite layer, a copper diamond composite layer, a molybdenum-copper alloy diamond composite layer, a tungsten-copper alloy diamond composite layer or a copper-graphene diamond composite layer.

[0094] In some examples, the diamond composite metal-based layer 101 is a copper diamond composite layer.

[0095] For example, the copper-diamond composite layer comprises: a plurality of surface-modified diamond particles and a copper matrix that is infiltrated to fill the gaps between the diamond particles.

[0096] In some examples, the diameter of the diamond particles ranges from, but is not limited to, 50 μm to 200 μm.

[0097] Optionally, the particle size of the diamond particles may be 50 μm, 60 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm or 200 μm, etc.

[0098] In some examples, the surface modification of the diamond particles can be achieved by, for example, coating a modified coating on the surface of the diamond particles using a chemical plating method, a magnetron sputtering method, or a sol-gel method.

[0099] In some examples, for electrode applications of high-power IGCT (Integrated Gate-Commutated Thyristor) devices, the material is required to have as high thermal conductivity as possible, as low thermal expansion coefficient (e.g., close to Si, 2.49×10 -6 / K), therefore, considering the interface effect, the volume fraction of diamond in the composition range of copper diamond or aluminum diamond materials can be controlled within 40%~70%, its thermal conductivity range can be controlled within 450W / m·K~600W / m·K, and the thermal expansion coefficient range can be controlled within 3.5×10 -6 / K~5.5×10 -6 / K.

[0100] For example, the diamond composite metal base layer 101 is a copper diamond composite layer. The material of the copper diamond composite layer includes a copper matrix and diamond particles, and the particle size of the diamond particles can be, for example, 100μm~300μm. Diamond has extremely high thermal conductivity and low thermal expansion coefficient. Therefore, the copper diamond composite layer obtained by combining diamond and copper has good heat dissipation performance. In this way, the diamond composite metal base layer 101 adopts a copper diamond composite layer, and the high thermal conductivity characteristics of copper diamond can be used to improve the thermal conductivity of the semiconductor packaging structure. In addition, the copper diamond composite layer can also achieve the combination and balance of the cathode 2 and / or the anode 3 in terms of thermal conductivity, thermal expansion and electrical conductivity by adjusting the filling ratio of diamond (that is, the volume ratio of copper to diamond).

[0101] For example, when the filling ratio of diamond particles in the copper-diamond composite layer is 30%, the electrical conductivity of the copper-diamond composite layer is 25% IACS, the thermal conductivity is 553 W / (m·K), and the average linear expansion coefficient thereof at 25°C to 125°C is 5.77 ppm / °C.

[0102] For example, when the filling ratio of diamond particles in the copper-diamond composite layer is 35%, the electrical conductivity of the copper-diamond composite layer is 22% IACS, the thermal conductivity is 584 W / (m·K), and the average linear expansion coefficient thereof at 25°C to 125°C is 5.62 ppm / °C.

[0103] For example, when the filling ratio of diamond particles in the copper diamond composite layer is 40%, the electrical conductivity of the copper diamond composite layer is 20% IACS, the thermal conductivity is 628 W / (m·K), and its average linear expansion coefficient at 25°C to 125°C is 5.55 ppm / °C.

[0104] In addition, in some examples, when the diamond composite metal base layer 101 is a copper diamond composite layer or an aluminum diamond composite layer, the diamond composite metal base layer 101 may have a diamond distribution concentration distributed in a radial gradient, so that the electrode has different thermal expansion coefficients in radial partitions; wherein, the closer to the center area of ​​the diamond composite metal electrode 10, the higher its thermal expansion coefficient. In this way, the thermal expansion coefficient of the diamond composite metal electrode 10 may be distributed in a gradient, which is conducive to further reducing the thermal stress of the electrode, thereby improving the reliability of the electrode.

[0105] For example, the thermal expansion coefficient of the central region of the diamond composite metal electrode 10 may be in the range of 5e -6 / K~7e -6 / K, the thermal expansion coefficient of the edge area of ​​the diamond composite metal electrode 10 can be 7e -6 / K~10e -6 / K.

[0106] For example, the difference in thermal expansion coefficient between the first alloy layer 102 and the electrode layer 101, and the difference in thermal expansion coefficient between the second alloy layer 103 and the electrode layer 101 are both less than the threshold value. That is, the thermal expansion coefficients of the first alloy layer 102, the second alloy layer 103, and the electrode layer 101 are close, which can reduce thermal stress mismatch and improve electrode life.

[0107] It should be added that, in some embodiments of the present disclosure, the conductive flange 104 of the diamond composite metal electrode 10 comprises a metal flange. The metal flange has the same metal component as the diamond composite metal base layer 101 .

[0108] Optionally, the metal flange and the diamond composite metal base layer 101 are integrally formed by infiltration or casting.

[0109] Illustratively, the conductive flange 104 is a pure copper flange or a copper alloy flange.

[0110] For example, the diamond composite metal base layer 101 is a copper diamond composite layer. The pure copper flange or the copper alloy flange can be prepared and formed in the same infiltration process or the same casting process as the diamond composite metal base layer 101.

[0111] In other embodiments of the present disclosure, the conductive flange 104 includes: a body made of the same material as the diamond composite metal base layer 101 and formed integrally, and a metal coating located on at least one side of the body. The surface of the metal coating facing away from the body is the flange welding surface.

[0112] For example, the thickness of the metal plating layer ranges from 2 μm to 8 μm; for example, it may be 2 μm, 3 μm, 5 μm, 6 μm, or 8 μm.

[0113] Illustratively, the metal plating layer includes, but is not limited to, a metal nickel layer.

[0114] For example, the metal coating layer may also cover the sidewalls of the diamond composite metal-based layer 101 .

[0115] In some embodiments of the present disclosure, the diamond composite metal electrode 10 further includes: a flange welded to the flange welding surface of the conductive flange 104. For example, the material of the flange welding surface of the conductive flange 104 is the same as that of the flange.

[0116] It should be added that in the related art, the flange is usually welded by cold pressure welding process, so as to use materials with better ductility to make it produce plastic deformation under pressure and realize interconnection at the metal atomic level. However, when the diamond composite metal electrode 10 adopts the diamond composite metal base layer 101, a large number of diamond particles will be exposed and dispersed on the surface of the diamond composite metal base layer 101, resulting in the inability of the solder to be evenly spread on the interface to be welded during the accumulation and melting process. The material difference between the flange and the diamond composite metal base layer 101 may cause the two to be unable to be tightly combined, resulting in welding failure. Therefore, the embodiment of the present disclosure integrally sets a conductive flange 104 on the side wall of the diamond composite metal base layer 101, and a high-reliability connection can be achieved with the flange through the flange welding surface of the conductive flange 104.

[0117] In other embodiments, the thicker one of the cathode 2 and the anode 3 is a hollow electrode to achieve the corresponding regulation of its thermal resistance.

[0118] For example, the hollow electrode includes an electrode body. A water inlet and a water outlet are provided on the crimping surface of the electrode body facing away from the wafer 1, and a fluid channel connecting the water inlet and the water outlet is provided inside the electrode body. The water inlet and the water outlet are used to connect to a radiator, and the fluid channel is used to hold and transmit a cooling medium. Here, the number of water inlets can be one or more. The number of water outlets can be one or more.

[0119] On this basis, optionally, the hollow electrode further comprises a crimping interface sealing device, which is arranged around the water inlet and the water outlet of the electrode body, and is used to form a sealing area around the water inlet and the water outlet after the electrode body and the radiator are crimped.

[0120] In some examples, the crimping interface sealing device includes, but is not limited to, a rubber sealing ring. A groove is provided on the electrode body around the water inlet and the water outlet to accommodate the aforementioned rubber sealing ring. Optionally, the rubber sealing ring is an O-ring. The outer diameter of the O-ring is the same as the outer diameter of the groove, and the cross-sectional diameter of the O-ring is, for example, greater than the depth of the aforementioned groove and less than the width of the aforementioned groove. After the O-ring is placed in the groove on the side of the corresponding water inlet or water outlet, the O-ring will be slightly higher than the crimping interface of the electrode body. In this way, when the radiator (such as a water-cooled plate) is crimped to the surface of the hollow electrode, the rubber sealing ring is deformed under pressure, and a sealing area around the water inlet and the water outlet can be generated on the crimping interface to achieve stable sealing of the inlet and outlet.

[0121] For example, please combine Figure 6 and Figure 7 It is understood that the hollow electrode 9 includes at least an electrode layer 91 and a flow channel layer stacked in sequence along a direction close to the wafer 1, wherein the electrode layer 91 has a water inlet through hole H1 and a water outlet through hole H2 for connecting to the radiator; the flow channel layer has a fluid channel connecting the water inlet through hole H1 and the water outlet through hole H2.

[0122] Here, the number of the water inlet through hole H1 and the water outlet through hole H2 may be one or more. Figure 8 and Fig. 9 Only one water inlet through hole H1 and one water outlet through hole H2 are used for illustration. In one example, the water inlet through hole H1 and the water outlet through hole H2 penetrate the electrode layer 91, adopting a through hole structure that passes straight through from top to bottom, and are centrally symmetrical with the center of the electrode layer 91. In addition, it can be understood that the apertures of the water inlet through hole H1 and the water outlet through hole H2 should be set to match the flow rate requirements of the radiator. For example, for an electrode layer 91 with a radial dimension of 6 inches, the apertures of the water inlet through hole H1 and the water outlet through hole H2 can range from 8mm to 15mm.

[0123] In some examples, the aforementioned crimping interface sealing device may also be provided around the water inlet through hole H1 and the water outlet through hole H2 of the electrode layer 91. The details will not be elaborated here.

[0124] In some examples, it can be understood that after the water inlet through hole H1 and the water outlet through hole H2 are set on the electrode layer 91, the electrode layer 91 will no longer be suitable for arbitrary rotation relative to the radiator; that is, the water inlet through hole H1 and the water outlet through hole H2 on the electrode layer 91 need to be precisely aligned with the water inlet / outlet of its external radiator (such as a water cooling plate) so that the cooling medium can be drawn out from the side of the radiator. Figure 8 and Fig. 9 A positioning hole H3 may be provided at the center of the electrode layer 91. The positioning hole H3 may be a square positioning pin hole, for example, to realize the rotational positioning constraint of the electrode layer 91, so as to ensure that the water inlet hole H1 and the water outlet hole H2 on the electrode layer 91 can be accurately aligned with the water inlet / outlet of the external radiator.

[0125] Please continue reading Figure 6 and Figure 7 The flow channel layer may be a single layer structure or a laminated structure. In some examples, the flow channel layer includes, for example, a manifold layer 92 and a microchannel layer 93 .

[0126] Please combine Figure 6 , Figure 7 , Fig.10 and Fig.11 It is understood that the manifold layer 92 is located on the side of the electrode layer 91 close to the wafer 1, and includes a first hollow pattern F1 and a second hollow pattern F2 that are separated, wherein the first hollow pattern F1 is connected to the aforementioned water inlet through hole H1, and the second hollow pattern F2 is connected to the aforementioned water outlet through hole H2. Optionally, the first hollow pattern F1 and the second hollow pattern F2 are separated and formed by a partition 921. The partition 921, for example, adopts an "M" shape, a "bow" shape or a serpentine structure to maximize the side wall area (i.e., the heat exchange area) of the first hollow pattern F1 and the second hollow pattern F2, thereby ensuring that the temperature distribution of the hollow electrode 9 is more uniform.

[0127] Optionally, the thickness of the manifold layer 92 includes but is not limited to 2 mm to 5 mm.

[0128] Optionally, the size of the first hollow pattern F1 connected to the water inlet hole H1 is not less than the aperture of the water inlet hole H1, and the size of the second hollow pattern F2 connected to the water outlet hole H2 is not less than the aperture of the water outlet hole H2 to ensure that the cooling medium can flow smoothly.

[0129] Please combine Figure 6 , Figure 7 , Fig.12 and Fig.13It is understood that the microchannel layer 93 is located on the side of the manifold layer 92 close to the wafer 1, and includes a plurality of microchannels 931 that are separated, that is, adjacent microchannels 931 are not connected. The microchannel 931 connects the aforementioned first hollow pattern F1 and the second hollow pattern F2. Accordingly, the fluid channel of the flow channel layer can be composed of the first hollow pattern F1, the microchannel 931 and the second hollow pattern F2. In this way, the convection heat exchange area inside the hollow electrode 9 can be further increased based on the high density of the microchannel 931, thereby greatly improving the heat dissipation performance of the radiator. And, as Fig.13 As shown in , matching the morphological design of the first hollow pattern F1 and the second hollow pattern F2, the number and direction of the microchannels 931 can be arbitrarily set to connect the first hollow pattern F1 and the second hollow pattern F2 and have a better cooling medium flow path.

[0130] For example, please combine Fig.14 and Fig.15 It is understood that the partition 921 in the manifold layer 92 adopts a serpentine structure. The water inlet channel formed by any target bending area of ​​the partition 921 in the first hollow pattern F1 can be connected to the water outlet channel formed by two adjacent bending areas of the aforementioned target bending area in the second hollow pattern F2 through multiple microchannels, so as to increase the flow path length of the cooling medium as much as possible.

[0131] Optionally, the thickness of the microchannel layer 93 includes but is not limited to 2 mm to 5 mm.

[0132] Optionally, the microchannel 931 of the microchannel layer 93 is arranged on a side thereof close to the manifold layer 92, and the size of the microchannel 931 can be controlled within the range of, for example, 0.5 mm to 1 mm in width, 1.5 mm to 2 mm in height, and 0.5 mm to 1 mm in wall thickness.

[0133] It is worth mentioning that all fluid channels in the hollow electrode 9 need to remain sealed, and the electrode layer 91 , the manifold layer 92 and the microchannel layer 93 of the hollow electrode 9 need to form a closed packaging structure.

[0134] For example, see Fig.16 , the electrode layer 91 and the manifold layer 92 are an integrated structure; that is, the manifold layer 92 can be directly processed on the side of the electrode layer 91 close to the wafer 1.

[0135] For example, the microchannel layer 93 is difficult to process, so it can be processed separately and then assembled with the manifold layer 92 or the integrated structure of the manifold layer 92 and the electrode layer 91. For example, the microchannel layer 93 and the manifold layer 92 or the integrated structure of the manifold layer 92 and the electrode layer 91 can be assembled and sealed by a sealing ring + threaded connection. Or, for example, the microchannel layer 93 and the manifold layer 92 or the integrated structure of the manifold layer 92 and the electrode layer 91 can be assembled and sealed by welding (including but not limited to brazing process).

[0136] In other examples, the manifold layer 92 and the microchannel layer 93 are an integrated structure. For example, the microchannel layer 93 and the manifold layer 92 can be integrally formed by 3D printing. This embodiment of the present disclosure does not specifically limit this.

[0137] In some embodiments of the present disclosure, the first crimping assembly includes, for example, one or more first subassemblies. When the first crimping assembly includes one first subassembly, the first subassembly is the cathode 2. When the first crimping assembly includes multiple first subassemblies, each first subassembly can be stacked in sequence along a direction away from the first side surface of the wafer 1, and each first subassembly can be the cathode 2 and other interlayer structures (such as a transition layer, etc.). Accordingly, the first thermal resistance R th-A It is the sum of the body thermal resistance of each first sub-assembly and the contact thermal resistance between each first sub-assembly and an adjacent first device, wherein the adjacent first device includes other first sub-assemblies or wafers in contact with the corresponding first sub-assembly.

[0138] Similarly, the second crimping assembly includes, for example, one or more second subassemblies. When the second crimping assembly includes one second subassembly, the second subassembly is the aforementioned anode 3. When the second crimping assembly includes multiple second subassemblies, each second subassembly can be stacked in sequence along a direction away from the second side surface of the wafer 1, and each second subassembly can be the anode 3 and other interlayer structures (such as a transition layer, etc.). Accordingly, the second thermal resistance R th-K It is the sum of the body thermal resistance of each second sub-assembly and the contact thermal resistance between each second sub-assembly and an adjacent second device, wherein the adjacent second device includes other second sub-assemblies or wafers in contact with the corresponding second sub-assembly.

[0139] Thus, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The sum of R th-series =(R th-A +R th-K ). The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-paralThe first thermal resistance R th-A and the second thermal resistance R th-K The product of divided by the first thermal resistance R th-A and the second thermal resistance R th-K The sum of R th-paral =(R th-A ×R th-K ) / (R th-A +R th-K ).

[0140] In some possible implementations of the present disclosure, please continue to refer to Figure 1 The first crimping assembly has only one first subassembly, which is the cathode 2. The second crimping assembly has only one second subassembly, which is the anode 3. Both the cathode 2 and the anode 3 are directly connected to the wafer 1.

[0141] Accordingly, the first thermal resistance R th-A is: the sum of the body thermal resistance of the cathode 2 and the first contact thermal resistance between the cathode 2 and the wafer 1 .

[0142] The second thermal resistance R th-K is: the sum of the body thermal resistance of the anode 3 and the second contact thermal resistance between the anode 3 and the wafer 2 .

[0143] Based on this, illustratively, both the cathode 2 and the anode 3 are thermally conductive composite electrodes. However, this is not limited to this. In this embodiment, both the cathode 2 and the anode 3 are metal electrodes, or one of the cathode 2 and the anode 3 is a thermally conductive composite electrode and the other is a metal electrode, such as a copper electrode, which is also allowed.

[0144] On this basis, illustratively, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio ranges from 7 to 20.

[0145] In some examples, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio is 7.88.

[0146] Exemplarily, the total thickness of the semiconductor package structure is, for example, 35 mm. Accordingly, the thickness of the smaller one is less than or equal to 5 mm.

[0147] For example, the thickness of the anode 3 is less than the thickness of the cathode 2, and the thickness of the anode 3 is less than or equal to 5 mm, for example, it can be 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm. Optionally, the sum of the thicknesses of the anode 3 and the cathode 2 is the target value, and after the thickness of the anode 3 is thinned, the thickness of the cathode 2 can be increased accordingly. Accordingly, the gate assembly interconnected with the cathode 2 can be adjusted to one side of the anode 3, for example, the spokes of the gate lead ring are bent upward to match the cathode 2 after the thickness is increased. In the embodiment of the present disclosure, through the verification of the finite element simulation model, when the thickness of the anode 3 is thinned to 3 mm~5 mm, the junction-shell thermal resistance of the semiconductor packaging structure will drop from 3.0 K / kW to 1.5 K / kW, and the reduction can reach 50%. The embodiment of the present disclosure can greatly improve the device heat dissipation efficiency and device flow capacity of the semiconductor packaging structure.

[0148] Or, for another example, the thickness of the cathode 2 is less than the thickness of the anode 3, and the thickness of the cathode 2 is less than or equal to 5 mm, for example, it can be 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm.

[0149] In some other possible implementations of the present disclosure, please refer to Fig.14 and Fig.15 The semiconductor packaging structure further includes a transition layer. One of the cathode 2 and the anode 3 is directly connected to the wafer 1, and the other is connected to the wafer 1 through the transition layer.

[0150] Here, the setting position of the transition layer is matched, and the transition layer can serve as a sub-component corresponding to the first crimping component or the second crimping component.

[0151] For example, the first crimping assembly includes a cathode 2 and a transition layer, and the transition layer is located between the wafer 1 and the cathode 2; accordingly, the first thermal resistance R th-A is the sum of the bulk thermal resistance of the transition layer, the third contact thermal resistance between the transition layer and the wafer 1, the bulk thermal resistance of the cathode 2, and the fourth contact thermal resistance between the cathode 2 and the transition layer. The second crimping assembly only includes the anode 3; accordingly, the second thermal resistance R th-K is: the sum of the body thermal resistance of the anode 3 and the second contact thermal resistance between the anode 3 and the wafer 1 .

[0152] Alternatively, for example, the first crimping assembly includes only the cathode 2; accordingly, the first thermal resistor R th-A is the sum of the body thermal resistance of the cathode 2 and the first contact thermal resistance between the cathode 2 and the wafer 1. The second crimping assembly includes an anode 3 and a transition layer, and the transition layer is located between the wafer 1 and the anode 3; accordingly, the second thermal resistance R th-K It is the sum of the bulk thermal resistance of the transition layer, the fifth contact thermal resistance between the transition layer and the wafer 1 , the bulk thermal resistance of the anode 3 , and the sixth contact thermal resistance between the anode 3 and the transition layer.

[0153] Fig.14 and Fig.15 In the figure, only the transition layer (ie, the first transition layer 7 ) between the cathode 2 and the wafer 1 is used as an example for illustration, but it can be understood that it is also permitted to only provide a transition layer between the anode 3 and the wafer 1 .

[0154] Furthermore, the transition layer can be used, for example, to match the thermal expansion coefficients of the wafer 1 and the corresponding electrode (e.g., cathode 2 or anode 3), and as a thermal expansion coefficient transition layer between the wafer 1 and the corresponding electrode (e.g., cathode 2 or anode 3), so as to transitionally balance the difference in thermal expansion coefficients between the wafer 1 and the corresponding electrode (e.g., cathode 2 or anode 3). However, the present invention is not limited thereto, and the transition layer can also be, for example, a stress transition layer or a transition layer having other functions.

[0155] For example, the transition layer includes but is not limited to a molybdenum sheet, and may also be a thermally conductive and electrically conductive composite metal sheet.

[0156] In some examples, the transition layer may be formed of a thermally conductive and electrically conductive composite metal material such as aluminum diamond or copper diamond to have higher thermal conductivity, higher electrical conductivity, and lower expansion coefficient, thereby further reducing the overall thermal resistance of the semiconductor package structure.

[0157] On this basis, illustratively, the electrode directly connected to the wafer 1 among the cathode 2 and the anode 3 is the aforementioned thermally conductive composite material electrode. The electrode connected to the wafer 1 through the transition layer among the cathode 2 and the anode 3 is a metal electrode, for example, a copper electrode. However, it is not limited to this. In this embodiment, both the cathode 2 and the anode 3 use metal electrodes, or both use the aforementioned thermally conductive composite material electrode, or the electrode directly connected to the wafer 1 is a metal electrode and the electrode connected to the wafer 1 through the transition layer uses the aforementioned thermally conductive composite material electrode, which are all allowed.

[0158] Exemplarily, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio ranges from 5 to 20.

[0159] In some examples, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio is 5.77.

[0160] Exemplarily, the total thickness of the semiconductor package structure is, for example, 35 mm. Accordingly, the thickness of the smaller one is less than or equal to 5 mm.

[0161] For example, the thickness of the anode 3 is less than the thickness of the cathode 2, and the thickness of the anode 3 is less than or equal to 5 mm, for example, it can be 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm. Optionally, the sum of the thicknesses of the anode 3 and the cathode 2 is the target value, and after the thickness of the anode 3 is thinned, the thickness of the cathode 2 can be increased accordingly. Accordingly, the gate assembly interconnected with the cathode 2 can be adjusted to one side of the anode 3, for example, the spokes of the gate lead ring are bent upward to match the cathode 2 after the thickness is increased. In the embodiment of the present disclosure, through the verification of the finite element simulation model, when the thickness of the anode 3 is thinned to 3 mm~5 mm, the junction-shell thermal resistance of the semiconductor packaging structure will drop from 3.0 K / kW to 1.7 K / kW, and the reduction can reach 43%. The embodiment of the present disclosure can take into account the production cost of the semiconductor packaging structure, the heat dissipation efficiency of its devices, and the current carrying capacity of its devices.

[0162] Or, for another example, the thickness of the cathode 2 is less than the thickness of the anode 3, and the thickness of the cathode 2 is less than or equal to 5 mm, for example, it can be 3 mm, 3.5 mm, 4 mm, 4.5 mm or 5 mm.

[0163] In some possible implementations of the present disclosure, please refer to Fig.16 The first crimping assembly includes: a cathode 2, and a first transition layer 7 located between the cathode 2 and the wafer 1 and connecting the cathode 2 and the wafer 1. The second crimping assembly includes: an anode 3, and a second transition layer 8 located between the anode 3 and the wafer 1 and connecting the anode 3 and the wafer 1.

[0164] Accordingly, the first thermal resistance R th-A The second thermal resistance R is the sum of the body thermal resistance of the first transition layer 7, the seventh contact thermal resistance between the first transition layer 7 and the wafer 1, the body thermal resistance of the cathode 2, and the eighth contact thermal resistance between the cathode 2 and the first transition layer 7. th-K It is the sum of the body thermal resistance of the second transition layer 8 , the ninth contact thermal resistance between the second transition layer 8 and the wafer 1 , the body thermal resistance of the anode 3 , and the tenth contact thermal resistance between the anode 3 and the second transition layer 8 .

[0165] Based on this, illustratively, the cathode 2 and the anode 3 are both metal electrodes, such as copper electrodes. However, this is not limited to this. In this embodiment, the cathode 2 and the anode 3 are both made of the aforementioned thermally conductive composite material electrodes, which is also permitted.

[0166] Exemplarily, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio is greater than or equal to 4.4.

[0167] In some examples, the first thermal resistance R th-A and the second thermal resistance R th-K The series thermal resistance R th-series The first thermal resistance R th-A and the second thermal resistance R th-K The parallel thermal resistance R th-para The ratio is 4.43.

[0168] Exemplarily, the total thickness of the semiconductor package structure is, for example, 35 mm. Accordingly, the thickness of the smaller one is less than or equal to 2.5 mm.

[0169] For example, the thickness of the anode 3 is less than the thickness of the cathode 2, and the thickness of the anode 3 is less than or equal to 2.5 mm, for example, it can be 1 mm, 1.5 mm, 2 mm or 2.5 mm. Optionally, the sum of the thicknesses of the anode 3 and the cathode 2 is the target value, and after the thickness of the anode 3 is thinned, the thickness of the cathode 2 can be increased accordingly. Accordingly, the gate assembly interconnected with the cathode 2 can be adjusted to one side of the anode 3, for example, the spokes of the gate lead ring are bent upward to match the cathode 2 after the thickness is increased. In the embodiment of the present disclosure, through the verification of the finite element simulation model, when the thickness of the anode 3 is thinned to 1 mm~2.5 mm, the junction-shell thermal resistance of the semiconductor packaging structure will drop from 3.0 K / kW to 2.7 K / kW, and the reduction can reach 20%. The embodiment of the present disclosure can effectively improve the heat dissipation efficiency and the flow capacity of the device based on the offset structure design of the semiconductor packaging structure while ensuring that the semiconductor packaging structure has a lower production cost.

[0170] Or, for another example, the thickness of the cathode 2 is less than the thickness of the anode 3, and the thickness of the cathode 2 is less than or equal to 2.5 mm, for example, it can be 1 mm, 1.5 mm, 2 mm or 2.5 mm.

[0171] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor packaging structure, which is used to prepare the semiconductor packaging structure described in any of the above embodiments. The features of each component structure in the above semiconductor packaging structure can be implemented with reference to the relevant records in the above embodiments, and the technical advantages of the above semiconductor packaging structure are also possessed by the manufacturing method, which will not be described in detail here.

[0172] The manufacturing method of the semiconductor packaging structure includes: crimping a first crimping assembly on a first side of a wafer; crimping a second crimping assembly on a second side of the wafer; wherein the first crimping assembly includes a cathode for rigidly crimping the first side surface of the wafer. The second crimping assembly includes an anode for rigidly crimping the second side surface of the wafer. The second side surface is opposite to the first side surface. The thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3.

[0173] In the embodiment of the present disclosure, the structures of the first crimping assembly and the second crimping assembly can refer to the relevant records in the aforementioned embodiments and will not be described in detail here.

[0174] Optionally, the first crimping assembly can be crimped on the first side of the wafer by mechanical pressure, bonding, welding, sintering, bonding, etc. Similarly, the second crimping assembly can be crimped on the second side of the wafer by mechanical pressure, bonding, welding, sintering, bonding, etc.

[0175] Some embodiments of the present disclosure further provide a power device, including a thyristor or a diode; wherein the thyristor or the diode includes the semiconductor packaging structure as described in any of the above embodiments.

[0176] It should be noted that the thyristors in the embodiments of the present disclosure include common thyristors and thyristor-derived devices, such as gate turn-off thyristors, gate-commutated thyristors (GCTs) or integrated gate-commutated thyristors (IGCTs).

[0177] Some embodiments of the present disclosure also provide an electronic device, comprising the power device as described in any of the above embodiments.

[0178] For example, in an electronic device, a power device may be used as a control element and / or a switching element. The electronic device may be, for example, a converter valve.

[0179] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0180] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: Wafer; A first crimping assembly, comprising a cathode located on a first side of the wafer and used for rigidly crimping the first side surface of the wafer; A second crimping assembly, comprising an anode located on a second side of the wafer and used for rigidly crimping the second side surface of the wafer; The second side surface is opposite to the first side surface; the thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3; The thickness of one of the cathode and the anode is smaller than that of the other; wherein the ratio of the smaller thickness to the larger thickness is less than or equal to 0.

6.

2. The semiconductor package structure according to claim 1, wherein: The ratio of the series thermal resistance of the first thermal resistor and the second thermal resistor to the parallel thermal resistance of the first thermal resistor and the second thermal resistor is in the range of 4.3-20.

3. The semiconductor package structure according to claim 1, wherein: The cathode and / or the anode are solid electrodes; Alternatively, the cathode and / or the anode is a hollow electrode.

4. The semiconductor package structure according to claim 3, wherein: The cathode and / or the anode are hollow electrodes; The hollow electrode comprises an electrode body; a water inlet and a water outlet are provided on the crimping surface of the electrode body away from the wafer, and a fluid channel connecting the water inlet and the water outlet is provided inside the electrode body; the water inlet and the water outlet are used to connect to a radiator; Alternatively, the hollow electrode comprises at least an electrode layer and a flow channel layer stacked in sequence along a direction close to the wafer; the electrode layer has a water inlet hole and a water outlet hole for connecting to a radiator; the flow channel layer has a fluid channel connecting the water inlet hole and the water outlet hole.

5. The semiconductor package structure according to claim 4, wherein: The hollow electrode comprises: an electrode layer and a flow channel layer stacked in sequence in a direction close to the wafer; the flow channel layer comprises: a manifold layer, located on a side of the electrode layer close to the wafer, comprising a first hollow pattern and a second hollow pattern that are separated and arranged, wherein the first hollow pattern is connected to the water inlet through hole, and the second hollow pattern is connected to the water outlet through hole; A microchannel layer, located on a side of the manifold layer close to the wafer, comprising a plurality of microchannels arranged separately; the microchannels communicate with the first hollow pattern and the second hollow pattern; Wherein, the fluid channel is composed of the first hollow pattern, the microchannel and the second hollow pattern.

6. The semiconductor package structure according to claim 5, wherein: The electrode layer and the manifold layer are an integrated structure; Alternatively, the manifold layer and the microchannel layer are an integrated structure.

7. The semiconductor package structure according to any one of claims 1 to 6, wherein: The first crimping assembly includes one or more first subassemblies; the first thermal resistance is the sum of the body thermal resistance of each of the first subassemblies and the contact thermal resistance between each of the first subassemblies and an adjacent first device, wherein the adjacent first device includes other first subassemblies or the wafer in contact with the corresponding first subassembly; The second crimping assembly includes one or more second subassemblies; the second thermal resistance is the sum of the body thermal resistance of each second subassembly and the contact thermal resistance between each second subassembly and an adjacent second device, and the adjacent second device includes other second subassemblies or the wafer in contact with the corresponding second subassembly; The series thermal resistance of the first thermal resistance and the second thermal resistance is: the sum of the first thermal resistance and the second thermal resistance; The parallel thermal resistance of the first thermal resistor and the second thermal resistor is: the product of the first thermal resistor and the second thermal resistor divided by the sum of the first thermal resistor and the second thermal resistor.

8. The semiconductor package structure according to claim 7, wherein: The first crimping assembly includes a first subassembly, the first subassembly is the cathode; the second crimping assembly includes a second subassembly, the second subassembly is the anode; the cathode and the anode are both directly connected to the wafer; wherein, The first thermal resistance is: the sum of the body thermal resistance of the cathode and the first contact thermal resistance between the cathode and the wafer; The second thermal resistance is: the sum of the body thermal resistance of the anode and the second contact thermal resistance between the anode and the wafer.

9. The semiconductor package structure according to claim 8, wherein: The cathode and the anode are both thermally conductive composite material electrodes.

10. The semiconductor package structure according to claim 7, wherein: The semiconductor packaging structure further includes: a transition layer; one of the cathode and the anode is directly connected to the wafer, and the other is connected to the wafer through the transition layer; Wherein, the first crimping assembly includes the cathode and the transition layer, and the transition layer is located between the wafer and the cathode; the first thermal resistance is: the sum of the body thermal resistance of the transition layer, the third contact thermal resistance between the transition layer and the wafer, the body thermal resistance of the cathode, and the fourth contact thermal resistance between the cathode and the transition layer; the second thermal resistance is: the sum of the body thermal resistance of the anode and the second contact thermal resistance between the anode and the wafer; Or, the second crimping assembly includes the anode and the transition layer, and the transition layer is located between the wafer and the anode; the first thermal resistance is: the sum of the body thermal resistance of the cathode and the first contact thermal resistance of the cathode and the wafer; the second thermal resistance is: the sum of the body thermal resistance of the transition layer, the fifth contact thermal resistance of the transition layer and the wafer, the body thermal resistance of the anode, and the sixth contact thermal resistance of the anode and the transition layer.

11. The semiconductor package structure according to claim 10, wherein: The electrode directly connected to the wafer among the cathode and the anode is a thermally conductive composite material electrode; The electrodes among the cathode and the anode connected to the wafer through the transition layer are metal electrodes.

12. The semiconductor package structure according to claim 7, wherein: The first crimping assembly includes the cathode and a first transition layer, the first transition layer is located between the cathode and the wafer and connects the cathode and the wafer; the second crimping assembly includes the anode and a second transition layer, the second transition layer is located between the anode and the wafer and connects the anode and the wafer; The first thermal resistance is: the sum of the body thermal resistance of the first transition layer, the seventh contact thermal resistance between the first transition layer and the wafer, the body thermal resistance of the cathode, and the eighth contact thermal resistance between the cathode and the first transition layer; The second thermal resistance is: the sum of the body thermal resistance of the second transition layer, the ninth contact thermal resistance between the second transition layer and the wafer, the body thermal resistance of the anode, and the tenth contact thermal resistance between the anode and the second transition layer.

13. The semiconductor package structure according to claim 12, wherein: The cathode and the anode are both metal electrodes.

14. A method for manufacturing a semiconductor packaging structure, characterized in that: crimping a first crimping assembly on a first side of the wafer; crimping a second crimping assembly on a second side of the wafer; Wherein, the first crimping assembly includes a cathode for rigidly crimping the first side surface of the wafer; the second crimping assembly includes an anode for rigidly crimping the second side surface of the wafer; the second side surface is opposite to the first side surface; the thermal resistance of the first side of the wafer is the first thermal resistance, and the thermal resistance of the second side of the wafer is the second thermal resistance; the ratio of the series thermal resistance of the first thermal resistance and the second thermal resistance to the parallel thermal resistance of the first thermal resistance and the second thermal resistance is greater than or equal to 4.3; The thickness of one of the cathode and the anode is smaller than that of the other; wherein the ratio of the smaller thickness to the larger thickness is less than or equal to 0.

6.

15. A power device, characterized in that: It comprises a thyristor or a diode; the thyristor or the diode comprises the semiconductor packaging structure as described in any one of claims 1 to 13.

16. An electronic device, characterized in that: Comprising the power device as claimed in claim 15.

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