Solar cell, photovoltaic module and semiconductor substrate

Abstract

The present invention discloses a solar cell, a photovoltaic module and a semiconductor substrate, which relate to the field of photovoltaic technology and are used to increase the specific surface area of ​​the doped semiconductor layer in the passivation layer or formed between the passivation layer and the semiconductor substrate while making the passivation layer have a good passivation effect on the semiconductor substrate. The solar cell includes a semiconductor substrate and a passivation layer. The side of the passivation layer facing away from the semiconductor substrate has a plurality of first texture structures. A single first texture structure includes a tower-like texture portion and a ridgeline concave portion arranged on the side of the tower-like texture portion close to the semiconductor substrate. The tower-like texture portion includes a side surface concave into the passivation layer, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion. The ridgeline concave portion includes a ridgeline concave into the passivation layer from at least one corner of the polygonal bottom surface, and the ridgelines included in the ridgeline concave portion gradually converge toward the central axis of the tower-like texture portion along the length direction.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell, a photovoltaic module and a semiconductor substrate. Background Art

[0002] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0003] However, existing solar cells have difficulty in achieving both good passivation effects and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells. Summary of the Invention

[0004] The object of the present invention is to provide a solar cell, a photovoltaic module and a semiconductor substrate, which are used to ensure that the passivation layer has a good passivation effect on the semiconductor substrate, while increasing the surface roughness of the passivation layer on the side away from the semiconductor substrate by arranging a ridgeline recessed portion on the side of the tower-like texture portion close to the semiconductor substrate, which is beneficial to increase the specific surface area of ​​the doped semiconductor layer in the passivation layer or formed between the passivation layer and the semiconductor substrate, improve the contact performance between the doped semiconductor layer and the electrode, and the shaping of the electrode, thereby improving the conversion efficiency of the solar cell.

[0005] In order to achieve the above-mentioned objectives, in a first aspect, the present invention provides a solar cell, which comprises: a semiconductor substrate and a passivation layer. The semiconductor substrate has a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The passivation layer is arranged on the target surface. The side of the passivation layer facing away from the semiconductor substrate has a plurality of first texture structures. A single first texture structure comprises a tower-like texture portion, and a ridgeline recessed portion arranged on the side of the tower-like texture portion close to the semiconductor substrate. The tower-like texture portion comprises a side surface recessed into the passivation layer, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion. The ridgeline recessed portion comprises a ridgeline recessed into the passivation layer by at least one corner of the polygonal bottom surface, and the ridgeline recessed portion comprises a ridgeline gradually converging toward the central axis of the tower-like texture portion along the length direction.

[0006] When adopting the above technical solution, the passivation layer is disposed on the target surface of the semiconductor substrate, which can passivate the target surface side of the semiconductor substrate and reduce the carrier recombination rate. In addition, the side of the passivation layer facing away from the semiconductor substrate has multiple first texture structures. In addition, a single first texture structure includes a base-like texture portion. When other factors are the same, compared with texture structures with a large degree of undulation, such as a pyramid-shaped velvet structure, the base-like texture portion has a relatively small degree of undulation, making the surface of the side of the passivation layer facing away from the semiconductor substrate relatively flat from a macroscopic perspective. In addition, during the actual manufacturing process, the passivation layer is formed on the target surface of the semiconductor substrate through processes such as deposition. The surface undulation morphology of the passivation layer facing away from the semiconductor substrate is also affected by the surface undulation morphology of the target surface. Accordingly, the surface undulation morphology of the passivation layer facing away from the semiconductor substrate can also reflect the surface undulation morphology of the target surface of the semiconductor substrate to a certain extent. Based on this, when the surface of the passivation layer facing away from the semiconductor substrate is relatively flat on a macroscopic scale, the target surface of the semiconductor substrate is also roughly a relatively flat surface, which is conducive to improving the formation quality and film thickness of the passivation layer on the target surface, and then conducive to improving the passivation effect of the passivation layer on the semiconductor substrate and improving the conversion efficiency of the solar cell.

[0007] In addition, the tower-like texture portion includes side surfaces that are recessed into the passivation layer, with the side surfaces of the tower-like texture portion enclosing a polygonal bottom surface. Furthermore, the first texture structure also includes a ridgeline recessed portion disposed on the side of the tower-like texture portion proximal to the semiconductor substrate. The ridgeline recessed portion includes a ridgeline recessed into the passivation layer from at least one corner of the polygonal bottom surface. This allows the bottom of the tower-like texture portion, which originally has an undulating morphology, to have the undulations of the ridgeline recessed portion superimposed on the bottom surface, thereby increasing the specific surface area of ​​the bottom surface of the first texture structure. This results in the passivation layer having a relatively large surface roughness on the side facing away from the semiconductor substrate, thereby increasing the specific surface area of ​​the doped semiconductor layer included in the passivation layer, or the doped semiconductor layer formed between the passivation layer and the semiconductor substrate. This in turn increases the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. At the same time, the ridges included in the ridge concave portion gradually converge toward the central axis of the tower base-shaped texture portion along the length direction. At this time, along the depth direction of the concave portion, the space enclosed by the ridge concave portion gradually converges, which can prevent the roughness of the bottom surface of the first texture structure from being too large, so that the passivation layer has a higher passivation effect.

[0008] As a possible implementation scheme, in the same first texture structure, the angle between the ridge of the ridge concave portion and the adjacent side ridge in the tower base-shaped texture portion is greater than 90° and less than or equal to 175°. In this case, the optional range of the above-mentioned angle is relatively large, which is conducive to selecting the appropriate angle size according to different actual needs. For example: if it is necessary to increase the surface roughness of the passivation layer away from the semiconductor substrate as much as possible, the size of the angle can be set within a range of larger values, so that the ridges included in the ridge concave portion can be recessed into the passivation layer to a greater depth. On the contrary, if the passivation layer is required to have a higher passivation effect in the actual application scenario, the size of the angle can be set within a range of smaller values, so that the depth of the ridges included in the ridge concave portion recessed into the passivation layer is relatively small, so as to regulate the surface roughness of the passivation layer away from the semiconductor wafer side, thereby improving the applicability of the solar cell provided by the present invention in different application scenarios.

[0009] As a possible implementation, at least one ridgeline concave portion includes at least two ridgelines respectively concave from at least two corners of the polygonal bottom surface into the passivation layer, and the at least two ridgelines included in the ridgeline concave portion intersect at at least one point.

[0010] When the above technical solution is adopted, there are multiple ridges in a single ridge concave portion that are recessed into the passivation layer based on the polygonal bottom surface, and compared with the divergent distribution of at least two ridges included in the ridge concave portion, when the at least two ridges included in the same ridge concave portion intersect at at least one point, the side of the ridge concave portion that is away from the tower-like base texture portion is more convergent. At this time, when the recessed depth of the ridge concave portion is constant, the length of the ridges included in the ridge concave portion is larger, which can further increase the undulation of the bottom surface of the first texture structure, thereby increasing the microscopic surface roughness of the passivation layer away from the semiconductor substrate, further increasing the contact area between the above-mentioned doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, further improving the conversion efficiency of the solar cell.

[0011] As a possible implementation solution, in the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is smaller than the depth of the tower base-like texture portion.

[0012] When adopting the above technical solution, the depth of the ridge concave portion relative to the polygonal bottom surface is smaller, so that after the ridge concave portion is superimposed, the bottom of the tower base-like texture portion has an additional undulation degree on the undulating topography originally provided with the tower base-like portion. This is beneficial to controlling the surface roughness of the passivation layer away from the semiconductor substrate from being too large, and correspondingly, the surface roughness of the target surface on which the passivation layer is formed is not too large, thereby ensuring that the passivation layer has a higher formation quality and passivation effect.

[0013] As a possible implementation solution, the concave depth of the tower base-like texture portion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm.

[0014] When the above technical solution is adopted, the depth of the concave portion of the tower-like base texture portion is within the above range, which helps prevent the specific surface area of ​​the passivation layer on the side away from the semiconductor substrate from being too small due to the concave depth of the tower-like base texture portion being too small, ensuring a larger contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and improving the conversion efficiency of the solar cell. In addition, it can also prevent the specific surface area of ​​the passivation layer on the side away from the semiconductor substrate from being too large due to the concave depth of the tower-like base texture portion being too large, ensuring that the target surface is relatively flat on a macroscopic scale, improving the formation quality and film thickness of the passivation layer on the target surface, and ensuring that the passivation layer has a higher passivation effect.

[0015] As a possible implementation solution, the depth of the ridgeline concave portion relative to the polygonal bottom surface is greater than or equal to 0.1 μm and less than or equal to 0.3 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the concave depth of the tower base-shaped texture portion being greater than or equal to 0.2 μm and less than or equal to 0.8 μm described above, and will not be repeated here.

[0016] As a possible implementation solution, the passivation layer includes a doped semiconductor layer, and the ratio between the depth of the ridgeline concave portion relative to the polygonal bottom surface and the thickness of the doped semiconductor layer is greater than or equal to 0.95 and less than or equal to 1.05. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the concave depth of the tower base-shaped texture portion being greater than or equal to 0.2μm and less than or equal to 0.8μm described above, and will not be repeated here.

[0017] As a possible implementation solution, the side length of the polygonal bottom surface is greater than or equal to 2 μm and less than or equal to 12 μm.

[0018] When adopting the above technical solution, with other factors being equal, the side length of the quasi-polygonal bottom surface is within the above range, which helps prevent the distribution density of the first texture structure on the side of the passivation layer facing away from the semiconductor substrate from being too high due to the side length of the quasi-polygonal bottom surface being too small, and helps control the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Accordingly, the target surface is relatively flat at a macroscopic level, further improving the formation quality of the passivation layer on the target surface and enhancing the passivation effect of the passivation layer. In addition, it can also prevent the distribution density of the first texture structure on the side of the passivation layer facing away from the semiconductor substrate from being too low due to the side length of the quasi-polygonal bottom surface being too large, ensuring that the side of the passivation layer facing away from the semiconductor substrate has a certain surface roughness at a microscopic level, increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and helping to improve the conversion efficiency of the solar cell.

[0019] As a possible implementation solution, the length of the ridge line of the ridge line concave portion is greater than or equal to 2 μm and less than or equal to 8 μm.

[0020] When employing the above technical solution, if the dimensions of the tower-like base-shaped texture portion included in the first texture structure are constant, the greater the ridgeline length of the ridgeline concave portion, the greater the depth of the ridgeline concave portion relative to the polygonal base. Based on this, when the ridgeline length of the ridgeline concave portion is within the above range, it is helpful to prevent the specific surface area of ​​the passivation layer facing away from the semiconductor substrate from being too small due to the ridgeline length of the ridgeline concave portion being too small, thereby ensuring a larger contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. In addition, it can also prevent the specific surface area of ​​the passivation layer on the side away from the semiconductor substrate from being too large due to the length of the ridge line of the ridge line concave portion being too large, which makes the concave depth of the ridge line concave portion relative to the polygonal bottom surface too large. It ensures the macroscopic flatness of the passivation layer on the side away from the semiconductor substrate, and the corresponding target surface has a smaller surface roughness, thereby improving the formation quality and passivation effect of the passivation layer on the target surface.

[0021] As a possible implementation, at least one side surface of the first texture structure has a plurality of raised portions that rise along the extending direction of the side ridgeline, and the plurality of raised portions on the same side surface have an undulating topography extending parallel to a first direction different from the longitudinal direction of the side ridgeline of the tower-like base-shaped texture portion.

[0022] When adopting the above technical solution, the presence of the raised portion can increase the surface undulation of the side of the tower-like texture portion, further increase the surface roughness of the passivation layer on the side away from the semiconductor substrate, thereby further increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of solar cells.

[0023] As a possible implementation, at least one side surface of at least one of the tower-base-like textured portions has at least two raised structures distributed in a stepped manner along the side ridgeline extension direction. Each raised structure includes multiple raised portions extending along a first direction. The ridgeline recessed portion extends from the bottom of the raised structure located on the bottom layer into the passivation layer.

[0024] When the above-mentioned technical solution is adopted, at least two raised structures distributed in a stepped manner can further increase the degree of undulation of the side surface of the tower-like texture portion along the direction of extension of the ridge line, further increase the surface roughness of the passivation layer on the side away from the semiconductor substrate, which is beneficial to increase the contact area between the above-mentioned doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, and improve the conversion efficiency of the solar cell.

[0025] As a possible implementation, within the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is less than the sum of the heights of all raised structures on the side surfaces of the tower-base-like texture portion. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect of the ridgeline concave portion relative to the polygonal bottom surface being less than the concave depth of the tower-base-like texture portion within the same first texture structure, and will not be repeated here.

[0026] As one possible implementation, the passivation layer further comprises multiple second texture structures on a side facing away from the semiconductor substrate. Each second texture structure is a tower-shaped texture structure, and the tower-shaped texture structure includes side surfaces and a bottom surface that are recessed into the passivation layer. The bottom surface of the tower-shaped texture structure is flat. The recessed depth of the first texture portion is greater than that of the second texture structure.

[0027] When adopting the above technical solution, no ridge concave portion is set on the bottom surface of the tower base-shaped texture structure with a smaller concave depth, which is beneficial to controlling the specific surface area of ​​the passivation layer away from the semiconductor substrate side, and correspondingly beneficial to controlling the surface roughness of the target surface, ensuring the formation quality and passivation effect of the passivation layer on the target surface, and beneficial to improving the conversion efficiency of solar cells.

[0028] As a possible implementation, the second texture structure has a recessed depth of 0.1 μm or less. In this case, the smaller recessed depth of the second texture structure ensures that the side of the passivation layer facing away from the semiconductor substrate is macroscopically smoother, further improving the formation quality and passivation effect of the passivation layer on the target surface, thereby increasing the conversion efficiency of the solar cell.

[0029] As a possible implementation, at least one side surface of the first or second texture structure has multiple raised portions that rise along the direction of the side ridgeline, and the multiple raised portions on the same side surface have an undulating topography extending parallel to a second direction. The second direction is different from the direction of the side ridgeline. The application principle of the beneficial effect in this case can be referred to the beneficial effect of at least one side surface of the first texture structure having multiple raised portions that rise along the direction of the side ridgeline described above, and will not be repeated here.

[0030] As a possible implementation, when at least one side surface of at least one first texture structure has multiple raised portions, at least one raised portion extends from the ridgeline of the ridgeline recessed portion to the corresponding side surface of the tower-like base-shaped texture portion. In this case, the ridgeline extension length of the ridgeline recessed portion is increased, further increasing the specific surface area of ​​the first texture structure, increasing the surface roughness of the passivation layer on the side facing away from the semiconductor substrate, and increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby increasing the conversion efficiency of the solar cell.

[0031] As a possible implementation scheme, the side of the passivation layer facing away from the semiconductor substrate also has a linear texture structure, at least one side of the linear texture structure has a plurality of raised portions intersecting with the extension direction of the linear texture structure, and the plurality of raised portions located on the same side of the linear texture structure have an undulating morphology extending in a direction parallel to the bottom surface of the linear texture structure.

[0032] When using the above technical solution, the presence of the linear texture structure can increase the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Secondly, the presence of multiple raised portions on at least one side of the linear texture structure—that is, the undulation of the raised portions superimposed on the linear texture structure with an undulating morphology—helps further increase the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby increasing the conversion efficiency of the solar cell.

[0033] As one possible implementation, the side of the passivation layer facing away from the semiconductor substrate further comprises a linear texture structure, with the surface of the linear texture structure having a plurality of discretely distributed conical-shaped protrusions. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect described above, "the side of the passivation layer facing away from the semiconductor substrate further comprises a linear texture structure, and at least one side of the linear texture structure comprises a plurality of protrusions intersecting the extension direction of the linear texture structure..." and will not be further elaborated here.

[0034] As a possible implementation, at least one linear texture structure has two ends along its length that have bent portions bent toward the same side, and a connecting portion located between the two bent portions, wherein the angle between the bent portion and the connecting portion is greater than 0° and less than 90°.

[0035] When the above technical solution is adopted, compared with a straight linear texture structure, when at least one linear texture structure has a bending portion, it is beneficial to increase the degree of morphological change of the linear texture structure, and to increase the surface roughness of the passivation layer on the side away from the semiconductor substrate, further increasing the contact area between the above-mentioned doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0036] As a possible implementation, only one of the first and second surfaces is the target surface. Along a direction parallel to the target surface, the passivation layer includes alternating first and second doped semiconductor portions of opposite conductivity types, with at least portions of the first doped semiconductor portions separated from at least portions of the second doped semiconductor portions. The surface of the passivation layer corresponding to the portion of the first doped semiconductor portion facing away from the semiconductor substrate is the first sub-surface, and the surface of the passivation layer corresponding to the portion of the second doped semiconductor portion facing away from the semiconductor substrate is the second sub-surface. The first texture structure is distributed only on the second sub-surface; alternatively, the first sub-surface and the second sub-surface have different one-dimensional dimensions of the first texture structure.

[0037] When adopting the above-mentioned technical solution, the distribution area of ​​the first texture structure and the one-dimensional size of the first texture structure of the first sub-surface and the second sub-surface can be respectively set according to the requirements for different passivation effects of the first doped semiconductor part and the second doped semiconductor part in the actual application scenario, and the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor part and the second doped semiconductor part respectively have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor part and the second doped semiconductor part have different surface morphologies, thereby helping to reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor part and the second doped semiconductor part respectively, and helping to reduce the difference in contact performance between the first doped semiconductor part and the second doped semiconductor part and the corresponding electrodes respectively.

[0038] As a possible implementation solution, the conductivity type of the first doped semiconductor portion is N-type, and the conductivity type of the second doped semiconductor portion is P-type.

[0039] When the above technical solution is adopted, due to the limitation of doping solid concentration and doping concentration, the dopant concentration of the dopant in the N-type doped semiconductor part is greater than the doping concentration of the dopant in the P-type doped semiconductor part, so the passivation characteristics of the P-type doped semiconductor part and its contact characteristics with the positive electrode are relatively worse. Based on this, when the first texture structure is only distributed on the second sub-surface corresponding to the P-type doped semiconductor part, the surface roughness of the second sub-surface is relatively flat on a macroscopic scale, which is conducive to improving the formation quality and passivation effect of the P-type doped semiconductor part, and reducing the difference in passivation effect between the P-type doped semiconductor part and the N-type doped semiconductor part. Secondly, due to the presence of the ridgeline concave part, the P-type doped semiconductor part and the positive electrode can have a larger contact area, improve the contact performance between the P-type doped semiconductor part and the positive electrode, and the adhesion and shaping of the positive electrode on the P-type doped semiconductor part, thereby improving the conversion efficiency of the solar cell.

[0040] In a second aspect, the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

[0041] The beneficial effects of the second aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0042] In a third aspect, the present invention provides a semiconductor substrate having a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of first texture structures. A single first texture structure includes a tower-like texture portion and a ridgeline recessed portion provided on a side of the tower-like texture portion close to the semiconductor substrate. The tower-like texture portion includes a side surface recessed in the semiconductor substrate, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion. The ridgeline recessed portion includes a ridgeline recessed into the semiconductor substrate by at least one corner of the polygonal bottom surface, and the ridgeline recessed portion includes a ridgeline gradually converging toward the central axis of the tower-like texture portion along the length direction.

[0043] The beneficial effects of the third aspect of the present invention and its various implementations can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0045] Figure 1 This is a SEM image of a local surface of a passivation layer facing away from a semiconductor substrate in the related art;

[0046] Figure 2 A schematic longitudinal cross-sectional view of a first structure of a solar cell provided by an embodiment of the present invention;

[0047] Figure 3 A schematic longitudinal cross-sectional view of a second structure of a solar cell provided by an embodiment of the present invention;

[0048] Figure 4 A schematic longitudinal cross-sectional view of a third structure of a solar cell provided by an embodiment of the present invention;

[0049] Figure 5 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 1 ;

[0050] Figure 6 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 2 ;

[0051] Figure 7 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 3 ;

[0052] Figure 8is a SEM image of a local surface of the target surface in an embodiment of the present invention;

[0053] Figure 9 A schematic longitudinal cross-sectional view of a fourth structure of a solar cell provided by an embodiment of the present invention;

[0054] Figure 10 A schematic longitudinal cross-sectional view of a fifth structure of a solar cell provided by an embodiment of the present invention;

[0055] Figure 11 A schematic longitudinal cross-sectional view of a sixth structure of a solar cell provided by an embodiment of the present invention;

[0056] Figure 12 Schematic diagram of the positional relationship between the tower base-like texture portion and the ridgeline concave portion included in the first texture structure in an embodiment of the present invention;

[0057] Figure 13 Schematic top view of the ridgeline concave portion in the first texture structure in an embodiment of the present invention;

[0058] Figure 14 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 4 ;

[0059] Figure 15 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 5 ;

[0060] Figure 16 This is a SEM image of a local surface of the passivation layer facing away from the semiconductor substrate in an embodiment of the present invention. Figure 6 .

[0061] Figure numerals: 11 is a semiconductor substrate, 12 is a first surface, 13 is a second surface, 14 is a passivation layer, 15 is a first texture structure, 16 is a tower-like texture portion, 17 is a ridgeline concave portion, 18 is a convex portion, 19 is a convex structure, 20 is a doped semiconductor layer, 21 is a second texture structure, 22 is a first doped semiconductor portion, 23 is a second doped semiconductor portion, 24 is a cone-like convex structure, 25 is an interface passivation layer, 26 is a surface passivation layer, 27 is an anti-reflection layer, and 28 is a transparent conductive layer. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present invention.

[0063] The accompanying drawings illustrate various structural schematics according to embodiments of the present invention. These figures are not drawn to scale; certain details are exaggerated and may be omitted for clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positions, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0064] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or an intervening layer / element may exist between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to illustrate the present invention and are not intended to limit the present invention.

[0065] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0066] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0067] As a green energy source, solar cells play a positive role in energy conservation and emission reduction. With the development of the photovoltaic industry, solar cell technology has become increasingly mature. Photovoltaic solar cells are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers and then use electrodes to extract these charge carriers, thereby facilitating the efficient use of electrical energy. As an environmentally friendly and renewable energy source, solar energy has garnered increasing attention in recent years. Consequently, the application range of photovoltaic solar cells, which are based on the photoelectric effect, has also expanded.

[0068] Specifically, existing solar cells generally include a semiconductor substrate and a passivation layer formed on the semiconductor substrate. The passivation layer may include a doped semiconductor layer with a field passivation effect, or may include at least one of a surface passivation layer with a chemical passivation effect, an anti-reflection layer, and a transparent conductive layer. Figure 1 As shown, the surface of the semiconductor substrate on which the passivation layer is formed can be a simple polished surface. In this case, the surface has a relatively flat morphology, which is conducive to improving the formation quality of the passivation layer and enhancing the passivation effect of the passivation layer on the semiconductor substrate. However, the passivation layer formed on a semiconductor substrate with a flat surface also tends to be flat. This results in poor shaping and adhesion of the electrode material on the flat surface when forming an electrode for conducting carriers on the passivation layer, thereby reducing the selection and matching of electrode materials. At the same time, it also causes the contact area between the formed electrode and the doped semiconductor layer formed on the flat surface to decrease, increasing contact loss. Although the pyramid-shaped velvet surface with an undulating morphology has a large surface roughness, which is conducive to improving the electrical contact performance between the electrode and the doped semiconductor layer, as well as the shaping and adhesion of the electrode, the pyramid-shaped velvet surface has a large undulating surface morphology and an overly sharp surface, resulting in poor formation quality of the doped semiconductor layer on the velvet surface, and its passivation effect is reduced. Therefore, existing solar cells cannot achieve both good passivation effect and good electrode contact performance and shaping, which is not conducive to improving the conversion efficiency of solar cells.

[0069] In order to solve the above technical problems, in the first aspect, an embodiment of the present invention provides a solar cell. Figures 2 to 7As shown, the solar cell includes: a semiconductor substrate 11 and a passivation layer 14. The semiconductor substrate 11 has a first surface 12 and a second surface 13 relative to each other. At least one of the first surface 12 and the second surface 13 is a target surface. The passivation layer 14 is arranged on the target surface. The side of the passivation layer 14 facing away from the semiconductor substrate 11 has a plurality of first texture structures 15. A single first texture structure 15 includes a tower-like texture portion and a ridgeline concave portion arranged on the side of the tower-like texture portion close to the semiconductor substrate 11. The tower-like texture portion includes a side surface concave into the passivation layer 14, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion. The ridgeline concave portion includes a ridgeline concave into the passivation layer 14 from at least one corner of the polygonal bottom surface, and the ridgeline concave portion includes ridgelines that gradually converge toward the central axis of the tower-like texture portion along the length direction.

[0070] When the above technical solution is adopted, Figures 2 to 7As shown, a passivation layer 14 is disposed on the target surface of the semiconductor substrate 11, which can passivate the target surface side of the semiconductor substrate 11 and reduce the carrier recombination rate. Furthermore, the side of the passivation layer 14 facing away from the semiconductor substrate 11 has multiple first texture structures 15. Each first texture structure 15 includes a base-like texture portion. With other factors remaining the same, compared to texture structures with greater undulations, such as pyramid-shaped velvet structures, the base-like texture portion has a relatively smaller undulation, resulting in a relatively flat surface on the side of the passivation layer 14 facing away from the semiconductor substrate 11 from a macroscopic perspective. Furthermore, during the actual manufacturing process, the passivation layer 14 is formed on the target surface of the semiconductor substrate 11 through processes such as deposition. The surface undulation of the passivation layer 14 facing away from the semiconductor substrate 11 is also affected by the surface undulation of the target surface. Accordingly, the surface undulation of the passivation layer 14 facing away from the semiconductor substrate 11 can, to a certain extent, also reflect the surface undulation of the target surface of the semiconductor substrate 11. Based on this, when the surface of the side of the passivation layer 14 facing away from the semiconductor substrate 11 is relatively flat on a macroscopic scale, the target surface of the semiconductor substrate 11 is also generally relatively flat, which is beneficial to improving the formation quality and film thickness of the passivation layer 14 on the target surface, thereby improving the passivation effect of the passivation layer 14 on the semiconductor substrate 11 and improving the conversion efficiency of the solar cell. In addition, the tower-like base-shaped texture portion includes a side surface that is recessed into the passivation layer 14, and the side surface of the tower-like base-shaped texture portion is surrounded to form a polygonal bottom surface. In addition, the first texture structure 15 also includes a ridgeline recessed portion provided on the side of the tower-like base-shaped texture portion close to the semiconductor substrate 11. The ridgeline concave portion includes a ridgeline that extends from at least one corner of the polygonal bottom surface into the passivation layer 14. This creates an undulating tower-like texture with an undulating morphology, superimposed with the ridgeline concave portion at its bottom. This increases the specific surface area of ​​the bottom surface of the first texture structure 15, thereby imparting a relatively large surface roughness to the side of the passivation layer 14 facing away from the semiconductor substrate 11. This increases the specific surface area of ​​the doped semiconductor layer included in the passivation layer 14, or the doped semiconductor layer formed between the passivation layer 14 and the semiconductor substrate 11. This in turn increases the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby enhancing the conversion efficiency of the solar cell. Furthermore, the ridgelines included in the ridgeline concave portion gradually converge toward the central axis of the tower-like texture along the length direction. At this time, the space enclosed by the ridgeline concave portion gradually converges along the depth direction of the concave portion, thereby preventing excessive roughness of the bottom surface of the first texture structure 15 and ensuring that the passivation layer 14 has a high passivation effect.

[0071] In actual applications, the solar cell provided by the embodiments of the present invention can be a double-sided contact cell, that is, one of the positive electrode and the negative electrode of the solar cell is arranged on the front side of the cell, and the other is arranged on the back side of the cell. Alternatively, the solar cell provided by the embodiments of the present invention can also be a back-contact cell, that is, both the positive electrode and the negative electrode of the solar cell are arranged on the back side of the cell.

[0072] Secondly, the solar cell provided by the embodiment of the present invention may be a cell having a tunneling passivation contact structure or a heterogeneous contact structure, or may be a conventional solar cell without the interface passivation layer included in the above structure.

[0073] Specifically, the embodiment of the present invention does not impose any specific limitation on the material of the semiconductor substrate. For example, the semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0074] Regarding the first and second surfaces of the semiconductor substrate, the first surface of the semiconductor substrate can correspond to the front surface of the solar cell, in which case the second surface of the semiconductor substrate can correspond to the back surface of the solar cell; alternatively, the first surface of the semiconductor substrate can correspond to the back surface of the solar cell, in which case the second surface of the semiconductor substrate corresponds to the front surface of the solar cell. Whether the first and second surfaces are target surfaces can be determined based on the type of solar cell and the corresponding relationship between the first and second surfaces and the front and back surfaces of the solar cell, respectively, and is not specifically limited here.

[0075] For example, in the case where the solar cell is a double-sided contact cell, of the first and second surfaces of the semiconductor substrate, only the first surface may be the target surface, only the second surface may be the target surface, or both the first and second surfaces may be the target surface.

[0076] For example, in the case where the solar cell is a back-contact cell, one of the first surface and the second surface of the semiconductor substrate corresponding to the back surface of the cell is the target surface.

[0077] As for the surface topography of the target surface of the semiconductor substrate, as previously described, the surface topography of the passivation layer facing away from the semiconductor substrate can, to a certain extent, reflect the surface topography of the target surface of the semiconductor substrate. Therefore, the surface topography of the target surface can be referenced to the surface topography of the passivation layer facing away from the semiconductor substrate. Specifically, because the surface topography of the passivation layer facing away from the semiconductor substrate is a macroscopically flat surface having multiple first texture structures, the surface topography of the target surface is also relatively flat macroscopically.

[0078] For example, Figure 8As shown, the target surface can have multiple first texture structures 15. A single first texture structure 15 includes a tower-like texture portion and a ridgeline concave portion arranged on the side of the tower-like texture portion close to the semiconductor substrate 11. The tower-like texture portion includes a side surface that is concave into the semiconductor substrate 11, and the side surface of the tower-like texture portion is surrounded by a polygonal bottom surface. The ridgeline concave portion includes a ridgeline that is concave into the semiconductor substrate 11 from at least one corner of the polygonal bottom surface, and the ridgelines included in the ridgeline concave portion gradually converge toward the central axis of the tower-like texture portion along the length direction. In this case, compared with texture structures with a large degree of undulation, such as a pyramid-shaped velvet structure, the ridgeline-like texture portion has a relatively small degree of undulation, making the target surface relatively flat from a macroscopic perspective, which is beneficial to improving the formation quality and film thickness of the passivation layer 14 on the target surface, and further beneficial to improving the passivation effect of the passivation layer 14 on the semiconductor substrate 11, thereby improving the conversion efficiency of the solar cell. In addition, the provision of the ridgeline concave portion is beneficial for increasing the specific surface area of ​​the target surface, and is beneficial for ensuring that the doped semiconductor layer formed on the target surface through deposition or other processes also has a relatively large specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial for improving the conversion efficiency of the solar cell. At the same time, the ridges included in the ridgeline concave portion gradually converge toward the central axis of the tower base texture portion along the length direction. At this time, the space enclosed by the ridgeline concave portion gradually converges along the depth direction of the concave portion, which can prevent the roughness of the bottom surface of the first texture structure 15 from being too large, so that the passivation layer 14 has a higher passivation effect. As for the specific morphology of the first texture structure 15 on the target surface, the number and distribution of the ridges included in the ridgeline concave portion, etc., please refer to the specific morphology of the first texture structure 15 on the side of the passivation layer 14 facing away from the semiconductor substrate 11, the number and distribution of the ridges included in the ridgeline concave portion, etc., which will not be repeated here.

[0079] The passivation layer is disposed on the target surface, with the surface of the passivation layer facing away from the semiconductor substrate serving as the front and / or back surface of the solar cell. The specific structure and materials of the passivation layer can be determined based on the type of solar cell and the actual application scenario, and are not specifically limited here. Exemplarily, the passivation layer may include at least one of an interface passivation layer, a doped semiconductor layer, a surface passivation layer, an anti-reflection layer, and a transparent conductive layer.

[0080] Among them, Figures 2 to 4 As shown, when the passivation layer 14 is merely a doped semiconductor layer, the first textured structure is formed on the side of the doped semiconductor layer facing away from the semiconductor substrate 11. The material of the passivation layer 14 can include any semiconductor material such as silicon, silicon germanium, or germanium. The crystalline phase of the passivation layer 14 can be single crystal, polycrystalline, microcrystalline, nanocrystalline, or amorphous.

[0081] like Figure 9 As shown, when the passivation layer 14 includes only at least one of a surface passivation layer 26, an anti-reflection layer 27, and a transparent conductive layer 28, the first textured structure is formed on the outermost layer of the passivation layer 14 (i.e., the layer with the greatest distance from the semiconductor substrate 11 along the thickness of the cell), on the side of the surface facing away from the semiconductor substrate 11. For example, when the passivation layer 14 includes only a surface passivation layer 26 and an anti-reflection layer 27, and the anti-reflection layer 27 is disposed on the side of the surface passivation layer 26 facing away from the semiconductor substrate 11, the first textured structure is formed on the side of the anti-reflection layer 27 facing away from the semiconductor substrate 11. Furthermore, the materials of the surface passivation layer 26, anti-reflection layer 27, and transparent conductive layer 28 can be determined based on actual needs. For example, the material of the surface passivation layer 26 can include any passivating material, such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the anti-reflection layer 27 can include silicon nitride or silicon oxynitride, among others. The material of the transparent conductive layer 28 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. In the above case, the solar cell provided by the embodiment of the present invention further includes a doped semiconductor layer 20 disposed in or on the target surface (when the doped semiconductor layer 20 is disposed on the target surface, the material of the doped semiconductor layer 20 can be referred to above and will not be described again here), and the passivation layer 14 is located on the side of the doped semiconductor layer 20 facing away from the semiconductor substrate 11.

[0082] like Figure 10 As shown, when the passivation layer 14 includes at least one of a surface passivation layer, an anti-reflection layer, and a transparent conductive layer 28 in addition to the doped semiconductor layer 20, the first textured structure is formed on the outermost layer of the passivation layer 14 (i.e., the layer with the greatest distance from the semiconductor substrate 11 along the thickness of the cell), on the surface facing away from the semiconductor substrate 11. For example, when the passivation layer 14 includes only the doped semiconductor layer 20 and the transparent conductive layer 28, and the transparent conductive layer 28 is disposed on the side of the doped semiconductor layer 20 facing away from the semiconductor substrate 11, the first textured structure is formed on the side of the transparent conductive layer 28 facing away from the semiconductor substrate 11. The formation position of the doped semiconductor layer 20 in the solar cell, as well as the materials of the surface passivation layer, anti-reflection layer, transparent conductive layer 28, and doped semiconductor layer 20, can be found in the previous text and will not be further elaborated here.

[0083] It should be noted that, when the solar cell provided in the embodiment of the present invention is a double-sided contact cell and the passivation layer includes a doped semiconductor layer, the doped semiconductor layer in the same passivation layer is an N-type doped semiconductor layer or a P-type doped semiconductor layer. When the solar cell is a back contact cell and the passivation layer includes a doped semiconductor layer, as Figure 11As shown, along a direction parallel to the target surface, the doped semiconductor layer in the passivation layer includes alternating first doped semiconductor portions 22 and second doped semiconductor portions 23 of opposite conductivity types, and at least a portion of the first doped semiconductor layer is separated from at least a portion of the second doped semiconductor portion 23. Specifically, at least a portion of the first doped semiconductor portion 22 and at least a portion of the second doped semiconductor portion 23 can be spaced apart along a direction parallel to the target surface, or can be separated along the thickness direction of the semiconductor substrate 11 by a dielectric layer made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0084] In addition, when the doped semiconductor layer is disposed on the target surface, as Figure 10 As shown, the doped semiconductor layer 20 may be in direct contact with the semiconductor substrate 11; or Figure 11 As shown, the solar cell may further include an interface passivation layer 25 located between the semiconductor substrate 11 and the doped semiconductor layer. The material and thickness of the interface passivation layer 25 can be determined based on the material of the doped semiconductor layer and are not specifically limited herein. For example, when the doped semiconductor layer comprises a doped polycrystalline silicon layer, the interface passivation layer is a tunneling oxide layer. For another example, when the doped semiconductor layer comprises a doped amorphous silicon layer, the interface passivation layer is an intrinsic amorphous silicon layer.

[0085] In terms of surface morphology, the surface of the passivation layer facing away from the semiconductor substrate has multiple first texture structures. The first texture structure includes a pyramid-like texture portion, in which the polygonal bottom surface surrounded by the side surfaces is a virtual surface. The polygonal bottom surface can be regular or irregular (such as a quadrilateral, pentagonal, hexagonal, or octagonal bottom surface; the polygon can be a regular polygon with the same side length or a polygon with different side lengths). The corners of the polygonal bottom surface can be sharp or chamfered with a smooth transition.

[0086] Specifically, the one-dimensional size of the tower-like base-shaped texture portion, as well as the length, number and distribution of the ridges included in the ridge concave portion, can be determined according to the requirements for the surface roughness of the passivation layer on the side away from the semiconductor substrate in the actual application scenario, as long as it can be applied to the solar cell provided in the embodiment of the present invention. Among them, the one-dimensional size of the tower-like base-shaped texture portion can be the side length of the polygon-like bottom surface, the diagonal length of the polygon-like bottom surface or the concave depth (it should be noted that the concave depth of the tower-like base-shaped texture portion is the concave depth of the main surface of the polygon-like bottom surface relative to the side of the passivation layer away from the semiconductor substrate, that is, the maximum height of the side of the tower-like base-shaped texture portion along the thickness direction of the semiconductor substrate).

[0087] Exemplarily, the side length of the quasi-polygonal bottom surface can be greater than or equal to 2 μm and less than or equal to 12 μm. For example, the side length of the quasi-polygonal bottom surface can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, or 12 μm. When other factors are the same, the side length of the quasi-polygonal bottom surface is within the above range, which helps prevent the distribution density of the first texture structure on the side of the passivation layer facing away from the semiconductor substrate from being too high due to the side length of the quasi-polygon being too small, and helps control the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Accordingly, the target surface is relatively flat on a macroscopic scale, further improving the formation quality of the passivation layer on the target surface and improving the passivation effect of the passivation layer. In addition, it can also prevent the distribution density of the first texture structure on the side of the passivation layer away from the semiconductor substrate from being too small due to the excessive length of the side of the polygonal bottom surface, ensure that the passivation layer has a certain surface roughness on the side away from the semiconductor substrate at the microscopic level, increase the contact area between the doped semiconductor layer and the electrode, improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of solar cells.

[0088] Exemplarily, the concave depth of the tower-like base-shaped texture portion can be greater than or equal to 0.2μm and less than or equal to 0.8μm. For example, the concave depth of the tower-like base-shaped texture portion can be 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm or 0.8μm, etc. In this case, the concave depth of the tower-like base-shaped texture portion is within the above range, which is conducive to preventing the specific surface area of ​​the passivation layer away from the semiconductor substrate from being too small due to the concave depth of the tower-like base-shaped texture portion being too small, ensuring a larger contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. In addition, it can also prevent the specific surface area of ​​the passivation layer away from the semiconductor substrate from being too large due to the concave depth of the tower-like base-shaped texture portion being too large, ensuring that the target surface is relatively flat on a macroscopic scale, improving the formation quality and film thickness of the passivation layer on the target surface, ensuring that the passivation layer has a higher passivation effect, and improving the conversion efficiency of the solar cell.

[0089] As for the ridge concave portion, Figure 12As shown, within the same first texture structure 15, the depth of the ridgeline concave portion 17 relative to the polygonal bottom surface can be less than the depth of the tower-like base-shaped texture portion 16. In this case, the depth of the ridgeline concave portion 17 relative to the polygonal bottom surface is smaller, so that after the ridgeline concave portion 17 is superimposed on the bottom of the tower-like base-shaped texture portion 16, the additional undulation added to the undulating topography originally provided with the tower-like base-shaped portion is smaller. This helps to control the surface roughness of the passivation layer 14 on the side facing away from the semiconductor substrate 11 from being too large, and accordingly, the surface roughness of the target surface on which the passivation layer 14 is formed is not too large, ensuring that the passivation layer 14 has a high formation quality and passivation effect. Alternatively, within the same first texture structure 15, the depth of the ridgeline concave portion 17 relative to the polygonal bottom surface can also be equal to the depth of the tower-like base-shaped texture portion 16.

[0090] Exemplarily, the ratio between the depth of the ridgeline concave portion relative to the polygonal bottom surface and the thickness of the doped semiconductor layer can be greater than or equal to 0.95 and less than or equal to 1.05. The doped semiconductor layer can be a doped semiconductor layer included in the passivation layer, or it can be a doped semiconductor layer arranged between the passivation layer and the semiconductor substrate in the solar cell. For example, the ratio between the depth of the ridgeline concave portion relative to the polygonal bottom surface and the thickness of the doped semiconductor layer can be 0.95, 0.96, 0.97, 0.98, 1, 1.02, 1.04 or 1.05, etc. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the concave depth of the tower-like base texture portion being greater than or equal to 0.2μm and less than or equal to 0.8μm described above, and will not be repeated here.

[0091] As for the specific depth of the ridgeline concave portion, it can be determined according to the depth of the concave portion of the tower base-like texture portion and actual needs.

[0092] Exemplarily, the depth of the ridgeline concave portion relative to the polygonal bottom surface may be greater than or equal to 0.1 μm and less than or equal to 0.3 μm. For example, the depth of the ridgeline concave portion relative to the polygonal bottom surface may be greater than or equal to 0.1 μm, 0.12 μm, 0.14 μm, 0.16 μm, 0.18 μm, 0.2 μm, 0.22 μm, 0.24 μm, 0.26 μm, 0.28 μm, or 0.3 μm. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the concave depth of the tower base-shaped texture portion being greater than or equal to 0.2 μm and less than or equal to 0.8 μm described above, and will not be repeated here.

[0093] The length of the ridgeline concave portion can be determined based on the one-dimensional size of the tower-like texture portion in the same first texture structure and the surface roughness of the passivation layer on the side facing away from the semiconductor substrate in actual application scenarios. For example, the ridgeline length of the ridgeline concave portion can be greater than or equal to 2 μm and less than or equal to 8 μm.

[0094] For example, the length of the ridge line of the ridge concave portion may be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm.

[0095] When employing the above technical solution, if the dimensions of the tower-like base-shaped texture portion included in the first texture structure are constant, the greater the ridgeline length of the ridgeline concave portion, the greater the depth of the ridgeline concave portion relative to the polygonal base. Based on this, when the ridgeline length of the ridgeline concave portion is within the above range, it is helpful to prevent the specific surface area of ​​the passivation layer facing away from the semiconductor substrate from being too small due to the ridgeline length of the ridgeline concave portion being too small, thereby ensuring a larger contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. In addition, it can also prevent the specific surface area of ​​the passivation layer on the side away from the semiconductor substrate from being too large due to the length of the ridge line of the ridge line concave portion being too large, which makes the concave depth of the ridge line concave portion relative to the polygonal bottom surface too large. It ensures the macroscopic flatness of the passivation layer on the side away from the semiconductor substrate, and the corresponding target surface has a smaller surface roughness, thereby improving the formation quality and passivation effect of the passivation layer on the target surface.

[0096] As for the setting angle of the ridge line of the ridge line concave portion, it can be determined according to the ridge line length requirement of the ridge line concave portion in the actual application scenario, and is not specifically limited here.

[0097] Exemplarily, in the same first texture structure, the angle between the ridge line of the ridge line concave portion and the adjacent side ridge line in the tower base-shaped texture portion can be greater than 90° and less than or equal to 175°. For example, the angle between the ridge line of the ridge line concave portion and the adjacent side ridge line in the tower base-shaped texture portion can be 91°, 95°, 100°, 110°, 120°, 130°, 140°, 150°, 160°, 170° or 175°, etc. In this case, the optional range of the above-mentioned angle is relatively large, which is conducive to selecting the appropriate angle size according to different actual needs. For example, if it is necessary to increase the surface roughness of the passivation layer away from the semiconductor substrate as much as possible, the size of the angle can be set within a larger numerical range so that the ridge line included in the ridge line concave portion can be recessed into the passivation layer to a greater depth. On the contrary, if the passivation layer is required to have a higher passivation effect in an actual application scenario, the size of the angle can be set within a smaller numerical range, so that the depth of the ridge line included in the ridge concave portion into the passivation layer is relatively small, so as to regulate the surface roughness of the passivation layer on the side away from the semiconductor wafer, thereby improving the applicability of the solar cell provided by the embodiment of the present invention in different application scenarios.

[0098] Secondly, if Figure 13 As shown in part (5) of FIG. , at least one ridgeline recess may have only one ridgeline; or, as shown in FIG. Figure 13 As shown in parts (1) to (4) and parts (6) to (7) of the present invention, at least one ridgeline concave portion may also include at least two ridgelines that are respectively recessed from at least two corners of the polygonal bottom surface into the passivation layer. In this case, the presence of multiple ridgelines that are recessed from the polygonal bottom surface into the passivation layer within a single ridgeline concave portion can increase the microscopic surface roughness of the side of the passivation layer facing away from the semiconductor substrate, further increase the contact area between the doped semiconductor layer and the electrode, improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, further improving the conversion efficiency of the solar cell.

[0099] In the case where at least one ridgeline concave portion includes at least two ridgelines, the number of ridgelines included in the ridgeline concave portion can be determined based on the number of corners of the quasi-polygonal bottom surface and the surface roughness requirements for the side of the passivation layer facing away from the semiconductor substrate in the actual application scenario. Specifically, the number of ridgelines included in the ridgeline concave portion can be equal to the number of corners included in the quasi-polygonal bottom surface. Alternatively, the number of ridgelines included in the ridgeline concave portion can be less than the number of corners included in the quasi-polygonal bottom surface. In this case, the distribution between different ridgelines in the ridgeline concave portion can be set according to actual needs. For example, the different corners of the quasi-polygonal bottom surface corresponding to different ridges in the ridgeline concave portion can be distributed adjacent to each other, or can be distributed diagonally, etc.

[0100] In addition, if Figure 13As shown in parts (1) to (4), and parts (6) to (7), when at least one ridgeline concave portion includes at least two ridgelines, any two of the different ridgelines may not intersect. Alternatively, the different ridgelines may intersect at at least one point. At this time, compared with the divergent distribution of the at least two ridgelines included in the ridgeline concave portion, when the at least two ridgelines included in the same ridgeline concave portion intersect at at least one point, the side of the ridgeline concave portion away from the tower base-shaped texture portion is more convergent. At this time, when the concave depth of the ridgeline concave portion is constant, the length of the ridgeline included in the ridgeline concave portion is larger, which can further increase the undulation of the bottom surface of the first texture structure, further improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer.

[0101] Specifically, when at least one ridgeline concave portion includes at least two ridgelines, and the different ridgelines intersect at at least one point, the different ridgelines may only intersect at the same point. Alternatively, when at least one ridgeline concave portion includes at least two ridgelines, the different ridgelines may intersect at different points. In this case, the number of intersection points and the relative positional relationship between the different intersection points can be set based on the positional relationship between the different ridgelines and actual needs, and are not specifically limited here.

[0102] It should be noted that the side lengths and / or recessed depths of the tower-base-like texture portions included in different first texture structures may be the same or different. Furthermore, the recessed depths of the ridgeline recessed portions, the number and length of ridges in the ridgeline recessed portions, the distribution of the different ridges in the ridgeline recessed portions, and the angles between the ridges of the ridgeline recessed portions and the corresponding side edges of the tower-base-like texture portion may be the same or at least one of these may be different.

[0103] Among them, as shown above, when the side length and recess depth of the tower-like texture portion included in different first texture structures, and the recess depth of different ridge recessed portions, the number and length of ridges of the ridge recessed portions, the distribution between different ridges of the ridge recessed portions, and the angle between the ridges of the ridge recessed portions and the corresponding side edges in the tower-like texture portion are different, it will affect the surface roughness of the passivation layer facing away from the semiconductor substrate. Therefore, the size range of the above parameters corresponding to different areas of the passivation layer facing away from the semiconductor substrate can be determined based on the different requirements for the surface roughness of different areas of the passivation layer in actual application scenarios, and no specific limitation is made here.

[0104] For example, in the case where the solar cell provided in an embodiment of the present invention is a double-sided contact cell, a collector electrode is provided on the side of the passivation layer facing away from the semiconductor substrate. The collector electrode is in ohmic contact with the doped semiconductor layer included in the double-sided contact cell. Furthermore, the region of the passivation layer facing away from the semiconductor substrate corresponding to the collector electrode is defined as a first region, and the remaining region is defined as a second region. In this case, the one-dimensional dimensions of the first region and the second region may differ. Specifically, it may be that: the side length of the tower-base-like texture portion in the first texture structure on the surface of the first area is smaller than the side length of the tower-base-like texture portion in the first texture structure on the surface of the second area, and / or the depth of the recess of the tower-base-like texture portion in the first texture structure on the surface of the first area is greater than the depth of the recess of the tower-base-like texture portion in the first texture structure on the surface of the second area, and / or the depth of the recess of the ridge line recessed portion in the first texture structure on the surface of the first area is greater than the depth of the recess of the ridge line recessed portion in the first texture structure on the surface of the second area, and / or the number and / or length of the ridge lines of the ridge line recessed portion in the surface of the first area are respectively greater than the number and / or length of the ridge lines of the ridge line recessed portion in the surface of the second area, and / or the angle between the ridge line of the ridge line recessed portion in the surface of the first area and the corresponding side edge in the tower-base-like texture portion is greater than the angle between the ridge line of the ridge line recessed portion in the surface of the second area and the corresponding side edge in the tower-base-like texture portion. Such a setting can make the surface of the first region have a larger surface roughness relative to the surface of the second region, which is beneficial to increasing the contact area between the doped semiconductor layer and the collecting electrode, improving the contact performance between the doped semiconductor layer and the collecting electrode, and enhancing the adhesion and shaping of the collecting electrode on the doped semiconductor layer.

[0105] For example, Figure 11 As shown, in the case where only one of the first and second surfaces is the target surface, and along a direction parallel to the target surface, the passivation layer includes alternating first doped semiconductor portions 22 and second doped semiconductor portions 23 of opposite conductivity types, and at least portions of the first doped semiconductor portions 22 and at least portions of the second doped semiconductor portions 23 are spaced apart, the surface of the passivation layer corresponding to the first doped semiconductor portions 22 facing away from the semiconductor substrate 11 is defined as a first sub-surface, and the surface of the passivation layer 14 corresponding to the second doped semiconductor portions 23 facing away from the semiconductor substrate 11 is defined as a second sub-surface. Based on this, the one-dimensional size of the first texture structure on the first sub-surface and the second sub-surface can be different.

[0106] Specifically, the difference in one-dimensional dimensions of the first texture structures of the first sub-surface and the second sub-surface may refer to: the side lengths and recessed depths of the tower-base-like texture portions included in the different first texture structures in the first sub-surface and the second sub-surface, as well as the recessed depths of different ridgeline recessed portions, the number and lengths of ridges in the ridgeline recessed portions, the distribution between different ridges in the ridgeline recessed portions, and the angles between the ridges in the ridgeline recessed portions and the corresponding side edges in the tower-base-like texture portions are different in at least one of the following.

[0107] When the above technical solution is adopted, the one-dimensional size of the first texture structure on the first sub-surface and the second sub-surface can be set according to the requirements for different passivation effects of the first doped semiconductor portion and the second doped semiconductor portion in the actual application scenario, as well as the requirements for the contact performance between the two and the corresponding electrodes, so that the two parts of the passivation layer corresponding to the first doped semiconductor portion and the second doped semiconductor portion have different passivation effects on the semiconductor substrate, and are conducive to making the first doped semiconductor portion and the second doped semiconductor portion have different surface morphologies, thereby facilitating the reduction of the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor portion and the second doped semiconductor portion, and facilitating the reduction of the difference in contact performance between the first doped semiconductor portion and the second doped semiconductor portion and the corresponding electrodes. Among them, the specific conductivity type of the first doped semiconductor portion and the second doped semiconductor portion, and the size relationship of the one-dimensional size of the first texture structure on the first sub-surface and the second sub-surface under the corresponding conductivity type can be set according to actual needs, as long as it can help reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor portion and the second doped semiconductor portion, and help reduce the difference in contact performance between the first doped semiconductor portion and the second doped semiconductor portion and the corresponding electrodes.

[0108] For example: when the conductivity type of the first doped semiconductor portion is N-type, the side length of the tower-like texture portion in the first texture structure of the first sub-surface is smaller than the side length of the tower-like texture portion in the first texture structure of the second sub-surface, and / or the recess depth of the tower-like texture portion in the first texture structure of the first sub-surface is greater than the recess depth of the tower-like texture portion in the first texture structure of the second sub-surface, and / or the recess depth of the ridge line recess portion in the first texture structure of the first sub-surface is greater than the recess depth of the ridge line recess portion in the first texture structure of the second sub-surface, and / or the number and / or length of ridges of the ridge line recess portion in the first sub-surface are respectively greater than the number and / or length of ridges of the ridge line recess portion in the second sub-surface, and / or the angle between the ridge line of the ridge line recess portion in the first sub-surface and the corresponding side ridge in the tower-like texture portion is greater than the angle between the ridge line of the ridge line recess portion in the second sub-surface and the corresponding side ridge in the tower-like texture portion. Such a setting can make the second sub-surface have a smaller surface roughness relative to the first sub-surface, which is beneficial to reducing the surface roughness of the area corresponding to the second sub-surface in the target surface, and is beneficial to improving the formation quality and film thickness of the P-type doped semiconductor part, increasing the passivation effect of the P-type doped semiconductor part, and reducing the difference in passivation effect between the N-type doped polysilicon layer and the P-type doped semiconductor part.

[0109] In addition, in actual application, the distribution density of the first texture structure in different areas of the passivation layer facing away from the semiconductor substrate may be roughly the same or different. Alternatively, in different areas of the passivation layer facing away from the semiconductor substrate, only some areas have the first texture structure, while the remaining areas do not have the first texture structure. For example, the above-mentioned first texture structure may be distributed only on the second sub-surface, and the first sub-surface does not have the first texture structure. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the first sub-surface and the second sub-surface having different one-dimensional sizes as described above, and is not specifically limited here.

[0110] Among them, the specific conductivity types of the above-mentioned first doped semiconductor part and the second doped semiconductor part can be set according to actual needs, as long as it can help reduce the passivation difference between the two parts of the passivation layer corresponding to the first doped semiconductor part and the second doped semiconductor part, and help reduce the difference in contact performance between the first doped semiconductor part and the second doped semiconductor part and the corresponding electrodes.

[0111] Exemplarily, the conductivity type of the first doped semiconductor portion may be N-type, and the conductivity type of the second doped semiconductor portion may be P-type. In this case, when the first texture structure is distributed only on the second sub-surface corresponding to the P-type doped semiconductor portion, the surface roughness of the second sub-surface is relatively smooth on a macroscopic scale, which is beneficial to improving the formation quality and passivation effect of the P-type doped semiconductor portion, and reducing the difference in passivation effect between the P-type doped semiconductor portion and the N-type doped semiconductor portion. Secondly, due to the presence of the ridgeline concave portion, the P-type doped semiconductor portion and the positive electrode can have a larger contact area, thereby improving the contact performance between the P-type doped semiconductor portion and the positive electrode, as well as the adhesion and shaping of the positive electrode on the P-type doped semiconductor portion, thereby improving the conversion efficiency of the solar cell.

[0112] In addition, in actual application, the side surface of the tower base-like texture portion can be a relatively flat surface. Figures 5 to 7 As shown, at least one side of the first texture structure 15 has multiple raised portions 18 that rise along the extension direction of the side ridges, and multiple raised portions 18 on the same side have an undulating morphology extending parallel to the first direction. The first direction is different from the length direction of the side ridges of the tower-like texture portion. In this case, the presence of the raised portions 18 can increase the surface undulation of the side of the tower-like texture portion, further increasing the surface roughness of the side of the passivation layer facing away from the semiconductor substrate, thereby further increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of the solar cell. In addition, the raised portions 18 rise on the side of the tower-like texture portion, and the direction of their rise is roughly parallel to the extension direction of the side ridges. In this case, the inclination angle of the raised portions 18 relative to the polygonal bottom surface of the tower-like texture portion can range from 30° to 60°.

[0113] Specifically, the first direction may be any direction different from the length direction of the side ridgeline of the base-like texture portion. The optional first direction may be parallel to the target surface. Secondly, the convex portion may be formed on the side corresponding to only one corner of the polygonal bottom surface of the base-like texture portion. Or, as Figure 7 As shown, the side surfaces corresponding to at least two corners of the polygonal base may have raised portions 18; in this case, the distribution relationship between the different corners having raised portions 18 in the same polygonal base may be determined according to the actual manufacturing process.

[0114] For example, Figure 7As shown, in at least one of the tower-like base-shaped texture portions, at least one pair of corners corresponding to the polygonal base surface each have a raised portion 18 on the side surface. The at least one pair of corners can be two diagonally disposed corners of the polygonal base surface. In this case, compared to having raised portions 18 on only one corner of the polygonal base surface, when at least one of the corners corresponding to the polygonal base surface each have raised portions 18 on the side surface, more raised portions 18 are provided in at least one of the same tower-like base-shaped texture portions. This further increases the undulation of the passivation layer on the side facing away from the semiconductor substrate. It also facilitates the diagonal distribution of different raised portions 18 at different corners of the polygonal base surface, rather than concentrating them at a single corner. This further facilitates higher surface roughness in different diagonal regions of the same tower-like base-shaped texture portion, improving contact between different regions of the doped semiconductor layer and the electrode, and ensuring strong adhesion and good shaping of the electrode on different regions of the doped semiconductor layer.

[0115] In addition, as mentioned above, the presence of the protrusion is beneficial to increasing the surface roughness of the side of the passivation layer facing away from the semiconductor substrate at the microscopic level, and thus helps to increase the contact area between the doped semiconductor layer and the electrode, improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. However, if the size of the protrusion is too large, it will affect the formation quality of the passivation layer on the target surface. Therefore, the size of the protrusion can be determined based on the requirements for the passivation effect of the passivation layer, the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0116] like Figure 14 As shown, when a single protrusion only rises from one corner of the polygonal bottom surface to the height of the side surface, the corner may have only one protrusion structure 19 along the extension direction of the side ridge line (each protrusion structure 19 includes multiple protrusions extending and distributed along the first direction). At this time, a part of the side surface of the tower base-like texture portion is exposed. Or, as Figure 15 As shown, in at least one of the tower-like base-shaped texture portions, at least one corner of the polygonal bottom surface may also have at least two raised structures 19 distributed in a stepped manner along the direction in which the side ridges extend (each raised structure 19 includes multiple raised portions extending along the first direction). In this case, the at least two raised structures 19 distributed in a stepped manner can further increase the degree of undulation of the side surface of the tower-like base-shaped texture portion along the direction in which the ridges extend, further increasing the surface roughness of the side of the passivation layer facing away from the semiconductor substrate, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby increasing the conversion efficiency of the solar cell.

[0117] As for the morphology of the raised portion and the undulating morphology of multiple raised portions included in the same raised structure extending along the first direction, they can be determined according to the recessed depth of the tower base-like texture portion and the actual application scenario, and are not specifically limited here.

[0118] For example, Figure 14 and Figure 15 As shown, the multiple protrusions included in the same protrusion structure 19 can have a zigzag or wavy undulation extending along the first direction. In this case, compared with a single convex or concave undulation such as an arc, the zigzag and wavy undulations both have a continuous undulation of convex, concave, convex, concave, etc., which can further increase the surface roughness of the tower-like texture portion, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer.

[0119] For example, Figure 14 and Figure 15 As shown, at least one raised portion can be shaped like a triangular prism, a cone, or a cylinder. In this case, the raised portion has a variety of morphologies, which helps improve the applicability of the solar cell provided by the embodiments of the present invention in different application scenarios. Furthermore, the difficulty of manufacturing the tower-base-like texture portion can be reduced.

[0120] It should be noted that the aforementioned quasi-triangular prism shape may be a regular triangular prism shape, the ridge lines of which are substantially parallel to the side ridge lines of the tower-base-like texture portion; or the quasi-triangular prism shape may be a quasi-triangular prism shape with irregular morphologies such as arc-shaped ridge lines or side surfaces. For example: Figure 14 and Figure 15 As shown, at least one raised structure 19 includes a raised portion in the shape of a triangular prism, and the ridgeline of the raised portion can be in the shape of an arc that is concave toward the direction close to the semiconductor substrate. In this case, when the raised portion on at least one corner is in the shape of a triangular prism, compared to when the ridgeline of the raised portion is a straight line, when the ridgeline of the raised portion is in the shape of an arc that is concave toward the direction close to the semiconductor substrate, the portion of the raised portion corresponding to the concave arc-shaped ridgeline also has a concave undulating morphology, which can further increase the surface roughness of the tower-like texture portion in the area where the raised portion is provided, which is conducive to further increasing the specific surface area of ​​the above-mentioned doped semiconductor layer, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. It should be noted that the arc-shaped ridgeline in the raised portion that is concave toward the direction close to the semiconductor substrate refers to the top ridgeline of the triangular prism-like structure.

[0121] The above-mentioned conical and cylindrical shapes can be regular conical or regular cylindrical shapes respectively (a part of the side of the regular conical or regular cylindrical shape can be integrated with the side of the tower base-shaped texture part); or the conical and cylindrical shapes can also be irregular conical or cylindrical shapes with concave or convex microstructures on the side.

[0122] Furthermore, when a raised structure is provided on the side of the tower-base-like texture portion, the ridgeline recessed portion may be recessed into the passivation layer from the bottom of the raised structure located on the bottom layer. The raised structure located on the bottom layer is the raised structure closest to the bottom surface of the polygonal-like surface on the same side of the tower-base-like texture portion.

[0123] Secondly, in the case where a raised structure is provided on the side of the tower-base-like texture portion, in the same first texture structure, the depth of the recessed portion of the ridge line relative to the bottom surface of the quasi-polygonal surface can be less than the sum of the heights of all the raised structures on the side of the tower-base-like texture portion. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the recessed depth of the ridge line recessed portion relative to the bottom surface of the quasi-polygonal surface being less than the recessed depth of the tower-base-like texture portion in the same first texture structure described above, and will not be repeated here. Alternatively, the recessed depth of the ridge line recessed portion relative to the bottom surface of the quasi-polygonal surface can also be equal to the sum of the heights of all the raised structures on the side of the tower-base-like texture portion.

[0124] As a possible implementation, Figure 5 As shown, the side of the passivation layer facing away from the semiconductor substrate may also have multiple second texture structures 21, wherein a single second texture structure 21 is a tower-shaped texture structure, and the tower-shaped texture structure includes a side surface and a bottom surface that are concave into the passivation layer, and the bottom surface of the tower-shaped texture structure is flat. In this case, the bottom surface of the tower-shaped texture structure included in the second texture structure 21 is flatter than the bottom surface of the first texture structure, which helps reduce the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. The corresponding target surface has a lower surface roughness, which helps improve the formation quality of the passivation layer on the target surface and the passivation effect.

[0125] Specifically, the bottom surface of the tower base-shaped texture structure included in the second texture structure can be a regular or irregular polygonal bottom surface (such as a quadrilateral bottom surface, a pentagonal bottom surface, a hexagonal bottom surface, or an octagonal bottom surface; the polygonal bottom surface can be a regular polygon with the same side length or a polygon with different side lengths). The corners of the polygonal bottom surface can be sharp corners or chamfered corners with smooth transitions. Alternatively, it can be an irregular bottom surface with a curved contour.

[0126] The recessed depth of the first texture portion can be greater than or equal to the recessed depth of the second texture structure. When the recessed depth of the first texture portion is greater than the recessed depth of the second texture structure, no ridgeline recessed portion is provided on the bottom surface of the tower-shaped texture structure, where the recessed depth is smaller. This facilitates controlling the specific surface area of ​​the passivation layer on the side facing away from the semiconductor substrate, and accordingly facilitates controlling the surface roughness of the target surface, further improving the formation quality and passivation effect of the passivation layer on the target surface, and thereby improving the conversion efficiency of the solar cell.

[0127] As for the specific one-dimensional size of the second texture structure, it can be set according to the actual application scenario. For example, the recessed depth of the second texture structure can be less than or equal to 0.1μm. For example, the recessed depth of the second texture structure can be 10nm, 20nm, 40nm, 50nm, 70nm or 0.1μm, etc. In this case, the recessed depth of the second texture structure is smaller, ensuring that the side of the passivation layer away from the semiconductor substrate is macroscopically smoother, further improving the formation quality and passivation effect of the passivation layer on the target surface, and helping to improve the conversion efficiency of the solar cell.

[0128] In addition, when the side of the passivation layer facing away from the semiconductor substrate also includes a second texture structure, at least one side of the first texture structure or the second texture structure may be a plane, or at least one side may have multiple raised portions that rise along the direction in which the side ridges extend, with the multiple raised portions on the same side having an undulating topography extending parallel to a second direction. The second direction is different from the direction in which the side ridges extend. The size and distribution of the raised portions in this case can be referenced to the size and distribution of the multiple raised portions that rise along the direction in which the side ridges extend on at least one side of the first texture structure, and will not be further described here.

[0129] Among them, when there are multiple raised portions on at least one side of at least one first texture structure, at least one raised portion can extend from the ridge line of the ridge concave portion to the corresponding side of the tower-like base texture portion. In this case, it is beneficial to increase the ridge extension length of the ridge concave portion, further increase the specific surface area of ​​the first texture structure, increase the surface roughness of the passivation layer away from the semiconductor substrate, increase the contact area between the doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. Alternatively, at least one raised portion can also extend from the top of the ridge concave portion (i.e., the side close to the tower-like base texture portion) to the corresponding side of the tower-like base texture portion.

[0130] Furthermore, when the side of the passivation layer facing away from the semiconductor substrate further includes a second texture structure, the second texture structure may be distributed throughout the regions of the side of the passivation layer facing away from the semiconductor substrate, or may be distributed only in a local region of the side of the passivation layer facing away from the semiconductor substrate. Specifically, when the second texture structure is distributed only in a local region of the side of the passivation layer facing away from the semiconductor substrate, which regions of the side of the passivation layer facing away from the semiconductor substrate have the second texture structure and which regions do not have the second texture structure can be determined based on actual needs and are not specifically limited herein.

[0131] For example, the side of the passivation layer facing away from the semiconductor substrate includes an electrode region and a non-electrode region. The electrode region is the area of ​​the passivation layer facing away from the semiconductor substrate where the collector electrode is located, and the non-electrode region is any area of ​​the passivation layer facing away from the semiconductor substrate where the collector electrode is not located. Based on this, the first texture structure can be distributed in the electrode region, and the second texture structure can be distributed in the non-electrode region.

[0132] For another example, the side of the passivation layer facing away from the semiconductor substrate includes a first region and a second region. The first region is the area of ​​the passivation layer facing away from the semiconductor substrate corresponding to the doped semiconductor layer, and the second region is the area of ​​the passivation layer facing away from the semiconductor substrate that does not correspond to the doped semiconductor layer. Based on this, the first texture structure can be distributed in the first region, and the second texture structure can be distributed in the second region.

[0133] As a possible implementation scheme, the side of the passivation layer facing away from the semiconductor substrate may also have a linear texture structure, with at least one side of the linear texture structure having multiple raised portions intersecting with the extension direction of the linear texture structure, and the multiple raised portions located on the same side of the linear texture structure having an undulating morphology extending in a direction parallel to the bottom surface of the linear texture structure. In this case, the presence of the linear texture structure can increase the surface roughness of the side of the passivation layer facing away from the semiconductor substrate. Secondly, having multiple raised portions on at least one side of the linear texture structure, that is, superimposing the undulating degree of the raised portions on the linear texture structure with an undulating morphology, is conducive to further increasing the contact area between the above-mentioned doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, as well as the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell.

[0134] Specifically, the linear texture structure can be a cutting line formed when cutting a semiconductor substrate during the actual manufacturing process. After polishing and cleaning, the linear texture structure remains and imparts a substantially similar morphology to the surface of the passivation layer disposed on the target surface. Therefore, the size and extension direction of the linear texture structure can be determined by the size of the cutting line and the specific manufacturing process of polishing and cleaning, and are not specifically limited here.

[0135] The above-mentioned linear texture structure can be a linear protrusion structure extending in a single direction. Alternatively, at least one linear texture structure has a bending portion bent toward the same side at both ends along the length direction, and a connecting portion located between the two bending portions. The angle between the bending portion and the connecting portion is greater than 0 and less than 90°. In this case, compared with a linear linear texture structure, when at least one linear texture structure has a bending portion, it is beneficial to increase the degree of morphological change of the linear texture structure, and to increase the surface roughness of the side of the passivation layer away from the semiconductor substrate, further increase the contact area between the above-mentioned doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, thereby improving the conversion efficiency of the solar cell. The specific size of the angle can be determined according to the parameters of the cutting operation on the semiconductor substrate in the actual manufacturing process and actual needs, and is not specifically limited here.

[0136] As a possible implementation, the side of the passivation layer facing away from the semiconductor substrate may also have a linear texture structure, with the surface of the linear texture structure having a plurality of discretely distributed conical-shaped protrusions. The morphology of the linear texture structure in this case can be referred to above and will not be repeated here.

[0137] As for the cone-like protrusion structures, such as Figure 16 As shown, the conical protrusion structure 24 refers to a conical protrusion structure with a smooth top. At this time, the surface morphology of the conical protrusion structure 24 is relatively smooth, which can ensure that the surface of the side of the passivation layer away from the semiconductor substrate is relatively flat from a macroscopic perspective; secondly, because the conical protrusion structure 24 has a certain degree of undulation relative to the surface of the passivation layer, compared with the surface only having a tower-like texture portion and a linear texture structure, when the surface of the side of the passivation layer away from the semiconductor substrate also has the above-mentioned conical protrusion structure 24, the side of the passivation layer 14 away from the semiconductor substrate can have a relatively large surface roughness at the microscopic level, which is beneficial to increase the doped semiconductor layer included in the passivation layer 14, or the doped semiconductor layer formed between the passivation layer and the semiconductor substrate has a larger specific surface area, thereby increasing the contact area between the doped semiconductor layer and the electrode, improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improving the conversion efficiency of the solar cell. Secondly, different types of conical protrusion structures 24 are distributed in a discrete manner rather than in a close proximity, so that their distribution density on the side of the passivation layer away from the semiconductor substrate is relatively small, further improving the macroscopic flatness of the surface of the passivation layer away from the semiconductor substrate.

[0138] It is understood that the size of the quasi-conical protrusions affects the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Specifically, with all other factors being equal, the smaller the spacing between two adjacent quasi-conical protrusions, the greater the distribution density of the quasi-conical protrusions on the side of the passivation layer facing away from the semiconductor substrate, resulting in greater surface roughness on the side of the passivation layer facing away from the semiconductor substrate. Conversely, the larger the spacing between two adjacent quasi-conical protrusions, the smaller the distribution density of the quasi-conical protrusions on the side of the passivation layer facing away from the semiconductor substrate, resulting in less surface roughness on the side of the passivation layer facing away from the semiconductor substrate. Secondly, with all other factors being equal, the height of the quasi-conical protrusion is proportional to its own undulation and to the surface roughness of the passivation layer on the side facing away from the semiconductor substrate. Furthermore, with all other factors being equal, the smaller the diameter of the quasi-conical protrusion, the smaller the angle corresponding to its rounded top, resulting in a "slender" appearance with greater surface undulation. Conversely, the larger the diameter of the conical protrusion, the larger the angle corresponding to its rounded top, resulting in a "short and fat" shape with less surface undulation. Based on this, the surface roughness requirements for the side of the passivation layer facing away from the semiconductor substrate can be determined based on the actual application scenario and are not specifically limited here.

[0139] Exemplarily, the spacing between two adjacent quasi-conical protrusion structures can be greater than or equal to 0.5 μm and less than or equal to 3 μm. For example, the spacing between two adjacent quasi-conical protrusion structures can be 0.5 μm, 0.06 μm, 0.08 μm, 1 μm, 1.2 μm, 1.4 μm, 1.8 μm, 2 μm, 2.4 μm, 2.8 μm or 3 μm, etc. In this case, based on this, when the spacing between two adjacent quasi-conical protrusion structures is within the above range, it can prevent the surface roughness of the passivation layer on the side away from the semiconductor substrate from being larger due to the spacing being too small, ensuring that the target surface of the semiconductor substrate has a relatively flat surface, further improving the formation quality of the passivation layer on the target surface, and facilitating the increase of the film thickness of the passivation layer, which is conducive to further improving the passivation effect of the passivation layer on the semiconductor substrate. In addition, it can also prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being smaller due to the large spacing, which is beneficial to further increase the specific surface area of ​​the above-mentioned doped semiconductor layer, and then increase the contact area between the doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell.

[0140] Exemplarily, the height of the above-mentioned cone-shaped protrusion structure can be greater than or equal to 0.2 μm and less than or equal to the height of the non-pyramid texture structure. In this case, based on this, when the height of the cone-shaped protrusion structure is within the above-mentioned range, it is beneficial to prevent the surface roughness of the passivation layer away from the semiconductor substrate from being too small due to the height being too small, and it is beneficial to further increase the specific surface area of ​​the above-mentioned doped semiconductor layer, thereby increasing the contact area between the doped semiconductor layer and the electrode, further improving the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer. In addition, it can also prevent the surface roughness of the passivation layer away from the semiconductor substrate from being too large due to the height being too large, ensuring that the target surface of the semiconductor substrate on which the passivation layer is formed has a relatively flat surface, further improving the formation quality of the passivation layer on the target surface, and facilitating the increase of the film thickness of the passivation layer, further improving the passivation effect of the passivation layer on the semiconductor substrate, and improving the conversion efficiency of the solar cell.

[0141] For example, the height of the cone-like protrusion structure is less than or equal to 0.5 μm. In this case, the height of the cone-like protrusion structure can be prevented from being too large. The beneficial effects thereof can be referred to above and will not be described in detail here.

[0142] For example, the height of the cone-like protrusion structure may be 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, 0.45 μm or 0.5 μm, etc.

[0143] Specifically, such as Figure 16 As shown, the height of the aforementioned quasi-conical protrusion structure 24 can be less than the base diameter of the quasi-conical protrusion structure 24. In this case, compared to a "tall and thin" quasi-conical protrusion structure 24 whose height is less than its base diameter, when the height of the quasi-conical protrusion structure 24 is less than the base diameter of the quasi-conical protrusion structure 24, the quasi-conical protrusion structure 24 appears "short and fat," ensuring that the side of the passivation layer facing away from the semiconductor substrate has relatively small undulations, ensuring that the side of the passivation layer facing away from the semiconductor substrate and the target surface of the semiconductor substrate are macroscopically flat, further improving the formation quality of the passivation layer on the target surface, and facilitating the increase of the film thickness of the passivation layer, thereby improving the passivation effect of the passivation layer on the semiconductor substrate and the conversion efficiency of the solar cell. Of course, at least one quasi-conical protrusion structure 24 may have a height greater than or equal to the width of the quasi-conical protrusion structure 24.

[0144] Exemplarily, the diameter of the aforementioned quasi-conical protrusion structure may be greater than or equal to 0.5 μm and less than or equal to 0.65 μm. For example, the diameter of the quasi-conical protrusion structure may be 0.5 μm, 0.51 μm, 0.53 μm, 0.55 μm, 0.58 μm, 0.6 μm, 0.62 μm, or 0.65 μm, etc. In this case, based on this, when the diameter of the quasi-conical protrusion structure is within the above range, it is beneficial to prevent the surface roughness of the passivation layer on the side away from the semiconductor substrate from being larger due to the smaller diameter, ensuring that the target surface of the semiconductor substrate has a relatively flat surface, further improving the formation quality of the passivation layer on the target surface, and facilitating an increase in the film thickness of the passivation layer, thereby further improving the passivation effect of the passivation layer on the semiconductor substrate. In addition, it can also prevent the surface roughness of the passivation layer on the side facing away from the semiconductor substrate from being smaller due to the larger diameter, which is beneficial to further increase the specific surface area of ​​the above-mentioned doped semiconductor layer, and then increase the contact area between the doped semiconductor layer and the electrode, further improve the contact performance between the doped semiconductor layer and the electrode, and the adhesion and shaping of the electrode on the doped semiconductor layer, which is beneficial to improve the conversion efficiency of the solar cell.

[0145] As a possible implementation scheme, the side of the passivation layer facing away from the semiconductor substrate may also have a convex-type structure. The convex-type structure may be the convex-type structure remaining after the top of the pyramid-type structure is eliminated. The application principle of the beneficial effect in this case can refer to the application principle of the beneficial effect of the passivation layer having a linear texture structure on the side facing away from the semiconductor substrate described above, and will not be repeated here. Secondly, the surface of the convex-type structure may also have the above-mentioned conical-like protrusion structure to further increase the microscopic surface roughness of the side of the passivation layer facing away from the semiconductor substrate.

[0146] In a second aspect, an embodiment of the present invention provides a photovoltaic module, which includes the solar cell provided by the first aspect and various implementations thereof.

[0147] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0148] In a third aspect, an embodiment of the present invention provides a semiconductor substrate having a first surface and a second surface relative to each other. At least one of the first surface and the second surface is a target surface. The target surface has a plurality of first texture structures. A single first texture structure includes a tower-like texture portion and a ridgeline recessed portion provided on a side of the tower-like texture portion close to the semiconductor substrate. The tower-like texture portion includes a side surface recessed in the semiconductor substrate, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion. The ridgeline recessed portion includes a ridgeline recessed into the semiconductor substrate by at least one corner of the polygonal bottom surface, and the ridgeline recessed portion includes a ridgeline gradually converging toward the central axis of the tower-like texture portion along the length direction.

[0149] In one example, on the target surface, in the same first texture structure, the angle between the ridge of the ridge concave portion and the adjacent side ridge of the tower base-like texture portion is greater than 90° and less than or equal to 175°.

[0150] In one example, on the target surface, at least one ridgeline recess includes at least two ridgelines recessed into the semiconductor substrate from at least two corners of the polygonal bottom surface, and the at least two ridgelines included in the ridgeline recess meet at at least one point.

[0151] In one example, on the target surface, in the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is smaller than the depth of the tower base-like texture portion.

[0152] In one example, on the target surface, the concave depth of the pyramid-like texture portion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm.

[0153] In one example, on the target surface, the depth of the ridgeline concave portion relative to the quasi-polygonal bottom surface is greater than or equal to 0.1 μm and less than or equal to 0.3 μm.

[0154] In one example, on the target surface, the side length of the polygonal bottom surface is greater than or equal to 2 μm and less than or equal to 12 μm.

[0155] In one example, on the target surface, the ridgeline concave portion has a ridgeline with a length greater than or equal to 2 μm and less than or equal to 8 μm.

[0156] In one example, on the target surface, at least one side surface of the first texture structure has a plurality of raised portions rising along the extension direction of the side ridge line, and the plurality of raised portions on the same side surface have an undulating morphology extending parallel to the first direction; the first direction is different from the length direction of the side ridge line of the tower base-shaped texture portion.

[0157] In one example, on the target surface, in at least one tower-base-shaped texture portion, at least one side has at least two raised structures distributed in a stepped manner along the extension direction of the side ridge line, and each raised structure includes a plurality of raised portions extending along the first direction; the ridge line concave portion is concave from the bottom of the raised structure located at the bottom layer into the semiconductor substrate.

[0158] In one example, on the target surface, in the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is less than the sum of the heights of all convex structures on the side surface of the tower base-like texture portion.

[0159] In one example, the target surface also has multiple second texture structures, a single second texture structure is a tower-shaped texture structure, and the tower-shaped texture structure includes side surfaces and a bottom surface that are concave into the semiconductor substrate, and the bottom surface of the tower-shaped texture structure is a plane; the concave depth of the first texture portion is greater than the concave depth of the second texture structure.

[0160] In one example, on the target surface, a recessed depth of the second texture structure is less than or equal to 0.1 μm.

[0161] In one example, on the target surface, at least one side of the first texture structure or the second texture structure has a plurality of raised portions rising along the extension direction of the side ridge line, and the plurality of raised portions on the same side have an undulating topography extending parallel to a second direction; the second direction is different from the extension direction of the side ridge line.

[0162] In one example, on the target surface, when there are multiple protrusions on at least one side of at least one first texture structure, at least one protrusion extends from the ridge line of the ridge line concave portion to the corresponding side of the tower base-shaped texture portion.

[0163] In one example, the target surface also has a linear texture structure, at least one side of the linear texture structure has a plurality of raised portions intersecting with an extension direction of the linear texture structure, and the plurality of raised portions located on the same side of the linear texture structure have an undulating topography extending in a direction parallel to a bottom surface of the linear texture structure.

[0164] In one example, on the target surface, at least one linear texture structure has a bending portion bent toward the same side at both ends along the length direction, and a connecting portion located between the two bending portions; the angle between the bending portion and the connecting portion is greater than 0 and less than 90°.

[0165] It should be noted that the semiconductor substrate provided in the third aspect of the present invention is used to manufacture the solar cell provided in the first aspect. The specific morphology of the first texture structure on the target surface of the semiconductor substrate, as well as the number and distribution of ridges included in the ridgeline recesses, can be found in the aforementioned information regarding the specific morphology of the first texture structure on the side of the passivation layer facing away from the semiconductor substrate, as well as the number and distribution of ridges included in the ridgeline recesses, and will not be further described here.

[0166] The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be analyzed with reference to the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0167] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0168] The above describes the embodiments of the present invention. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Various substitutions and modifications may be made by those skilled in the art without departing from the scope of the present invention, and such substitutions and modifications are intended to fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: a semiconductor substrate having a first side and a second side opposite to each other; At least one of the first surface and the second surface is a target surface; a passivation layer, disposed on the target surface; The passivation layer has a plurality of first texture structures on a side facing away from the semiconductor substrate; a single first texture structure includes a tower-like texture portion and a ridgeline concave portion provided on a side of the tower-like texture portion close to the semiconductor substrate; the tower-like texture portion includes a side surface concave into the passivation layer, and a polygonal bottom surface is formed by the side surfaces of the tower-like texture portion; the ridgeline concave portion includes a ridge line concave into the passivation layer from at least one corner of the polygonal bottom surface, and the ridge lines included in the ridgeline concave portion gradually converge toward the central axis of the tower-like texture portion along the length direction; The side of the passivation layer facing away from the semiconductor substrate also has a linear texture structure, and at least one side of the linear texture structure has a plurality of protrusions intersecting with the extension direction of the linear texture structure, and the plurality of protrusions located on the same side of the linear texture structure have an undulating morphology extending in a direction parallel to the bottom surface of the linear texture structure.

2. The solar cell according to claim 1, wherein In the same first texture structure, the angle between the ridge of the ridge concave portion and the adjacent side ridge of the tower base-like texture portion is greater than 90° and less than or equal to 175°.

3. The solar cell according to claim 1, wherein At least one of the ridgeline concave portions includes at least two ridgelines respectively concave from at least two corners of the quasi-polygonal bottom surface into the passivation layer, and the at least two ridgelines included in the ridgeline concave portion intersect at at least one point.

4. The solar cell according to claim 1, wherein In the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is smaller than the depth of the tower base-like texture portion; And / or, the concave depth of the tower base-like texture portion is greater than or equal to 0.2 μm and less than or equal to 0.8 μm; And / or, a depth of the ridgeline concave portion relative to the quasi-polygonal bottom surface is greater than or equal to 0.1 μm and less than or equal to 0.3 μm.

5. The solar cell according to claim 1, wherein The passivation layer includes a doped semiconductor layer, and a ratio of a depth of the ridgeline concave portion relative to the polygonal bottom surface to a thickness of the doped semiconductor layer is greater than or equal to 0.95 and less than or equal to 1.

05.

6. The solar cell according to claim 1, wherein The side length of the polygonal bottom surface is greater than or equal to 2 μm and less than or equal to 12 μm; And / or, the length of the ridge line of the ridge line concave portion is greater than or equal to 2 μm and less than or equal to 8 μm.

7. The solar cell according to claim 1, wherein At least one side of the first texture structure has a plurality of raised portions rising along the extension direction of the side ridge line, and the plurality of raised portions on the same side have an undulating morphology extending parallel to the first direction; the first direction is different from the length direction of the side ridge line of the tower base-like texture portion.

8. The solar cell according to claim 7, characterized in that At least one side surface of at least one of the tower base-like texture portions has at least two raised structures distributed in a stepped manner along the extending direction of the side ridge line, and each of the raised structures includes a plurality of raised portions extending and distributed along the first direction; The ridgeline concave portion is concave from the bottom of the convex structure located at the bottom layer into the passivation layer.

9. The solar cell according to claim 8, characterized in that In the same first texture structure, the depth of the ridgeline concave portion relative to the polygonal bottom surface is less than the sum of the heights of all the convex structures on the side surface of the tower base-like texture portion.

10. The solar cell according to claim 1, wherein The passivation layer further has a plurality of second texture structures on a side facing away from the semiconductor substrate, wherein each of the second texture structures is a tower-shaped texture structure, and the tower-shaped texture structure includes a side surface and a bottom surface that are concave into the passivation layer, and the bottom surface of the tower-shaped texture structure is a plane; The recessed depth of the first texture structure is greater than the recessed depth of the second texture structure.

11. The solar cell according to claim 10, characterized in that The recessed depth of the second texture structure is less than or equal to 0.1 μm.

12. The solar cell according to claim 10, characterized in that At least one side of the first texture structure or the second texture structure has a plurality of raised portions rising along the extension direction of the side ridge line, and the plurality of raised portions on the same side have an undulating morphology extending parallel to a second direction; the second direction is different from the extension direction of the side ridge line.

13. The solar cell according to claim 12, wherein: In the case where at least one side surface of at least one of the first texture structures has a plurality of the protrusions, at least one of the protrusions extends from the ridge line of the ridge line recessed portion to the corresponding side surface of the tower base-like texture portion.

14. The solar cell according to claim 1, wherein The side of the passivation layer facing away from the semiconductor substrate further has a linear texture structure, and the surface of the linear texture structure has a plurality of discretely distributed cone-like protrusion structures.

15. The solar cell according to claim 1 or 14, characterized in that At least one of the linear texture structures has two ends along the length direction of the bent portion bent toward the same side, and a connecting portion located between the two bent portions; the angle between the bent portion and the connecting portion is greater than 0 and less than 90°.

16. The solar cell according to claim 1, wherein Only one of the first surface and the second surface is the target surface; along a direction parallel to the target surface, the passivation layer includes first doped semiconductor portions and second doped semiconductor portions that are alternately distributed and have opposite conductivity types, and at least a portion of the first doped semiconductor portion is spaced apart from at least a portion of the second doped semiconductor portion; The surface of the passivation layer corresponding to the first doped semiconductor portion and facing away from the semiconductor substrate is a first sub-surface, and the surface of the passivation layer corresponding to the second doped semiconductor portion and facing away from the semiconductor substrate is a second sub-surface. The first texture structure is distributed only on the second sub-surface; or the first texture structure has different one-dimensional sizes on the first sub-surface and the second sub-surface.

17. The solar cell according to claim 16, characterized in that The conductivity type of the first doped semiconductor portion is N-type, and the conductivity type of the second doped semiconductor portion is P-type.

18. A photovoltaic module, characterized in that: The solar cell comprises the solar cell according to any one of claims 1 to 17.

19. A semiconductor substrate, characterized in that: The semiconductor substrate has a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; the target surface has a plurality of first texture structures; a single first texture structure includes a tower-like texture portion and a ridgeline concave portion provided on a side of the tower-like texture portion close to the semiconductor substrate; the tower-like texture portion includes a side surface concave in the semiconductor substrate, and a polygonal bottom surface is formed by the side surface of the tower-like texture portion; the ridgeline concave portion includes a ridgeline concave in the semiconductor substrate from at least one corner of the polygonal bottom surface, and the ridgelines included in the ridgeline concave portion gradually converge toward the central axis of the tower-like texture portion along the length direction; The target surface also has a linear texture structure, at least one side of the linear texture structure has a plurality of raised portions intersecting with the extension direction of the linear texture structure, and the plurality of raised portions located on the same side of the linear texture structure have an undulating morphology extending in a direction parallel to the bottom surface of the linear texture structure.

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