Display panel and display device

Abstract

A display panel includes a plurality of first data lines and a plurality of second data lines each extending in a first direction in a display area and alternately arranged in a second direction different from the second direction; the projection of the first data line projected to the second direction along the first direction is overlapped with the projection of the through hole and / or the winding area projected to the second direction along the first direction, and the first data line comprises a first data line branch and a second data line branch which are respectively positioned on two sides of the winding area along the first direction and are connected through a first connecting line; the first connecting line is located in the winding area; the projection projected to the second direction along the first direction of the second data line is overlapped with the projection projected to the second direction along the first direction of the through hole and / or the winding area along the first direction of the second data line, and the second data line comprises a third data line branch and a fourth data line branch which are located on the two sides of the winding area along the first direction respectively and connected through a second connecting line; the second connecting line is located in the display area.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to a display panel and a display device. Background Art

[0002] As display technology continues to upgrade, organic light-emitting diode (OLED) display panels have begun to gradually replace liquid crystal (LCD) display panels. Currently, the production cost of OLED display panels is still relatively high, so reducing the production cost of display panels is an important consideration in the development process of display panels. Summary of the invention

[0003] On the one hand, the present disclosure provides a display panel, comprising: a through hole; a display area, which surrounds the through hole and is configured to display an image; and a winding area, which is located between the through hole and the display area, wherein the display panel comprises a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines all extend along a first direction in the display area and are alternately arranged along a second direction, the first direction is different from the second direction; a first data line whose projection from the first direction to the second direction overlaps with a projection of the through hole and / or the winding area from the first direction to the second direction, comprises a first data line segment The first data line section and the second data line section are respectively located on both sides of the winding area along the first direction and are connected by a first connecting line, and the first connecting line is located in the winding area; and a second data line whose projection along the first direction to the second direction overlaps with the projection of the through hole and / or the winding area along the first direction to the second direction, comprises a third data line section and a fourth data line section, the third data line section and the fourth data line section are respectively located on both sides of the winding area along the first direction and are connected by a second connecting line, and the second connecting line is located in the display area.

[0004] Optionally, a minimum distance between two adjacent first connection lines is in a range from 2.0 μm to 2.5 μm.

[0005] Optionally, a minimum distance between two adjacent second connection lines is in a range from 2.0 μm to 2.5 μm.

[0006] Optionally, the first data line is configured to provide a data signal to a green sub-pixel, and the second data line is configured to provide a data signal to a red sub-pixel and / or a blue sub-pixel.

[0007] Optionally, a first multiplexer switch is provided in the first data line, and the first multiplexer switch is configured to control the conduction and cutoff of the data signal on the first data line; a second multiplexer switch is provided in the second data line, and the second multiplexer switch is configured to control the conduction and cutoff of the data signal on the second data line; and the first data line and a second data line adjacent to it are connected to the same signal lead.

[0008] Optionally, the second connecting line includes a first connecting line section, a second connecting line section and a third connecting line section which are connected to each other, and the third connecting line section is connected to the first connecting line section, and the third connecting line section is connected to the fourth connecting line section, wherein the first connecting line section and the third connecting line section are parallel to each other, and / or the first connecting line section and the third connecting line section are parallel to each other and have the same length.

[0009] Optionally, the first section of the connecting line and the third section of the connecting line extend along the second direction; and the second section of the connecting line extends along the first direction.

[0010] Optionally, the display panel includes: a base substrate; a gate insulating layer located on the base substrate; a first gate metal layer located on a side of the gate insulating layer away from the gate insulating layer; a second insulating layer located on a side of the first gate metal layer away from the gate insulating layer; a second gate metal layer located on a side of the second insulating layer away from the gate insulating layer; an interlayer dielectric layer located on a side of the second gate metal layer away from the gate insulating layer; a first signal line layer located on a side of the interlayer dielectric layer away from the gate insulating layer; a passivation layer and / or a first planarization layer located on a side of the first signal line layer away from the gate insulating layer; and a second signal layer located on a side of the passivation layer and / or the first planarization layer away from the gate insulating layer.

[0011] Optionally, the third division of the data line is located in the second signal line layer and is connected to the second connecting line through a first via, at least a portion of the second connecting line connected to the third division of the data line is located in the first signal line layer, and the first via extends through the passivation layer and / or the first planarization layer; and the second connecting line is connected to the fourth division of the data line through a second via, the third division of the data line is located in the second signal line layer, at least a portion of the second connecting line connected to the fourth division of the data line is located in the first signal line layer, and the second via extends through the passivation layer and / or the first planarization layer.

[0012] Optionally, the second connecting line includes a first connecting line section, a second connecting line section and a third connecting line section which are connected to each other, and the first connecting line section and the third connecting line section are both located in the first signal line layer, the third connecting line section is connected to the first connecting line section through the first via hole, and the third connecting line section is connected to the fourth connecting line section through the second via hole.

[0013] Optionally, the second connecting line includes a first connecting line section, a second connecting line section and a third connecting line section which are connected to each other, the first connecting line section and the third connecting line section are located on the same layer, and the second connecting line section is located on a layer different from the first connecting line section and the third connecting line section, wherein the first connecting line section is connected to the second connecting line section through a third via hole; and the second connecting line section is connected to the third connecting line section through a fourth via hole.

[0014] Optionally, the first connection line section and the third connection line section are both located in the first signal line layer, the second connection line section is located in the second signal line layer, and the fourth via hole and the third via hole both extend through the passivation layer and / or the first planarization layer.

[0015] Optionally, the first data line section and the second data line section are both located in the second signal line layer, the first connecting line is located in the second signal line layer, and the first data line section, the second data line section and the first connecting line form an integral structure.

[0016] Optionally, the first division of the data line and the second division of the data line are both located in the second signal line layer, the first connecting line is located in the first signal line layer, and the first division of the data line is connected to the first connecting line through a fifth via, the first connecting line is connected to the second division of the data line through a sixth via, and the fifth via and the sixth via both extend through the passivation layer and / or the first planarization layer.

[0017] Optionally, the first division of the data line and the second division of the data line are both located in the second signal line layer, the first connecting line is located in the second gate metal layer, and the first division of the data line is connected to the first connecting line through a seventh via, the first connecting line is connected to the second division of the data line through an eighth via, and the seventh via and the eighth via both extend through the passivation layer and / or the first planarization layer, and the interlayer dielectric layer.

[0018] Optionally, the first division of the data line and the second division of the data line are both located in the second signal line layer, the first connecting line is located in the first gate metal layer, and the first division of the data line is connected to the first connecting line through a ninth via, and the first connecting line is connected to the second division of the data line through a tenth via, and the ninth via and the tenth via both extend through the passivation layer and / or the first planarization layer, the interlayer dielectric layer, and the second insulating layer.

[0019] On the other hand, the present disclosure provides a display device, which includes the array substrate described herein, one or more integrated circuits connected to the array substrate, and a power supply component that provides power to the display panel and the integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0021] Figure 1 is a plan view of a display panel according to some embodiments of the present disclosure.

[0022] Figure 2 The diagram shows the connection between data lines and signal leads in a display panel according to some embodiments of the present disclosure.

[0023] Figure 3 is a schematic diagram showing connection lines in a wiring area of ​​a display panel according to some embodiments of the present disclosure.

[0024] Figure 4 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure.

[0025] Figure 5 is a plan view showing a structure in a winding area in a display panel according to some embodiments of the present disclosure.

[0026] Figure 6 It is shown Figure 5 A magnified view of the structure in the Z1 region.

[0027] Figure 7 It is shown Figure 5 A magnified view of the structure in the Z2 region.

[0028] Figure 8 It shows the comparison between the normal screen and the reloaded screen.

[0029] Fig. 9 It shows the defect of the display panel when displaying a heavy-loaded picture according to some embodiments of the present disclosure.

[0030] Fig.10 Show drive Figure 2 The switch driving signal of the multiplexer switch shown in FIG. 1 and the gate driving signal driving the gate line in the display panel.

[0031] Fig.11 is a plan view of a display panel according to some embodiments of the present disclosure.

[0032] Fig.12 The diagram shows the connection between data lines and signal leads in a display panel according to some embodiments of the present disclosure.

[0033] Fig.13 is a schematic diagram showing connection lines in a wiring area of ​​a display panel according to some embodiments of the present disclosure.

[0034] Fig.14 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure.

[0035] Fig.15 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure.

[0036] Fig.16 It is shown Fig.15 A magnified view of the structure in the Z3 region.

[0037] Fig.17 It is shown Fig.15 A magnified view of the structure in the Z4 region.

[0038] Fig.18 is a plan view showing a structure of a second data line in a display panel according to some embodiments of the present disclosure.

[0039] Fig.19 is a plan view showing a structure of a second connection line in a display panel according to some embodiments of the present disclosure.

[0040] Fig. 20 It is shown Fig.19 A magnified view of the structure in the Z5 region.

[0041] Fig.21 It is shown Fig.19 A magnified view of the structure in the Z6 region.

[0042] Fig. 22 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure.

[0043] Fig.23 It is shown Fig. 22 A magnified view of the structure in the Z7 region.

[0044] Fig.24 It is shown Fig. 22 A magnified view of the structure in the Z8 region.

[0045] Fig.25 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure.

[0046] Fig.26 It is shown Fig.25 A magnified view of the structure in the Z9 region.

[0047] Fig. 27 It is shown Fig.25 A magnified view of the structure in the Z10 region.

[0048] Fig.28 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure.

[0049] Fig.29 It is shown Fig.28 A magnified view of the structure in the Z11 region.

[0050] Fig.30 It is shown Fig.28 A magnified view of the structure in the Z12 region. DETAILED DESCRIPTION

[0051] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0052] Figure 1 is a plan view of a display panel according to some embodiments of the present disclosure. Figure 1 The display panel includes: a through hole TH configured to accommodate external electronic components such as a camera; a display area AA surrounding the through hole TH and configured to display an image; and a winding area RA located between the through hole TH and the display area AA.

[0053] In some embodiments, the display panel includes a plurality of first data lines D1 and a plurality of second data lines D2. Figure 1 As shown, a plurality of first data lines D1 and a plurality of second data lines D2 extend along a first direction DR1 in the display area and are alternately arranged along a second direction DR2. In some embodiments, the first direction DR1 is different from the second direction DR2, for example, the first direction DR1 is perpendicular to the second direction DR2.

[0054] like Figure 1As shown, the first data line D1, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a first data line sub-portion D1-1 and a second data line sub-portion D1-2. In some embodiments, the first data line sub-portion D1-1 and the second data line sub-portion D1-2 are respectively located on both sides of the winding area TH along the first direction DR1 and are connected by a first connection line CL1, wherein the first connection line CL1 is located in the winding area RA.

[0055] like Figure 1 As shown, the second data line D2, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a third data line section D2-1 and a fourth data line section D2-2. In some embodiments, the third data line section D2-1 and the fourth data line section D2-2 are respectively located on both sides of the winding area RA along the first direction DR1, and are connected by a second connection line CL2, wherein the second connection line CL2 is located in the winding area RA.

[0056] like Figure 1 As shown, in some embodiments, the first data line D1 and one second data line D2 adjacent thereto are connected to the same signal lead line SL, and the signal lead line SL is connected to the data driving circuit DDC through a fan-out line FL located in the fan-out region.

[0057] Figure 2 FIG. 4 shows the connection between the data line and the signal lead in the display panel according to some embodiments of the present disclosure. Figure 2 , among the first data line D1 and the second data line D2 connected to the same signal lead line SL, the first data line D1 is configured to provide a data signal to the green sub-pixel g; the second data line D2 is configured to provide a data signal to the red sub-pixel r and / or the blue sub-pixel b. Figure 2 As shown, a first multiplexer switch MUX1 is provided in the first data line D1, and the first multiplexer switch MUX1 is configured to control the conduction and cutoff of the data signal on the first data line D1. Figure 2 As shown, a second multiplexer switch MUX2 is provided in the second data line D2, and the second multiplexer switch MUX2 is configured to control the on and off of the data signal on the second data line D2.

[0058] By connecting the first data line D1 and a second data line D2 adjacent thereto to the same signal lead SL, the number of signal leads SL can be halved, which means that the size of the data driving circuit DDC will be reduced, thereby reducing the cost of the data driving circuit DDC and further reducing the production cost of the display panel.

[0059] Figure 3 Schematic diagram showing connection lines in a winding area of ​​a display panel according to some embodiments of the present disclosure. Figure 3 As shown, in some embodiments, the first data line D1 whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2 includes a first data line section D1-1 and a second data line section D1-2. In some embodiments, the first data line section D1-1 and the second data line section D1-2 are respectively located on both sides of the winding area RA along the first direction DR1 and are connected by a first connection line CL1, wherein the first connection line CL is located in the winding area RA. Figure 3 As shown, in some embodiments, the second data line D2, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a third data line section D2-1 and a fourth data line section D2-2. In some embodiments, the third data line section D2-1 and the fourth data line section D2-2 are respectively located on both sides of the winding area RA along the first direction DR1, and are connected by a second connection line CL2, wherein the second connection line CL2 is located in the winding area RA.

[0060] Figure 4 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure. Figure 4In some embodiments, the display panel includes in the display area: a substrate BS (for example, a flexible substrate); an active layer ACT of each thin film transistor in a plurality of thin film transistors TFT, which is located on the substrate BS; a gate insulating layer GI, which is located on a side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of the first gate metal layer Gate1), which are located on a side of the gate insulating layer GI away from the substrate BS; a second insulating layer IN, which is located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a part of the second gate metal layer Gate2), which is located on a side of the second insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD, which is located on the second capacitor electrode Ce1; 2 is located on the side away from the gate insulating layer GI; the source S and the drain D (part of the first signal line layer SD1), which are located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; the passivation layer PVX, which is located on the side of the source S and the drain D away from the interlayer dielectric layer ILD; the first planarization layer PLN1, which is located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; the relay electrode RE (part of the second signal layer SD2), which is located on the side of the first planarization layer PLN1 away from the passivation layer PVX; the second planarization layer PLN2, which is located on the side of the relay electrode RE away from the first planarization layer PLN1; the pixel defining layer PDL, which defines the sub-pixel opening and is located on the side of the second planarization layer PLN2 away from the substrate BS; and the light emitting element LE, which is located in the sub-pixel opening. The light emitting element LE includes: an anode AD, which is located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL, which is located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD, which is located on the side of the light emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates the light emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1, which is located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP, which is located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2, which is located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.

[0061] Reference Figure 4, the display panel includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SD1 and a second signal line layer SD2. The display panel also includes: a gate insulating layer GI, which is located between the active layer ACT and the second gate metal layer Gate2; a second insulating layer IN, which is located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD, which is located between the second gate metal layer Gate2 and the first signal line layer SLL1; and a passivation layer PVX and a first planarization layer PLN1, which are located between the first signal line layer SD1 and the second signal line layer SD2. Optionally, the display panel does not include the passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0062] In some embodiments, the first data line portion D1 - 1 , the second data line portion D1 - 2 , the third data line portion D2 - 1 , and the fourth data line portion D2 - 2 are all located in the second signal line layer SD2 .

[0063] Figure 5 is a plan view showing a structure in a winding area in a display panel according to some embodiments of the present disclosure. Figure 6 It is shown Figure 5 A magnified view of the structure in the Z1 region. Figure 7 It is shown Figure 5 A magnified view of the structure in the Z2 region.

[0064] like Figure 5 and Figure 6 As shown, the edge EG of the through hole TH constitutes a boundary line between the through hole TH and the wiring area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is a cutting line when cutting the display panel.

[0065] also, Figure 5 and Figure 6 A virtual boundary line DBL between the wiring area RA and the display area AA is also shown in FIG. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the wiring area RA and the display area AA, and does not actually exist.

[0066] like Figure 5 and Figure 6 As shown, the first data line section D1-1 is connected to the first connection line CL1, and the third data line section D2-1 is connected to the second connection line CL2. In the direction from the virtual boundary line DBL to the edge EG, a plurality of first connection lines CL1 and a plurality of second connection lines CL2 are alternately arranged.

[0067] In some embodiments, Figures 5 to 7As shown, the first connection line CL1 is located in the second signal line layer SD2, and the second connection line CL2 is located in the first signal line layer SD1. The first data line section D1-1 and the first connection line CL1 are an integral structure located in the same layer; the third data line section D2-1 extends through Figure 4 The via holes of the first planarization layer PLN1 and the passivation layer PVX shown in FIG. 5 are connected to the second connection line CL2 .

[0068] In an alternative embodiment, the first connection line CL1 may be located in the first signal line layer SD1, and the second connection line CL2 may be located in the first signal line layer. The third data line section D2-1 and the second connection line CL2 are an integral structure located in the same layer; the first data line section D1-1 is connected to the first connection line CL1 through a via extending through the first planarization layer PLN1 and the passivation layer PVX.

[0069] like Figure 5 and Figure 6 As shown, a plurality of isolation pillars SP are disposed on one side of the first connection line CL1 and the second connection line CL2 close to the edge EG. Figure 6 As shown, the plurality of isolation columns SP include seven isolation columns SP disposed near the edge EG and four isolation columns SP disposed near the first connection line CL1 and the second connection line CL2, and a retaining wall area WA is provided between the seven isolation columns SP and the four isolation columns SP. One or more retaining walls (not shown in the figure) are provided in the retaining wall area WA. Figure 4 The encapsulation layer EN shown in FIG. is in contact with the encapsulation layer EN shown in FIG. Figure 4 The package layer EN contacts are shown in Figure 1 and are configured to block Figure 4 The organic encapsulation sublayer IJP shown in FIG. 1 overflows during the formation process.

[0070] like Figure 5 and Figure 7 As shown, in the direction from the virtual boundary line DBL to the edge EG, a plurality of first connection lines CL1 and a plurality of second connection lines CL2 are alternately arranged, and the orthographic projections of the adjacent first connection lines CL1 and the second connection lines CL2 on the substrate BS partially overlap each other. In addition, the routing lengths of the first connection lines CL1 and the second connection lines CL2 in the winding area RA are relatively long. Therefore, there is a large coupling capacitance between the adjacent first connection lines CL1 and the second connection lines CL2.

[0071] It should be noted that there is no connection line of the gate line in the winding area RA. Because the gate line in the display panel is driven on both sides, even if the gate line is disconnected at the position of the through hole TH, it can be driven by the gate driving circuits on both sides of the display panel respectively, so there is no need to set the connection line of the gate line in the winding area RA, thereby reducing the difficulty of wiring.

[0072] Figure 8 It shows the comparison between the normal screen and the reloaded screen. Figure 8 As shown in Figure 1, in a normal picture, each sub-pixel is lit according to the corresponding grayscale. However, in a heavy-loaded picture, Figure 8 As shown, the upper two rows of sub-pixels are not lit to display black lines, and the lower two rows of sub-pixels are lit to display white lines; in the entire display panel, the two rows of sub-pixels that are not lit and the two rows of sub-pixels that are lit are arranged alternately.

[0073] The inventor of the present disclosure has found that when the display panel displays a normal picture, no display defect occurs. However, when the display panel displays a heavy-load picture, a vertical white bar appears.

[0074] Fig. 9 The figure shows the defect of the display panel in some embodiments of the present disclosure when displaying a heavy-loaded screen. Fig. 9 In the figure, the left part shows a schematic diagram of a defect, and the right part shows the actual defect. Fig. 9 As shown, when the display panel displays a reloaded image, a vertical white bar appears at a position where it overlaps with the through hole in the vertical direction. Fig. 9 The vertical white bar is marked by a dotted box in the right part. Fig. 9 There are also transverse bright lines in the right part, which are other defects and are not related to the defects discussed in this disclosure, so they will not be described in detail.

[0075] The following will analyze in detail Fig. 9 The reason why vertical white stripes appear in the middle.

[0076] Fig.10 Show drive Figure 2 The switch drive signal of the multiplexer switch shown in FIG. 1 and the gate drive signal driving the gate line in the display panel. Figure 2 and Fig.10 As shown, Figure 2The first multiplexer switch MUX1 and the second multiplexer switch MUX2 in the embodiment are both low level effective. That is, when a low level is applied to the gate of the first multiplexer switch MUX1, the first multiplexer switch MUX1 is turned on; when a high level is applied to the gate of the first multiplexer switch MUX1, the first multiplexer switch MUX1 is turned off. When a low level is applied to the gate of the second multiplexer switch MUX2, the second multiplexer switch MUX2 is turned on; when a high level is applied to the gate of the second multiplexer switch MUX2, the second multiplexer switch MUX2 is turned off.

[0077] In addition, if Fig.10 As shown, the thin film transistor TFT whose gate is connected to the gate line in each sub-pixel is also low level effective. That is, when a low level signal is loaded on the gate line, a low level is applied to the gate G of the thin film transistor TFT, and the thin film transistor TFT is turned on; when a high level signal is loaded on the gate line, a high level is applied to the gate G of the thin film transistor TFT, and the thin film transistor TFT is turned off.

[0078] Combination Figure 2 , Figure 4 , Fig. 9 and Fig.10 As shown, the driving process includes a first phase t1 and a second phase t2.

[0079] In the first phase t1, a low level is applied to the gate of the first multiplexer switch MUX1, and a high level is applied to the gate of the second multiplexer switch MUX2. At this time, the first multiplexer switch MUX1 is turned on, and the second multiplexer switch MUX2 is turned off. The signal on the data lead SL is written to the first data line D1 through the first multiplexer switch MUX2. At this time, the loading signal Gate_P on the gate line is a high level, the gate G of the thin film transistor TFT is applied with a high level, the thin film transistor TFT is turned off, and the first data line D1 is in a floating state.

[0080] In the second phase t2, a high level is applied to the gate of the first multiplexer switch MUX1, and a low level is applied to the gate of the second multiplexer switch MUX2. At this time, the first multiplexer switch MUX1 is turned off, and the second multiplexer switch MUX2 is turned on. The signal on the data lead SL is written into the second data line D2 through the second multiplexer switch MUX2. Subsequently, the loading signal Gate_P on the gate line changes from a high level to a low level, a low level is applied to the gate G of the thin film transistor TFT, the thin film transistor TFT is turned on, and the signals on the first data line D1 and the second data line D2 are simultaneously written into the corresponding sub-pixels through the corresponding thin film transistors TFT.

[0081] When the display panel shows the reload screen, Figure 8As shown, the upper 2 rows of sub-pixels are not lit to display black lines, and the lower 2 rows of sub-pixels are lit to display white lines; in the entire display panel, the 2 rows of sub-pixels that are not lit are arranged alternately with the 2 rows of sub-pixels that are lit. The data signals corresponding to the upper 2 rows of sub-pixels are high level, and the data signals corresponding to the lower 2 rows of sub-pixels are low level. When writing data signals to the third row of sub-pixels, the first data line D1 is in a floating state in the first stage t1, and the data signal of the second data line D2 in the second stage t2 jumps from the high level corresponding to the second row of sub-pixels to a low level. Since there is a large coupling capacitance between the first connecting line CL1 and the second connecting line CL2 adjacent to each other, the level jump on the second data line D2 will cause the level of the first data line D1 to be pulled down, thereby generating Fig. 9 The vertical white stripes shown are defective.

[0082] Therefore, the present disclosure provides, among other things, a display panel and a display device that substantially eliminate one or more problems caused by limitations and disadvantages of the prior art. On the one hand, the present disclosure provides a display panel. In some embodiments, the display panel includes: a through hole; a display area surrounding the through hole and configured to display an image; and a winding area located between the through hole and the display area. In some embodiments, the display panel includes a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines all extend along a first direction in the display area and are alternately arranged along a second direction, the first direction is different from the second direction; the first data line whose projection from the first direction to the second direction overlaps with the projection of the through hole and / or the winding area from the first direction to the second direction, includes a first data line section and a second data line section, the first data line section and the second data line section are respectively located on both sides of the winding area along the first direction and are connected by a first connecting line, the first connecting line is located in the winding area; and the second data line whose projection from the first direction to the second direction overlaps with the projection of the through hole and / or the winding area from the first direction to the second direction, includes a third data line section and a fourth data line section, the third data line section and the fourth data line section are respectively located on both sides of the winding area along the first direction and are connected by a second connecting line, the second connecting line is located in the display area.

[0083] Fig.11 is a plan view of a display panel according to some embodiments of the present disclosure. Fig.11 The display panel includes: a through hole TH configured to accommodate external electronic components such as a camera; a display area AA surrounding the through hole TH and configured to display an image; and a winding area RA located between the through hole TH and the display area AA.

[0084] In some embodiments, the display panel includes a plurality of first data lines D1 and a plurality of second data lines D2. Fig.11 As shown, a plurality of first data lines D1 and a plurality of second data lines D2 extend along a first direction DR1 in the display area and are alternately arranged along a second direction DR2. In some embodiments, the first direction DR1 is different from the second direction DR2, for example, the first direction DR1 is perpendicular to the second direction DR2.

[0085] like Fig.11 As shown, the first data line D1, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a first data line section D1-1 and a second data line section D1-2. In some embodiments, the first data line section D1-1 and the second data line section D1-2 are respectively located on both sides of the winding area RA along the first direction DR1 and are connected by a first connection line CL1, wherein the first connection line CL is located in the winding area RA.

[0086] like Fig.11 As shown, the second data line D2, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a third data line section D2-1 and a fourth data line section D2-2. In some embodiments, the third data line section D2-1 and the fourth data line section D2-2 are respectively located on both sides of the winding area RA along the first direction DR1, and are connected by a second connection line CL2, wherein the second connection line CL2 is located in the display area AA.

[0087] like Fig.11 As shown, in some embodiments, the first data line D1 and one second data line D2 adjacent thereto are connected to the same signal lead line SL, and the signal lead line SL is connected to the data driving circuit DDC through a fan-out line FL located in the fan-out region.

[0088] Fig.12 FIG. 4 shows the connection between the data line and the signal lead in the display panel according to some embodiments of the present disclosure. Fig.12 , among the first data line D1 and the second data line D2 connected to the same signal lead line SL, the first data line D1 is configured to provide a data signal to the green sub-pixel g; the second data line D2 is configured to provide a data signal to the red sub-pixel r and / or the blue sub-pixel b. Fig.12 As shown, a first multiplexer switch MUX1 is provided in the first data line D1, and the first multiplexer switch MUX1 is configured to control the conduction and cutoff of the data signal on the first data line D1. Figure 2As shown, a second multiplexer switch MUX2 is provided in the second data line D2, and the second multiplexer switch MUX2 is configured to control the on and off of the data signal on the second data line D2.

[0089] By connecting the first data line D1 and a second data line D2 adjacent thereto to the same signal lead SL, the number of signal leads SL can be halved, which means that the size of the data driving circuit DDC will be reduced, thereby reducing the cost of the data driving circuit DDC and further reducing the production cost of the display panel.

[0090] Fig.13 Schematic diagram showing connection lines in a winding area of ​​a display panel according to some embodiments of the present disclosure. Fig.13 As shown, in some embodiments, the first data line D1 whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2 includes a first data line section D1-1 and a second data line section D1-2. In some embodiments, the first data line section D1-1 and the second data line section D1-2 are respectively located on both sides of the winding area RA along the first direction DR1 and are connected by a first connection line CL1, wherein the first connection line CL is located in the winding area RA. Fig.13 As shown, in some embodiments, the second data line D2, whose projection along the first direction DR1 to the second direction DR2 overlaps with the projection of the through hole TH and / or the winding area RA along the first direction DR1 to the second direction DR2, includes a third data line section D2-1 and a fourth data line section D2-2. In some embodiments, the third data line section D2-1 and the fourth data line section D2-2 are respectively located on both sides of the winding area RA along the first direction DR1, and are connected by a second connection line CL2, wherein the second connection line CL2 is located in the display area AA.

[0091] Fig.13 The edge EG of the through hole TH and the virtual boundary line DBL between the winding area RA and the display area AA are also shown. The edge EG of the through hole TH constitutes the boundary line between the through hole TH and the winding area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is the cutting line when the display panel is cut. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the winding area RA and the display area AA, and does not actually exist.

[0092] Fig.14 is a cross-sectional view showing a detailed structure in a display area of ​​a display panel according to some embodiments of the present disclosure. Fig.14In some embodiments, the display panel includes in the display area: a substrate BS (for example, a flexible substrate); an active layer ACT of each thin film transistor in a plurality of thin film transistors TFT, which is located on the substrate BS; a gate insulating layer GI, which is located on a side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both are part of the first gate metal layer Gate1), which are located on a side of the gate insulating layer GI away from the substrate BS; a second insulating layer IN, which is located on a side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a part of the second gate metal layer Gate2), which is located on a side of the second insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD, which is located on the second capacitor electrode Ce1; 2 is located on the side away from the gate insulating layer GI; the source S and the drain D (part of the first signal line layer SD1), which are located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; the passivation layer PVX, which is located on the side of the source S and the drain D away from the interlayer dielectric layer ILD; the first planarization layer PLN1, which is located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; the relay electrode RE (part of the second signal layer SD2), which is located on the side of the first planarization layer PLN1 away from the passivation layer PVX; the second planarization layer PLN2, which is located on the side of the relay electrode RE away from the first planarization layer PLN1; the pixel defining layer PDL, which defines the sub-pixel opening and is located on the side of the second planarization layer PLN2 away from the substrate BS; and the light emitting element LE, which is located in the sub-pixel opening. The light emitting element LE includes: an anode AD, which is located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light emitting layer EL, which is located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD, which is located on the side of the light emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN in the display area, which encapsulates the light emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes: a first inorganic encapsulation sublayer CVD1, which is located on the side of the cathode layer CD away from the substrate BS; an organic encapsulation sublayer IJP, which is located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS; and a second inorganic encapsulation sublayer CVD2, which is located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1.

[0093] Reference Fig.14, the display panel includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SD1 and a second signal line layer SD2. The display panel also includes: a gate insulating layer GI, which is located between the active layer ACT and the second gate metal layer Gate2; a second insulating layer IN, which is located between the first gate metal layer Gate1 and the second gate metal layer Gate2; an interlayer dielectric layer ILD, which is located between the second gate metal layer Gate2 and the first signal line layer SLL1; and a passivation layer PVX and a first planarization layer PLN1, which are located between the first signal line layer SD1 and the second signal line layer SD2. Optionally, the display panel does not include the passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0094] In some embodiments, the first data line portion D1 - 1 , the second data line portion D1 - 2 , the third data line portion D2 - 1 , and the fourth data line portion D2 - 2 are all located in the second signal line layer SD2 .

[0095] Fig.15 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure. Fig.16 It is shown Fig.15 A magnified view of the structure in the Z3 region. Fig.17 It is shown Fig.15 A magnified view of the structure in the Z4 region. For clarity, Fig.15 The first data line section D1-1 and the third data line section D2-1 are omitted; Fig.16 A first data line subsection D1 - 1 and a third data line subsection D2 - 1 are shown in FIG.

[0096] like Fig.15 and Fig.16 As shown, the edge EG of the through hole TH constitutes a boundary line between the through hole TH and the wiring area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is a cutting line when cutting the display panel.

[0097] also, Fig.15 and Fig.16 A virtual boundary line DBL between the wiring area RA and the display area AA is also shown in FIG. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the wiring area RA and the display area AA, and does not actually exist.

[0098] like Fig.15 and Fig.16 As shown, the first data line segment D1-1 is connected to the first connection line CL1. Figures 15 to 17As shown, the first connection line CL1 is located in the second signal line layer SD2, and the first data line portion D1-1 and the first connection line CL1 are located in the same layer and are part of the overall structure.

[0099] In some embodiments, the first connection line CL1 is connected to the second data line subdivision D1-2. Similarly, the first connection line CL1 and the second data line subdivision D1-2 are located in the same layer and are part of the overall structure. In some embodiments, the first data line subdivision D1-1, the first connection line CL1 and the second data line subdivision D1-2 are formed as an overall structure.

[0100] like Fig.15 and Fig.16 As shown in FIG. 1 , a plurality of isolation pillars SP are disposed on one side of the first connection line CL1 close to the edge EG. Fig.16 As shown, the plurality of isolation columns SP include seven isolation columns SP disposed near the edge EG and four isolation columns SP disposed near the first connection line CL1, and a retaining wall area WA is provided between the seven isolation columns SP and the four isolation columns SP. One or more retaining walls (not shown in the figure) are provided in the retaining wall area WA. Fig.14 The encapsulation layer EN shown in FIG. is in contact with the encapsulation layer EN shown in FIG. Fig.14 The package layer EN contacts are shown in Figure 1 and are configured to block Fig.14 The organic encapsulation sublayer IJP shown in FIG. 1 overflows during the formation process.

[0101] It should be noted that there is no connection line of the gate line in the winding area RA. Because the gate line in the display panel is driven on both sides, even if the gate line is disconnected at the position of the through hole TH, it can be driven by the gate driving circuits on both sides of the display panel respectively, so there is no need to set the connection line of the gate line in the winding area RA, thereby reducing the difficulty of wiring.

[0102] like Fig.17 As shown, the minimum interval d1 between two adjacent first connection lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum interval d1 between two adjacent first connection lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0103] Fig.18 is a plan view showing a structure of a second data line in a display panel according to some embodiments of the present disclosure. Fig.19 is a plan view showing a structure of a second connection line in a display panel according to some embodiments of the present disclosure. Fig. 20 It is shown Fig.19 A magnified view of the structure in the Z5 region. Fig.21 It is shown Fig.19 A magnified view of the structure in the Z6 region.

[0104] like Fig.18 As shown, the third data line section D2-1 is connected to the second connection line CL2 through the first via hole, and the second connection line CL2 is connected to the fourth data line section D2-2 through the second via hole. The second connection line CL2 includes the first connection line section CL2-1, the second connection line section CL2-2, and the third connection line section CL2-3 connected to each other. The third data line section D2-1 is connected to the first connection line section CL2-1 through the first via hole v1, and the third connection line section CL2-3 is connected to the fourth data line section D2-2 through the second via hole v2.

[0105] In some embodiments, the third data line section D2-1 and the fourth data line section D2-2 are both located in the second signal line layer SD2; the first connection line section CL2-1 and the third connection line section CL2-3 are both located in the second signal line layer SD2, and the first via hole v1 and the second via hole v2 extend through Fig.14 The first planarization layer PLN1 and the passivation layer PVX shown in .

[0106] like Fig.18 As shown, the minimum interval d2 between two adjacent second connection lines CL2 is in the range of 2.0 μm to 2.5 μm. For example, the minimum interval d2 between two adjacent first connection lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0107] In some embodiments, the first connection line section CL2-1 extends from the third data line section D2-1 to the second connection line section CL2-2 along the second direction DR2; the third connection line section CL2-3 extends from the fourth data line section D2-2 to the second connection line section CL2-2 along the second direction DR2. That is, the first connection line section CL2-1 and the third connection line section CL2-3 are parallel to each other.

[0108] In some embodiments, the second connection line portion CL2-2 extends from the first connection line portion CL2-1 to the second connection line portion CL2-2 along the first direction DR1. In some embodiments, the first connection line portion CL2-1 and the third connection line portion CL2-3 have the same length.

[0109] In some embodiments, Fig.18 and Fig.19 As shown, the first connecting line section CL2-1, the second connecting line section CL2-2 and the third connecting line section CL2-3 are axially symmetrical about the perpendicular midline OO' of the second connecting line section CL2-2.

[0110] like Fig.18 and Fig.19 As shown, the first connection line section CL2-1 is connected to the second connection line section CL2-2 through the third via v3, and the second connection line section CL2-2 is connected to the third connection line section CL2-3 through the fourth via v4.

[0111] like Fig. 20 As shown, the third branch CL2-3 of the connecting line is located in the second signal line layer SD2, and the second branch CL2-2 of the connecting line is located in the first signal line layer SD1. The second branch CL2-2 of the connecting line is connected to the third branch CL2-3 of the connecting line through the fourth via v4, and the fourth via v4 extends through Fig.14 The first planarization layer PLN1 and the passivation layer PVX shown in .

[0112] like Fig.21 As shown, the first connection line section CL2-1 is located in the second signal line layer SD2, and the second connection line section CL2-2 is located in the first signal line layer SD1. The first connection line section CL2-1 is connected to the second connection line section CL2-2 through the third via v3, and the third via v3 extends through Fig.14 The first planarization layer PLN1 and the passivation layer PVX shown in .

[0113] In the display panel according to the present disclosure, only the first connection line CL1 is arranged in the winding area RA, and the second connection line CL2 is arranged in the display area AA. In this way, the coupling capacitance between the first connection line CL1 and the second connection line CL2 is avoided, so when the display panel displays a heavy-loaded picture, no Fig. 9 Vertical white bar shown.

[0114] In addition, in the display panel according to the present disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the brightness of the picture. Fig.10 The first stage t1 shown is in a floating state, while the second data line D2 is not in a floating state, so the anti-interference ability of the first data line D1 is weaker than that of the second data line D2. By setting the first connection line CL1 connected to the first data line D1 in the winding area RA, the interference of other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a strong anti-interference ability, setting the second connection line CL2 connected to the second data line D2 in the display area AA2 will not affect the normal display.

[0115] Fig. 22 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure. Fig.23 It is shown Fig. 22 A magnified view of the structure in the Z7 region. Fig.24 It is shown Fig. 22 A magnified view of the structure in the Z8 region. For clarity, Fig. 22 The first data line section D1-1 and the third data line section D2-1 are omitted; Fig.23 A first data line subsection D1 - 1 and a third data line subsection D2 - 1 are shown in FIG.

[0116] like Fig. 22 and Fig.23 As shown, the edge EG of the through hole TH constitutes a boundary line between the through hole TH and the wiring area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is a cutting line when cutting the display panel.

[0117] also, Fig. 22 and Fig.23 A virtual boundary line DBL between the wiring area RA and the display area AA is also shown in FIG. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the wiring area RA and the display area AA, and does not actually exist.

[0118] like Fig. 22 and Fig.23 As shown, the first data line segment D1-1 is connected to the first connection line CL1. Figure 22 to Figure 24 As shown, the first connection line CL1 is located in the first signal line layer SD1, the first data line portion D1-1 is connected to the first connection line CL1 through the fifth via hole v5, and the fifth via hole v5 extends through Fig.14 The first planarization layer PLN1 and the passivation layer PVX shown in .

[0119] Alternatively, the display panel may not include the passivation layer PVX in the display area, in which case the fifth via v5 only extends through the first planarization layer PLN1. Alternatively, without including the first planarization layer PLN1, the fifth via v5 only extends through the passivation layer PVX. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX.

[0120] Similarly, if Figure 22 to Figure 24 As shown, the first connection line CL1 is connected to the data line second sub-portion D1 - 2 through a sixth via hole v6 , and the sixth via hole v6 extends through the first planarization layer PLN1 and / or the passivation layer PVX.

[0121] like Fig. 22 and Fig.23 As shown in FIG. 1 , a plurality of isolation pillars SP are disposed on one side of the first connection line CL1 close to the edge EG. Fig.23 As shown, the plurality of isolation columns SP include seven isolation columns SP disposed near the edge EG and four isolation columns SP disposed near the first connection line CL1, and a retaining wall area WA is provided between the seven isolation columns SP and the four isolation columns SP. One or more retaining walls (not shown in the figure) are provided in the retaining wall area WA. Fig.14 The encapsulation layer EN shown in FIG. is in contact with the encapsulation layer EN shown in FIG. Fig.14 The package layer EN contacts are shown in Figure 1 and are configured to block Fig.14 The organic encapsulation sublayer IJP shown in FIG. 1 overflows during the formation process.

[0122] It should be noted that there is no connection line of the gate line in the winding area RA. Because the gate line in the display panel is driven on both sides, even if the gate line is disconnected at the position of the through hole TH, it can be driven by the gate driving circuits on both sides of the display panel respectively, so there is no need to set the connection line of the gate line in the winding area RA, thereby reducing the difficulty of wiring.

[0123] like Fig.24 As shown, the minimum interval d1 between two adjacent first connection lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum interval d1 between two adjacent first connection lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0124] In the display panel according to the present disclosure, only the first connection line CL1 is arranged in the winding area RA, and the second connection line CL2 is arranged in the display area AA. In this way, the coupling capacitance between the first connection line CL1 and the second connection line CL2 is avoided, so when the display panel displays a heavy-loaded picture, no Fig. 9 Vertical white bar shown.

[0125] In addition, in the display panel according to the present disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the brightness of the picture. Fig.10 The first stage t1 shown is in a floating state, while the second data line D2 is not in a floating state, so the anti-interference ability of the first data line D1 is weaker than that of the second data line D2. By setting the first connection line CL1 connected to the first data line D1 in the winding area RA, the interference of other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a strong anti-interference ability, setting the second connection line CL2 connected to the second data line D2 in the display area AA2 will not affect the normal display.

[0126] Fig.25 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure. Fig.26 It is shown Fig.25 A magnified view of the structure in the Z9 region. Fig. 27 It is shown Fig.25 A magnified view of the structure in the Z10 region. For clarity, Fig.25 The first data line section D1-1 and the third data line section D2-1 are omitted; Fig.26 A first data line subsection D1 - 1 and a third data line subsection D2 - 1 are shown in FIG.

[0127] like Fig.25 and Fig.26 As shown, the edge EG of the through hole TH constitutes a boundary line between the through hole TH and the wiring area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is a cutting line when cutting the display panel.

[0128] also, Fig.25 and Fig.26 A virtual boundary line DBL between the wiring area RA and the display area AA is also shown in FIG. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the wiring area RA and the display area AA, and does not actually exist.

[0129] like Fig.25 and Fig.26 As shown, the first data line segment D1-1 is connected to the first connection line CL1. Figure 25 to Figure 27 As shown, the first connection line CL1 is located in the second gate metal layer Gate2, the first data line portion D1-1 is connected to the first connection line CL1 through the seventh via hole v7, and the seventh via hole v7 extends through Fig.14 The first planarization layer PLN1 and the passivation layer PVX, and the interlayer dielectric layer ILD are shown in FIG.

[0130] Alternatively, the display panel may not include the passivation layer PVX in the display area, in which case the fifth via v5 extends through the first planarization layer PLN1 and the interlayer dielectric layer ILD. Alternatively, without including the first planarization layer PLN1, the fifth via v5 extends through the passivation layer PVX and the interlayer dielectric layer ILD. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX, and the interlayer dielectric layer ILD.

[0131] Similarly, if Figure 22 to Figure 24As shown, the first connection line CL1 is connected to the data line second sub-portion D1 - 2 through the eighth via hole v8 , and the eighth via hole v8 extends through the first planarization layer PLN1 and / or the passivation layer PVX, and the interlayer dielectric layer ILD.

[0132] like Fig.25 and Fig.26 As shown in FIG. 1 , a plurality of isolation pillars SP are disposed on one side of the first connection line CL1 close to the edge EG. Fig.26 As shown, the plurality of isolation columns SP include seven isolation columns SP disposed near the edge EG and four isolation columns SP disposed near the first connection line CL1, and a retaining wall area WA is provided between the seven isolation columns SP and the four isolation columns SP. One or more retaining walls (not shown in the figure) are provided in the retaining wall area WA. Fig.14 The encapsulation layer EN shown in FIG. is in contact with the encapsulation layer EN shown in FIG. Fig.14 The package layer EN contacts are shown in Figure 1 and are configured to block Fig.14 The organic encapsulation sublayer IJP shown in FIG. 1 overflows during the formation process.

[0133] It should be noted that there is no connection line of the gate line in the winding area RA. Because the gate line in the display panel is driven on both sides, even if the gate line is disconnected at the position of the through hole TH, it can be driven by the gate driving circuits on both sides of the display panel respectively, so there is no need to set the connection line of the gate line in the winding area RA, thereby reducing the difficulty of wiring.

[0134] like Fig. 27 As shown, the minimum interval d1 between two adjacent first connection lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum interval d1 between two adjacent first connection lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0135] In the display panel according to the present disclosure, only the first connection line CL1 is arranged in the winding area RA, and the second connection line CL2 is arranged in the display area AA. In this way, the coupling capacitance between the first connection line CL1 and the second connection line CL2 is avoided, so when the display panel displays a heavy-loaded picture, no Fig. 9 Vertical white bar shown.

[0136] In addition, in the display panel according to the present disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the brightness of the picture. Fig.10The first stage t1 shown is in a floating state, while the second data line D2 is not in a floating state, so the anti-interference ability of the first data line D1 is weaker than that of the second data line D2. By setting the first connection line CL1 connected to the first data line D1 in the winding area RA, the interference of other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a strong anti-interference ability, setting the second connection line CL2 connected to the second data line D2 in the display area AA2 will not affect the normal display.

[0137] Fig.28 is a plan view showing a structure of a first connection line in a display panel according to some embodiments of the present disclosure. Fig.29 It is shown Fig.28 A magnified view of the structure in the Z11 region. Fig.30 It is shown Fig.28 A magnified view of the structure in the Z12 region. For clarity, Fig.28 The first data line section D1-1 and the third data line section D2-1 are omitted; Fig.29 A first data line subsection D1 - 1 and a third data line subsection D2 - 1 are shown in FIG.

[0138] like Fig.28 and Fig.29 As shown, the edge EG of the through hole TH constitutes a boundary line between the through hole TH and the wiring area RA. The through hole TH is formed by cutting the display panel, so the edge EG of the through hole TH is a cutting line when cutting the display panel.

[0139] also, Fig.28 and Fig.29 A virtual boundary line DBL between the wiring area RA and the display area AA is also shown in FIG. It should be noted that, unlike the edge EG of the through hole TH, the virtual boundary line DBL is a virtual line for more clearly showing the division between the wiring area RA and the display area AA, and does not actually exist.

[0140] like Fig.28 and Fig.29 As shown, the first data line segment D1-1 is connected to the first connection line CL1. Figures 28 to 30 As shown, the first connection line CL1 is located in the first signal line layer SD1, and the first data line portion D1-1 is connected to the first connection line CL1 through the ninth via hole v9, and the ninth via hole v9 extends through Fig.14 The first planarization layer PLN1 and the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN are shown in FIG.

[0141] Alternatively, the display panel may not include the passivation layer PVX in the display area, in which case the ninth via v9 extends through the first planarization layer PLN1, the interlayer dielectric layer ILD, and the second insulating layer IN. Alternatively, without including the first planarization layer PLN1, the ninth via v9 extends through the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN. That is, the fifth via v5 extends through the first planarization layer PLN1 and / or the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN.

[0142] Similarly, if Figure 22 to Figure 24 As shown, the first connection line CL1 is connected to the data line second sub-portion D1 - 2 through the tenth via hole v10 , and the tenth via hole v10 extends through the first planarization layer PLN1 and / or the passivation layer PVX, the interlayer dielectric layer ILD, and the second insulating layer IN.

[0143] like Fig.28 and Fig.29 As shown in FIG. 1 , a plurality of isolation pillars SP are disposed on one side of the first connection line CL1 close to the edge EG. Fig.29 As shown, the plurality of isolation columns SP include seven isolation columns SP disposed near the edge EG and four isolation columns SP disposed near the first connection line CL1, and a retaining wall area WA is provided between the seven isolation columns SP and the four isolation columns SP. One or more retaining walls (not shown in the figure) are provided in the retaining wall area WA. Fig.14 The encapsulation layer EN shown in FIG. is in contact with the encapsulation layer EN shown in FIG. Fig.14 The package layer EN contacts are shown in Figure 1 and are configured to block Fig.14 The organic encapsulation sublayer IJP shown in FIG. 1 overflows during the formation process.

[0144] It should be noted that there is no connection line of the gate line in the winding area RA. Because the gate line in the display panel is driven on both sides, even if the gate line is disconnected at the position of the through hole TH, it can be driven by the gate driving circuits on both sides of the display panel respectively, so there is no need to set the connection line of the gate line in the winding area RA, thereby reducing the difficulty of wiring.

[0145] like Fig.30 As shown, the minimum interval d1 between two adjacent first connection lines CL1 is in the range of 2.0 μm to 2.5 μm. For example, the minimum interval d1 between two adjacent first connection lines CL1 is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, or 2.5 μm.

[0146] In the display panel according to the present disclosure, only the first connection line CL1 is arranged in the winding area RA, and the second connection line CL2 is arranged in the display area AA. In this way, the coupling capacitance between the first connection line CL1 and the second connection line CL2 is avoided, so when the display panel displays a heavy-loaded picture, no Fig. 9 Vertical white bar shown.

[0147] In addition, in the display panel according to the present disclosure, the first data line D1 is configured to provide a data signal to the green sub-pixel g. Since the human eye is most sensitive to green, the green sub-pixel g contributes the most to the brightness of the picture. Fig.10 The first stage t1 shown is in a floating state, while the second data line D2 is not in a floating state, so the anti-interference ability of the first data line D1 is weaker than that of the second data line D2. By setting the first connection line CL1 connected to the first data line D1 in the winding area RA, the interference of other signal lines in the display area to the first data line D1 can be avoided. Since the second data line D2 has a strong anti-interference ability, setting the second connection line CL2 connected to the second data line D2 in the display area AA2 will not affect the normal display.

[0148] In another aspect, the present invention provides a display device, comprising a display panel as described herein or manufactured by the method described herein, one or more integrated circuits connected to the display panel, and a power supply assembly for providing power to the display panel and the integrated circuit. Examples of suitable display devices include, but are not limited to, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Examples of suitable power supply assemblies may be batteries in small and medium-sized products such as mobile phones and tablets, or power supply access components in large-sized products such as computers and televisions.

[0149] On the other hand, the present disclosure provides a method for manufacturing a display panel. In some embodiments, the method includes: forming a through hole in the display panel. Optionally, the through hole is formed by cutting the display panel. Optionally, the display panel further includes: a display area surrounding the through hole and configured to display an image; and a winding area located between the through hole and the display area. Optionally, the display panel includes a plurality of first data lines and a plurality of second data lines, all of which extend along a first direction in the display area and are alternately arranged along a second direction different from the second direction; the first data line whose projection from the first direction to the second direction overlaps with the projection of the through hole and / or the winding area from the first direction to the second direction, includes a first data line section and a second data line section, which are respectively located on both sides of the winding area along the first direction and are connected by a first connecting line, and the first connecting line is located in the winding area; and the second data line whose projection from the first direction to the second direction overlaps with the projection of the through hole and / or the winding area from the first direction to the second direction, includes a third data line section and a fourth data line section, which are respectively located on both sides of the winding area along the first direction and are connected by a second connecting line, and the second connecting line is located in the display area.

[0150] For the purpose of illustration and description, the above description of the embodiment of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiment disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and changes will be obvious to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, in which all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to specific examples, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A display panel, comprising: Through hole; a display area surrounding the through hole and configured to display an image; as well as a wiring area located between the through hole and the display area, Wherein, the display panel comprises a plurality of first data lines and a plurality of second data lines, the plurality of first data lines and the plurality of second data lines are extended along a first direction in the display area and are alternately arranged along a second direction, and the first direction is different from the second direction; a first data line whose projection along the first direction toward the second direction overlaps with a projection of the through hole and / or the winding area along the first direction toward the second direction, comprising a first data line section and a second data line section, wherein the first data line section and the second data line section are respectively located at two sides of the winding area along the first direction and are connected by a first connecting line, and the first connecting line is located in the winding area; and A second data line whose projection along the first direction toward the second direction overlaps with a projection of the through hole and / or the winding area along the first direction toward the second direction, comprises a third data line section and a fourth data line section, wherein the third data line section and the fourth data line section are respectively located on both sides of the winding area along the first direction and are connected by a second connecting line, and the second connecting line is located in the display area.

2. The display panel according to claim 1, wherein: A minimum interval between two adjacent first connection lines is in a range of 2.0 μm to 2.5 μm.

3. The display panel according to claim 1, wherein: A minimum distance between two adjacent second connection lines is in the range of 2.0 μm to 2.5 μm.

4. The display panel according to claim 1, wherein: The first data line is configured to provide a data signal to a green sub-pixel, and the second data line is configured to provide a data signal to a red sub-pixel and / or a blue sub-pixel.

5. The display panel according to any one of claims 1 to 4, wherein: A first multiplexer switch is provided in the first data line, and the first multiplexer switch is configured to control the conduction and cutoff of the data signal on the first data line; A second multiplexer switch is provided in the second data line, and the second multiplexer switch is configured to control the conduction and cutoff of the data signal on the second data line; and The first data line and a second data line adjacent thereto are connected to the same signal lead line.

6. The display panel according to claim 1, wherein: The second connecting line includes a connecting line first section, a connecting line second section and a connecting line third section which are connected to each other, and The third branch of the data line is connected to the first branch of the connection line, and the third branch of the connection line is connected to the fourth branch of the data line. Wherein, the first section of the connecting line and the third section of the connecting line are parallel to each other, and / or The first section of the connecting line and the third section of the connecting line are parallel to each other and have the same length.

7. The display panel according to claim 6, wherein: The first section of the connecting line and the third section of the connecting line extend along the second direction; and The second section of the connecting line extends along the first direction.

8. The display panel according to claim 1, comprising: substrate substrate; A gate insulating layer, which is located on the substrate; A first gate metal layer, which is located on a side of the gate insulating layer away from the gate insulating layer; a second insulating layer, which is located on a side of the first gate metal layer away from the gate insulating layer; a second gate metal layer, which is located on a side of the second insulating layer away from the gate insulating layer; an interlayer dielectric layer, which is located on a side of the second gate metal layer away from the gate insulating layer; A first signal line layer, which is located on a side of the interlayer dielectric layer away from the gate insulating layer; a passivation layer and / or a first planarization layer, which is located on a side of the first signal line layer away from the gate insulating layer; as well as The second signal layer is located on a side of the passivation layer and / or the first planarization layer away from the gate insulating layer.

9. The display panel according to claim 8, wherein: The third subsection of the data line is located in the second signal line layer and is connected to the second connection line through a first via hole, at least a portion of the second connection line connected to the third subsection of the data line is located in the first signal line layer, and the first via hole extends through the passivation layer and / or the first planarization layer; as well as The second connecting line is connected to the fourth section of the data line through a second via, the third section of the data line is located in the second signal line layer, at least a portion of the second connecting line connected to the fourth section of the data line is located in the first signal line layer, and the second via extends through the passivation layer and / or the first planarization layer.

10. The display panel according to claim 9, wherein: The second connecting line includes a connecting line first section, a connecting line second section and a connecting line third section which are connected to each other, and The first connection line section and the third connection line section are both located in the first signal line layer, the third connection line section is connected to the first connection line section through the first via hole, and the third connection line section is connected to the fourth connection line section through the second via hole.

11. The display panel according to claim 9, wherein: The second connecting line includes a first connecting line section, a second connecting line section and a third connecting line section which are connected to each other. The first branch of the connecting line and the third branch of the connecting line are located in the same layer, and The second branch of the connecting line is located at a layer different from the first branch of the connecting line and the third branch of the connecting line, wherein the first section of the connection line is connected to the second section of the connection line through a third via hole; and The second branch of the connection line is connected to the third branch of the connection line through a fourth via hole.

12. The display panel according to claim 11, wherein: The first connection line section and the third connection line section are both located in the first signal line layer, The second branch of the connecting line is located in the second signal line layer, and The fourth via hole and the third via hole both extend through the passivation layer and / or the first planarization layer.

13. The display panel according to claim 8, wherein: The first data line section and the second data line section are both located in the second signal line layer, The first connection line is located in the second signal line layer, and The data line first subsection, the data line second subsection and the first connecting line are formed into an integral structure.

14. The display panel according to claim 8, wherein: The first data line section and the second data line section are both located in the second signal line layer, The first connecting line is located in the first signal line layer, and The first data line section is connected to the first connection line through a fifth via hole, and the first connection line is connected to the second data line section through a sixth via hole. Both the fifth via hole and the sixth via hole extend through the passivation layer and / or the first planarization layer.

15. The display panel according to claim 8, wherein: The first data line section and the second data line section are both located in the second signal line layer, The first connection line is located in the second gate metal layer, and The first section of the data line is connected to the first connecting line through a seventh via, and the first connecting line is connected to the second section of the data line through an eighth via. Both the seventh via and the eighth via extend through the passivation layer and / or the first planarization layer, and the interlayer dielectric layer.

16. The display panel according to claim 8, wherein: The first data line section and the second data line section are both located in the second signal line layer, The first connection line is located in the first gate metal layer, and The first section of the data line is connected to the first connecting line through a ninth via, and the first connecting line is connected to the second section of the data line through a tenth via, and both the ninth via and the tenth via extend through the passivation layer and / or the first planarization layer, the interlayer dielectric layer, and the second insulating layer.

17. A display device comprising a display panel according to any one of claims 1 to 16, one or more integrated circuits connected to the display panel, and a power supply component for providing power to the display panel and the integrated circuits.

Images