Booting processing system-on-chip node configuration

Abstract

There is provided a method for sharing access to a resource between SoCs, the method may include initializing a boot process for SoCs in a set of SoCs, initializing computing resources of the SoCs during the boot process, the computing resources including at least one of input / output functionality, processing units, and memory, a node configuration for a SoC is identified during the boot process, the node configuration defining a node, where the node configuration indicates that the SoC and at least one additional SoC of the set of SoCs correspond to the node, and access to the computing resource is shared with the at least one additional SoC of the set of SoCs during the boot process. A system and a computer program product are also provided.

Description

[0001] Related Applications

[0002] This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application 63 / 363,619, filed on April 26, 2022, entitled “BOOT PROCESS SOCNODE CONFIGURATION,” which is incorporated herein by reference in its entirety. Background Art

[0003] Autonomous robotic systems, such as autonomous vehicles, rely on a suite of sensors to detect static or dynamic objects in a real-time operating environment. Object detection is typically performed by a perception subsystem of the autonomous robotic system, which includes a neural network backbone for processing large amounts of two-dimensional (2D) and / or three-dimensional (3D) sensor data in real time and classifying and locating detected objects in the operating environment. The planning system of the autonomous robotic system uses the output of the perception subsystem to plan a route through the operating environment. Due to the large amount of sensor data to be processed in real time, existing distributed computing architectures cannot meet the desired performance and safety requirements required by certain autonomous robotic systems, such as autonomous vehicles. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is an example environment in which a vehicle including one or more components of an autonomous system may be implemented.

[0005] Figure 2 is a diagram of one or more systems of a vehicle including an autonomous system.

[0006] Figure 3 yes Figure 1 and Figure 2 A diagram of one or more devices and / or components of one or more systems.

[0007] Figure 4A is a diagram of some components of an autonomous system.

[0008] Figure 4B It is a diagram of the implementation of a neural network.

[0009] Figure 4C and Figure 4D is a diagram illustrating an example operation of a CNN.

[0010] Figure 5 is an example distributed computing architecture for an autonomous robotic system according to an embodiment.

[0011] Figure 6 A CCIX software stack according to an embodiment is illustrated.

[0012] Figure 7 Example according to the embodiment Figure 5 Binding processing to a specific core on a specific MPSoC in the distributed computing architecture shown in .

[0013] Figure 8 Example according to the embodiment Figure 5 Shared memory between two MPSoCs in the distributed computing architecture shown in FIG.

[0014] Fig. 9 Example according to the embodiment Figure 5 The “leakage” in the distributed computing architecture shown in .

[0015] Fig. 10A The process of skipping a buffer through a cache coherent structure according to an embodiment is illustrated.

[0016] Fig. 10B The process of selecting useful data from a buffer according to an embodiment is illustrated.

[0017] Fig.11 is a flow chart of a process of sharing memory between cores of different MPSoCs according to an embodiment.

[0018] Fig.12 is a block diagram of an example of distributing AV computational tasks to a portion of a deep learning network for a perception pipeline for AV in accordance with one or more embodiments.

[0019] Fig.13 is a block diagram of a chip layout for a computing unit of an autonomous robotic system according to one or more embodiments.

[0020] Fig.14 is a block diagram illustrating an example of a computing system for an autonomous robotic system (eg, autonomous vehicle computing).

[0021] Fig.15 is a block diagram illustrating an example guidance process for an autonomous robotic system in accordance with one or more embodiments.

[0022] Fig.16 is a block diagram illustrating an example logical grouping of SoCs within a multi-SoC architecture in accordance with one or more embodiments.

[0023] Fig.17 is a block diagram illustrating an example of a node of a multi-SoC architecture in accordance with one or more embodiments.

[0024] Fig.18 is a flow chart of a process of entering a multi-processing mode for a SoC during a boot process according to an embodiment. DETAILED DESCRIPTION

[0025] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent that the embodiments described in the present disclosure can be implemented without these specific details. In some instances, well-known configurations and devices are illustrated in block diagram form to avoid unnecessarily obscuring aspects of the present disclosure.

[0026] In the accompanying drawings, for ease of description, the specific arrangement or order of schematic elements (such as those representing systems, devices, modules, instruction blocks and / or data elements, etc.) is illustrated. However, those skilled in the art will understand that, unless explicitly described, the specific order or arrangement of schematic elements in the accompanying drawings is not intended to mean that a specific processing order or sequence, or separation of processing is required. In addition, unless explicitly described, the inclusion of schematic elements in the accompanying drawings is not intended to mean that such elements are required in all embodiments, nor is it intended to mean that the features represented by such elements cannot be included in some embodiments or cannot be combined with other elements in some embodiments.

[0027] In addition, in the accompanying drawings, connecting elements (such as solid or dotted lines or arrows, etc.) are used to illustrate the connection, relationship or association between or among two or more other schematic elements, and the absence of any such connecting elements is not intended to mean that there can be no connection, relationship or association. In other words, some connections, relationships or associations between elements are not illustrated in the accompanying drawings so as not to obscure the present disclosure. In addition, for ease of illustration, a single connecting element can be used to represent multiple connections, relationships or associations between elements. For example, if the connecting element represents the communication of a signal, data or instruction (e.g., "software instruction"), it will be understood by those skilled in the art that such an element can represent one or more than one signal path (e.g., bus) that may be needed to affect the communication.

[0028] Although the terms "first", "second" and / or "third", etc. are used to describe various elements, these elements should not be limited by these terms. The terms "first", "second" and / or "third" are only used to distinguish one element from another. For example, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact without departing from the scope of the described embodiments. Both the first contact and the second contact are contacts, but they are not the same contacts.

[0029] The terms used in the specification of the various embodiments described herein are included only for the purpose of describing specific embodiments and are not intended to be limiting. As used in the specification of the various embodiments described and the appended claims, the singular forms "a", "an" and "the" are also intended to include plural forms and can be used interchangeably with "one or more than one" or "at least one", unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and includes any and all possible combinations of one or more than one of the associated listed items. It will also be understood that when the terms "include", "comprise", "have" and / or "have" are used in this specification, the stated features, integers, steps, operations, elements and / or components are specifically stated, but the presence or addition of one or more than one other features, integers, steps, operations, elements, components and / or groups thereof are not excluded.

[0030] As used herein, the terms "communication" and "communicating" refer to at least one of receiving, receiving, transmitting, transmitting and / or providing information (or information represented by, for example, data, signals, messages, instructions and / or commands, etc.). For a unit (e.g., a device, a system, a component of a device or system, and / or a combination thereof) to communicate with another unit, this means that the unit is able to directly or indirectly receive information from the other unit and / or send (e.g., transmit) information to the other unit. This can refer to a direct or indirect connection that is wired and / or wireless in nature. In addition, even if the transmitted information can be modified, processed, relayed and / or routed between the first unit and the second unit, the two units can communicate with each other. For example, even if the first unit passively receives information and does not actively transmit information to the second unit, the first unit can communicate with the second unit. As another example, if at least one intermediary unit (e.g., a third unit located between the first unit and the second unit) processes the information received from the first unit and transmits the processed information to the second unit, the first unit can communicate with the second unit. In some embodiments, a message may refer to a network packet (eg, a data packet, etc.) that includes data.

[0031] As used herein, the term "if" is optionally interpreted to mean "when," "at," "in response to being determined to be," and / or "in response to being detected," etc., depending on the context. Similarly, the phrases "if it is determined" or "if [the stated condition or event] is detected" are optionally interpreted to mean "when determining," "in response to being determined to be" or "when [the stated condition or event] is detected," and / or "in response to being detected," etc., depending on the context. In addition, as used herein, the terms "have," "have," or "possess," etc. are intended to be open-ended terms. Furthermore, unless expressly stated otherwise, the phrase "based on" is intended to mean "based at least in part on."

[0032] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments described. However, it will be apparent to one of ordinary skill in the art that the various embodiments described may be implemented without these specific details. In other cases, well-known methods, processes, components, circuits, and networks have not yet been described in detail in order not to unnecessarily obscure aspects of the embodiments.

[0033] General Overview

[0034] In some aspects and / or embodiments, the systems, methods, and computer program products described herein include and / or implement techniques for a distributed computing architecture for an autonomous robotic system (e.g., such as autonomous vehicle (AV) computing, etc.) having shared memory for task distribution, data communication, and reconfiguration.

[0035] The disclosed distributed computing architecture includes multiple multi-processor systems on chip (MPSoCs) coupled together by a cache coherent structure. The distributed computing architecture uses software components (e.g., middleware) to distribute system resources (e.g., system memory) to the MPSoCs in real time. In an embodiment, the middleware binds a process or thread (hereinafter referred to as a "processor / thread") to at least one processor core (e.g., an accelerator core) of the MPSoC of the distributed computing architecture. In an embodiment, a "leak" buffer (e.g., a lock-free ring buffer) located on one or more MPSoCs ensures that the process / thread can operate in real time according to the performance and safety standards for the desired application (e.g., AV computing process / thread). In an embodiment, the system memory is shared between the processor cores of the MPSoC using a transparent mirror of the logical memory address. In an embodiment, the data consumer process / thread in the distributed computing architecture can skip reading one or more buffers (e.g., buffers with stale data) of the data provided by the data producer process / thread from its own MPSoC through a cache coherent structure. In an embodiment, only useful portions of the buffered data (eg, useful for a particular task in real time) are selectively extracted / transferred from the buffer to a data consuming process / thread rather than the entire contents of the buffer.

[0036] With the implementation of the systems, methods, and computer program products described herein, the technology for implementing a distributed computing architecture with shared memory for task distribution, data communication, and reconfiguration provides at least the following advantages: Large amounts of data (e.g., sensor data) can be processed in real time at high speed to meet stringent application requirements in terms of speed and security, such as implementing various parts of a neural network backbone (e.g., feature extraction, convolutional layers, fully connected layers / prediction heads), etc.

[0037] Generally described, aspects of the present disclosure relate to the definition of compute nodes on a multi-SoC architecture during a boot process of an SoC of the multi-SoC architecture. More specifically, embodiments of the present disclosure relate to a boot process that includes a software-implemented partitioning of the multi-SoC architecture into multiple logical compute nodes, each node being implemented by one or more SoCs (e.g., a SoC cluster) within the multi-SoC architecture. The boot process enables the multi-SoC architecture to be initialized into multiple logical compute nodes without the need for physical reconfiguration. Multiple logical compute nodes provide for the implementation of many types of redundancy and resilience architectures that enable the multi-SoC architecture to be applied to safety-critical systems such as autonomous vehicles.

[0038] In safety-critical systems, multiple redundant devices are often used to ensure the continued operation of related systems such as autonomous vehicles. Typically, such redundant devices are physically defined and are immutable without physical changes. For example, an autonomous vehicle may include a primary device and a secondary device, two peer devices, three peer devices, etc., which are physically distinct and hardwired to operate in the event of a single device failure to provide redundant computing. Because these redundancies are physically static, they are difficult to reconfigure and must often be custom designed based on the application at hand.

[0039] Typically, the SoC can use internal memory or external memory to configure pre-boot behavior. For example, the SoC can access the boot code (e.g., boot loader) that defines the pre-boot behavior of the SoC. The boot code can enable the SoC to initialize the processing unit, memory (e.g., cache, random access memory (RAM), etc.) and / or input / output devices of the SoC. The SoC can access the boot code from a read-only memory (ROM). The boot code can define the kernel. The kernel can be loaded into the memory (e.g., as an image file). The kernel can perform additional initialization tasks (e.g., initializing the operating environment, hypervisor, operating system, etc.).

[0040] In contrast, embodiments of the present disclosure provide for initialization of computing nodes on a multi-SoC architecture during a boot process, which can be deployed in many situations (e.g., without the need for custom designs based on each application). As disclosed herein, a multi-SoC architecture may include multiple SoCs (e.g., physically separate and different SoCs) such as a multi-processor SoC (MPSoC) coupled together by a high-speed memory interconnect such as an interconnect that complies with the Universal Chiplet Interconnect Express (UCIe) standard. The interconnection can enable system memory to be shared between SoCs, thereby enabling the SoC to operate as a single computing device (e.g., running a single operating system, "bare metal" applications, etc.). In addition, the interconnection can enable communication between devices according to a networking protocol (e.g., a transmission control protocol / Internet protocol or TCP / IP) or other device-to-device protocols. Therefore, different SoCs can interact as different computing nodes (e.g., each running a different operating system, bare metal applications, etc.).

[0041] During the boot process, the SoC may initialize resources (e.g., computing resources) for all or part of the SoC. For example, the SoC may initialize processing units, memories, and / or input / output devices for all or part of the SoC. The SoC may define computing nodes including resources of one or more SoCs during the boot process. The SoC may define computing nodes so that one or more SoCs share resources. For example, the 6SoC architecture may be divided into 6 different nodes of each single SoC, 3 different nodes of each 2 SoCs, 2 nodes of each 1 SoC, and 1 node of each 4 SoCs, etc. Each computing node may represent a different logical computing device, and different logical computing devices have corresponding different physical computing resources provided by the associated SoC. Therefore, redundancy may be provided by establishing multiple nodes within a multi-SoC architecture. Since each node logically operates as a different computing device and has hardware independent of other computing nodes, these nodes may operate as different physical nodes in a manner that is mostly the same as a manually designed redundant SoC. However, because the nodes are configurable, the nodes may alternatively be reconfigured (e.g., redefined) so that the same set of SoCs operate as a single node, thereby providing increased computing capacity (e.g., increased parallelism within a logical node). Thus, a single multi-SoC architecture may be suitable for a wide variety of uses and reconfigured via software to provide the appropriate level of redundancy and parallelism for a given use.

[0042] As will be appreciated by those skilled in the art from this disclosure, the embodiments disclosed herein provide improved operation of a multi-SoC architecture, thereby enabling the architecture to implement a wide variety of computing node configurations, varying the redundancy and parallelism provided by the architecture according to the desired use. This flexibility in redundancy and parallelism, in turn, enables a single multi-SoC architecture to be applied to a variety of use cases, thereby reducing the need for customized physical architectures in these use cases. The embodiments described herein may have particular uses in safety-critical real-time applications such as autonomous vehicles. In addition, the presently disclosed embodiments address technical problems inherent in computing systems; specifically, the difficulty of designing a physical architecture to support safety-critical real-time applications with appropriate redundancy and parallelism. Thus, the present disclosure embodies improvements in autonomous vehicle systems and computing systems in general.

[0043] The foregoing aspects of the present disclosure and many of the attendant advantages will become better understood by reference to the following description when taken in conjunction with the accompanying drawings, thereby becoming more readily appreciated.

[0044] Reference now Figure 1, illustrates an example environment 100 in which vehicles including autonomous systems and vehicles not including autonomous systems operate. As illustrated, the environment 100 includes vehicles 102a-102n, objects 104a-104n, routes 106a-106n, areas 108, vehicle-to-infrastructure (V2I) devices 110, a network 112, a remote autonomous vehicle (AV) system 114, a fleet management system 116, and a V2I system 118. The vehicles 102a-102n, the vehicle-to-infrastructure (V2I) devices 110, the network 112, the autonomous vehicle (AV) system 114, the fleet management system 116, and the V2I system 118 are interconnected (e.g., establish connections for communication, etc.) via wired connections, wireless connections, or a combination of wired or wireless connections. In some embodiments, objects 104a-104n are interconnected with at least one of vehicles 102a-102n, vehicle-to-infrastructure (V2I) devices 110, networks 112, autonomous vehicle (AV) systems 114, fleet management systems 116, and V2I systems 118 via wired connections, wireless connections, or a combination of wired or wireless connections.

[0045] Vehicles 102a-102n (individually referred to as vehicles 102 and collectively referred to as vehicles 102) include at least one device configured to transport goods and / or people. In some embodiments, vehicles 102 are configured to communicate with V2I devices 110, remote AV systems 114, fleet management systems 116, and / or V2I systems 118 via network 112. In some embodiments, vehicles 102 include cars, buses, trucks, and / or trains, etc. In some embodiments, vehicles 102 are similar to vehicles 200 described herein (see Figure 2 ). In some embodiments, vehicles 200 in the set of vehicles 200 are associated with an autonomous queue manager. In some embodiments, vehicles 102 travel along respective routes 106a-106n (individually referred to as routes 106 and collectively referred to as routes 106) as described herein. In some embodiments, one or more vehicles 102 include an autonomous system (e.g., an autonomous system that is the same as or similar to autonomous system 202).

[0046] Objects 104a-104n (individually referred to as objects 104 and collectively referred to as objects 104) include, for example, at least one vehicle, at least one pedestrian, at least one cyclist, and / or at least one structure (e.g., a building, a sign, a fire hydrant, etc.), etc. Each object 104 is stationary (e.g., located at a fixed location and over a period of time) or moves (e.g., has a speed and is associated with at least one trajectory). In some embodiments, objects 104 are associated with corresponding locations in area 108.

[0047] Routes 106a-106n (individually referred to as routes 106 and collectively referred to as routes 106) are each associated with (e.g., specify a series of actions (also referred to as trajectories) connecting states along which the AV can navigate. Each route 106 begins at an initial state (e.g., a state corresponding to a first spatiotemporal location and / or speed, etc.) and ends at a final target state (e.g., a state corresponding to a second spatiotemporal location different from the first spatiotemporal location) or a target zone (e.g., a subspace of acceptable states (e.g., terminal states)). In some embodiments, the first state includes a location where one or more individuals will board the AV, and the second state or zone includes one or more locations where one or more individuals boarding the AV will disembark. In some embodiments, routes 106 include multiple acceptable state sequences (e.g., multiple spatiotemporal location sequences) that are associated with (e.g., define multiple trajectories). In an example, routes 106 include only high-level actions or imprecise state locations, such as a series of connecting roads indicating a change of direction at a roadway intersection, etc. Additionally or alternatively, the route 106 may include more precise actions or states, such as, for example, specific target lanes or precise locations within lane regions and target speeds at those locations, etc. In an example, the route 106 includes a plurality of precise state sequences along at least one high-level action with a limited look-ahead horizon to an intermediate target, wherein a combination of consecutive iterations of the limited horizon state sequences cumulatively correspond to a plurality of trajectories that collectively form a high-level route terminating at a final target state or region.

[0048] The area 108 includes a physical area (e.g., a geographic region) in which the vehicle 102 can navigate. In an example, the area 108 includes at least one state (e.g., a country, a province, a separate state of a plurality of states included in a country, etc.), at least a portion of a state, at least one city, at least a portion of a city, etc. In some embodiments, the area 108 includes at least one named thoroughfare (referred to herein as a "road"), such as a highway, an interstate highway, a parkway, a city street, etc. Additionally or alternatively, in some examples, the area 108 includes at least one unnamed road, such as a driveway, a section of a parking lot, a section of an open space and / or undeveloped area, a dirt road, etc. In some embodiments, the road includes at least one lane (e.g., a portion of the road that the vehicle 102 can traverse). In an example, the road includes at least one lane associated with (e.g., identified based on) at least one lane marking line.

[0049] The vehicle-to-infrastructure (V2I) device 110 (sometimes referred to as a vehicle-to-infrastructure or vehicle-to-everything (V2X) device) includes at least one device configured to communicate with the vehicle 102 and / or the V2I system 118. In some embodiments, the V2I device 110 is configured to communicate with the vehicle 102, the remote AV system 114, the fleet management system 116, and / or the V2I system 118 via the network 112. In some embodiments, the V2I device 110 includes a radio frequency identification (RFID) device, a sign, a camera (e.g., a two-dimensional (2D) and / or three-dimensional (3D) camera), lane markings, street lights, parking meters, etc. In some embodiments, the V2I device 110 is configured to communicate directly with the vehicle 102. Additionally or alternatively, in some embodiments, the V2I device 110 is configured to communicate with the vehicle 102, the remote AV system 114, and / or the fleet management system 116 via the V2I system 118. In some embodiments, the V2I device 110 is configured to communicate with the V2I system 118 via the network 112.

[0050] The network 112 includes one or more wired and / or wireless networks. In an example, the network 112 includes a cellular network (e.g., a long-term evolution (LTE) network, a third generation (3G) network, a fourth generation (4G) network, a fifth generation (5G) network, a code division multiple access (CDMA) network, etc.), a public land mobile network (PLMN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a telephone network (e.g., a public switched telephone network (PSTN)), a private network, an ad hoc network, an intranet, the Internet, a fiber-based network, a cloud computing network, etc., and / or a combination of some or all of these networks, etc.

[0051] The remote AV system 114 includes at least one device configured to communicate with the vehicle 102, the V2I device 110, the network 112, the fleet management system 116, and / or the V2I system 118 via the network 112. In an example, the remote AV system 114 includes a server, a server group, and / or other similar devices. In some embodiments, the remote AV system 114 is co-located with the fleet management system 116. In some embodiments, the remote AV system 114 participates in the installation of some or all of the components of the vehicle (including autonomous systems, autonomous vehicle computing, and / or software implemented by autonomous vehicle computing, etc.). In some embodiments, the remote AV system 114 maintains (e.g., updates and / or replaces) these components and / or software during the life of the vehicle.

[0052] The queue management system 116 includes at least one device configured to communicate with the vehicles 102, the V2I devices 110, the remote AV system 114, and / or the V2I system 118. In an example, the queue management system 116 includes a server, a server group, and / or other similar devices. In some embodiments, the queue management system 116 is associated with a ridesharing company (e.g., an organization for controlling the operation of multiple vehicles (e.g., vehicles including autonomous systems and / or vehicles not including autonomous systems), etc.).

[0053] In some embodiments, the V2I system 118 includes at least one device configured to communicate with the vehicle 102, the V2I device 110, the remote AV system 114, and / or the fleet management system 116 via the network 112. In some examples, the V2I system 118 is configured to communicate with the V2I device 110 via a connection other than the network 112. In some embodiments, the V2I system 118 includes a server, a server group, and / or other similar devices. In some embodiments, the V2I system 118 is associated with a municipality or a private agency (e.g., a private agency for maintaining the V2I device 110, etc.).

[0054] supply Figure 1 The number and arrangement of elements illustrated are examples. Figure 1 There may be additional elements, fewer elements, different elements, and / or differently arranged elements than those illustrated. Additionally or alternatively, at least one element of environment 100 may be described as being Figure 1 Additionally or alternatively, at least one set of elements of environment 100 may perform one or more functions described as being performed by at least one different set of elements of environment 100.

[0055] Reference now Figure 2 , a vehicle 200 (the vehicle 200 may be Figure 1 102) includes or is associated with autonomous system 202, powertrain control system 204, steering control system 206, and braking system 208. In some embodiments, vehicle 200 is similar to vehicle 102 (see Figure 1 ) is the same or similar. In some embodiments, the autonomous system 202 is configured to give the vehicle 200 autonomous driving capabilities (e.g., implementing at least one of the following driving automatic or maneuver-based functions, features and / or devices, etc., which enable the vehicle 200 to operate partially or completely without human intervention, including but not limited to fully autonomous vehicles (e.g., vehicles that abandon reliance on human intervention, such as Level 5 ADS-operated vehicles, etc.), highly autonomous vehicles (e.g., vehicles that abandon reliance on human intervention in certain situations, such as Level 4 ADS-operated vehicles, etc.), and / or conditionally autonomous vehicles (e.g., vehicles that abandon reliance on human intervention in limited situations, such as Level 3 ADS-operated vehicles, etc.), etc.). In one embodiment, the autonomous system 202 includes the operational or tactical functionality required to enable the vehicle 200 to operate in traffic on the road and continuously perform part or all of the dynamic driving task (DDT). In another embodiment, the autonomous system 202 includes an advanced driver assistance system (ADAS) including driver support features. The autonomous system 202 supports various levels of driving automation ranging from no driving automation (e.g., level 0) to full driving automation (e.g., level 5). For a detailed description of fully autonomous vehicles and highly autonomous vehicles, reference may be made to SAE International's standard J3016: Taxonomy and Definitions for Terms Related to On-Road Motor Vehicle Automated Driving Systems, the entire contents of which are incorporated by reference. In some embodiments, the vehicle 200 is associated with an autonomous queue manager and / or a ridesharing company.

[0056] Autonomous system 202 includes a sensor suite that includes one or more devices such as a camera 202a, a LiDAR sensor 202b, a radar sensor 202c, and a microphone 202d. In some embodiments, autonomous system 202 may include more or fewer devices and / or different devices (e.g., ultrasonic sensors, inertial sensors, GPS receivers (discussed below), and / or odometer sensors for generating data associated with an indication of the distance that vehicle 200 has traveled, etc.). In some embodiments, autonomous system 202 uses one or more devices included in autonomous system 202 to generate data associated with environment 100 described herein. The data generated by one or more devices of autonomous system 202 can be used by one or more systems described herein to observe the environment (e.g., environment 100) in which vehicle 200 is located. In some embodiments, autonomous system 202 includes a communication device 202e, an autonomous vehicle computer 202f, a drive-by-wire (DBW) system 202h, and a safety controller 202g.

[0057] The camera 202a includes a communication device 202e, an autonomous vehicle computer 202f, and / or a safety controller 202g configured to communicate with the communication device 202e via a bus (e.g., Figure 3 The camera 202a includes at least one device for communicating with the autonomous vehicle computing 202f (e.g., an image processing unit 202a, a bus ... Figure 1In some embodiments, the autonomous vehicle computing 202f determines a depth to one or more objects in a field of view of at least two of the plurality of cameras based on image data from the at least two cameras. In some embodiments, the camera 202a is configured to capture images of objects within a distance relative to the camera 202a (e.g., up to 100 meters and / or up to 1 kilometer, etc.). Thus, the camera 202a includes features such as sensors and lenses that are optimized for sensing objects at one or more distances relative to the camera 202a.

[0058] In an embodiment, the camera 202a includes at least one camera configured to capture one or more images associated with one or more traffic lights, street signs, and / or other physical objects that provide visual navigation information. In some embodiments, the camera 202a generates traffic light data associated with the one or more images. In some examples, the camera 202a generates TLD (traffic light detection) data associated with one or more images including a format (e.g., RAW, JPEG, and / or PNG, etc.). In some embodiments, the camera 202a that generates TLD data differs from other systems incorporating cameras described herein in that the camera 202a may include one or more cameras with a wide field of view (e.g., a wide-angle lens, a fisheye lens, and / or a lens with a viewing angle of approximately 120 degrees or greater, etc.) to generate images related to as many physical objects as possible.

[0059] The light detection and ranging (LiDAR) sensor 202b includes a communication device 202e, an autonomous vehicle computing device 202f, and / or a safety controller 202g configured to communicate with the communication device 202e via a bus (e.g., Figure 3The LiDAR sensor 202b includes at least one device that communicates with a bus (the same or similar bus as the bus 302 of the embodiment of the present invention). The LiDAR sensor 202b includes a system configured to emit light from a light emitter (e.g., a laser emitter). The light emitted by the LiDAR sensor 202b includes light outside the visible spectrum (e.g., infrared light, etc.). In some embodiments, during operation, the light emitted by the LiDAR sensor 202b encounters a physical object (e.g., a vehicle) and is reflected back to the LiDAR sensor 202b. In some embodiments, the light emitted by the LiDAR sensor 202b does not penetrate the physical object encountered by the light. The LiDAR sensor 202b also includes at least one light detector that detects the light emitted from the light emitter after encountering the physical object. In some embodiments, at least one data processing system associated with the LiDAR sensor 202b generates an image (e.g., a point cloud and / or a combined point cloud, etc.) representing objects included in the field of view of the LiDAR sensor 202b. In some examples, at least one data processing system associated with the LiDAR sensor 202b generates an image representing the boundaries of the physical object and / or the surface of the physical object (e.g., the topology of the surface), etc. In such examples, the image is used to determine the boundaries of the physical object in the field of view of the LiDAR sensor 202b.

[0060] The radio detection and ranging (radar) sensor 202c includes a communication device 202e, an autonomous vehicle computing device 202f, and / or a safety controller 202g via a bus (e.g., Figure 3 The radar sensor 202c includes at least one device that communicates with a bus (same or similar to the bus 302 of the embodiment of the present invention). The radar sensor 202c includes a system configured to transmit (pulsed or continuous) radio waves. The radio waves transmitted by the radar sensor 202c include radio waves within a predetermined spectrum. In some embodiments, during operation, the radio waves transmitted by the radar sensor 202c encounter physical objects and are reflected back to the radar sensor 202c. In some embodiments, the radio waves transmitted by the radar sensor 202c are not reflected by some objects. In some embodiments, at least one data processing system associated with the radar sensor 202c generates a signal representing an object included in the field of view of the radar sensor 202c. For example, at least one data processing system associated with the radar sensor 202c generates an image representing the boundaries of the physical object and / or the surface of the physical object (e.g., the topology of the surface), etc. In some examples, the image is used to determine the boundaries of the physical objects in the field of view of the radar sensor 202c.

[0061] The microphone 202d includes a microphone configured to communicate with the communication device 202e, the autonomous vehicle computing device 202f, and / or the safety controller 202g via a bus (e.g., Figure 3At least one device for communicating with the vehicle 200 (the same or similar bus as bus 302 of FIG. 1 ). Microphone 202d includes one or more microphones (e.g., an array microphone and / or an external microphone, etc.) that capture an audio signal and generate data associated with (e.g., representing) the audio signal. In some examples, microphone 202d includes a transducer device and / or the like. In some embodiments, one or more systems described herein can receive the data generated by microphone 202d and determine the position (e.g., distance, etc.) of an object relative to vehicle 200 based on an audio signal associated with the data.

[0062] The communication device 202e includes at least one device configured to communicate with the camera 202a, the LiDAR sensor 202b, the radar sensor 202c, the microphone 202d, the autonomous vehicle computing 202f, the safety controller 202g, and / or the drive-by-wire (DBW) system 202h. For example, the communication device 202e may include at least one device configured to communicate with the camera 202a, the LiDAR sensor 202b, the radar sensor 202c, the microphone 202d, the autonomous vehicle computing 202f, the safety controller 202g, and / or the drive-by-wire (DBW) system 202h. Figure 3 The communication device 202e may be a device that is the same as or similar to the communication interface 314 of the vehicle. In some embodiments, the communication device 202e includes a vehicle-to-vehicle (V2V) communication device (eg, a device for enabling wireless communication of data between vehicles).

[0063] The autonomous vehicle computing 202f includes at least one device configured to communicate with the camera 202a, the LiDAR sensor 202b, the radar sensor 202c, the microphone 202d, the communication device 202e, the safety controller 202g and / or the DBW system 202h. In some examples, the autonomous vehicle computing 202f includes devices such as client devices, mobile devices (e.g., cellular phones and / or tablets, etc.), and / or servers (e.g., computing devices including one or more central processing units and / or graphics processing units, etc.). In some embodiments, the autonomous vehicle computing 202f is configured to implement the autonomous vehicle software 400 described herein. In an embodiment, the autonomous vehicle computing 202f is the same as or similar to the distributed computing architecture 500 described herein. Additionally or alternatively, in some embodiments, the autonomous vehicle computing 202f is configured to communicate with an autonomous vehicle system (e.g., with Figure 1 remote AV system 114 of the same or similar autonomous vehicle system), a fleet management system (e.g., Figure 1 of the same or similar queue management system as the queue management system 116), V2I devices (e.g., Figure 1 V2I device 110 that is the same as or similar to V2I device 110) and / or V2I system (e.g., Figure 1 The V2I system 118 may communicate with the same or similar V2I system.

[0064] Safety controller 202g includes at least one device configured to communicate with camera 202a, LiDAR sensor 202b, radar sensor 202c, microphone 202d, communication device 202e, autonomous vehicle computing 202f, and / or DBW system 202h. In some examples, safety controller 202g includes one or more controllers (electrical controllers and / or electromechanical controllers, etc.) configured to generate and / or transmit control signals to operate one or more devices of vehicle 200 (e.g., powertrain control system 204, steering control system 206, and / or braking system 208, etc.). In some embodiments, safety controller 202g is configured to generate control signals that take precedence over (e.g., override) control signals generated and / or transmitted by autonomous vehicle computing 202f.

[0065] The DBW system 202h includes at least one device configured to communicate with the communication device 202e and / or the autonomous vehicle computing 202f. In some examples, the DBW system 202h includes one or more controllers (e.g., electrical controllers and / or electromechanical controllers, etc.) configured to generate and / or transmit control signals to operate one or more devices of the vehicle 200 (e.g., powertrain control system 204, steering control system 206, and / or braking system 208, etc.). Additionally or alternatively, one or more controllers of the DBW system 202h are configured to generate and / or transmit control signals to operate at least one different device of the vehicle 200 (e.g., turn signals, headlights, door locks, and / or windshield wipers, etc.).

[0066] The powertrain control system 204 includes at least one device configured to communicate with the DBW system 202h. In some examples, the powertrain control system 204 includes at least one controller and / or actuator, etc. In some embodiments, the powertrain control system 204 receives control signals from the DBW system 202h, and the powertrain control system 204 causes the vehicle 200 to make longitudinal vehicle movements such as starting to move forward, stopping to move forward, starting to move backward, stopping to move backward, accelerating in a certain direction, decelerating in a certain direction, etc., or to make lateral vehicle movements such as turning left and / or turning right. In an example, the powertrain control system 204 increases, maintains the same, or decreases the energy (e.g., fuel and / or electricity, etc.) provided to the motor of the vehicle, thereby rotating or not rotating at least one wheel of the vehicle 200.

[0067] The steering control system 206 includes at least one device configured to rotate one or more wheels of the vehicle 200. In some examples, the steering control system 206 includes at least one controller and / or actuator, etc. In some embodiments, the steering control system 206 rotates the two front wheels and / or the two rear wheels of the vehicle 200 to the left or right to turn the vehicle 200 left or right. In other words, the steering control system 206 causes the activities necessary to adjust the y-axis component of the vehicle's motion.

[0068] Braking system 208 includes at least one device configured to actuate one or more brakes to decelerate and / or hold vehicle 200 stationary. In some examples, braking system 208 includes at least one controller and / or actuator configured to cause one or more calipers associated with one or more wheels of vehicle 200 to close on respective rotors of vehicle 200. Additionally or alternatively, in some examples, braking system 208 includes an automatic emergency braking (AEB) system and / or a regenerative braking system, etc.

[0069] In some embodiments, vehicle 200 includes at least one platform sensor (not explicitly illustrated) for measuring or inferring a property of a state or condition of vehicle 200. In some examples, vehicle 200 includes platform sensors such as a global positioning system (GPS) receiver, an inertial measurement unit (IMU), wheel rate sensors, wheel brake pressure sensors, wheel torque sensors, engine torque sensors, and / or steering angle sensors. Although braking system 208 is Figure 2 Although illustrated as being located on the proximal side of the vehicle 200 , the braking system 208 may be located anywhere in the vehicle 200 .

[0070] Reference now Figure 3 , a schematic diagram of an exemplary device 300. As illustrated, device 300 includes a processor 304, a memory 306, a storage component 308, an input interface 310, an output interface 312, a communication interface 314, and a bus 302. In some embodiments, device 300 corresponds to: at least one device of vehicle 102 (e.g., at least one device of a system of vehicle 102); and / or one or more devices of network 112 (e.g., one or more devices of a system of network 112). In some embodiments, one or more devices of vehicle 102 (e.g., one or more devices of a system of vehicle 102), and / or one or more devices of network 112 (e.g., one or more devices of a system of network 112) include at least one device 300 and / or at least one component of device 300. As Figure 3As shown, apparatus 300 includes a bus 302 , a processor 304 , a memory 306 , a storage component 308 , an input interface 310 , an output interface 312 , and a communication interface 314 .

[0071] The bus 302 includes components that permit communication between components of the device 300. In some cases, the processor 304 includes a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), and / or a neural processing unit (NPU), etc.), a digital signal processor (DSP), and / or any processing component that can be programmed to perform at least one function (e.g., a field programmable gate array (FPGA) and / or an application specific integrated circuit (ASIC), etc.). The memory 306 includes a random access memory (RAM), a read-only memory (ROM), a dynamic RAM (DRAM), and / or another type of dynamic and / or static storage device (e.g., flash memory, magnetic memory, and / or optical memory, etc.) that stores data and / or instructions for use by the processor 304.

[0072] Storage component 308 stores data and / or software related to the operation and use of device 300. In some examples, storage component 308 includes a hard disk (e.g., a magnetic disk, an optical disk, a magneto-optical disk, and / or a solid-state disk, etc.), a compact disk (CD), a digital versatile disk (DVD), a floppy disk, a cassette, a tape, a CD-ROM, a RAM, a PROM, an EPROM, a FLASH-EPROM, an NV-RAM, and / or another type of computer-readable medium, and a corresponding drive.

[0073] The input interface 310 includes components that permit the device 300 to receive information, such as via user input (e.g., a touch screen display, a keyboard, a keypad, a mouse, a button, a switch, a microphone, and / or a camera, etc.). Additionally or alternatively, in some embodiments, the input interface 310 includes a sensor for sensing information (e.g., a global positioning system (GPS) receiver, an accelerometer, a gyroscope, and / or an actuator, etc.). The output interface 312 includes components for providing output information from the device 300 (e.g., a display, a speaker, and / or one or more light emitting diodes (LEDs), etc.).

[0074] In some embodiments, communication interface 314 includes a transceiver-like component (e.g., a transceiver and / or a separate receiver and transmitter, etc.) that permits device 300 to communicate with other devices via a wired connection, a wireless connection, or a combination of a wired connection and a wireless connection. In some examples, communication interface 314 permits device 300 to receive information from another device and / or provide information to another device. In some examples, communication interface 314 includes an Ethernet interface, an optical interface, a coaxial interface, an infrared interface, a radio frequency (RF) interface, a universal serial bus (USB) interface, interface and / or cellular network interface, etc.

[0075] In some embodiments, the device 300 performs one or more processes described herein. The device 300 performs these processes based on the processor 304 executing software instructions stored by a computer-readable medium such as a memory 306 and / or a storage component 308. Computer-readable media (e.g., non-transitory computer-readable media) are defined herein as non-transitory memory devices. Non-transitory memory devices include storage space located within a single physical storage device or storage space distributed across multiple physical storage devices.

[0076] In some embodiments, the software instructions are read into the memory 306 and / or storage component 308 from another computer-readable medium or from another device via the communication interface 314. The software instructions stored in the memory 306 and / or storage component 308, when executed, cause the processor 304 to perform one or more processes described herein. Additionally or alternatively, hardwired circuitry is used in place of or in combination with the software instructions to perform one or more processes described herein. Therefore, unless expressly stated otherwise, the embodiments described herein are not limited to any specific combination of hardware circuitry and software.

[0077] The memory 306 and / or the storage component 308 include a data storage unit or at least one data structure (e.g., a database, etc.). The device 300 can receive information from the data storage unit or at least one data structure in the memory 306 or the storage component 308, store information in the data storage unit or at least one data structure, communicate information to the data storage unit or at least one data structure, or search for information stored in the data storage unit or at least one data structure. In some examples, the information includes network data, input data, output data, or any combination thereof.

[0078] In some embodiments, the device 300 is configured to execute software instructions stored in the memory 306 and / or the memory of another device (e.g., another device that is the same as or similar to the device 300). As used herein, the term "module" refers to at least one instruction stored in the memory 306 and / or the memory of another device, which, when executed by the processor 304 and / or the processor of another device (e.g., another device that is the same as or similar to the device 300), causes the device 300 (e.g., at least one component of the device 300) to perform one or more processes described herein. In some embodiments, the module is implemented in software, firmware, and / or hardware, etc.

[0079] supply Figure 3 The number and arrangement of components illustrated are examples. Figure 3 The device 300 may include additional components, fewer components, different components, or differently arranged components than those illustrated. Additionally or alternatively, a set of components (e.g., one or more components) of the device 300 may perform one or more functions described as being performed by another component or set of components of the device 300.

[0080] Reference now Figure 4A, illustrates an example block diagram of autonomous vehicle software 400 (sometimes referred to as an "AV stack"). As illustrated, autonomous vehicle software 400 includes a perception system 402 (sometimes referred to as a perception module), a planning system 404 (sometimes referred to as a planning module), a positioning system 406 (sometimes referred to as a positioning module), a control system 408 (sometimes referred to as a control module), and a database 410. In some embodiments, perception system 402, planning system 404, positioning system 406, control system 408, and database 410 are included in and / or implemented in an automatic navigation system of a vehicle (e.g., autonomous vehicle computing 202f of vehicle 200). Additionally or alternatively, in some embodiments, perception system 402, planning system 404, positioning system 406, control system 408, and database 410 are included in one or more independent systems (e.g., one or more systems that are the same or similar to autonomous vehicle software 400, etc.). In some examples, the perception system 402, planning system 404, positioning system 406, control system 408, and database 410 are included in one or more independent systems located in the vehicle and / or at least one remote system as described herein. In some embodiments, any and / or all of the systems included in the autonomous vehicle software 400 are implemented in software (e.g., software instructions stored in a memory), computer hardware (e.g., by a microprocessor, microcontroller, application specific integrated circuit (ASIC) and / or field programmable gate array (FPGA)), chiplets, or distributed computing architectures. It will also be understood that in some embodiments, the autonomous vehicle software 400 is configured to communicate with a remote system (e.g., an autonomous vehicle system that is the same or similar to the remote AV system 114, a fleet management system 116 that is the same or similar to the fleet management system 116, and / or a V2I system that is the same or similar to the V2I system 118, etc.).

[0081] In some embodiments, the perception system 402 receives data associated with at least one physical object in the environment (e.g., data used by the perception system 402 to detect at least one physical object) and classifies the at least one physical object. In some examples, the perception system 402 receives image data captured by at least one camera (e.g., camera 202a), the image being associated with (e.g., representing) one or more physical objects within the field of view of the at least one camera. In such examples, the perception system 402 classifies the at least one physical object based on one or more groups of physical objects (e.g., bicycles, vehicles, traffic signs, and / or pedestrians, etc.). In some embodiments, based on the classification of the physical object by the perception system 402, the perception system 402 transmits data associated with the classification of the physical object to the planning system 404.

[0082] In some embodiments, the planning system 404 receives data associated with a destination and generates data associated with at least one route (e.g., route 106) along which a vehicle (e.g., vehicle 102) can travel toward the destination. In some embodiments, the planning system 404 periodically or continuously receives data (e.g., data associated with the classification of physical objects described above) from the perception system 402, and the planning system 404 updates at least one trajectory or generates at least one different trajectory based on the data generated by the perception system 402. In other words, the planning system 404 can perform tasks related to the tactical functions required to operate the vehicle 101 in traffic on the road. Tactical efforts involve maneuvering the vehicle in traffic during the journey, which includes but is not limited to deciding whether and when to overtake another vehicle, change lanes, or select an appropriate rate, acceleration, deceleration, etc. In some embodiments, the planning system 404 receives data associated with an updated position of the vehicle (e.g., vehicle 102) from the positioning system 406, and the planning system 404 updates at least one trajectory or generates at least one different trajectory based on the data generated by the positioning system 406.

[0083] In some embodiments, the positioning system 406 receives data associated with (e.g., representing) a location of a vehicle (e.g., vehicle 102) in an area. In some examples, the positioning system 406 receives LiDAR data associated with at least one point cloud generated by at least one LiDAR sensor (e.g., LiDAR sensor 202b). In some examples, the positioning system 406 receives data associated with at least one point cloud from multiple LiDAR sensors, and the positioning system 406 generates a combined point cloud based on each point cloud. In these examples, the positioning system 406 compares the at least one point cloud or the combined point cloud with a two-dimensional (2D) and / or three-dimensional (3D) map of the area stored in the database 410. Then, based on the positioning system 406 comparing the at least one point cloud or the combined point cloud with the map, the positioning system 406 determines the position of the vehicle in the area. In some embodiments, the map includes a combined point cloud of the area generated before the navigation of the vehicle. In some embodiments, the map includes, but is not limited to, a high-precision map of roadway geometry, a map describing the road network connectivity, a map describing the physical properties of the roadway (such as traffic speed, traffic volume, the number of vehicle and bicycle traffic lanes, lane width, lane traffic direction or the type and location of lane markings, or a combination thereof, etc.), and a map describing the spatial location of road features (such as crosswalks, traffic signs, or various types of other driving lights, etc.). In some embodiments, the map is generated in real time based on data received by the perception system.

[0084] In another example, positioning system 406 receives global navigation satellite system (GNSS) data generated by a global positioning system (GPS) receiver. In some examples, positioning system 406 receives GNSS data associated with a location of a vehicle in an area, and positioning system 406 determines the latitude and longitude of the vehicle in the area. In such an example, positioning system 406 determines the position of the vehicle in the area based on the latitude and longitude of the vehicle. In some embodiments, positioning system 406 generates data associated with the position of the vehicle. In some examples, based on the location of the vehicle determined by positioning system 406, positioning system 406 generates data associated with the position of the vehicle. In such an example, the data associated with the position of the vehicle include data associated with one or more semantic properties corresponding to the position of the vehicle.

[0085] In some embodiments, the control system 408 receives data associated with at least one trajectory from the planning system 404, and the control system 408 controls the operation of the vehicle. In some examples, the control system 408 receives data associated with at least one trajectory from the planning system 404, and the control system 408 controls the operation of the vehicle by generating and transmitting control signals to operate the powertrain control system (e.g., DBW system 202h and / or powertrain control system 204, etc.), the steering control system (e.g., steering control system 206) and / or the braking system (e.g., braking system 208). For example, the control system 408 is configured to perform operational functions such as lateral vehicle motion control or longitudinal vehicle motion control. Lateral vehicle motion control causes the necessary activities for the adjustment of the y-axis component of the vehicle motion. Longitudinal vehicle motion control causes the necessary activities for the adjustment of the x-axis component of the vehicle motion. In the example, in the case where the trajectory includes a left turn, the control system 408 transmits a control signal to cause the steering control system 206 to adjust the steering angle of the vehicle 200, thereby turning the vehicle 200 left. Additionally or alternatively, the control system 408 generates and transmits control signals to cause other devices of the vehicle 200 (eg, headlights, turn signals, door locks, and / or windshield wipers, etc.) to change states.

[0086] In some embodiments, perception system 402, planning system 404, positioning system 406, and / or control system 408 implement at least one machine learning model (e.g., at least one multi-layer perceptron (MLP), at least one convolutional neural network (CNN), at least one recurrent neural network (RNN), at least one autoencoder, and / or at least one transformer, etc.). In some examples, perception system 402, planning system 404, positioning system 406, and / or control system 408 implement at least one machine learning model alone or in combination with one or more of the above systems. In some examples, perception system 402, planning system 404, positioning system 406, and / or control system 408 implement at least one machine learning model as part of a pipeline (e.g., a pipeline for identifying one or more objects located in an environment, etc.). The following is about FIG. 4B to FIG. 4D Includes examples of implementations of machine learning models.

[0087] Database 410 stores data transmitted to, received from, and / or updated by perception system 402, planning system 404, positioning system 406, and / or control system 408. In some examples, database 410 includes a storage component (e.g., a storage component) for storing data and / or software related to operations and using at least one system of autonomous vehicle software 400. Figure 3 In some embodiments, database 410 stores data associated with a 2D and / or 3D map of at least one area. In some examples, database 410 stores data associated with a 2D and / or 3D map of a portion of a city, portions of multiple cities, multiple cities, counties, states, and / or countries (State) (e.g., a country), etc. In such an example, a vehicle (e.g., a vehicle that is the same or similar to vehicle 102 and / or vehicle 200) can be driven along one or more drivable areas (e.g., single-lane roads, multi-lane roads, highways, remote roads, and / or off-road roads, etc.) and cause at least one LiDAR sensor (e.g., a LiDAR sensor that is the same or similar to LiDAR sensor 202b) to generate data associated with an image representing an object included in the field of view of the at least one LiDAR sensor.

[0088] In some embodiments, database 410 can be implemented across multiple devices. In some examples, database 410 includes a vehicle (e.g., a vehicle that is the same or similar to vehicle 102 and / or vehicle 200), an autonomous vehicle system (e.g., an autonomous vehicle system that is the same or similar to remote AV system 114), a fleet management system (e.g., a vehicle that is the same or similar to remote AV system 114), and a fleet management system (e.g., a vehicle that is the same or similar to remote AV system 114). Figure 1The same or similar queue management system as the queue management system 116 of FIG. 1 and / or the V2I system (e.g., Figure 1 The V2I system 118 is the same as or similar to the V2I system 118).

[0089] Reference now Figure 4B , a diagram illustrating an implementation of a machine learning model. More specifically, a diagram illustrating an implementation of a convolutional neural network (CNN) 420. For purposes of illustration, the following description of CNN 420 will be with respect to implementing CNN 420 by perception system 402. However, it will be understood that in some examples, CNN 420 (e.g., one or more components of CNN 420) is implemented by other systems (such as planning system 404, positioning system 406, and / or control system 408, etc.) other than or in addition to perception system 402. Although CNN 420 includes certain features as described herein, these features are provided for purposes of illustration and are not intended to limit the present disclosure.

[0090] CNN 420 includes a plurality of convolutional layers (convolutional layers) including a first convolutional layer 422, a second convolutional layer 424, and a convolutional layer 426. In some embodiments, CNN 420 includes a subsampling layer 428 (sometimes referred to as a pooling layer). In some embodiments, subsampling layer 428 and / or other subsampling layers have a dimension that is smaller than the dimension of the upstream system (i.e., the number of nodes). With the subsampling layer 428 having a dimension that is smaller than the dimension of the upstream layer, CNN 420 merges the amount of data associated with the initial input and / or output of the upstream layer, thereby reducing the amount of computation required for CNN 420 to perform downstream convolution operations. Additionally or alternatively, with the subsampling layer 428 being associated with (e.g., configured to perform) at least one subsampling function (as described below with respect to Figure 4C and Figure 4D As described above, CNN 420 incorporates the amount of data associated with the initial input.

[0091] The perception system 402 performs the convolution operation based on the perception system 402 providing respective inputs and / or outputs associated with each of the first convolution layer 422, the second convolution layer 424, and the convolution layer 426 to generate respective outputs. In some examples, the perception system 402 implements the CNN 420 based on the perception system 402 providing data as input to the first convolution layer 422, the second convolution layer 424, and the convolution layer 426. In such examples, the perception system 402 provides data as input to the first convolution layer 422, the second convolution layer 424, and the convolution layer 426 based on the perception system 402 receiving data from one or more different systems (e.g., one or more systems of a vehicle that is the same or similar to the vehicle 102, a remote AV system that is the same or similar to the remote AV system 114, a queue management system that is the same or similar to the queue management system 116, and / or a V2I system that is the same or similar to the V2I system 118, etc.). The following is about Figure 4C Includes a detailed description of the convolution operation.

[0092] In some embodiments, the perception system 402 provides data associated with the input (referred to as the initial input) to the first convolutional layer 422, and the perception system 402 generates data associated with the output using the first convolutional layer 422. In some embodiments, the perception system 402 provides the output generated by the convolutional layer as input to a different convolutional layer. For example, the perception system 402 provides the output of the first convolutional layer 422 as input to the subsampling layer 428, the second convolutional layer 424, and / or the convolutional layer 426. In such an example, the first convolutional layer 422 is referred to as an upstream layer, and the subsampling layer 428, the second convolutional layer 424, and / or the convolutional layer 426 are referred to as downstream layers. Similarly, in some embodiments, the perception system 402 provides the output of the subsampling layer 428 to the second convolutional layer 424 and / or the convolutional layer 426, and in this example, the subsampling layer 428 will be referred to as the upstream layer, and the second convolutional layer 424 and / or the convolutional layer 426 will be referred to as the downstream layer.

[0093] In some embodiments, before the perception system 402 provides the input to the CNN 420, the perception system 402 processes the data associated with the input provided to the CNN 420. For example, the perception system 402 processes the data associated with the input provided to the CNN 420 based on the perception system 402 normalizing the sensor data (e.g., image data, LiDAR data, and / or radar data, etc.).

[0094] In some embodiments, CNN 420 generates an output based on perception system 402 performing convolution operations associated with each convolution layer. In some examples, CNN 420 generates an output based on perception system 402 performing convolution operations associated with each convolution layer and the initial input. In some embodiments, perception system 402 generates an output and provides the output to fully connected layer 430. In some examples, perception system 402 provides the output of convolution layer 426 to fully connected layer 430, wherein fully connected layer 430 includes data associated with multiple feature values ​​referred to as F1, F2, ..., FN. In this example, the output of convolution layer 426 includes data associated with multiple output feature values ​​representing predictions.

[0095] In some embodiments, perception system 402 identifies a prediction from the plurality of predictions based on perception system 402 identifying a feature value associated with a highest likelihood of being a correct prediction from the plurality of predictions. For example, where fully connected layer 430 includes feature values ​​F1, F2, ..., FN and F1 is the largest feature value, perception system 402 identifies the prediction associated with F1 as the correct prediction from the plurality of predictions. In some embodiments, perception system 402 trains CNN 420 to generate the predictions. In some examples, perception system 402 trains CNN 420 to generate the predictions based on perception system 402 providing training data associated with the predictions to CNN 420.

[0096] Reference now Figure 4C and Figure 4D , a diagram illustrating an example operation of CNN 440 utilizing perception system 402. In some embodiments, CNN 440 (e.g., one or more components of CNN 440) is coupled to CNN 420 (e.g., one or more components of CNN 420) (see Figure 4B ) are the same or similar.

[0097] At step 450, perception system 402 provides data associated with the image as input to CNN 440 (step 450). For example, as illustrated, perception system 402 provides data associated with the image to CNN 440, where the image is a grayscale image represented as values ​​stored in a two-dimensional (2D) array. In some embodiments, the data associated with the image may include data associated with a color image represented as values ​​stored in a three-dimensional (3D) array. Additionally or alternatively, the data associated with the image may include data associated with an infrared image and / or a radar image, etc.

[0098] At step 455, CNN 440 performs a first convolution function. For example, CNN 440 performs a first convolution function based on CNN 440 providing a value representing an image as an input to one or more neurons (not explicitly illustrated) included in first convolution layer 442. In this example, the value representing the image may correspond to a value of a region (sometimes referred to as a receptive field) representing the image. In some embodiments, each neuron is associated with a filter (not explicitly illustrated). The filter (sometimes referred to as a kernel) may be represented as an array of values ​​corresponding in size to the value provided as input to the neuron. In one example, the filter may be configured to identify edges (e.g., horizontal lines, vertical lines, and / or straight lines, etc.). In successive convolution layers, the filters associated with the neurons may be configured to continuously identify more complex patterns (e.g., arcs and / or objects, etc.).

[0099] In some embodiments, CNN 440 performs a first convolution function based on CNN 440 multiplying the values ​​of each neuron provided as input to one or more neurons included in the first convolution layer 442 by the values ​​of the filters corresponding to each neuron in the same or more neurons. For example, CNN 440 may multiply the values ​​of each neuron provided as input to one or more neurons included in the first convolution layer 442 by the values ​​of the filters corresponding to each neuron in the one or more neurons to generate a single value or an array of values ​​as output. In some embodiments, the collective output of the neurons of the first convolution layer 442 is referred to as a convolution output. In some embodiments, when each neuron has the same filter, the convolution output is referred to as a feature map.

[0100] In some embodiments, CNN 440 provides the output of each neuron of the first convolutional layer 442 to the neurons of the downstream layer. For clarity, the upstream layer may be a layer that transmits data to a different layer (referred to as the downstream layer). For example, CNN 440 may provide the output of each neuron of the first convolutional layer 442 to the corresponding neurons of the subsampling layer. In the example, CNN 440 provides the output of each neuron of the first convolutional layer 442 to the corresponding neurons of the first subsampling layer 444. In some embodiments, CNN 440 adds a bias value to the aggregate set of all values ​​provided to each neuron of the downstream layer. For example, CNN 440 adds a bias value to the aggregate set of all values ​​provided to each neuron of the first subsampling layer 444. In such an example, CNN 440 determines the final value to be provided to each neuron of the first subsampling layer 444 based on the aggregate set of all values ​​provided to each neuron and the activation function associated with each neuron of the first subsampling layer 444.

[0101] At step 460, CNN 440 performs a first subsampling function. For example, based on CNN 440 providing the values ​​output by first convolutional layer 442 to the corresponding neurons of first subsampling layer 444, CNN 440 may perform the first subsampling function. In some embodiments, CNN 440 performs the first subsampling function based on an aggregation function. In an example, CNN 440 performs the first subsampling function based on CNN 440 determining the maximum input (referred to as a maximum pooling function) among the values ​​provided to a given neuron. In another example, CNN 440 performs the first subsampling function based on CNN 440 determining the average input (referred to as an average pooling function) among the values ​​provided to a given neuron. In some embodiments, based on CNN 440 providing values ​​to the respective neurons of first subsampling layer 444, CNN 440 generates an output, which is sometimes referred to as a subsampled convolution output.

[0102] At step 465, CNN 440 performs a second convolution function. In some embodiments, CNN 440 performs the second convolution function in a manner similar to how CNN 440 performs the first convolution function described above. In some embodiments, CNN 440 performs the second convolution function based on CNN 440 providing the value output by first subsampling layer 444 as input to one or more neurons (not explicitly illustrated) included in second convolution layer 446. In some embodiments, as described above, each neuron of second convolution layer 446 is associated with a filter. As described above, the filter (one or more) associated with second convolution layer 446 can be configured to recognize more complex patterns than the filter associated with first convolution layer 442.

[0103] In some embodiments, the CNN 440 performs a second convolution function based on the CNN 440 multiplying the value of each neuron provided as input to the one or more neurons included in the second convolution layer 446 by the value of the filter corresponding to each neuron of the one or more neurons. For example, the CNN 440 may multiply the value of each neuron provided as input to the one or more neurons included in the second convolution layer 446 by the value of the filter corresponding to each neuron of the one or more neurons to generate a single value or a value array as an output.

[0104] In some embodiments, the CNN 440 provides the output of each neuron of the second convolutional layer 446 to the neurons of the downstream layer. For example, the CNN 440 may provide the output of each neuron of the first convolutional layer 442 to the corresponding neurons of the subsampling layer. In an example, the CNN 440 provides the output of each neuron of the first convolutional layer 442 to the corresponding neurons of the second subsampling layer 448. In some embodiments, the CNN 440 adds a bias value to the aggregate set of all values ​​provided to each neuron of the downstream layer. For example, the CNN 440 adds a bias value to the aggregate set of all values ​​provided to each neuron of the second subsampling layer 448. In such an example, the CNN 440 determines the final value provided to each neuron of the second subsampling layer 448 based on the aggregate set of all values ​​provided to each neuron and the activation function associated with each neuron of the second subsampling layer 448.

[0105] At step 470, CNN 440 performs a second subsampling function. For example, based on CNN 440 providing the values ​​output by second convolutional layer 446 to corresponding neurons of second subsampling layer 448, CNN 440 may perform a second subsampling function. In some embodiments, based on CNN 440 using an aggregation function, CNN 440 performs a second subsampling function. In an example, as described above, based on CNN 440 determining the maximum input or average input among the values ​​provided to a given neuron, CNN 440 performs a first subsampling function. In some embodiments, based on CNN 440 providing values ​​to respective neurons of second subsampling layer 448, CNN 440 generates an output.

[0106] At step 475, CNN 440 provides the output of each neuron of the second subsampling layer 448 to the fully connected layer 449. For example, CNN 440 provides the output of each neuron of the second subsampling layer 448 to the fully connected layer 449 so that the fully connected layer 449 generates an output. In some embodiments, the fully connected layer 449 is configured to generate an output associated with a prediction (sometimes referred to as a classification). The prediction may include an indication that the objects included in the image provided as input to CNN 440 include objects and / or sets of objects, etc. In some embodiments, the perception system 402 performs one or more operations and / or provides data associated with the prediction to the various systems described herein.

[0107] Example distributed computing architecture

[0108] Figure 55 is an example distributed computing architecture 500 for an autonomous robotic system according to an embodiment. The distributed computing architecture 500 is a heterogeneous or homogeneous system that can be used for machine learning (ML) related software components, such as neural networks (e.g., convolutional neural networks) or deep learning networks or "backbones" (e.g., ResNet, AlexNet, VGGNet, Inception) and / or prediction heads for various tasks, etc. In the example shown, the distributed computing architecture 500 includes N chiplets or MPSoCs 501-1 to 501-N interconnected by a cache coherent structure 502, where N is a positive integer greater than 1. The distributed computing architecture 500 receives one or more inputs 503 (e.g., sensor data from a camera, LiDAR, RADAR, V2X data, etc.) and provides one or more outputs 504 (e.g., control signals for controlling an autonomous robotic system).

[0109] In some embodiments, the distributed computing architecture 500 runs (e.g., completely and / or partially, etc.) one or more processes and / or threads for at least one of the systems 402, 404, 406, and 408 of the AV software 400. In some embodiments, the distributed computing architecture 500 runs (e.g., completely and / or partially, etc.) one or more processes and / or threads for another device or system or another group of devices and / or systems that are separate from or include the AV software 400. For example, the distributed computing architecture 500 can be used to run (e.g., completely and / or partially, etc.) one or more processes and / or threads of a remote AV system 114, a vehicle 200 (e.g., an autonomous system 202 of the vehicle 200) in addition to one or more systems of the AV software 400. In some embodiments, the process / thread can be pinned to one or more cores of one of the MPSoCs of any of the above systems that cooperate with each other. The distributed computing architecture 500 can also be used to run (e.g., completely and / or partially, etc.) a reference AV system 114. FIG. 4B to FIG. 4D One or more processes and / or threads of any task or computation described.

[0110] In an embodiment, the MPSoC 501-1 to 501-N includes multiple processor cores, optional functional units, memory blocks, timing sources (e.g., crystal oscillators, phase-locked loops) for generating clock signals to control the execution of SoC functions, peripherals (e.g., counters, power-on reset generators), and communication protocols (e.g., Ethernet, USART, SPI, I2C, etc.). 2 C) external interfaces and interconnects such as network-on-chip (NoC) interconnects for communication and sharing data between processor cores, optional functional units, and other components of the MPSoC. Processor cores may include, but are not limited to: M cores Central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), FPGA, ASIC, and chiplets including one or more of the foregoing hardware, etc. In an embodiment, M-core CPUs can be clustered in a single package. For example, multiple quad-core or deca-core CPUs can be combined in an MPSoC to achieve the desired core count for the desired application.

[0111] In the embodiments, as referenced Figures 7 to 12 More fully described, one or more of the MPSoCs 501-1 through 501-N include on-chip cache memory that can be shared with one or more processor cores on that MPSoC using an interconnect (e.g., CCIX, CXL, silicon interposer, NoC), or with processor cores on another MPSoC via a cache coherent fabric 502. In another embodiment, the distributed computing architecture 500 includes one or more separate memory chips / controllers shared by two or more MPSoCs via a cache coherent fabric 502.

[0112] An example of a cache coherent structure 502 is referenced Figure 6 The Cache Coherent Interconnect for Accelerators (CCIX) described in the present invention is a chip-to-chip interconnect that enables two or more devices to share data in a cache-coherent manner. For AV computing tasks, accelerators (e.g., GPUs, FPGAs, smart network interface cards (smart NICs), etc.) can complete the required functionality faster and with lower power consumption than a single central processing unit (CPU). CCIX allows for the optimization and simplification of heterogeneous systems while increasing bandwidth and reducing latency in systems built from devices processed by processors with different instruction set architectures (ISAs) or application-specific accelerators.

[0113] Example Cache Coherent Structure

[0114] refer to Figure 6 , CCIX is based on PCI Architecturally extended layer-based architecture: CCIX includes a protocol layer 601 , a link layer 602 , a CCIX transaction layer 603 , a PCIe transaction layer 604 , a PCIe data link layer 605 , and a CCIX / PCIe physical layer 606 .

[0115] Protocol layer 601 is responsible for the coherence protocol, including memory read and write flows. Layer 601 targets An on-chip coherency protocol such as AMBA CHI provides the mapping. The cache states defined in layer 601 allow the hardware to determine the state of the memory (eg, determine whether the data is unique and clean, or whether the data is shared and dirty).

[0116] Link layer 602 is responsible for formatting traffic (eg, CCIX traffic) for targeted transmission. Additionally, layer 602 manages port aggregation, allowing multiple ports to be aggregated together to increase bandwidth.

[0117] The transaction layers 603, 604 are responsible for handling their respective packets. The PCIe protocol allows for the implementation of virtual channels that allow different data streams to travel across a single PCIe link. By splitting the first traffic (e.g., CCIX traffic) into one virtual channel and the second traffic (e.g., PCIe traffic) into a second virtual channel, both the first traffic and the second traffic can share the same link.

[0118] The data link layer 605 performs all normal functions of the data link layer, including but not limited to: cyclic redundancy code (CRC) error checking, packet acknowledgment and timeout checking, and credit initialization and exchange.

[0119] Physical layer 606 is a PCIe physical layer that extends the physical layer to support PCIe link rates and provides backward support for various PCIe rates plus extended speeds.

[0120] In other embodiments, other cache coherent structures may be used in the distributed computing architecture 500, such as Compute Express Link (CXL), which is an open standard for high-speed central processing unit (CPU)-to-device and CPU-to-memory connections.

[0121] Figure 7 The processing according to the embodiment is illustrated Figure 55. The pinning (also referred to as "binding") of a specific processor core on a specific MPSoC in the distributed computing architecture 500 shown in FIG. 5. In the example shown, process 1 is pinned to core 7 of MPSoC 501-3 (MPSoC 3), and process 2 is pinned to core 6 of MPSoC 501-2 (MPSoC 2). Data generated by process 1 can be stored in an on-chip cache memory 701-1 (e.g., shared memory) of MPSoC 501-2 and retrieved by process 2 for use in process 2 to perform tasks. For example, in an AV computing application, process 1 can be detecting objects in 2D (e.g., video data) and / or 3D sensor data (e.g., LiDAR point cloud), and process 2 can be obtaining object detection data output by process 1 from cache memory 701-1 and using the object detection data to plan a route for the AV or perform motion control tasks (e.g., DBW).

[0122] In an embodiment, the distributed computing architecture 500 uses one or more processor cores from multiple MPSoCs to implement one or more parts of the deep learning backbone. For example, at least one core of the first MPSoC can implement the data embedding / encoding function of the neural network, at least one processor core of the second MPSoC can implement the feature extraction layer of the neural network, at least one processor core of the third MPSoC can implement the zoom-in / zoom-out of the feature vector, at least one processor core of the fourth MPSoC can implement the pooling layer, and at least one processor core of the fifth MPSoC can implement a fully connected network or a prediction head, etc. An example operation implemented by at least one processor core can be, for example, a multiply-accumulate (MAC) operation often used in machine learning algorithms. In addition to dividing deep learning tasks between multiple MPSoCs in the distributed computing architecture 500, deep learning tasks can also be divided between processor cores on the same MPSoC.

[0123] The shared memory access operation may be implemented by one or more memory controllers integrated on one or more MPSoCs, or one or more separate memory controllers may be included in the distributed computing architecture 500 as separate chiplets. The access operation from the buffer of the MPSoC to the shared memory location or separate memory included in the MPSoC / from the shared memory location or separate memory included in the MPSoC to the buffer of the MPSoC may be implemented using a cache coherent structure 502, an on-chip NoC, and a multithreaded programming model (e.g., Open Multiprocessing (OpenMP), Open Asymmetric Multiprocessing (OpenAMP), Message Passing Interface (MPI)) or a multiprocessing multi-device programming model (e.g., Open Enhanced and Alternative Communications (OpenAAC)). In an embodiment, the distributed computing architecture 500 uses a partitioned global address space (PGAS) programming model that extends across cores and clusters of the MPSoC while retaining a similar shared memory programming model. In an embodiment, the Compute Unified Device Architecture (CUDA) is used to facilitate computing on the GPU in the distributed computing architecture 500.

[0124] Figure 8 Example according to the embodiment Figure 5 . In the example shown, the cache memory 701-1 in MPSoC 2 includes a logical address space 801 (local memory space) for process 2, and the cache memory 701-2 in MPSoC 3 includes a logical address space 802 (local memory space) for process 1. A portion 803 of the logical address space 801 is transparently mirrored to a portion 804 of the logical address space 802 as needed, thereby obtaining a shared memory space for process 1 and process 2 to store and retrieve data required for the respective tasks of process 1 and process 2. In an embodiment, the shared memory is implemented using a non-uniform memory access (NUMA) architecture and a multi-threaded programming model (e.g., OpenMP threads, POSIX threads, Intel thread building blocks, Cilk plus threads).

[0125] Fig. 9 Example according to the embodiment Figure 5900 . With "leakage", if a data consumer (e.g., data consumer 903) needs to "catch up" with real time, one or more processes running on the distributed computing architecture 500 discard data. In an embodiment, a ring buffer 902 (e.g., a lock-free ring buffer) coupled to a data producer 901 on the MPSoC is used to discard data output from its local memory. The ring buffer 902 (also called a circular buffer) is a queue with a fixed maximum allowed size that continuously reuses the allocated memory space to store data.

[0126] Fig. 9 Also shown is a magnified view of the ring buffer 902, wherein each packet stored in the buffer includes a header 902a, a timestamp 902b, and a sentinel value 902d (e.g., a value whose presence is used to indicate the end of a packet in the buffer). The use of a "lockless" or "lock-free" ring buffer means that a slow or stopped process does not prevent other processes from accessing data from the ring buffer 902.

[0127] Fig. 10A The process of skipping buffer 1001 via cache coherent structure according to an embodiment is illustrated. In an embodiment, the shared memory can be optimized to allow the data consumer 903 to skip the buffer 1001 from its own MPSoC via the cache coherent structure 502 and read the final timestamp, real-time data and sentinel value from the buffer in a lock-free manner.

[0128] Fig. 10B The process of selecting useful data from within the buffer 1001 according to an embodiment is illustrated. In an embodiment, the shared memory can be optimized by allowing the data producer to selectively transmit a portion of the "useful" data 1002 from the buffer content instead of acquiring the entire buffer content, where the "useful" data 1002 is any data in the buffer 1001 that is required by the data consumer 903 to perform any task that uses the data, such as a task that is performed in real time or non-real time.

[0129] Fig.11 1 is a flow chart of a process 1100 for sharing memory between processes of different cores of different MPSoCs fixed to the distributed computing architecture 500 using middleware according to an embodiment. The process 1100 may be, for example, referred to as Figure 1 to Figure 1 0 is implemented by the distributed computing architecture 500 described in FIG.

[0130] Process 1100 includes: executing a first process / thread on input data using a first core of a first MPSoC (1101); storing first data generated from the first process / thread in a shared memory using a cache coherent structure (1102); obtaining / receiving first data from the shared memory using a second core of a second MPSoC (1103); executing a second process / thread on the first data (1104); and optionally storing second data generated by the second process / thread in a shared memory (1105).

[0131] Example distribution of AV perception tasks to MPSoC cores

[0132] Fig.12 is a block diagram of an example of distributing AV computation tasks to portions of a deep learning network 1200 for a perception pipeline for an AV, according to one or more embodiments. The deep learning network 1200 is configured to accept a modified point cloud 1201 (e.g., a LiDAR point cloud) as input and estimate / predict oriented 3D bounding boxes 1205 for various classes (including, but not limited to, cars, pedestrians, and cyclists). The deep learning network 1200 includes three main stages: 1) a pillar feature network 1202 (feature encoder), which converts the point cloud into a sparse pseudo image (e.g., a 2D image embedding with more than 3 RGB channels); 2) a 2D convolutional neural network (CNN) backbone 1203 for processing the pseudo image into a high-level representation; and 3) a detection head 1204, which detects and regresses 3D boxes (predictions) 1205.

[0133] In an embodiment, the column feature network 1202 converts a point cloud into a pseudo image (e.g., a 2D image embedding (tensor) with more than three channels). Points in the point cloud have position coordinates x, y, z and reflectance r. As a first step, the point cloud is discretized into a uniformly spaced grid in the xy plane, creating a set of columns P. The points in each column are then enhanced with x_c, y_c, z_c, x_p, and y_p, where the c subscript represents the arithmetic mean distance to all points in the column P and the p subscript represents the offset relative to the x, y center of the column. In this example, the enhanced points have 9 dimensions.

[0134] In an embodiment, the enhanced points are further enhanced (fused) using semantic segmentation data output by an image semantic network (ISN) (not shown). The ISN takes an image formed by, for example, a video camera as input, and predicts a category for each pixel in the image, and outputs semantic segmentation data (e.g., a semantic segmentation score) for each pixel in the image. In an embodiment, the ISN is trained using an image dataset including images, wherein each image is annotated with a 2D bounding box and a segmentation label for a category in the image dataset. The example semantic segmentation score is a probability value indicating the probability that the category of the pixel is correctly predicted. For example, each point can be further enhanced by being summarized into semantic segmentation scores for categories such as cars, bicycles, pedestrians, and backgrounds, thereby obtaining enhanced points with 13 dimensions.

[0135] Next, a simplified version of the PointNet classification network is applied to each augmented point as described in Qi, Charles R., et al. “PointNet: Deep Learning on Point Sets for 3D Classification and Segmentation” (ArXiv.org, April 10, 2017, https: / / ArXiv.org / abs / 1612.00593).

[0136] For each point, a linear layer is applied followed by Batch-Norm and ReLU to generate a tensor of size (C, P, N). The linear layer is followed by a max operation on the channels to create an output tensor of size (C, P). Once encoded, the features are scattered back to the original column positions to create a pseudo image of size (C, H, W), where H and W indicate the height and width, respectively.

[0137] Next, the pseudo image is input into the deep learning backbone 1203. In an embodiment, the backbone 1203 has two sub-networks: a top-down network that produces features with increasingly smaller spatial resolutions; and a second network that upsamples and concatenates the top-down features. The top-down backbone can be characterized by a series of blocks Block(S, L, F). Each block operates with a stride S (measured relative to the pseudo image of the original input). In the example shown, the block has L3×3 2D convolutional layers with F output channels, each followed by Batch-Norm and ReLU. The first convolution within a layer has a stride of To ensure that the block receives stride S in The input blob is then operated on with stride S. All subsequent convolutions in the block have stride 1.

[0138] The final features from each top-down block are combined by upsampling and concatenation as follows. First, a transposed 2D convolution with F final features is used from the initial stride S in To the final stride S out (Both of which are also measured for the original pseudo image) Upsample the features (Sin, Sout, F). Next, apply Batch-Norm and ReLU to the upsampled features. The final output feature is the concatenation of all features from different step amplitudes.

[0139] In an embodiment, the detection (prediction) head 1204 is implemented using a single shot detector setup for 3D object detection. Similar to SSD, the previous box is matched to the ground truth using 2D intersection over union (IoU).

[0140] like Fig.12 As shown in , the tasks performed by the above-mentioned deep learning network 1200 can each be fixed to at least one processor core of at least one MPSoC of the distributed computing architecture 500. For example, MPSoC 1206 can be responsible for the tasks of the column feature network 1202. Fig.12 The distribution of tasks shown in is only one example distribution. In practice, processing / threads are distributed among processor cores / MPSoCs in a manner that facilitates rapid real-time processing of large amounts of data while complying with any performance and / or safety requirements for a particular application.

[0141] For example, processing / threads running in parallel may be distributed to different cores within a single MPSoC or between two or more MPSoCs in the distributed computing architecture 500. In another example, processing / threads that share data may be distributed to processor cores on the same MPSoC and using shared memory on the MPSoC, another MPSoC, and / or off-chip memory via the cache coherent structure 502.

[0142] In another example, two or more MPSoCs can be assigned to a “cluster” to perform specific AV computing tasks. Fig.12 In FIG. 1 , Cluster A includes MPSoC 1207 and MPSoC 1208 responsible for handling the tasks of the backbone 1203. In an embodiment, the tasks of the detection head 1204 may be handled by Cluster A or another MPSoC or MPSoC cluster.

[0143] In an embodiment, one or more clusters may be used to handle various tasks of the AV software 400, including but not limited to, Figure 4A404, the perception system 402, and the control system 408. For example, a first MPSoC cluster may implement one or more processes / threads for the positioning system 406, a second MPSoC cluster may implement one or more processes / threads for the planning system 404, a third MPSoC cluster may implement one or more processes / threads for the perception system 402 (e.g., object detection, classification, and positioning), and a fourth MPSoC cluster may implement control system 408 tasks (e.g., implementing model predictive control (MPC) tasks, DBW tasks).

[0144] Within a particular MPSoC cluster, tasks can be further distributed. For example, a cluster implementing a perception pipeline task may include a first MPSoC for object detection and classification, a second MPSoC for object localization, a third MPSoC for determining 2D or 3D bounding boxes, a fourth MPSoC for ground plane estimation, a fifth MPSoC for fusion 2D and 3D processing pipelines, and so on.

[0145] Within each MPSoC, the processor core can be used to implement repetitive mathematical operations such as MAC operations, vector and matrix operations, scaling operations, convolutions, mask operations, coordinate transformations, time / frequency transformations, control laws, state estimators (e.g., Kalman filter prediction / correction steps) and other predictors, state machines, communication protocols, protection operations, safety operations, security operations, health monitoring, log generation, remote operation tasks, etc.

[0146] In an embodiment, machine learning tasks may be distributed to multiple MPSoCs, each of which includes multiple NPUs. The NPUs may be used for training, inference, or both training and inference. In an embodiment, the NPUs perform both training and inference independently.

[0147] By replicating as many NPUs as required in each MPSoC, open-scale scalability can be achieved in the distributed computing architecture 500. The example NPU architecture includes the following components: CPU, separate cache memories for instructions and data (e.g., L1 cache), interrupt controller, timer, communication interface for debugging purposes (e.g., UART), embedded memory (e.g., RAM), network interface (e.g., NoC interface for packet switching), router (e.g., XY router to allow deterministic routing), and local bus (e.g., OpenCores wishbone bus).

[0148] In an embodiment, the NPU architecture includes: direct memory access (DMA) capability, which includes a read engine with a read buffer and a write engine with a write buffer; and a controller configured to use DMA to perform hardware pre-processing of data in the read buffer and post-processing of data in the write buffer in blocks or other data units (e.g., data stripes) of data to, for example, process tensors in a neural network (e.g., images with an arbitrary number of channels).

[0149] To implement a distributed memory structure and maintain the scalability of the MPSoC, and to allow global decisions to be made in a distributed manner without using a global shared memory, the NPUs may operate asynchronously and use, for example, an MPI application programming interface (API) for message passing communication.

[0150] In an embodiment, each NPU runs an open-scale real-time operating system (RTOS) that performs basic RTOS services (e.g., function calls), communication services, and uses drivers and libraries. In an embodiment, the RTOS uses a thread priority-based scheduler (e.g., a round-robin scheduler) to provide multi-threaded preemptive execution, which is executed periodically according to, for example, fixed time slots. In an embodiment, the RTOS kernel may include an MPI API, an exception manager, a memory manager, a task manager, a scheduler, an interrupt manager (e.g., for managing hardware interrupts), a runtime task loader (e.g., for migrating running tasks between NPUs to achieve dynamic load balancing), a routing table, etc. Application tasks can communicate with the RTOS via the MPI API. Memory management can be implemented using paging, dynamic memory allocation / deallocation, or any other suitable memory management process.

[0151] In an embodiment, the NPU accelerates training tasks by, for example, creating a new machine learning model, including but not limited to inputting a training dataset (e.g., a labeled dataset) and iterating on the dataset, adjusting model weights and biases to ensure an accurate model, correcting inaccurate predictions using backpropagation through network layers, and estimating corrections to weights in the layers until a desired accuracy is achieved.

[0152] In an embodiment, the NPU accelerates the inference operation of the completed model. For example, the NPU can input new sensor data (e.g., a new camera frame) and accelerate the processing of the new sensor data and generate results through the trained machine learning model.

[0153] In an embodiment, one or more MPSoC clusters may be used to provide redundancy for various critical AV tasks, thereby ensuring continued operation in the event of a system or subsystem failure.

[0154] In an embodiment, one or more MPSoC clusters are assigned to different sections or areas of the AV. For example, a first cluster may be assigned to sensors facing the right front, a second cluster may be assigned to sensors facing the left front, a third cluster may be assigned to sensors facing the right, a fourth cluster may be assigned to sensors facing the left, and a fifth cluster may be assigned to sensors facing the rear. In an embodiment, one or more clusters may be assigned to handle safe maneuvering tasks, process occupancy grids, process V2X communications, etc.

[0155] Fig.13 1 is a block diagram of a chip layout for a computing unit 1300 for an autonomous robotic system according to one or more embodiments. The computing unit 1300 can be implemented in, for example, an AV computing (e.g., AV computing 202f). The computing unit 1300 includes a sensor multiplexer (Mux) 1301, a main computing cluster 1302-1 to 1302-5, a failover computing cluster 1302-6, and an Ethernet switch 1302. The Ethernet switch 1302 includes a plurality of Ethernet transceivers for sending commands 1315 to a vehicle 1303, wherein the vehicle 1303 is configured as a vehicle 1303. Figure 2 One or more of the DBW system 202h, safety controller 202g, braking system 208, powertrain control system 204, and / or steering control system 206 shown in FIG. 13 may receive command 1315.

[0156] The first master computing cluster 1302-1 includes a SoC 1303-1, volatile memories 1305-1, 1305-2, a power management integrated circuit (PMIC) 1304-1, and a flash boot 1311-1. The second master computing cluster 1302-2 includes a SoC 1303-2, volatile memories 1306-1, 1306-2 (e.g., DRAM), a PMIC 1304-2, and a flash operating system (OS) 1312-2. The third master computing cluster 1302-3 includes a SoC 1303-3, volatile memories 1307-1, 1307-2, a PMIC 1304-3, and a flash OS memory 1312-1. The fourth master computing cluster 1302-4 includes a SoC 1303-5, volatile memories 1308-1, 1308-2, a PMIC 1304-5, and a flash boot memory 1311-2. The fifth primary computing cluster 1302-5 includes a SoC 1303-4, volatile memories 1309-1, 1309-2, a PMIC 1304-4, and a flash boot memory 1311-3. The failover computing cluster 1302-6 includes a SoC 1303-6, volatile memories 1310-1, 1310-2, a PMIC 1304-6, and a flash OS memory 1312-3.

[0157] Each of SoC 1303-1 to 1303-6 may be as shown in reference Figures 1 to 12 The MPSoC described in reference Figure 6 As described, SoCs 1303-1 to 1303-6 may share memory via a cache coherent structure.

[0158] In an embodiment, PMICs 1304-1 to 1304-6 monitor relevant signals on a bus (e.g., a PCIe bus) and communicate with a corresponding memory controller (e.g., a memory controller in a DRAM chip) to notify the memory controller of a power mode change, such as a change from a normal mode to a low power mode or a change from a low power mode to a normal mode, etc. In an embodiment, PMICs 1304-1 to 1304-6 also receive communication signals from their respective memory controllers for monitoring the bus and operate to prepare the memory for a lower power mode. When the memory chip is ready to enter a low power mode, the memory controller communicates with its respective slave PMIC to instruct the slave PMIC to start a lower power mode.

[0159] In an embodiment, the sensor mux 1301 receives and multiplexes sensor data (e.g., video data, LiDAR point cloud, RADAR data) from the sensor bus through the sensor interface 1313, which in some embodiments is a low voltage differential signal (LVDS) interface. In an embodiment, the sensor mux 1301 manipulates the video data channel (e.g., mobile industrial processor interface The failover computing cluster 1302-6 may provide a copy of the video data to the primary computing cluster 1302-1, such as when one or more primary computing clusters 1302-1 fail, etc. The failover computing cluster 1302-6 may provide a backup for the primary computing cluster to operate the AV using the video data during a failover 1314. In some such cases, the failover computing cluster 1302-6 may issue a command 1316 to the vehicle 1303.

[0160] Computing unit 1300 is an example of a high-performance computing unit such as AV computing for an autonomous robotic system, and other embodiments may include more or fewer clusters, and each cluster may have more or fewer SoCs, volatile memory chips, non-volatile memory chips, NPUs, GPUs, and Ethernet switches / transceivers.

[0161] In the previous description, aspects and embodiments of the present disclosure have been described with reference to many specific details, which may vary depending on implementation. Therefore, the specification and drawings should be regarded as illustrative, rather than restrictive. The only and exclusive indication of the scope of the invention, and the applicant's expectation that the content of the scope of the invention is the literal and equivalent scope of such claims issued from the present application in the specific form of the claims, including any subsequent amendments. Any definition of the terms used to be included in such claims clearly set forth herein should be based on the meaning of such terms as used in the claims. In addition, when the term "also includes" is used in the previous specification or the appended claims, the phrase may be followed by additional steps or entities, or sub-steps / sub-entities of the previously described steps or entities.

[0162] Fig.14 is a block diagram illustrating an example of a computing system for an autonomous robotic system (e.g., autonomous vehicle computing). In the illustrated example, computing system 1400 is implemented using a multi-SoC architecture and includes multiple SoCs. Computing system 1400 can receive sensor data associated with one or more sensors and use the sensor data to implement one or more functions (e.g., implement lane changes, implement cruise control, implement voice navigation, etc.). Computing system 1400 can receive sensor data from sensors and provide the sensor data to a computing unit and / or a failover unit via a splitter. Fig.14 In the example of , computing system 1400 includes one or more connections (e.g., Ethernet connections) to receive additional sensor data (e.g., lidar data) associated with one or more sensors via an Ethernet physical layer (e.g., Auto Eth PHY).

[0163] The computing system 1400 may include one or more SoCs. Fig.14 In the example of , computing system 1400 includes seven SoCs. Computing system 1400 may include a first subset of SoCs in the computing unit and a second subset of SoCs in the failover unit. Fig.14 In the example of FIG. 14 , computing system 1400 includes six SoCs in the computing unit and one SoC in the failover unit.

[0164] Fig.14Not shown in the figure, computing system 1400 may include an isolated execution environment manager. As described herein, the isolated execution environment manager may partition all or part of one or more SoCs, and may assign functions to specific partitions of one or more SoCs for implementation. For example, the isolated execution environment manager may partition the SoC into a first partition corresponding to a first isolated execution environment instance for implementing a first function and a second partition corresponding to a second isolated execution environment instance and a third isolated execution environment instance for implementing a second function.

[0165] Computing system 1400 may include one or more power management integrated circuits (PMICs) to manage power supplied to one or more SoCs. For example, computing system 1400 may include a primary PMIC and / or a secondary PMIC for all or a portion of one or more SoCs.

[0166] All or part of the SoC may include memory. The SoC may include volatile and / or non-volatile storage. For example, the SoC may include removable memory, RAM (e.g., low power double data rate synchronous dynamic RAM), flash memory, etc. The memory may store boot instructions (e.g., boot code, boot loader, boot driver, boot code, etc.), operating system, etc.

[0167] Boot process SoC node configuration

[0168] The multi-SoC architecture as described herein can be used to implement various functions (e.g., implement lane change, implement cruise control, implement voice navigation, etc.). To implement various functions, the multi-SoC architecture can include multiple SoCs, each of which is booted and assigned specific functions. Multiple SoCs can be booted based on a boot process.

[0169] In some systems, the boot process may include a processing unit and cache initialization phase, a memory training and input / output initialization phase, and / or a storage and network initialization phase. In such a system, the SoC may be booted and computing resources associated with the SoC (e.g., initialized during the boot process for the SoC) may be identified. Thus, the boot process may be used to initialize and implement the SoC.

[0170] However, a boot process that does not include the interconnect configuration phase 1506 (e.g., CCIX configuration phase) may not provide high resilience, high consistency operation for real-time safety-critical applications. Instead, such a boot process may result in a SoC that must be adapted to each specific environment or requires the implementation of a compute node after the boot process of the SoC.

[0171] Embodiments of the present disclosure provide an interconnect configuration phase during the boot process to Figure 5 The computing nodes are defined on a multi-SoC architecture such as the architecture 500 to address these issues. During the interconnect configuration phase 1506, the SoC can identify logically interconnected individual SoCs on the multi-SoC architecture to form a set of nodes, where each SoC can be used as an independent computing device. The SoCs associated with different nodes can operate independently so that the failure of the SoC in any given node will not cause the failure of other nodes. The SoCs associated with individual nodes can operate together so that the computing resources available at the node can be expanded according to the number of SoCs assigned to the node.

[0172] Fig.15 1500. In the illustrated example, the boot process 1500 includes multiple stages (e.g., levels, layers, etc.). For example, the boot process 1500 includes a processing unit and cache initialization stage 1502, a memory training and input / output initialization stage 1504, an interconnect configuration stage 1506, and a storage and network initialization stage 1508. The stages can be implemented iteratively. For example, the processing unit and cache initialization stage 1502 can be implemented first, the memory training and input / output initialization stage 1504 can be implemented second, the interconnect configuration stage 1506 can be implemented again, and the storage and network initialization stage 1508 can be implemented last. In some cases, the SoC can use the boot process 1500 to boot and implement one or more isolated execution environment instances. For example, the SoC can initialize an isolated execution environment manager during the boot process. The isolated execution environment manager can use the SoC to instantiate an isolated execution environment.

[0173] The processing unit and cache initialization phase 1502 may be a pre-boot phase. During the processing unit and cache initialization phase 1502, the SoC may access pre-boot instructions (e.g., a boot loader, a pre-boot image, a BIOS, etc.). For example, the pre-boot instructions may include a boot code stored in a memory (e.g., a read-only memory (ROM)) of the SoC. Based on the pre-boot instructions, the SoC may initialize a processing unit (e.g., a CPU), a memory (e.g., a cache), etc. of the SoC. In addition, the SoC may initialize a boot process based on the pre-boot instructions (e.g., the boot code).

[0174] During the memory training and input / output initialization phase 1504, the SoC may train the memory of the SoC and / or initialize one or more input / output devices of the SoC. In some cases, the SoC may initialize the input / output functionality of the SoC.

[0175] During the interconnect configuration phase 1506, the SoC may initialize the interconnect to enable sharing of data in a cache-consistent manner. Prior to or during the interconnect configuration phase 1506 (e.g., at the beginning of the interconnect configuration phase 1506), the SoC may enter a node configuration phase. During the node configuration phase, the SoC may identify a computing node associated with the SoC (e.g., a computing node with which the SoC will share computing resources). The SoC may identify a computing node based on a node configuration indicating the computing node and one or more SoCs associated with the computing node. For example, the SoC may identify (e.g., access, obtain, etc.) and / or determine a node configuration associated with the SoC based on a node configuration indicating the SoC. In some cases, the SoC may identify a node configuration stored in a configuration table.

[0176] As part of the node configuration phase, the SoC may use the node configuration to identify one or more additional SoCs associated with the compute node. Based on the one or more additional SoCs, the SoC may identify computing resources associated with the additional SoC (e.g., initialized computing resources of the additional SoC). For example, the computing resources may include one or more processing units, memory, one or more input / output devices, etc. Based on identifying the computing resources, the SoC may enter a multi-processing mode in which the SoC shares its computing resources with other SoCs and uses computing resources of other SoCs (e.g., shared computing resources of additional SoCs associated with the same compute node).

[0177] During the storage and network initialization phase 1508, the SoC may initialize an operating environment for the SoC, such as, but not limited to, an operating system, a hypervisor, etc. In some cases, the boot process 1500 may include one or more phases for a kernel implemented by the SoC.

[0178] Fig.16 is a block diagram illustrating an example logical grouping of SoC 1600 into different nodes within a multi-SoC architecture during the boot process. Specifically, Fig.16 n SoCs 1602, 1612, ..., 16n2 are depicted, where n may be any number greater than zero. SoCs 1602, 1612, ..., 16n2 may be related to Figure 5 The MPSoCs described above are similar to those MPSoCs. Fig.1616n2 can be linked to various other inputs and outputs, such as sensor interfaces, network interfaces, etc. In addition, as described herein, SoCs 1602, 1612, ..., 16n2 can be linked via interconnects such as UCIe interconnects. In some cases, SoCs 1602, 1612, ..., 16n2 are interconnected via a mesh topology so that each SoC can communicate with other SoCs independently. In some cases, other topologies can be used.

[0179] Fig.16 SoC 1602, 1612, ..., 16n2 may be specifically configured for real-time, safety-critical applications. For example, all or a portion of SoC 1602, 1612, ..., 16n2 may implement a deterministic processing architecture. In some instances, all or a portion of SoC 1602, 1612, ..., 16n2 may include internal redundant hardware to further provide resilience. For example, all or a portion of SoC 1602, 1612, ..., 16n2 may include a safety coprocessor that is configured to monitor the health of all or a portion of SoC 1602, 1612, ..., 16n2 and report failures of the SoC to other SoCs so that (for example) another SoC may take over the operation of the failed SoC.

[0180] like Fig.16 As shown in , some or all of SoCs 1602, 1612, ..., 16n2 may be logically arranged as node 1601. Node 1601 may operate as a single computing device. For example, node 1601 may share a common memory space, execute a single operating system, etc. Different nodes may operate as different computing devices, and therefore maintain different memory spaces, execute different computing devices, etc. Therefore, by grouping SoCs 1602, 1612, ..., 16n2 together into node 1601, the computing resources of SoCs 1602, 1612, ..., 16n2 may be shared within the node 1601. For example, Fig.16 Node 1601 in includes SoCs 1602, 1612, ..., 16n2, and thus represents a logical computing device having a processor, memory, etc. available to SoCs 1602, 1612, ..., 16n2.

[0181] Each of the SoCs 1602, 1612, ..., 16n2 may implement a boot process. During the first phase of the boot process, each of the SoCs 1602, 1612, ..., 16n2 may implement one or more processing units and cache initialization tasks. Fig.16In the example of , SoC 1602 implements a processing unit and cache initialization phase 1604, SoC 1612 implements a processing unit and cache initialization phase 1614, and SoC 16n2 implements a processing unit and cache initialization phase 16n4. Thus, all or a portion of SoCs 1602, 1612, ..., 16n2 may implement a processing unit and cache initialization phase and initialize one or more processing units and caches. During the processing unit and cache initialization phase 1604, separate SoCs 1602, 1612, ..., 16n2 may access separate and different memories including a boot loader to initialize separate and different processing units of the respective SoCs. As described herein, the memory may be implemented as a read-only memory (ROM) and / or a flash memory.

[0182] During the second stage of the boot process, SoCs 1602, 1612, ..., 16n2 may each perform one or more memory training and input / output initialization tasks. Fig.16 In the example of , SoC 1602 implements a memory training and input / output initialization phase 1606, SoC 1612 implements a memory training and input / output initialization phase 1616, and SoC 16n2 implements a memory training and input / output initialization phase 16n6. Thus, all or a portion of SoCs 1602, 1612, ..., 16n2 may implement different memory training and input / output initialization phases and train the memory of the SoC and initialize one or more input / output devices. During the memory training and input / output initialization phase 1606, separate SoCs 1602, 1612, ..., 16n2 may access separate and different memories including a boot loader to initialize separate and different memories and input / outputs of the respective SoCs. As described herein, the memory may be implemented as a read-only memory (ROM) and / or a flash memory.

[0183] During the third stage of the boot process, SoCs 1602, 1612, ..., 16n2 may each perform one or more node configuration tasks. Fig.16 In the example of , SoC 1602 implements node configuration stage 1608, SoC 1612 implements node configuration stage 1618, and SoC 16n2 implements node configuration stage 16n8.

[0184] During the node configuration phase, SoCs 1602, 1612, ..., 16n2 can identify nodes associated with respective SoCs (e.g., nodes with which the respective SoCs will share their computing resources), identify the shared computing resources of the nodes (e.g., computing resources from the respective SoCs that will be shared with other SoCs of the node, such as but not limited to memory, processors, input / output, etc.), and map the shared computing resources of the nodes for use by other SoCs of the node (e.g., other SoCs identified as belonging to the same node).

[0185] Fig.17 is a block diagram illustrating an example of a node 1701 of a multi-SoC architecture 1700. In the illustrated example, the multi-SoC architecture 1700 includes a first SoC 1702, a second SoC 1712, ..., and an nth SoC 17n2 that have been configured as the node 1701. It will be understood that the multi-SoC architecture 1700 may include any number of SoCs.

[0186] The first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2 may be related to Figure 5 The first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2 may each include one or more computing resources. For example, the first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2 may each include one or more processing units (e.g., microprocessors), memories (e.g., volatile memories or non-volatile memories), and / or input / output devices. The first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2 may include memories (e.g., physical memories), which may correspond to any combination of volatile computer-readable storage media or non-volatile computer-readable storage media. The memories may store information including various programs, program data, and other modules. The first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2 may also include one or more physical processing units (e.g., CPUs), one or more disks (e.g., hard disks, removable disks, or other volatile storage media or non-volatile storage media), one or more input / output devices, and / or one or more network cards (e.g., wired network cards, wireless network cards, etc.).

[0187] like Fig.17As shown in FIG, a first SoC 1702 includes a memory 1704 and is associated with (e.g., in communication with) an input / output device 1706, a second SoC 1712 includes a memory 1714 and is associated with (e.g., in communication with) an input / output device 1716, and an nth SoC 17n2 includes a memory 17n4 and is associated with (e.g., in communication with) an input / output device 17n6. It will be understood that all or a portion of the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 may include more, fewer, or different computing resources.

[0188] As described herein, each of the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 corresponds to the node 1701. The first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 may share physical computing resources based on the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 corresponding to the node 1701. For example, the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 may each share one or more input / output devices, one or more processing units, memory, etc., so that the processor of the SoC 1702 may use the memory 1714 of the SoC 1712, etc.

[0189] Further, the input / output devices, processing units, and / or memories of the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2 may be accessible and usable by the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2. Fig.17 In the example of , based on the node configuration of node 1701, memory 1704, memory 1714, memory 17n4, input / output device 1706, input / output device 1716, and / or input / output device 17n6 may be accessible and / or usable by all or part of first SoC 1702, second SoC 1712, ..., and nth SoC 17n2. In some cases, the combination of SoC 1702, SoC 1712, SoC 17n2 may be considered the reverse of virtual machine / containerization, because the combination corresponds to the combination of physical computing resources from multiple physically different SoCs to form one logical computing device, while virtual machine / containerization corresponds to dividing the computing resources of a single physical computing device into multiple logical (or virtualized) computing devices.

[0190] Continue to refer Fig.17, the multi-SoC architecture 1700 also includes an isolated execution environment manager 1720 to manage and / or implement instances of isolated execution environments using the computing resources of the node 1701 (e.g., the computing resources of the first SoC 1702, the second SoC 1712, ... and the nth SoC 17n2). The isolated execution environment manager 1720 can use the computing resources of the node 1701 to implement (e.g., instantiate) any number of isolated execution environment instances. For example, the isolated execution environment manager 1720 can use the computing resources of the node 1701 to implement 4, 6, 7, 10, etc. isolated execution environment instances. In some cases, the isolated execution environment manager 1720 can use SoCs (e.g., the first SoC 1702, the second SoC 1712, etc.) to implement isolated execution environment instances.

[0191] In some cases, since the node 1701 is composed of multiple SoCs 1702, SoCs 1712, SoCs 17n2, the isolated execution environment instances may be distributed across different SoCs 1702, SoCs 1712, SoCs 17n2. In some such cases, the isolated execution environment manager 1720 may have insight and / or control as to which isolated execution environment is assigned to which SoC 1702, SoC 1712, SoC 17n2, etc. For example, the isolated execution environment manager 1720 may include a table, or otherwise identify the SoC 1702, SoC 1712, SoC 17n2 that instantiates the isolated execution environment. In some such cases, the isolated execution environment manager 1720 may instruct a particular SoC 1702, SoC 1712, SoC 17n2 to implement a particular isolated execution environment.

[0192] In some cases, the isolated execution environment manager 1720 may not have insight into which isolated execution environment is assigned to which SoC 1702, SoC 1712, SoC 17n2, etc. For example, from the perspective of the isolated execution environment manager 1720, SoC 1702, SoC 1712, SoC 17n2 (or node 1701) may constitute a single computing device (but with greater computing resources than one of SoC 1702, SoC 1712, SoC 17n2).

[0193] Typically, the isolated execution environment manager 1720 can be software, firmware, or hardware for creating and running an isolated execution environment such as, but not limited to, a VM instance. For example, the isolated execution environment manager 1720 may include an embedded, hosted, native, or bare metal hypervisor configured to instantiate and subsequently monitor one or more isolated execution environment instances. The isolated execution environment manager 1720 can associate and manage physical computing resources between isolated execution environments. In some cases, the isolated execution environment can be configured to appear and operate as a personal computer or other specific type of computer. Therefore, part of the physical computing resources can be "virtualized" so that the isolated execution environment operates as if the virtualized resources (e.g., virtual processing resources, virtual memory resources, and virtual input / output (I / O) resources) are physical resources of the isolated execution environment. In some cases, the isolated execution environment manager 1720 manages the physical computing resources on the physical computing system (e.g., SoC) that constitute the virtual computing resources for each instantiated isolated execution environment instance. As a result, physical computing resources can be shared to support the instantiated virtual components of each instantiated isolated execution environment instance.

[0194] In some cases, the isolated execution environment manager 1720 operates in a partition of the multi-SoC architecture that is separate and isolated from the isolated execution environment instances of the first SoC 1702, the second SoC 1712, ..., and the nth SoC 17n2. The isolated execution environment manager 1720 can implement one or more isolated execution environment instances using the first SoC 1702, the second SoC 1712, ..., and / or the nth SoC 17n2. For example, the isolated execution environment manager 1720 can implement a first isolated execution environment instance using the first SoC 1702, and implement a second isolated execution environment instance using the second SoC 1712.

[0195] Fig.18 1800 is a flowchart illustrating an example of a routine 1800 implemented by one or more processors of a SoC (e.g., one or more cores of MPSoC 101-2). Fig.18 It will be appreciated that the flow chart illustrated in FIG. Fig.18 One or more steps of the routines illustrated in the example, or the order of the steps may be changed. In addition, for the purpose of illustrating the examples clearly, one or more specific system components are described in the context of performing various operations during various data flow stages. However, other system arrangements and distribution of processing steps across system components may be used.

[0196] At block 1802, one or more processors may identify a boot process for a SoC in the set of SoCs. The boot process may include instructions for booting the SoC. In some cases, the boot process may include one or more layers, steps, levels, etc. Based on identifying the boot process, the one or more processors may implement (e.g., initialize) the boot process for the SoC. In some cases, the one or more processors may boot the SoC based on implementing the boot process for the SoC.

[0197] At block 1804, one or more processors may initialize computing resources (e.g., physical computing resources) of the SoC. For example, one or more processors may initialize processing units (e.g., central processing units), input / output devices and / or input / output functionality, memory (e.g., cache, random access memory, etc.), etc. of the SoC. One or more processors may initialize computing resources of the SoC during one or more initial stages of the boot process of the SoC. In some cases, during the boot process, one or more processors may train computing resources. For example, one or more processors may train the memory of the SoC. In order to initialize the computing resources of the SoC, one or more processors may execute a code set and / or load a pre-boot image. In some cases, one or more processors may authenticate and load a pre-boot image.

[0198] At box 1806, one or more processors can dynamically identify the node configuration of the SoC. As described herein, the node configuration can identify the node associated with the SoC (e.g., the node with which the SoC will share computing resources). As described herein, the SoC set can be configured as one or more nodes, wherein the SoC of a particular node shares computing resources. In addition, SoCs corresponding to different nodes (e.g., different nodes) may not be able to share computing resources. For example, based on the SoC of the first node and the SoC of the second node corresponding to different nodes, the SoC of the first node may not be able to share resources with the SoC of the second node, and the SoC of the second node may not be able to access the resource. In some cases, each node may include at least one SoC in the SoC set. In some cases, the SoC in the SoC set and one or more additional SoCs may correspond to the first computing node. In some cases, one or more other SoCs in the SoC set may correspond to the second computing node.

[0199] The node configuration may be associated with a multi-SoC architecture (e.g., created by an operator) and stored in a persistent or substantially persistent memory (e.g., a hard drive, a read-only memory including an erasable programmable read-only memory, a flash memory, etc.) coupled to and communicating with the multi-SoC architecture. For example, the memory may be a memory of an SoC, a memory of a collection of SoCs, etc. The node configuration may specify one or more computing nodes and a plurality of SoCs to be associated with each node. In some cases, the node configuration specifies a specific SoC within the multi-SoC architecture to be associated with each node. For example, the node configuration may specify that SoC 1, SoC 3, and SoC 5 form a first node, SoC 2 and SoC 4 form a second node, SoC 6 forms a third node, etc. In another case, the node configuration does not specify a specific SoC, and the multi-SoC architecture is configured to map (e.g., dynamically map) a specific SoC to a requested node during routine 1800. In some instances, the node configuration may specify a specific role for each node. For example, the configuration may specify that multiple nodes are combined into a redundant architecture. In other examples, redundancy may be established through individual configuration of the nodes (eg, through software executed on each node after initialization).

[0200] At box 1808, one or more processors may enter a multi-processing mode for the SoC. One or more processors may enter a multi-processing mode for the SoC during the boot process of the SoC. For example, one or more processors may cause the SoC to enter a multi-processing mode while booting the SoC. In order to enter a multi-processing mode (e.g., a multi-socket symmetric multi-processing mode), one or more processors may identify at least one computing resource of the SoC to be shared with other SoCs of the node. For example, the SoC may identify a memory, one or more input / output devices, and / or one or more processing units to share with other SoCs of the node. In addition, the SoC may identify computing resources shared with the SoC from other SoCs of the node (e.g., computing resources that the SoC from other SoCs can use). For example, the SoC may identify a memory, one or more input / output devices, and / or one or more processing units shared with the SoC of another SoC. In a multi-processing mode, the SoC and other SoCs of the node may share access to computing resources.

[0201] The SoC may share access to computing resources of the SoC with other SoCs of the node during the boot process. For example, the SoC may identify other SoCs during the boot process, determine that the other SoCs and the SoC correspond to the same node, and share access to computing resources of the SoC with the other SoCs based on the determination that the other SoCs and the SoC correspond to the same node.

[0202] Based on entering the multi-processing mode, one or more processors can implement subsequent stages of the boot process for the SoC. For example, one or more processors can boot a first-stage kernel of an operating system or hypervisor for the SoC. In some cases, one or more processors can implement subsequent stages (e.g., booting a first-stage kernel) after sharing access to computing resources.

[0203] As described above, one or more processors may assign one or more functions to the SoC based on the execution of the guided process. For example, the functions may include implementing lane changes, implementing cruise control, implementing voice navigation, etc.

[0204] In the previous description, aspects and embodiments of the present disclosure have been described with reference to many specific details, which may vary depending on implementation. Therefore, the specification and drawings should be regarded as illustrative, rather than restrictive. The only and exclusive indication of the scope of the invention, and the applicant's expectation that the content of the scope of the invention is the literal and equivalent scope of such claims issued from the present application in the specific form of the claims, including any subsequent amendments. Any definition of the terms used to be included in such claims clearly set forth herein should be based on the meaning of such terms as used in the claims. In addition, when the term "also includes" is used in the previous specification or the appended claims, the phrase may be followed by additional steps or entities, or sub-steps / sub-entities of the previously described steps or entities.

[0205] Various additional example embodiments of the present disclosure may be described by the following clauses:

[0206] Clause 1: A method comprising,

[0207] Initializing, using at least one processor, a boot process for a SoC in the set of SoCs;

[0208] During the boot process:

[0209] Initializing computing resources of the SoC using the at least one processor, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory;

[0210] identifying, using the at least one processor, a node configuration for the SoC, the node configuration defining a node, wherein the node configuration indicates the SoC and the SoC set

[0211] at least one additional SoC in corresponds to the node; and

[0212] Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

[0213] Clause 2: The method of clause 1, further comprising accessing a boot code from a memory of the SoC, wherein the boot process for the SoC is initialized based on the boot code.

[0214] Clause 3: The method of clause 2, wherein the memory of the SoC comprises read-only memory.

[0215] Clause 4: A method according to any one of clauses 1 to 3, further comprising during the boot process:

[0216] identifying the at least one additional SoC in the set of SoCs; and

[0217] Determine that the SoC and at least one additional SoC in the set of SoCs correspond to the node, wherein, based on determining that the SoC and at least one additional SoC in the set of SoCs correspond to the node, share access to the computing resource with the at least one additional SoC in the set of SoCs.

[0218] Clause 5: The method of any one of clauses 1 to 4, wherein the boot process is based on a boot image, the method further comprising loading and authenticating the boot image during the boot process.

[0219] Clause 6: The method of any one of clauses 1 to 5, wherein the computing resource comprises at least one of a central processing unit, a cache, a random access memory, and an input / output device.

[0220] Clause 7: The method of any one of clauses 1 to 6, wherein the computing resource is a physical computing resource.

[0221] Clause 8: The method of any one of clauses 1 to 7, further comprising training the computing resource during the boot process.

[0222] Clause 9: The method of any one of clauses 1 to 8, further comprising initializing an isolated execution environment manager during the boot process, wherein the isolated execution environment manager instantiates an isolated execution environment using the SoC.

[0223] Clause 10: The method of any of clauses 1 to 9, further comprising, during the boot process and after sharing access to the computing resources with the at least one additional SoC in the set of SoCs, booting a kernel.

[0224] Clause 11: The method of any of clauses 1 to 10, wherein the node configuration is associated with an operator of the set of SoCs.

[0225] Clause 12: The method of any one of clauses 1 to 11, further comprising obtaining the node configuration from a memory of the SoC during the boot process.

[0226] Clause 13: The method of any one of clauses 1 to 11, further comprising obtaining the node configuration from a memory of the SoC set during the boot process, wherein the memory of the SoC set is coupled to and in communication with the SoC set.

[0227] Clause 14: The method of any of clauses 1 to 13, wherein the SoC and the at least one additional SoC in the set of SoCs operate in a multi-processing mode based on sharing access to the computing resources.

[0228] Clause 15: The method of any one of clauses 1 to 14, further comprising allocating functionality to the SoC based on execution of the boot process.

[0229] Clause 16: The method according to any one of clauses 1 to 14, further comprising:

[0230] assigning a first function to the SoC based on execution of the boot process; and

[0231] A second function is assigned to the at least one additional SoC in the set of SoCs, wherein the SoC uses the computing resources to perform the first function and the at least one additional SoC in the set of SoCs uses the computing resources to perform the second function.

[0232] Clause 17: A method according to any one of clauses 1 to 16, wherein a second SoC in the SoC set does not correspond to the node, and wherein, based on the fact that the second SoC in the SoC set does not correspond to the node, access to the computing resource is not shared with the second SoC in the SoC set.

[0233] Clause 18: The method of any one of clauses 1 to 17, further comprising booting the SoC based on initializing the boot process.

[0234] Clause 19: A system comprising:

[0235] at least one processor, and

[0236] at least one non-transitory storage medium storing instructions that, when executed by the at least one processor, cause the at least one processor to:

[0237] Initialize a boot process for a SoC in the SoC set;

[0238] During the boot process,

[0239] Initializing computing resources of the SoC, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory;

[0240] identifying a node configuration for the SoC, the node configuration defining a node, wherein the node configuration indicates that the SoC and at least one additional SoC from the set of SoCs correspond to the node; and

[0241] Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

[0242] Clause 20: At least one non-transitory storage medium storing instructions that, when executed by a computing system including a processor, cause the computing system to:

[0243] Initialize a boot process for a SoC in the SoC set;

[0244] During the boot process,

[0245] Initializing computing resources for the SoC, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory;

[0246] identifying a node configuration for the SoC, the node configuration defining a node, wherein the node configuration indicates that the SoC and at least one additional SoC from the set of SoCs correspond to the node; and

[0247] Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

[0248] Clause 21: The system of clause 19, wherein execution of the instructions further causes the at least one processor to access boot code from a memory of the SoC, wherein the boot process for the SoC is initialized based on the boot code.

[0249] Clause 22: The system of clause 21, wherein the memory of the SoC comprises read-only memory.

[0250] Clause 23: The system of any one of clauses 19, 21, and 22, wherein execution of the instructions further causes the at least one processor to:

[0251] identifying the at least one additional SoC in the set of SoCs; and

[0252] Determine that the SoC and at least one additional SoC in the set of SoCs correspond to the node, wherein, based on determining that the SoC and at least one additional SoC in the set of SoCs correspond to the node, share access to the computing resource with the at least one additional SoC in the set of SoCs.

[0253] Clause 24: The system of any one of clauses 19, 21 to 23, wherein the boot process is based on a boot image, wherein execution of the instructions further causes the at least one processor to load and authenticate the boot image during the boot process.

[0254] Clause 25: The system of any one of clauses 19, 21 to 24, wherein the computing resources further comprise at least one of a central processing unit, a cache, a random access memory, and an input / output device.

[0255] Clause 26: The system of any one of clauses 19, 21 to 25, wherein the computing resource is a physical computing resource.

[0256] Clause 27: The system of any one of clauses 19, 21 to 26, wherein execution of the instructions further causes the at least one processor to train the computing resource during the boot process.

[0257] Clause 28: A system according to any one of Clauses 19, 21 to 27, wherein execution of the instructions also causes the at least one processor to initialize an isolated execution environment manager during the boot process, wherein the isolated execution environment manager instantiates an isolated execution environment using the SoC.

[0258] Clause 29: A system according to any one of clauses 19, 21 to 28, wherein execution of the instructions further causes the at least one processor to boot a kernel during the boot process and after sharing access to the computing resources with the at least one additional SoC in the set of SoCs.

[0259] Clause 30: The system of any one of clauses 19, 21 to 29, wherein the node configuration is associated with an operator of the set of SoCs.

[0260] Clause 31: The system of any one of Clauses 19, 21 to 30, wherein execution of the instructions further causes the at least one processor to obtain the node configuration from a memory of the SoC during the boot process.

[0261] Clause 32: A system according to any one of clauses 19, 21 to 30, wherein execution of the instructions also causes the at least one processor to obtain the node configuration from a memory of the SoC set during the boot process, wherein the memory of the SoC set is coupled to the SoC set and communicates with the SoC set.

[0262] Clause 33: The system of any one of clauses 19, 21 to 32, wherein the SoC and the at least one additional SoC in the set of SoCs operate in a multi-processing mode based on sharing access to the computing resources.

[0263] Clause 34: The system of any one of Clauses 19, 21 to 33, wherein execution of the instructions further causes the at least one processor to allocate functionality to the SoC based on execution of the boot process.

[0264] Clause 35: A system according to any one of clauses 19, 21 to 33, wherein execution of the instructions further causes the at least one processor to:

[0265] assigning a first function to the SoC based on execution of the boot process; and

[0266] A second function is assigned to the at least one additional SoC in the set of SoCs, wherein the SoC uses the computing resources to perform the first function and the at least one additional SoC in the set of SoCs uses the computing resources to perform the second function.

[0267] Clause 36: A system according to any one of Clauses 19 and Clauses 21 to Clause 35, wherein a second SoC in the SoC set does not correspond to the node, and wherein access to the computing resource is not shared with the second SoC in the SoC set based on the fact that the second SoC in the SoC set does not correspond to the node.

[0268] Clause 37: The system of any one of Clauses 19, 21 to 36, wherein execution of the instructions further causes the at least one processor to boot the SoC based on initializing the boot process.

[0269] Clause 38: The at least one non-transitory storage medium of clause 20, wherein execution of the instructions further causes the computing system to access boot code from a memory of the SoC, wherein the boot process for the SoC is initialized based on the boot code.

[0270] Clause 39: The at least one non-transitory storage medium of clause 38, wherein the memory of the SoC comprises read-only memory.

[0271] Clause 40: At least one non-transitory storage medium as recited in any one of Clause 20, Clause 38, and Clause 39, wherein execution of the instructions further causes the computing system, during the boot process:

[0272] identifying the at least one additional SoC in the set of SoCs; and

[0273] Determine that the SoC and at least one additional SoC in the set of SoCs correspond to the node, wherein, based on determining that the SoC and at least one additional SoC in the set of SoCs correspond to the node, share access to the computing resource with the at least one additional SoC in the set of SoCs.

[0274] Clause 41: At least one non-transitory storage medium according to any one of clauses 20, 38 to 40, wherein the boot process is based on a boot image, wherein execution of the instructions further causes the computing system to load and authenticate the boot image during the boot process.

[0275] Clause 42: At least one non-transitory storage medium according to any one of clauses 20, 38 to 41, wherein the computing resource further comprises at least one of a central processing unit, a cache, a random access memory, and an input / output device.

[0276] Clause 43: At least one non-transitory storage medium as recited in any one of Clauses 20, 38, to 42, wherein the computing resource is a physical computing resource.

[0277] Clause 44: At least one non-transitory storage medium as recited in any one of Clauses 20, 38, to 43, wherein execution of the instructions further causes the computing system to train the computing resources during the boot process.

[0278] Clause 45: At least one non-transitory storage medium according to any one of Clauses 20, 38 to 44, wherein execution of the instructions further causes the computing system to initialize an isolated execution environment manager during the boot process, wherein the isolated execution environment manager instantiates an isolated execution environment using the SoC.

[0279] Clause 46: At least one non-transitory storage medium according to any one of Clauses 20, 38 to 45, wherein execution of the instructions further causes the computing system to boot a kernel during the boot process and after sharing access to the computing resources with at least one additional SoC in the SoC set.

[0280] Clause 47: At least one non-transitory storage medium as recited in any one of Clauses 20, 38, to 46, wherein the node configuration is associated with an operator of the set of SoCs.

[0281] Clause 48: At least one non-transitory storage medium as recited in any one of Clauses 20, 38, to 47, wherein execution of the instructions further causes the computing system to obtain the node configuration from a memory of the SoC during the boot process.

[0282] Clause 49: At least one non-transitory storage medium according to any one of Clauses 20, 38 to 47, wherein execution of the instructions further causes the computing system to obtain the node configuration from a memory of the SoC set during the boot process, wherein the memory of the SoC set is coupled to and communicates with the SoC set.

[0283] Clause 50: At least one non-transitory storage medium as recited in any one of clauses 20, 38 to 49, wherein the SoC and the at least one additional SoC in the set of SoCs operate in a multi-processing mode based on sharing access to the computing resources.

[0284] Clause 51: At least one non-transitory storage medium as recited in any one of Clauses 20, 38, to 50, wherein execution of the instructions further causes the computing system to allocate functionality to the SoC based on execution of the boot process.

[0285] Clause 52: At least one non-transitory storage medium according to any one of Clauses 20, 38 to 50, wherein execution of the instructions further causes the computing system to:

[0286] assigning a first function to the SoC based on execution of the boot process; and

[0287] A second function is assigned to the at least one additional SoC in the set of SoCs, wherein the SoC uses the computing resources to perform the first function and the at least one additional SoC in the set of SoCs uses the computing resources to perform the second function.

[0288] Clause 53: At least one non-transitory storage medium according to any one of Clauses 20 and Clauses 38 to Clause 52, wherein a second SoC in the SoC set does not correspond to the node, and wherein, based on the fact that the second SoC in the SoC set does not correspond to the node, access to the computing resource is not shared with the second SoC in the SoC set.

[0289] Clause 54: The at least one non-transitory storage medium of any one of Clause 20, Clause 38 to Clause 53, wherein execution of the instructions further causes the computing system to boot the SoC based on initializing the boot process.

Claims

1. A method comprising, Initializing, using at least one processor, a boot process for a SoC in a set of system-on-chips (SoCs); During the boot process: Initializing computing resources of the SoC using the at least one processor, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory; identifying, with the at least one processor, a node configuration for the SoC, the node configuration defining a node, wherein the node configuration indicates that the SoC and at least one additional SoC from the set of SoCs correspond to the node; as well as Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

2. The method of claim 1 , further comprising accessing boot code from a memory of the SoC, wherein: The boot process for the SoC is initialized based on the boot code.

3. The method according to claim 2, wherein: The memory of the SoC includes a read-only memory.

4. The method according to any one of claims 1 to 3, further comprising during the boot process: identifying the at least one additional SoC in the set of SoCs; and The SoC and the at least one additional SoC in the set of SoCs are determined to correspond to the node, wherein: Based on a determination that the SoC and the at least one additional SoC in the set of SoCs correspond to the node, sharing access to the computing resource with the at least one additional SoC in the set of SoCs.

5. The method according to any one of claims 1 to 4, wherein: The boot process is based on a boot image, and the method further comprises loading and authenticating the boot image during the boot process.

6. The method according to any one of claims 1 to 5, wherein: The computing resources include at least one of a central processing unit, a cache, a random access memory, and an input / output device.

7. The method according to any one of claims 1 to 6, wherein: The computing resources are physical computing resources.

8. The method of any one of claims 1 to 7, further comprising training the computing resource during the boot process.

9. The method according to any one of claims 1 to 8, further comprising initializing an isolated execution environment manager during the boot process, wherein: The isolated execution environment manager instantiates an isolated execution environment using the SoC.

10. The method of any one of claims 1 to 9, further comprising booting a kernel during the boot process and after sharing access to the computing resources with the at least one additional SoC in the set of SoCs.

11. The method according to any one of claims 1 to 10, wherein: The node configuration is associated with an operator of the SoC set.

12. The method of any one of claims 1 to 11, further comprising obtaining the node configuration from a memory of the SoC during the boot process.

13. The method according to any one of claims 1 to 11, further comprising obtaining the node configuration from a memory of the SoC set during the boot process, wherein, The memory of the SoC set is coupled to and in communication with the SoC set.

14. The method according to any one of claims 1 to 13, wherein: The SoC and the at least one additional SoC in the set of SoCs operate in a multi-processing mode based on sharing access to the computing resources.

15. The method of any one of claims 1 to 14, further comprising allocating functionality to the SoC based on execution of the boot process.

16. The method according to any one of claims 1 to 14, further comprising: assigning a first function to the SoC based on execution of the boot process; as well as A second function is assigned to the at least one additional SoC in the set of SoCs, wherein the SoC uses the computing resources to perform the first function and the at least one additional SoC in the set of SoCs uses the computing resources to perform the second function.

17. The method according to any one of claims 1 to 16, wherein: A second SoC in the set of SoCs does not correspond to the node, wherein access to the computing resource is not shared with the second SoC in the set of SoCs based on the second SoC in the set of SoCs not corresponding to the node.

18. The method of any one of claims 1 to 17, further comprising booting the SoC based on initializing the boot process.

19. A system comprising: at least one processor, and at least one non-transitory storage medium storing instructions that, when executed by the at least one processor, cause the at least one processor to: Initialize a boot process for a SoC in the SoC set; During the boot process, Initializing computing resources of the SoC, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory; identifying a node configuration for the SoC, the node configuration defining a node, wherein The node configuration indicates that the SoC and at least one additional SoC in the set of SoCs correspond to the node; as well as Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

20. At least one non-transitory storage medium storing instructions that, when executed by a computing system including a processor, cause the computing system to: Initialize a boot process for a SoC in the SoC set; During the boot process, Initializing computing resources for the SoC, the computing resources comprising at least one of input / output functionality, a processing unit, and a memory; identifying a node configuration for the SoC, the node configuration defining a node, wherein The node configuration indicates that the SoC and at least one additional SoC in the set of SoCs correspond to the node; as well as Access to the computing resources is shared with the at least one additional SoC in the set of SoCs.

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