Voltage converter and voltage conversion method

Abstract

A converter for generating a multi-phase output voltage is described that employs a three-level converter that provides an upper pair of switches (upper and middle-lower switches) and a lower pair of switches (lower and middle-upper switches) between positive and negative DC input voltages and an intermediate DC voltage. The controller controls the upper and lower switch pairs through PWM over a plurality of PWM cycles to generate a multi-phase AC output voltage. And for each PWM period, the controller respectively controls the upper switch pair or the lower switch pair to apply corresponding positive or negative bias voltage to each phase of output voltage at the same time, and the positive and negative bias voltages respectively represent the average peak-to-peak voltage of the phase output voltage relative to the positive bias or the negative bias of the intermediate DC voltage. When the intermediate DC voltage is different from the average phase output voltage, the advantage of reducing the conduction loss can be obtained.

Description

Technical Field

[0001] The invention relates to a converter and a method for generating a multi-phase voltage for powering an electrical machine, such as a motor or a generator. Background Art

[0002] There is an overall trend away from internal combustion engines towards more electrified or fully electric vehicles. The automotive industry has a reputation for reliability and technological innovation, and the rapid move towards more electrification is further demanding maximum performance in all aspects of the power supply and electric drive train. Power supplies, inverters / rectifiers / converters, switching circuits, controllers, and passive components are key components of the electric drive train, and their reliability is of paramount importance. Innovation is driven by how to maximize reliability and efficiency in all aspects of transient / modal drive cycle testing while minimizing cost of ownership.

[0003] The two-level inverter generates an alternating current (AC) output waveform by pulse width modulating (PWM) semiconductor switches between two voltage levels. During each switching cycle, the output phase is connected to a positive DC voltage for part of the time period and to a negative DC voltage for part of the time period. The ratio between these two time periods determines the output voltage of the AC waveform.

[0004] Although two-level inverters have good efficiency under heavy load conditions (i.e., in most of the available voltage range), they are not efficient under light load conditions where switching losses dominate. In addition, the switching operation also causes disturbances (ripples) to the DC power supply voltage, which may have adverse effects on other devices. To solve this problem, DC capacitors with a rated voltage range covering the entire operating voltage range are usually used to smooth the ripple disturbances caused by switching and achieve local energy storage.

[0005] As the name implies, a three-level inverter is an inverter that performs PWM on switches set between three voltage levels. The operation of the upper and lower voltages is consistent with that of a two-level inverter, and the other power supply voltage is between these two limit voltages, called the intermediate voltage or midpoint voltage.

[0006] The intermediate voltage levels are provided by capacitive voltage dividers. Since each capacitor is responsible for only a portion of the total voltage range, each capacitor can be smaller with lower specifications and cost compared to a two-level inverter.

[0007] Although three-level inverters can be used over the entire voltage range, it is more advantageous to reduce the midpoint voltage switch and series capacitor size under low load conditions. Three-level inverters generally use a neutral point clamp (NPC) to protect the lower-spec components.

[0008] In our previous application (GB2203651.1), a converter using a three-level topology was proposed, in which the mid-point level switch uses a switch with lower voltage and current ratings than the upper and lower switches. The disadvantage of this arrangement is that in the three-level topology, since the mid-point level switch has a different on-resistance than the upper and lower switches (due to having different (lower) ratings), the conduction losses between the upper and lower switches and the mid-point level cannot be balanced.

[0009] For this type of three-level topology, when the phase output voltage needs to be reduced, the midpoint level switch needs to be turned on for a longer time. As a result, the conduction loss increases as the output voltage (and modulation index) decreases, resulting in a decrease in system efficiency.

[0010] For the reasons stated above, we believe that there is a need for a converter that has the advantages of three-level converter technology and can be used over the entire operating range of the three-level converter. Summary of the invention

[0011] Therefore, the present invention provides a method for generating a multi-phase output voltage and a converter for generating a multi-phase output voltage for driving a motor according to the accompanying independent claims.

[0012] Furthermore, further advantageous embodiments are provided according to the attached dependent claims.

[0013] Here, a converter for generating a multi-phase voltage for powering a motor is described, comprising: an input terminal for receiving a positive DC input voltage and a negative DC input voltage; a plurality of AC output terminals, one for each phase, for outputting a multi-phase AC output voltage, the multi-phase AC output voltage being used to drive the motor; for each phase, a plurality of switches arranged in a T-type structure between the DC input terminal and the corresponding AC phase output terminal, the T-type structure comprising an upper switch connected between the positive DC input terminal and the corresponding AC phase output terminal, a lower switch connected between the corresponding AC phase output terminal and the negative DC input terminal, and a middle upper switch and a middle lower switch connected between the AC phase output terminal and an intermediate DC voltage, the switches being arranged into corresponding upper switch pairs and lower switch pairs, the upper switch pairs comprising the The upper switch and the middle-lower switch, the lower switch pair includes the lower switch and the middle-upper switch, the intermediate DC voltage is a voltage between the positive DC input voltage and the negative DC input voltage; an input terminal for receiving data, the data representing the phase voltage requirement required by the motor; and a controller, the controller is used to control each of the switches within a plurality of PWM cycles through pulse width modulation (PWM) to generate the multi-phase AC output voltage for the motor, wherein the controller is configured to, for each PWM cycle: respectively control the upper or lower switch pair to simultaneously apply a corresponding positive or negative bias voltage to each of the phase output voltages, wherein the positive and negative bias voltages respectively represent the average peak-to-peak voltage of the phase output voltage relative to the positive or negative bias of the intermediate DC voltage.

[0014] When the intermediate DC voltage is different from the average phase output voltage, the advantage of reduced conduction losses can be obtained.

[0015] Respectively controlling the upper or lower switch pairs to apply the corresponding positive or negative bias voltage may include: determining the positive and negative bias voltages applied to each of the phase output voltages based on one or more of a bias voltage buffer amount, an output phase voltage requirement, the negative DC input voltage, the positive DC input voltage, and an output load power factor, wherein the bias voltage buffer amount represents a minimum voltage difference between a peak phase output voltage and the corresponding positive and negative DC input voltages.

[0016] Respectively controlling the upper or lower switch pairs to apply the corresponding positive or negative bias voltage may include: determining positive and negative intermediate voltage target values ​​based on one or more of the positive or negative bias voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage requirement, the intermediate voltage target value buffer amount, and the frequency of the intermediate DC voltage, wherein the positive and negative intermediate voltage target values ​​represent the target voltage deviation of the intermediate DC voltage.

[0017] In either of the above two situations, the controller may apply the positive or negative bias voltage respectively when the difference between the positive or negative bias voltage and the intermediate DC voltage is greater than a threshold voltage.

[0018] For the first PWM cycle, the controller may determine which of the positive bias voltage or the negative bias voltage to apply based on the voltage difference between the positive bias voltage and the intermediate DC voltage and between the negative bias voltage and the intermediate DC voltage. For the first PWM cycle, when the controller applies the positive or negative bias voltage, the controller may be configured to: apply the positive bias voltage when the difference between the positive bias voltage and the intermediate DC voltage is greater than the difference between the negative bias voltage and the intermediate DC voltage; and apply the negative bias voltage when the difference between the negative bias voltage and the intermediate DC voltage is greater than the difference between the positive bias voltage and the intermediate DC voltage.

[0019] For subsequent PWM cycles, when the controller controls the upper switch pair to apply the positive bias voltage, and when the intermediate DC voltage approaches the positive intermediate voltage target value, the controller can be configured to apply a negative bias voltage to the phase output voltage by controlling the lower switch pair.

[0020] For subsequent PWM cycles, when the controller controls the lower switch pair to apply the negative bias voltage, and when the intermediate DC voltage approaches the negative intermediate voltage target value, the controller can be configured to apply a positive bias voltage to the phase output voltage by controlling the upper switch pair.

[0021] When the controller switches between applying the positive bias voltage and applying the negative bias voltage, the controller may control the upper and / or lower switch pairs to apply a slope to a deviation voltage between the positive and negative bias voltages.

[0022] The intermediate DC voltage may be provided by a capacitive voltage divider disposed between the positive DC input terminal and the negative DC input terminal. Alternatively, the intermediate DC voltage may be provided by a second DC source.

[0023] In addition, a method for generating a multi-phase voltage for powering a motor is described, comprising: receiving a positive DC input voltage and a negative DC input voltage; receiving data representing a phase voltage requirement required by the motor; controlling a plurality of switches within a plurality of PWM cycles through pulse width modulation (PWM) to generate the multi-phase AC output voltage for the motor, the plurality of switches being arranged into a plurality of groups, one group for each phase, wherein, for each phase, the group of switches is arranged in a T-type structure between a DC input terminal and a corresponding AC phase output terminal, the T-type structure comprising an upper switch connected between a positive DC input terminal and a corresponding AC phase output terminal, a lower switch connected between a corresponding AC phase output terminal and a negative DC input terminal, and a lower switch connected to the AC phase output terminal. and an upper middle switch and a lower middle switch between the intermediate DC voltage, wherein each switch is configured into a corresponding upper switch pair and a lower switch pair, wherein the upper switch pair includes the upper switch and the lower middle switch, and the lower switch pair includes the lower switch and the upper middle switch, wherein the intermediate DC voltage is a voltage between the positive DC input voltage and the negative DC input voltage; and outputting the multi-phase AC output voltage to drive the motor, wherein for each PWM cycle, controlling the plurality of switches includes: respectively controlling the upper or lower switch pairs to simultaneously apply the corresponding positive or negative bias voltage to each of the phase output voltages, wherein the positive and negative bias voltages respectively represent the average peak-to-peak voltage of the phase output voltage relative to the positive or negative bias of the intermediate DC voltage.

[0024] When the intermediate DC voltage is different from the average phase output voltage, the advantage of reduced conduction losses can be obtained.

[0025] Respectively controlling the upper or lower switch pairs to apply the corresponding positive or negative bias voltage may include: determining the positive and negative bias voltages applied to each of the phase output voltages based on one or more of a bias voltage buffer amount, an output phase voltage requirement, the negative DC input voltage, the positive DC input voltage, and an output load power factor, wherein the bias voltage buffer amount represents a minimum voltage difference between a peak phase output voltage and the corresponding positive and negative DC input voltages.

[0026] Respectively controlling the upper or lower switch pairs to apply the corresponding positive or negative bias voltage may include: determining positive and negative intermediate voltage target values ​​based on one or more of the positive or negative bias voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage requirement, the intermediate voltage target value buffer amount, and the frequency of the intermediate DC voltage, wherein the positive and negative intermediate voltage target values ​​represent the target voltage deviation of the intermediate DC voltage.

[0027] When the difference between the positive or negative bias voltage and the intermediate DC voltage is greater than a threshold voltage, the positive or negative bias voltage may be applied accordingly.

[0028] For the first PWM cycle, it can be determined whether to apply the positive bias voltage or the negative bias voltage according to the voltage difference between the positive bias voltage and the intermediate DC voltage and between the negative bias voltage and the intermediate DC voltage.

[0029] For the first PWM cycle, when applying the positive or negative bias voltage: when the difference between the positive bias voltage and the intermediate DC voltage is greater than the difference between the negative bias voltage and the intermediate DC voltage, the positive bias voltage can be applied; when the difference between the negative bias voltage and the intermediate DC voltage is greater than the difference between the positive bias voltage and the intermediate DC voltage, the negative bias voltage can be applied.

[0030] For subsequent PWM cycles, when the upper switch pair is controlled to apply the positive bias voltage, and when the intermediate DC voltage approaches the positive intermediate voltage target value, a negative bias voltage may be applied to the phase output voltage by controlling the lower switch pair.

[0031] For subsequent PWM cycles, when the lower switch pair is controlled to apply the negative bias voltage and when the intermediate DC voltage approaches the negative intermediate voltage target value, a positive bias voltage may be applied to the phase output voltage by controlling the upper switch pair.

[0032] When switching between applying the positive bias voltage and applying the negative bias voltage, the upper and / or lower switch pairs may be controlled to apply a slope to a deviation voltage between the positive and negative bias voltages.

[0033] The intermediate DC voltage may be provided by a capacitive voltage divider disposed between the positive DC input terminal and the negative DC input terminal. Alternatively, the intermediate DC voltage may be provided by a second DC source. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The present invention will be described below by way of example only with reference to the accompanying drawings.

[0035] Figure 1 Simplified schematic diagram for the inverter;

[0036] Figure 2 The positive DC bus and negative DC bus are shown in Figure 1 The phase voltage generated at the inverter output (relative to the 0V line);

[0037] Figure 3 The motor is shown Figure 1 the resulting line-to-line voltage at the inverter output;

[0038] Figure 4 A simplified layout embodiment of a three-level converter implementation is shown, wherein a series T-type structure is adopted;

[0039] Figure 5 Another single-phase T-type structure is shown, wherein the structure is a so-called parallel T-type three-level converter;

[0040] Figure 6 Shown is a simplified multiphase converter (a three-phase converter in this case) in which each phase uses a three-level series T-type switch structure;

[0041] Figure 7 FIG. 1 is a graph showing the relationship between conduction loss and output current at different modulation levels (the lower the modulation index, the lower the output voltage) in one embodiment;

[0042] Figure 8 Shown is a phase output voltage timing diagram in one embodiment with and without the common bias voltage introduced;

[0043] Fig. 9 FIG. 1 is a timing diagram of phase output voltages in the second embodiment when a common bias voltage is introduced and not introduced;

[0044] Fig.10 FIG. 1 is a timing diagram of phase output voltages with and without the common bias voltage introduced in the third embodiment. DETAILED DESCRIPTION

[0045] Briefly, this article describes a converter for generating a multi-phase output voltage, which uses a three-level converter with an upper switch pair (upper switch and middle lower switch) and a lower switch pair (lower switch and middle upper switch) disposed between a positive and negative DC input voltage and an intermediate DC voltage. A controller controls the upper and lower switch pairs via PWM over multiple PWM cycles to generate a multi-phase AC output voltage. For each PWM cycle, the controller controls the upper or lower switch pair to simultaneously apply a corresponding positive or negative bias voltage to each phase output voltage, respectively, wherein the positive and negative bias voltages represent the average peak-to-peak voltage of the phase output voltage relative to the intermediate DC voltage, respectively, in a positive or negative bias. When the intermediate DC voltage is different from the average phase output voltage, the advantage of reduced conduction losses can be obtained.

[0046] First, a brief background is given. Power converters are well known in the art. One example can be found in US8958222 ( Figure 1 Excerpted from the article). Figure 1Shown is a three-phase, two-level power inverter 100 for converting a DC power supply voltage 101 into an AC output voltage. The AC output terminal 103 can then be connected to a load (not shown). The inverter includes three independent phases 200, 300, 400 (referred to as U phase, V phase, and W phase, respectively). Each phase includes two switches connected in series: phase 200 (U phase) includes switches 200a, 200b; phase 300 (V phase) includes switches 300a, 300b; phase 400 (W phase) includes switches 400a, 400b. Switches 200a, 300a, 400a are connected to the positive rail 105 (and can be referred to as "upper" switches), and switches 200b, 300b, 400b are connected to the negative rail 107 (and can be referred to as "lower" switches). Figure 1 In the embodiment of the present invention, each switch can be an insulated gate bipolar transistor (IGBT) or a metal oxide semiconductor field effect transistor (MOSFET), and for each IGBT or MOSFET, a corresponding anti-parallel diode (not shown) can be used. In addition, any switch with fast switching capability can also be used. Switches 200a, 200b, 300a, 300b, 400a, 400b are switched under the control of a control system (such as a processor) (not shown) to achieve AC output control of the inverter 100. The control is usually implemented using pulse width modulation (PWM) technology or a variant of PWM technology. The power inverter also includes a DC bus capacitor 102 for providing a more stable DC voltage to limit fluctuations when the inverter is occasionally required to provide a large current. Since each phase in 200, 300, 400 switches between two DC levels, the inverter is a so-called two-level inverter. In this example, the two DC levels are a DC voltage and a ground voltage. In addition, the two DC levels can also be a positive DC level and a negative DC level.

[0047] By using the PWM switching mode, the AC output terminal 103 can generate a sinusoidal output current under the combined action of the switch states of the above six switches. However, in order to prevent the DC power supply voltage 101 from being short-circuited, the inverter 100 must be controlled so that the two switches of the same phase are never turned on at the same time. That is, if 200a is turned on, 200b must be turned off, and vice versa; if 300a is turned on, 300b must be turned off, and vice versa; if 400a is turned on, 400b must be turned off, and vice versa.

[0048] Figure 2 The phase voltage (with Figure 1 The relationship between the voltage relative to the 0V line shown in the figure is half the DC bus voltage) and the output voltage phase angle (the DC bus voltage is 250V and the required peak voltage is 200V). Figure 3 Shown is the line-to-line voltage obtained at an electric machine such as an electric motor.

[0049] The two-level inverter needs to switch the entire DC bus voltage in each PWM cycle, which generates large switching harmonics. In addition, under low load / low current conditions where conduction losses dominate, it leads to increased losses in electrical loads such as motors or generators.

[0050] A known technology that can overcome at least some of the disadvantages of a two-level converter is a three-level converter.

[0051] Figure 4 The figure shows a simplified layout embodiment of a three-level converter implementation scheme, in which a series T-type structure is used. This figure only shows one phase, which is equivalent to Figure 1 The U phase 200 in the embodiment. In this structure, the upper switch (Q1) 200a and the lower switch (Q4) 200b are connected between the positive DC power supply voltage (+DC) and the negative DC power supply voltage (-DC), and provide a phase output terminal (AC output terminal) 103. The middle lower switch (Q3) 200d and the middle upper switch (Q2) 200c are connected between the intermediate DC voltage and the phase output terminal 103. The intermediate DC voltage is a DC voltage with a level between the positive and negative DC power supply voltages. In this structure, the intermediate DC voltage is generated by the series capacitor network 102a, 102b. In addition, it can also be provided by an external voltage source. The intermediate DC voltage can be exactly at the midpoint of the positive and negative DC power supply voltages, but it does not necessarily have to be exactly at the midpoint of the positive and negative DC power supply voltages. The intermediate DC voltage can be shared by all phases.

[0052] In the illustrated three-level structure, each switch forms an upper switch and a lower switch pair. The upper switch pair includes an upper switch (Q1) 200a and a middle lower switch (Q3) 200d switch, and the lower switch pair includes a lower switch (Q4) 200b and a middle upper switch (Q2) 200c switch. The upper switch pair can be connected to a positive DC voltage or an intermediate DC voltage, and the lower switch pair can be connected to an intermediate DC voltage and a negative DC voltage. Similarly, each switch is controlled by a controller and switched in accordance with a PWM switching mode to generate the desired phase output voltage. If the phase output voltage level is higher than the intermediate DC voltage level, the upper switch pair is used; if the phase output voltage level is lower than the intermediate DC voltage level, the lower switch pair is used. Each pair of switches switches only half of the DC voltage (assuming that the midpoint voltage is exactly half of the DC bus voltage).

[0053] Figure 5 Another single-phase T-type structure is shown. This structure is a so-called parallel T-type three-level converter. The parallel T-type structure has two independent midpoint voltage connection paths, each of which must be provided with a blocking diode to prevent uncontrolled reverse conduction.

[0054] Figure 6Shown is a simplified multiphase converter (in this case a three-phase converter) using a three-level series T-switch structure for each phase.

[0055] Among them, by switching half of the DC bus voltage, harmonics and load losses are greatly reduced. Some simulation tests show that in the World Harmonized Light Vehicle Test Procedure (WLTP), when a three-level inverter replaces a two-level inverter, the losses caused by PWM harmonics can be reduced by about 80%. For a standard car, this means that the cruising range can be increased by about 5%.

[0056] In a preferred embodiment of the three-level converter of the present invention, the ratings of the middle lower switch and the middle upper switch are adapted to the required switch output voltage and may be different from the ratings of the upper switch and the lower switch.

[0057] By using this structure, the channel resistance of the upper switch and the lower switch can be much lower than the channel resistance of the middle lower switch and the middle upper switch. For example, in a preferred embodiment, MOSFET is used as a power switch device, the channel resistance of the upper switch and the lower switch (i.e., the high-rated value switch) can be about 1.4mΩ, and the channel resistance of the middle lower switch and the middle upper switch (i.e., the low-rated value switch) can be about 10mΩ. Figure 4 and Figure 6 In the illustrated embodiment, the lower middle switch and the upper middle switch are connected in series. Figure 5 In the illustrated embodiment, a blocking diode is provided. All these structures increase the conduction loss due to the series arrangement of the devices.

[0058] For example, the time-averaged power loss due to the MOSFET being on depends on the duty cycle, the square of the on-current in the MOSFET, and the channel resistance of the MOSFET. Therefore, it can be seen that by making a low-rated switch have a higher channel resistance, the on-state power loss of the switch can be affected.

[0059] Figure 7 The diagram shows the relationship between conduction loss and output current at different modulation levels (the lower the modulation index, the lower the output voltage) in one embodiment. It can be seen that as the modulation index or modulation depth decreases (that is, as the output voltage decreases), the loss increases greatly.

[0060] This phenomenon is due in part to the variable duty cycle used in the PWM scheme - the duty cycle ratio between the pairs of switches (upper switch / lower middle switch and lower switch / upper middle switch) needs to be changed to achieve the desired output voltage within a particular PWM period. In other words, as the phase output voltage approaches the midpoint DC voltage, the on (on) time of the corresponding midpoint level switch needs to be increased, and the on time of the corresponding upper and lower switches needs to be decreased. As the phase output voltage becomes more positive or negative (i.e., moves further away from the midpoint DC level), the (current) on time of the midpoint level switch needs to be decreased, and the on time of the corresponding upper switch (when more positive) or lower switch (when more negative) needs to be increased.

[0061] When the need for midpoint switching is greater (i.e., when the switching pattern used to generate the output voltage requires the midpoint switch to be on for a longer time than the corresponding upper and lower switches), one approach to reducing converter losses is to introduce a bias voltage into the phase output voltage so that the average phase output voltage deviates from the midpoint voltage toward the positive or negative DC bus voltage. If the same bias voltage is applied to each phase output voltage, the electrical load is not affected by the bias voltage because the bias voltages cancel each other out in the line-to-line (phase-to-phase) voltages of each phase.

[0062] In summary, by adding a bias voltage to each phase voltage, the phase voltage can be deviated from the second DC voltage toward the positive DC bus voltage or the negative DC bus voltage. In this way, when the bias voltage applied to the phase output voltage causes the phase output voltage to deviate toward the positive DC bus voltage, the conduction time required by the upper switch will be longer than the conduction time required by the middle and lower switches. Similarly, when the bias voltage applied to the phase output voltage causes the phase output voltage to deviate toward the negative DC bus voltage, the conduction time required by the lower switch will be longer than the conduction time required by the middle and upper switches.

[0063] By using this method, at a given phase output voltage, the conduction time of the upper switch and the lower switch can be made longer than the conduction time of the middle lower switch or the middle upper switch (respectively), thereby reducing the conduction loss of the three-level converter, and this is true for various modulation index levels (i.e., phase output voltages). However, this scheme may affect the intermediate DC voltage level.

[0064] The intermediate DC voltage can be generated by a capacitor voltage divider disposed between the positive DC bus and the negative DC bus. Nominally, the intermediate voltage can be half of the DC voltage (DC / 2), that is, approximately at the midpoint of the positive DC bus voltage and the negative DC bus voltage. However, this is not necessarily the case, and the intermediate voltage can also have other levels. In this structure, the intermediate DC voltage will naturally balance at the average phase output voltage over time. Therefore, when the on-time of the upper switch is extended (i.e., the bias voltage causes the phase output voltage to deviate in the direction of the positive DC bus voltage), over time, the intermediate DC voltage will gradually drift in the direction close to the positive bias voltage +Offset due to the gradual increase in the charge of the capacitor voltage divider. Similarly, when the on-time of the lower switch is extended (i.e., the bias voltage causes the phase output voltage to deviate in the direction of the negative DC bus voltage), over time, the intermediate DC voltage will gradually drift in the direction close to the negative bias voltage -Offset due to the gradual depletion of the charge of the capacitor voltage divider. As described above, the intermediate DC voltage will gradually drift in the direction close to the average phase output voltage. The drift rate depends on various factors, including but not limited to capacitor size and current loading effects.

[0065] Figure 8 Shown is a phase output voltage timing diagram with and without the introduction of a common bias voltage in an embodiment.

[0066] The figure shows the phase output voltages for several output cycles. In this embodiment, a low phase output voltage is desired (ie a low modulation index). Initially, no common bias voltage is applied, so the average phase output voltage remains at an intermediate voltage.

[0067] In a cycle where the bias voltage is not introduced, when a phase output voltage lower than the intermediate voltage is required, the lower switch pair (lower switch and middle upper switch) is used to generate the phase output voltage, and when a phase output voltage higher than the intermediate DC voltage is required, the upper switch pair (upper switch and middle lower switch) is used to generate the phase output voltage. Since the required phase output voltage is too low, the conduction time of the middle lower switch and the middle upper switch is longer than the conduction time of the upper switch and the lower switch, respectively.

[0068] Accordingly, by controlling the upper switch and the middle and lower switches, a common bias voltage is applied (the bias voltage is shown as +Offset in the figure because it must cause the average phase output voltage to shift from the middle voltage toward the positive DC bus voltage), so that the phase output voltage drifts to about the +Offset level. Since the phase output voltage is positively biased from the middle DC voltage, the switching pattern used to generate the phase output voltage requires a longer conduction time of the upper switch and a shorter conduction time of the middle and lower switches compared to the case where the bias voltage is not applied. In this way, the conduction loss is reduced compared to the case where the bias voltage is not applied.

[0069] In general, when the intermediate voltage is different from the average phase output voltage (ie, +Offset), the conduction loss can be reduced.

[0070] However, as shown in the figure, this also causes the intermediate voltage to drift positively towards the average phase output voltage (i.e., +Offset). The slope of the positive drift depends on the capacitance of the capacitor used to generate the intermediate DC voltage, the current of the electrical load, and the common bias voltage used.

[0071] In order to prevent the intermediate voltage from drifting too close to the average phase output voltage (i.e., the bias voltage; in this case, the advantages of this solution cannot be achieved), this solution can further apply a negative DC bias voltage, i.e., a negative bias voltage close to the negative DC bus voltage. In this embodiment, a negative bias voltage -Offset is applied by controlling the lower switch and the middle and upper switches so that the average phase output voltage is at the -Offset level. Since the phase output voltage is lower than the intermediate voltage, the switching mode for generating the phase output voltage requires a longer conduction time of the lower switch and a shorter conduction time of the middle and upper switches compared to the case where the bias voltage is not applied. In this way, the conduction loss is reduced compared to the case where the bias voltage is not applied.

[0072] In general, conduction losses are reduced when the intermediate voltage is different from the average phase output voltage.

[0073] In addition, it can be seen that after the negative bias voltage is applied, the intermediate voltage gradually drifts negatively from the previous value (similarly, it shows a trend of being stable at the average phase output voltage (in this case, -Offset)). Similarly, in order to prevent the intermediate voltage from drifting too close to the new average phase output voltage (i.e., -Offset; in this case, the advantages of this solution will be weakened or made impossible to achieve), this solution can apply a positive DC bias voltage again, i.e., a bias voltage greater than the intermediate DC voltage.

[0074] Preferably, the intermediate DC voltage is prevented from reaching the corresponding nearest peak of the phase output voltage by selecting the positive and negative intermediate DC voltage target values. Taking the example of applying a +Offset voltage to make the intermediate DC voltage drift positively toward the +Offset voltage, once the intermediate DC voltage reaches the positive intermediate DC voltage target value (+Intermediate Target), the switching scheme switches to applying -Offset in the above manner so that the intermediate DC voltage gradually drifts negatively toward -Offset. Similarly, once the intermediate voltage reaches the negative intermediate DC voltage target value (-Intermediate Target), the switching scheme switches to applying +Offset in the above manner. This pattern is repeated.

[0075] It can be seen that the alternating operation between +Offset and -Offset makes the waveform of the intermediate voltage similar to a triangular waveform, wherein the approximate triangular wave of the intermediate DC voltage has a frequency. The frequency depends on the capacitance, phase voltage, bias voltage, intermediate voltage target value, load current, and phase angle.

[0076] Fig. 9 FIG. 1 is a timing diagram of phase output voltages in the second embodiment when a common bias voltage is introduced and not introduced. Fig. 9 In the embodiment, the +Offset voltage value and the -Offset voltage value are closer to the positive DC rail and the negative DC rail, respectively. The positive intermediate DC voltage target value and the negative intermediate DC voltage target value can be the same or different.

[0077] and Figure 8 The embodiment is consistent with Fig. 9 The scheme repeatedly applies +Offset voltage and -Offset voltage to the phase output voltage by controlling the switching mode of the upper switch pair (upper switch and middle lower switch) when the phase output voltage is higher than the intermediate DC voltage, and controlling the switching mode of the lower switch pair (lower switch and middle upper switch) when the phase output voltage is lower than the intermediate DC voltage. Figure 8 The embodiment is consistent, the phase output voltage is relatively low (ie the modulation index is relatively low). Similarly, when a +Offset voltage is applied to the phase output voltage, the intermediate voltage gradually drifts positively; when a -Offset voltage is applied to the phase output voltage, the intermediate voltage gradually drifts negatively.

[0078] As above combined Figure 8 As described above, when the intermediate voltage is different from the average phase output voltage, the conduction loss of the switch can be reduced.

[0079] exist Fig. 9 In the example, by making the common bias voltage closer to the DC rail, the peak value of the triangle wave of the intermediate voltage can be maximized, thereby minimizing the conduction loss. In order to prevent the peaks or valleys of the phase output voltage from touching the DC rail (which would cause the system to overmodulate), the maximum phase output voltage is selected to be within the DC rail range to leave a margin or bias voltage buffer. This margin or bias voltage buffer can vary with the output phase voltage demand (i.e., modulation index).

[0080] Fig.10 FIG. 1 is a timing diagram of phase output voltages in the third embodiment when a common bias voltage is introduced and not introduced. Figure 8 and Fig. 9 In comparison, the phase output voltage in this embodiment is larger (ie, the modulation index is larger).

[0081] and Figure 8 and Fig. 9 The embodiment is consistent with Fig.10The scheme repeatedly applies +Offset voltage and -Offset voltage to the phase output voltage by controlling the switching mode of the upper switch pair (upper switch and middle lower switch) when the phase output voltage is higher than the intermediate DC voltage, and controlling the switching mode of the lower switch pair (lower switch and middle upper switch) when the phase output voltage is lower than the intermediate DC voltage. Similarly, when the +Offset voltage is applied to the phase output voltage, the intermediate voltage gradually drifts positively; when the -Offset voltage is applied to the phase output voltage, the intermediate voltage gradually drifts negatively.

[0082] As above combined Figure 8 and Fig. 9 As described above, when the intermediate voltage is different from the average phase output voltage, the conduction loss of the switch can be reduced.

[0083] exist Fig.10 In order to prevent the phase output voltage from touching the DC rails, the common offset voltages (+Offset and -Offset) are lower (i.e., closer to the midpoint of the positive and negative DC rails).

[0084] Preferably, the phase output voltage should not cross the intermediate voltage, otherwise the inverter will switch to another pair of switches and the advantages of the present invention will not be achieved.

[0085] The positive and negative common bias voltages may be calculated based on one or more of several parameters including bias voltage buffer, output phase voltage requirement, negative DC input voltage, positive DC input voltage and output load power factor. Preferably, in order to prevent the phase output voltage from touching any DC rail, a sufficiently large margin (bias voltage buffer) should be set above the peak and below the trough of the output phase voltage requirement. Preferably, the bias voltage buffer is set to a value large enough to be as close as possible to the required DC rail, so that the phase output voltage deviates from the intermediate voltage to a degree sufficient to minimize conduction losses.

[0086] In one embodiment, the bias voltage may be calculated based on the output phase voltage demand (related to the modulation index) and the value of the margin or bias voltage buffer provided above the output phase voltage demand peaks and below the troughs to prevent the phase output voltage from touching the DC rail.

[0087] In terms of the intermediate voltage, the appropriate positive and negative intermediate voltage target values ​​(i.e., the voltage target value that allows the intermediate voltage to drift toward the positive bias voltage or the negative bias voltage) can be calculated based on one or more of the positive bias voltage or the negative bias voltage, the negative DC input voltage, the positive DC input voltage, the required phase voltage (related to the modulation index), the intermediate voltage target value buffer, and the frequency of the intermediate DC voltage. The intermediate voltage target value buffer is the margin above the output phase voltage demand peak or below the trough, which is used to prevent the phase output voltage from touching or crossing the intermediate DC voltage. The intermediate voltage target value buffer may be the same as the bias voltage buffer, or different from the bias voltage buffer. The intermediate voltage target value buffer may be zero.

[0088] Since the intermediate voltage drifts over time when this bias voltage technique is used (starting from the generation of the intermediate DC voltage from the positive and negative DC rails in the manner described above), and since the advantage of reduced conduction losses can be achieved when the phase output voltage is different from the intermediate DC voltage, the intermediate DC voltage can be used to determine whether the technique should be used at the very beginning. For example, when the difference between the +Offset voltage and the -Offset voltage (these two voltages are the average phase output voltages when the positive and negative bias voltages are applied to the phase output voltages, respectively) and the intermediate DC voltage is greater than a threshold, the controller can determine that the technique can be beneficial, and therefore implement the +Offset voltage and the -Offset voltage by controlling the switches accordingly in the manner described above.

[0089] As an additional or alternative solution, whether to use the above-mentioned bias voltage technology can also be determined based on one or more of the following parameters: output phase voltage requirement; DC input voltage (positive DC input voltage and negative DC input voltage); and load power factor.

[0090] When the scheme is first started, that is, for the first PWM cycle to which +Offset or -Offset is to be applied, the controller can first determine which of the +Offset voltage and the -Offset voltage to apply. This determination can be made, for example, based on the voltage difference between the positive bias voltage and the intermediate DC voltage and the voltage difference between the negative bias voltage and the intermediate DC voltage.

[0091] For example, the controller may be configured to apply the positive bias voltage when the difference between the positive bias voltage and the intermediate DC voltage is greater than the difference between the negative bias voltage and the intermediate DC voltage. In addition, the controller may be configured to apply the negative bias voltage when the difference between the negative bias voltage and the intermediate DC voltage is greater than the difference between the positive bias voltage and the intermediate DC voltage.

[0092] Alternatively, the controller may directly implement the +Offset voltage or the -Offset voltage without considering the values ​​of the +Offset, -Offset, and intermediate DC voltages.

[0093] After the scheme is started, ie for subsequent PWM cycles, it can be determined which bias voltage to apply in the manner described above in conjunction with the method of making the intermediate DC voltage approach the corresponding positive or negative intermediate voltage target value.

[0094] When switching between applying the +Offset voltage and applying the -Offset voltage, i.e., switching between using the corresponding upper switch pair and using the corresponding lower switch pair, it is preferred to incorporate a slope into the switching scheme. This is done to minimize NVH (noise, vibration and harshness) issues that may be caused by the rapid change in the phase output voltage when switching between the +Offset and -Offset states.

[0095] Although the above describes an embodiment in which the intermediate DC voltage is generated based on the positive and negative DC rails (e.g., with a voltage dividing capacitor), the intermediate DC voltage can also be provided by a second DC input voltage source. In one embodiment, the second DC input voltage source can have the ability to provide and sink current during the time period when the +Offset voltage and the -Offset voltage are applied to the phase output voltage so that the intermediate DC voltage remains constant. In this case, it can be determined based on other parameters, such as the characteristics of the switch used, noise considerations, thermodynamic characteristics of the switch, etc., which of the +Offset voltage and the -Offset voltage is applied.

[0096] Alternatively, the second DC input voltage source may be configured to provide a variable or varying intermediate DC voltage, in which case the controller determines which of +Offset and -Offset to apply in the same manner as in the above-mentioned varying intermediate DC voltage case.

[0097] The second DC input voltage source may be provided, for example, by the center tap of a battery pack providing positive and negative DC rails. In this structure, +Offset voltage and -Offset voltage may be applied alternately to control the charging and discharging of the two halves of the battery pack, depending on functional requirements and battery pack status.

[0098] Although the generation of three-phase voltage is described and illustrated above, the above three-level converter is also applicable to output voltages of more phases. Therefore, the present technology is also applicable to the generation of multi-phase output voltages.

[0099] Needless to say, those skilled in the art will also come up with other effective alternatives. It should be understood that the present invention is not limited to the above-mentioned embodiments, and further encompasses modifications that are obvious to those skilled in the art and fall within the scope of the appended claims.

Claims

1. A converter for generating a multiphase output voltage for powering a motor, characterized in that include: An input terminal for receiving a positive DC input voltage and a negative DC input voltage; a plurality of AC output terminals, one for each phase, for outputting a multi-phase AC output voltage to drive the motor; For each phase, a plurality of switches in a T-type structure are arranged between a DC input terminal and a corresponding AC phase output terminal, the T-type structure comprising: an upper switch connected between a positive DC input terminal and a corresponding AC phase output terminal, a lower switch connected between a corresponding AC phase output terminal and a negative DC input terminal, and a middle upper switch and a middle lower switch connected between the AC phase output terminal and an intermediate DC voltage, each of the switches being arranged into a corresponding upper switch pair and a lower switch pair, the upper switch pair comprising the upper switch and the middle lower switch, the lower switch pair comprising the lower switch and the middle upper switch, and the intermediate DC voltage being a voltage between the positive DC input voltage and the negative DC input voltage; An input for receiving data representing a phase voltage requirement required by the motor; and a controller for controlling each of the switches by pulse width modulation (PWM) during a plurality of PWM cycles to generate the multi-phase AC output voltage for the motor, The controller is configured to: The upper switch pair or the lower switch pair is controlled respectively to simultaneously apply a corresponding positive bias voltage or negative bias voltage to each of the phase output voltages, wherein the positive bias voltage and the negative bias voltage respectively represent the average peak-to-peak voltage of the phase output voltage that is positively biased or negatively biased relative to the intermediate DC voltage.

2. The converter according to claim 1, characterized in that Respectively controlling the upper switch pair or the lower switch pair to apply the corresponding positive bias voltage or negative bias voltage comprises: The positive bias voltage and the negative bias voltage applied to each of the phase output voltages are determined based on one or more of a bias voltage buffer amount, an output phase voltage requirement, the negative DC input voltage, the positive DC input voltage, and an output load power factor, wherein the bias voltage buffer amount represents a minimum voltage difference between a peak phase output voltage and the corresponding positive DC input voltage and negative DC input voltage.

3. The converter according to claim 2, characterized in that Respectively controlling the upper switch pair or the lower switch pair to apply the corresponding positive bias voltage or negative bias voltage comprises: A positive intermediate voltage target value and a negative intermediate voltage target value are determined based on one or more of the positive bias voltage or the negative bias voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage requirement, the intermediate voltage target value buffer amount, and the frequency of the intermediate DC voltage, wherein the positive intermediate voltage target value and the negative intermediate voltage target value represent the target voltage deviation of the intermediate DC voltage.

4. The converter according to claim 2 or 3, characterized in that: When the difference between the positive bias voltage or the negative bias voltage and the intermediate DC voltage is greater than a threshold voltage, the controller applies the positive bias voltage or the negative bias voltage accordingly.

5. The converter according to claim 3 or 4, characterized in that: For a first PWM cycle, the controller determines which one of the positive bias voltage and the negative bias voltage to apply according to a difference between the positive bias voltage and the intermediate DC voltage and a difference between the negative bias voltage and the intermediate DC voltage.

6. The converter according to claim 5, characterized in that For the first PWM cycle, when the controller applies the positive bias voltage or the negative bias voltage, the controller is configured to: apply the positive bias voltage when the difference between the positive bias voltage and the intermediate DC voltage is greater than the difference between the negative bias voltage and the intermediate DC voltage; apply the negative bias voltage when the difference between the negative bias voltage and the intermediate DC voltage is greater than the difference between the positive bias voltage and the intermediate DC voltage.

7. The converter according to claim 5 or 6, characterized in that: For subsequent PWM cycles, when the controller controls the upper switch pair to apply the positive bias voltage, and when the intermediate DC voltage approaches the positive intermediate voltage target value, the controller is configured to apply the negative bias voltage to the phase output voltage by controlling the lower switch pair.

8. The converter according to claim 5, 6 or 7, characterized in that For subsequent PWM cycles, when the controller controls the lower switch pair to apply the negative bias voltage, and when the intermediate DC voltage approaches the negative intermediate voltage target value, the controller is configured to apply the positive bias voltage to the phase output voltage by controlling the upper switch pair.

9. The converter according to claim 7 or 8, characterized in that: When the controller switches between applying the positive bias voltage and applying the negative bias voltage, the controller controls the upper switch pair and / or the lower switch pair to apply a slope to a deviation voltage between the positive bias voltage and the negative bias voltage.

10. A converter according to any preceding claim, characterised in that The intermediate DC voltage is provided by a capacitive voltage divider disposed between the positive DC input terminal and the negative DC input terminal.

11. The converter according to any one of claims 1 to 9, characterized in that The intermediate DC voltage is provided by a second DC source.

12. A method for generating a multi-phase output voltage for powering a motor, characterized in that: include: receiving a positive DC input voltage and a negative DC input voltage; receiving data, the data representing a phase voltage requirement required by the motor; Controlling a plurality of switches in a plurality of PWM cycles by pulse width modulation (PWM) to generate the multi-phase AC output voltage for the motor, the plurality of switches being arranged into a plurality of groups, one group for each phase, wherein for each phase, a corresponding group of switches is arranged in a T-type structure between a DC input terminal and a corresponding AC phase output terminal, the T-type structure comprising: an upper switch connected between a positive DC input terminal and a corresponding AC phase output terminal, a lower switch connected between a corresponding AC phase output terminal and a negative DC input terminal, and a middle upper switch and a middle lower switch connected between the AC phase output terminal and an intermediate DC voltage, each of the switches being arranged into a corresponding upper switch pair and a lower switch pair, the upper switch pair comprising the upper switch and the middle lower switch, the lower switch pair comprising the lower switch and the middle upper switch, the intermediate DC voltage being a voltage between the positive DC input voltage and the negative DC input voltage; and outputting the multi-phase AC output voltage to drive the motor, Wherein, for each PWM cycle, controlling the plurality of switches comprises: The upper switch pair or the lower switch pair is controlled respectively to simultaneously apply a corresponding positive bias voltage or negative bias voltage to each phase output voltage, wherein the positive bias voltage and the negative bias voltage respectively represent the average peak-to-peak voltage of the phase output voltage that is positively biased or negatively biased relative to the intermediate DC voltage.

13. The method according to claim 12, characterized in that Respectively controlling the upper switch pair or the lower switch pair to apply the corresponding positive bias voltage or negative bias voltage comprises: The positive bias voltage and the negative bias voltage applied to each of the phase output voltages are determined based on one or more of a bias voltage buffer amount, an output phase voltage requirement, the negative DC input voltage, the positive DC input voltage, and an output load power factor, wherein the bias voltage buffer amount represents a minimum voltage difference between a peak phase output voltage and the corresponding positive DC input voltage and negative DC input voltage.

14. The method according to claim 13, characterized in that Respectively controlling the upper switch pair or the lower switch pair to apply the corresponding positive bias voltage or negative bias voltage comprises: A positive intermediate voltage target value and a negative intermediate voltage target value are determined based on one or more of the positive bias voltage or the negative bias voltage, the negative DC input voltage, the positive DC input voltage, the phase voltage requirement, the intermediate voltage target value buffer amount, and the frequency of the intermediate DC voltage, wherein the positive intermediate voltage target value and the negative intermediate voltage target value represent the target voltage deviation of the intermediate DC voltage.

15. The method according to claim 13 or 14, characterized in that When the difference between the positive bias voltage or the negative bias voltage and the intermediate DC voltage is greater than a threshold voltage, the positive bias voltage or the negative bias voltage is applied accordingly.

16. The method according to claim 14 or 15, characterized in that For a first PWM cycle, it is determined whether to apply the positive bias voltage or the negative bias voltage according to a difference between the positive bias voltage and the intermediate DC voltage and a difference between the negative bias voltage and the intermediate DC voltage.

17. The method according to claim 16, characterized in that For the first PWM cycle, when applying the positive bias voltage or the negative bias voltage: when the difference between the positive bias voltage and the intermediate DC voltage is greater than the difference between the negative bias voltage and the intermediate DC voltage, the positive bias voltage is applied; when the difference between the negative bias voltage and the intermediate DC voltage is greater than the difference between the positive bias voltage and the intermediate DC voltage, the negative bias voltage is applied.

18. The method according to claim 16 or 17, characterized in that For subsequent PWM cycles, when the upper switch pair is controlled to apply the positive bias voltage, and when the intermediate DC voltage approaches the positive intermediate voltage target value, the negative bias voltage is applied to the phase output voltage by controlling the lower switch pair.

19. The method according to claim 16, 17 or 18, characterized in that For subsequent PWM cycles, when the lower switch pair is controlled to apply the negative bias voltage, and when the intermediate DC voltage approaches the negative intermediate voltage target value, the positive bias voltage is applied to the phase output voltage by controlling the upper switch pair.

20. The method according to claim 18 or 19, characterized in that When switching between applying the positive bias voltage and applying the negative bias voltage, the upper switch pair and / or the lower switch pair are controlled to apply a slope to a deviation voltage between the positive bias voltage and the negative bias voltage.

21. A method according to any preceding claim, characterised in that include: The intermediate DC voltage is provided by a capacitive voltage divider disposed between the positive DC input terminal and the negative DC input terminal.

22. The method according to any one of claims 12 to 20, characterized in that include: The intermediate DC voltage is provided from a second DC source.

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