Resistive random access memory device with compound non-reactive electrode

Abstract

The invention relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode, a second electrode including a first conductive material, and a switching oxide layer between the first electrode and the second electrode. The switching oxide layer includes at least one transition metal oxide. The first electrode includes a metal nitride layer including a metal nitride and a metal layer fabricated on the metal nitride layer. The metal layer includes a metal that does not react with the at least one transition metal oxide. In some embodiments, the metal nitride in the first electrode includes titanium nitride and / or tantalum nitride. The metal layer includes a noble metal layer, such as platinum, palladium, iridium or ruthenium, etc.

Description

Technical Field

[0001] The disclosed embodiments generally relate to a resistive random access memory (RRAM), and more particularly, to a RRAM device having a compound non-reactive electrode. Background Art

[0002] An RRAM device is a two-terminal passive device with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form a crossbar array, which can be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc. Summary of the invention

[0003] The following is a brief summary of the present disclosure, which is used to provide a basic understanding of some aspects of the present disclosure. The summary is not an extensive overview of the present disclosure. The summary is not intended to identify the key or important elements of the present disclosure, nor is it intended to illustrate any scope of a particular implementation of the present disclosure or any scope of the claims. The sole purpose of the summary is to present some concepts of the present disclosure as a language simplification of a more detailed description presented subsequently.

[0004] According to one or more aspects of the present disclosure, a resistive random access memory (RRAM) device includes: a first electrode, a second electrode including a first conductive material; and a switching oxide layer located between the first electrode and the second electrode. The first electrode includes a metal nitride layer including a metal nitride and a metal layer fabricated on the metal nitride layer. The switching oxide layer includes at least one transition metal oxide. In some embodiments, the metal layer includes a metal that does not react with the at least one transition metal oxide.

[0005] In some embodiments, the metal nitride includes at least one of titanium nitride or tantalum nitride.

[0006] In some embodiments, the metal that is unreactive with the at least one transition metal oxide comprises at least one of platinum, palladium, iridium, or ruthenium.

[0007] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0008] In some embodiments, the thickness of the metal layer is between 3 nm and 10 nm.

[0009] In some embodiments, the metal nitride layer has a thickness between 20 nm and 50 nm.

[0010] In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x≤2.0 and y≤2.5.

[0011] In some embodiments, the conductive material in the second electrode includes tantalum.

[0012] In some embodiments, the RRAM device further comprises an interface layer between the switching oxide layer and the second electrode. In some embodiments, the interface layer comprises aluminum oxide.

[0013] In some embodiments, the RRAM device further includes an adhesion layer including at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

[0014] According to one or more methods disclosed in the present disclosure, a method for manufacturing a resistive random access memory (RRAM) device includes: manufacturing a first electrode; manufacturing the switching oxide layer on the first electrode; and manufacturing a second electrode including a conductive material on the switching oxide layer. The switching oxide layer includes at least one transition metal oxide. The first electrode includes: a metal nitride layer and a metal layer. The metal nitride layer includes a metal nitride. The metal layer is manufactured on the metal nitride layer. In some embodiments, the metal layer includes a metal that does not react with the at least one transition metal oxide.

[0015] In some embodiments, the metal nitride includes at least one of titanium nitride or tantalum nitride.

[0016] In some embodiments, the metal that is unreactive with the at least one transition metal oxide comprises at least one of platinum, palladium, iridium, or ruthenium.

[0017] In some embodiments, the metal layer is thinner than the metal nitride layer.

[0018] In some embodiments, the thickness of the metal layer is between 3 nm and 10 nm.

[0019] In some embodiments, the metal nitride layer has a thickness between 20 nm and 50 nm.

[0020] In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, wherein x≤2.0 and y≤2.5.

[0021] In some embodiments, the method further comprises fabricating an interfacial layer on the switching oxide layer, wherein the interfacial layer is located between the switching oxide layer and the second electrode, and the interfacial layer comprises aluminum oxide.

[0022] In some embodiments, the method further comprises fabricating an adhesion layer comprising at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

[0023] According to one or more aspects of the present disclosure, a method for manufacturing a non-reactive electrode includes: manufacturing an adhesion layer including at least one of titanium or tantalum; manufacturing a metal nitride layer including at least one metal nitride on the adhesion layer, wherein the metal nitride includes at least one of titanium nitride or tantalum nitride; manufacturing a metal layer including a noble metal on the metal nitride layer; and selectively removing one or more portions of the adhesion layer, the metal nitride layer, and the metal layer to manufacture the non-reactive electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0025] Figure 1 is a schematic diagram showing an example of a crossbar switch circuit according to some embodiments of the present disclosure.

[0026] Figure 2 is a schematic diagram showing an example of a cross-point device according to some embodiments of the present disclosure.

[0027] Figure 3A A cross-sectional view of an example RRAM device according to some embodiments of the present disclosure is shown.

[0028] Figure 3B and Figure 3C They are shown respectively Figure 3A Cross-sectional view of the RRAM device in low-resistance state and high-resistance state.

[0029] Figure 4 A cross-sectional view of an example 400 of a compound non-reactive electrode according to another embodiment of the present disclosure is shown.

[0030] Figure 5 , Figure 6 and Figure 7 A cross-sectional view of an example RRAM device according to some embodiments of the present disclosure is shown.

[0031] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Figure 8F is a schematic diagram of a structural cross-sectional view of a non-reactive electrode for manufacturing an RRAM device according to some embodiments of the present disclosure.

[0032] Fig.9A shows IV (current-voltage) characteristics of RRAM devices according to some embodiments of the present disclosure;

[0033] Fig. 9B is an IV curve showing simulated behavior of a RRAM device according to some embodiments of the present disclosure;

[0034] Fig. 9C is a graph showing device read current characteristics over time of an example RRAM device according to some embodiments of the present disclosure.

[0035] Fig.10 is a flow chart illustrating an example method for fabricating a RRAM device according to some embodiments of the present disclosure.

[0036] Fig.11 is a flow chart illustrating an example of a method for manufacturing a non-reactive electrode according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] Various aspects of the present disclosure provide RRAM devices and methods for making RRAM devices. An RRAM device is a two-terminal passive device with adjustable resistance. The RRAM device may include a first electrode, a second electrode, and a switching oxide layer located between the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode may be the bottom electrode and the top electrode of the RRAM device, respectively. In some embodiments, the first electrode and the second electrode may be the top electrode and the bottom electrode of the RRAM device, respectively. The first electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), ruthenium (Ru), etc. The second electrode may include a reactive metal, such as tantalum (Ta). An electrode including a non-reactive metal may also be referred to as a "non-reactive electrode". An electrode including a reactive metal may also be referred to as a "reactive electrode". The switching oxide layer may include a transition metal oxide, such as hafnium oxide (HfO x ) or tantalum oxide (TaO x). The RRAM device may be in an initial state or original state and have an initial high resistance before it receives an appropriate electrical stimulus (e.g., a voltage or current signal applied to the RRAM device). The RRAM device may be converted from the original state to a low resistance state through a formation process, or may be switched from a high resistance state to a low resistance state through a setting process. The formation process refers to programming the device from the original state. The setting process refers to programming the device from a high resistance state (HRS). After the reactive metal electrode is deposited on the switching oxide, the reactive metal may absorb oxygen ions from the switching oxide layer, creating oxygen vacancies in the switching oxide layer, and the oxygen ions may migrate in the switching oxide through a vacancy mechanism. During the formation process, an appropriate programming signal (e.g., a voltage or current signal) applied to the RRAM device may cause oxygen ions to drift and migrate from the switching oxide to the reactive electrode. Therefore, a conductive channel or conductive filament may pass through the switching oxide layer (e.g., from a reactive electrode to a non-reactive electrode). Then, the RRAM device may be reset to a high resistance state by applying a reset signal (e.g., a voltage signal, a current signal) to the RRAM device. Applying the reset signal to the RRAM device can cause the oxygen ions to migrate back to the switching oxide layer, thereby possibly interrupting the conductive filament. By applying an appropriate programming signal (e.g., a voltage signal, a current signal) to the RRAM device, the RRAM device can be electrically switched between a high resistance state and a low resistance state. In a crossbar array circuit, the programming signal can be provided to a specified RRAM device through a selector, such as a transistor or a diode.

[0038] An RRAM device containing platinum (Pt) in a non-reactive electrode can provide RRAM high performance, such as reliability, durability, multi-level, retention, etc. In an RRAM device including a bottom electrode containing platinum, a switching oxide layer including tantalum oxide, and a Ta-containing switching oxide layer (also referred to as "Pt / TaO x / Ta system”), TaO x The Ta wire in the Pt / HfO x In the / Ta system, Ta can migrate to HfO x Thus in HfO x Ta-rich filaments are formed in ferrite and have demonstrated excellent linearity, simulation, retention, and durability in IMC applications. However, platinum has high material and processing costs, and major manufacturing plants may not be ready to incorporate platinum into their production processes.

[0039] According to some embodiments of the present disclosure, the compound non-reactive electrode of the RRAM device may include a metal nitride layer and a metal layer. The metal nitride layer may include one or more metal nitrides, such as TiN, TaN, etc. The metal layer may include a non-reactive metal, such as Pt, Pd, Ru, Ir, etc. The metal layer may be much thinner than the metal nitride. For example, in some embodiments, the metal nitride layer may be between about 20nm and 25nm, and the metal layer may be between about 3nm and about 8nm.

[0040] Both TiN and TaN are conductive materials and are also compatible with CMOS processes, can be mass-produced, and have a much lower production cost than Pt. RRAM devices containing TiN or TaN in non-reactive electrodes can exhibit specific characteristics required for IMC applications, such as multi-level switching resistance and / or analog behavior. RRAM devices with non-reactive electrodes containing Pt can have better performance than RRAM devices with non-reactive electrodes that include TiN or TaN alone, but may be more expensive. By combining a metal nitride layer and a metal layer that is much thinner than the metal nitride layer (e.g., a layer of Pt, Pd, Ru, Ir, etc.), the compound non-reactive electrode described in this article provides a cost-effective solution for manufacturing RRAM devices with desired switching and analog resistance behaviors.

[0041] Compared with conventional RRAM devices using Pt-based non-reactive electrodes, the RRAM devices using compound non-reactive electrodes disclosed in the present disclosure have lower material and manufacturing costs, can be used in CMOS processes, and can be mass-produced. The RRAM devices disclosed herein exhibit appropriate performance and capabilities in multi-level switching and analog behavior.

[0042] Figure 11 is a schematic diagram showing an example 100 of a crossbar switch circuit according to some embodiments of the present disclosure. As shown, the crossbar switch circuit 100 may include a plurality of interconnected conductive lines for a crossbar array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n, and column lines 113a, 113b, ..., 113j, ..., 113m. The crossbar switch circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect a row line and a column line. For example, the crosspoint device 120ij may connect a row line 111i and a column line 113j. In some embodiments, the crossbar switch circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and one or more suitable circuit components for implementing a crossbar-based device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

[0043] The row lines 111 may include a first row line 111a, a second row line 111b, ..., an i-th row line 111i, ..., and an n-th row line 111n. Each row line 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

[0044] The column lines 113 may include a first column line 113a, a second column line 113b, ... and an mth column line 113m. Each column line 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

[0045] Each cross-point device 120 may be and / or include any suitable device having an adjustable resistance, such as a memristor, a phase change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include, for example, a combination of Figure 3A-9C RRAM devices are described.

[0046] The crossbar switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar switch circuit 100. The input signal can flow through the crosspoint devices of the rows of the crossbar switch circuit 100. The conductance of the crosspoint device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductance and generates a current flowing through the crosspoint device. Through Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductance matrix of the crosspoint device. Therefore, the input signal is weighted by its conductance at each crosspoint device according to Ohm's law. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computing (IMC).

[0047] Figure 2 2 is a schematic diagram showing an example 200 of a cross-point device according to an embodiment of the present disclosure. As shown, the cross-point device 200 can connect a bit line (BL) 211, a select line (SEL) 213, and a word line (WL) 215. The bit line 211 and the word line 215 can be respectively as shown in FIG. Figure 1 The column lines and row lines.

[0048] The cross-point device 200 may include a RRAM device 201 and a transistor 203. A transistor is a three-terminal device, which may be labeled as a gate (G), a source (S), and a drain (D). The transistor 203 may be connected in series to the RRAM device 201. Figure 2 As shown, the first electrode of the RRAM device 201 may be connected to the drain of the transistor 203. The second electrode of the RRAM device 201 may be connected to the bit line 211. The source of the transistor 203 may be connected to the word line 215. The gate of the transistor 203 may be connected to the select line 213. The RRAM device 201 may include a combination of the following Figure 3A-9COne or more RRAM devices described. The cross-point device 200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 203 may be used as a selector and a current controller, which may set the current compliance of the RRAM device 201 during programming. The gate voltage of the transistor 203 may set the current compliance of the cross-point device 200 during programming, and thus control the conductance and analog behavior of the cross-point device 200. For example, when the cross-point device 200 is set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) may be provided via a bit line (BL) 211. Another voltage, also referred to as a select voltage or a gate voltage, may be applied to the transistor gate via a select line (SEL) 213 to turn on the gate and set the current compliance, while a word line (WL) 215 may be set to ground. When the cross-point device 200 is reset from a low-resistance state to a high-resistance state, a gate voltage may be applied to the gate of the transistor via a select line 213 to turn on the transistor gate. At the same time, a reset signal may be sent to the RRAM device 201 via the word line 215 , while the bit line 211 may be set to ground.

[0049] Figure 3A , 3B 3C show cross-sectional views of example RRAM devices 300a, 300b, and 300c according to some embodiments of the present disclosure. The RRAM devices 300b and 300c may correspond to the low resistance state and the high resistance state of the RRAM device 300a, respectively.

[0050] like Figure 3A As shown, the RRAM device 300a may include a substrate 310, a first electrode 320 fabricated on the substrate 310, a switching oxide layer 330, and a second electrode 340. The switching oxide layer 330 is fabricated between the first electrode 320 and the second electrode 340. The substrate 310 may include one or more layers of any suitable material that can be used for a RRAM device substrate, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include a diode, a transistor, an interconnect, an integrated circuit, etc. In some embodiments, the substrate may include a driving circuit, which includes one or more circuits (e.g., a circuit array) that can be controlled individually. In some embodiments, the driving circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

[0051] The first electrode 320 may include a metal nitride that is conductive and non-reactive to the fabricated switching oxide layer. The metal nitride may have suitable chemical stability so that it does not react with oxygen during RRAM switching. The metal nitride may include, for example, titanium nitride (TiN), tantalum nitride (TaN), etc. The first electrode 320 may also include a non-reactive metal that has electronic conductivity and does not react with oxygen during RRAM switching, such as platinum (Pt), palladium (Pd), iridium (Ir), ruthenium (Ru), etc. RRAM devices having metal nitrides and non-reactive metals at their non-reactive electrodes have multi-level resistance and analog behavior required for IMC applications.

[0052] In some embodiments, the first electrode 320 may be and / or include a combination of Figure 4 The compound bottom electrode described. For example, the first electrode 320 may include a metal nitride layer including one or more metal nitrides (e.g., TiN, TaN, etc.). The first electrode 320 further includes a metal layer including one or more noble metals (e.g., Pt, Pb, Ir, Ru, etc.) manufactured on the metal nitride layer. In some embodiments, the metal layer is thinner than the metal nitride layer.

[0053] In some embodiments, a Ta and / or Ti layer may be fabricated between the first electrode and the substrate 310 to enhance adhesion between the substrate 310 and the RRAM device 320 components.

[0054] The switching oxide layer 330 may include one or more transition metal oxides among binary oxides, ternary oxides, and advanced oxides, such as TaO x , HfO x 、TiO x 、NbO x 、ZrO x In some embodiments, the chemical stability of the non-reactive material in the first electrode 320 may be higher than the chemical stability of the transition metal oxide in the switching oxide layer 330. In some embodiments, the transition metal oxide includes HfO x or TaO x At least one of: wherein x can be used to indicate that the oxide is oxygen deficient compared to its complete (or terminal) oxide, and the value of x can vary depending on the ratio of oxygen to metal atoms in the stoichiometry of its complete oxide, for example, for HfO x (where HfO2 is a complete oxide) x≤2.0, for TaO x (where Ta2O5 is a complete oxide), x≤2.5.

[0055] The second electrode 340 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the second electrode 340 may include Ta, Hf, Ti, TiN, TaN, etc. The second electrode 340 may react with the switching oxide and have a suitable oxygen solubility so that oxygen can be absorbed from the switching oxide layer 330 and oxygen vacancies can be generated in the switching oxide layer 330. In other words, the reactive metal material in the second electrode 340 may have a suitable oxygen solubility and / or oxygen mobility. In some embodiments, the second electrode 340 may not only generate oxygen vacancies in the switching oxide layer 330 (e.g., by scavenging oxygen), but may also act as an oxygen storage or oxygen source for the switching oxide layer 330 during cell programming.

[0056] The RRAM device 330a may have an initial resistance (also referred to herein as “original resistance”) after fabrication. The initial resistance of the RRAM device 300a may be changed, and the RRAM device 300a may be switched to a state of lower resistance through a formation process. For example, an appropriate voltage or current may be applied to the RRAM device 300a. The voltage applied to the RRAM device 300a may cause the metal material in the second electrode to absorb oxygen from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer. As a result, a conductive channel (e.g., a conductive filament) rich in oxygen vacancies may be formed in the switching oxide layer 330. For example, as Figure 3B As shown, a conductive channel 335a can be formed in the switching oxide layer. As shown, the conductive channel 335a can cross the switching oxide layer 330 from the second electrode 340 to the first electrode 320. The RRAM device 300b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 300b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, such as a positive signal and a negative signal, respectively. The application of the reset signal can cause oxygen to drift back to the switching oxide layer 330 and recombine with one or more oxygen vacancies. For example, during the reset process, a conductive channel 335a can be formed in the switching oxide layer 330. Figure 3C As shown, the conductive channel can be interrupted by an oxide gap located between the interrupted conductive channel 335b and the first electrode 320. The lateral dimension of the interrupted conductive channel 335b can be smaller than the lateral dimension of the conductive channel 335a. In some embodiments, the interrupted conductive channel 335b discontinuously connects the first electrode 320 and the second electrode 340. The RRAM device 300a-c can be electrically switched between a high resistance state and a low resistance state by applying an appropriate programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0057] In one embodiment, the second electrode 340 may include one or more alloys. Each alloy may include two or more metal elements. Each alloy may include a binary alloy (e.g., an alloy containing two metal elements), a ternary alloy (e.g., an alloy containing three metal elements), a quaternary alloy (e.g., an alloy containing four metal elements), a quinary alloy (e.g., an alloy containing five metal elements), and / or a high-order alloy (e.g., an alloy containing more than six metal elements). In some embodiments, the second electrode 340 may include one or more alloys, the alloy containing a first metal element and one or more second metal elements. Each second metal element has a reactivity less than or greater than the first metal element to the transition metal oxide in the switching oxide layer. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of tungsten (W), hafnium (Hf), molybdenum (Mo), niobium (Nb), zirconium (Zr), etc. In some embodiments, the ratio of the first metal element to the second metal element in the alloy of the second electrode 340 may be 50 atomic percent. In some embodiments, the appropriate ratio of the first metal element to the second metal element in the alloy may be optimized from the entire composition range. During the formation process, the second metal element can generate less oxygen vacancies in the switching oxide layer than the first metal element. Therefore, the lateral size of the conductive filament formed in the RRAM device including the second electrode containing the alloy can be smaller than the lateral size of the conductive filament formed in the RRAM device including the second electrode made of only the first metal.

[0058] In one embodiment, the second electrode 340 may include multiple layers of different metal materials. For example, the second electrode 340 may include a titanium (Ti) layer and a tantalum (Ta) layer. The Ti layer may be much thinner than the Ta layer. For example, the thickness of the Ti layer may be between about 0.2nm and 5nm. The thickness of the Ta layer may be about 50nm. In some embodiments, the thickness of the Ti layer may be between 0.3nm and 2nm. Both Ti and Ta can capture and release oxygen during device operation. Adding a thin Ti layer to a RRAM device can change the original resistance of the RRAM device, resulting in a less obtrusive formation process, lowering the formation voltage, lowering the reset current, and reducing the voltage and / or current requirements in subsequent operations.

[0059] Figure 4 A cross-sectional view of an example of a compound non-reactive electrode 400 in accordance with another embodiment of the present disclosure is shown.

[0060] As shown, the non-reactive electrode 400 may include a metal nitride layer 410 and a metal layer 420. The metal layer 420 may be fabricated on the metal nitride layer 410. The metal nitride layer 410 may include one or more layers of one or more metal nitrides. Examples of the metal nitrides may include TiN, TaN, etc. The metal layer 420 may include one or more noble metals (e.g., Pt, Pb, Ru, etc.). In some embodiments, the metal layer 420 may be thinner than the metal nitride layer 410. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20nm and about 25nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20nm and about 50nm. In some embodiments, the thickness of the metal nitride layer 410 may be between about 20nm and about 30nm. The thickness of the metal layer 420 may be between about 3nm and about 10nm. In some embodiments, the metal layer 420 may be thicker than 2-3nm and may include a continuous film of a noble metal covering the metal nitride layer 410.

[0061] Figure 5 A cross-sectional view of an example RRAM device 500 including a compound non-reactive electrode in accordance with one embodiment of the present disclosure is shown.

[0062] The RRAM device 500 may include an adhesive layer 510, a first electrode 520, a switching oxide layer 530, an interface layer A (ILA) 550, and a second electrode 540. The first electrode 520, the switching oxide layer 530, and the second electrode 540 may be bonded to the adhesive layer 510, respectively. Figure 3A The first electrode 320, the switching oxide layer 330 and the second electrode 340 are the same. As shown in the figure, the first electrode 520 may include a combination of Figure 4 The metal nitride layer 410 and the metal layer 420 are shown. In some embodiments, the adhesion layer 510 can be considered as a part of the first electrode 520.

[0063] The adhesion layer 510 may include one or more suitable metallic materials that may enhance adhesion between the substrate and the components of the RRAM device 500. In some embodiments, the adhesion layer 510 may include one or more layers of Ti, Ta, or the like.

[0064] ILA 550 (also referred to as a "first interface layer") may include a first material that is more chemically stable than the transition metal oxide in the switching oxide layer. The first material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. ILA 550 may include a discontinuous film of the first material and / or a continuous film of the first material. In some embodiments, the thickness of ILA 550 may be between about 0.2nm and about 0.5nm. In some embodiments, ILA 550 may include an Al2O3 film having a thickness equal to or less than 0.5nm. In some embodiments, ILA 550 may be and / or include an Al2O3 film having a thickness less than 1nm. In the case where ILA 550 includes aluminum oxide, the RRAM device may be a high resistance and annealing resistant RRAM device.

[0065] Figure 6 A cross-sectional view of an example RRAM device 600 including a compound non-reactive electrode in accordance with further embodiments of the present disclosure is shown.

[0066] The RRAM device 600 may include an adhesive layer 610, a first electrode 620, an interface layer B (ILB) 660, a switching oxide layer 630, an interface layer A (ILA) 650, and a second electrode 640. The first electrode 620, the switching oxide layer 630, and the second electrode 640 may be respectively bonded to Figure 3A The first electrode 320, the switching oxide layer 330 and the second electrode 340 are the same. The adhesive layer 610 may be Figure 5 The ILA 650 can be the same as the adhesive layer 510 in FIG. Figure 5 In some embodiments, the RRAM device 600 may further include a combination of Figure 3A A substrate (not shown) is described.

[0067] ILB 660 may include a second material that is more chemically stable than the transition metal oxide in the switching oxide layer 630. The second material may include, for example, Al2O3, MgO, Y2O3, La2O3, etc. ILB 660 may include a discontinuous film of the second material and / or a continuous film of the second material. In some embodiments, the thickness of ILB 660 may be between about 0.2nm and about 0.5nm. In some embodiments, ILB 660 may include an Al2O3 film having a thickness equal to or less than 0.5nm. In some embodiments, ILB 660 may be and / or include an Al2O3 film having a thickness less than 1nm. With the first interface layer and the second interface layer, the RRAM device may be a high resistance and annealing resistant RRAM device.

[0068] In some embodiments, the ILA 650 may be omitted from the RRAM device 600. For example, Figure 7 As shown, the RRAM device 700 may include Figure 6 An adhesion layer 610 , a first electrode 620 , an interface layer B (ILB) 660 , a switching oxide layer 630 , and a second electrode 640 are depicted.

[0069] Fig. 8A , 8B , 8C, 8D, 8E and 8F are schematic diagrams showing structural cross-sectional views of non-reactive electrodes in manufacturing RRAM devices according to some embodiments of the present disclosure.

[0070] like Fig. 8A As shown, a substrate 810 may be provided. The substrate 810 may include one or more layers of any suitable material that can be used to manufacture a substrate of an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 810 may include diodes, transistors, interconnects, integrated circuits, etc. The substrate 810 may include a drive circuit that can individually control one or more circuits (e.g., a circuit array). In some embodiments, the drive circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers. In some embodiments, the substrate 810 may include one or more dielectric layers, interconnect layers, transistors, and / or any other suitable components (not shown) for manufacturing crossover circuits. Each interconnect layer may include one or more metal pads and / or metal vias, and may provide electrical connections between devices manufactured on the substrate 810.

[0071] like Fig. 8A As shown, the substrate 810 may include an interconnect layer including one or more metal interconnects (e.g., metal pads and / or metal vias). For example, the first interconnect layer may include metal interconnects 811a and 811b (also referred to as "first metal interconnects" and "second metal interconnects"). In some embodiments, the metal interconnects 811a and 811b may be metal pads including tungsten (W), Al, Cu, and any other suitable metal. In some embodiments, the metal interconnects 811a and 811b may be metal vias including aluminum (Al), copper (Cu), tungsten (W), etc. Each of the metal interconnects 811a and 811b may be connected to other components (not shown), such as transistors, diodes, etc. In some embodiments, the metal interconnects 811a-b may include tungsten (W) holes and doped polysilicon (poly-Si) terminals, wherein the polysilicon terminals may be connected to transistor or diode terminals (not shown).

[0072] like Figure 8BAs shown, adhesion layer 821 may be fabricated on metal interconnects 811a and 811b and substrate 810. Adhesion layer 821 may include a Ta layer, a Ti layer, and / or a layer of any suitable material that may enhance adhesion of substrate 810 and other components in a RRAM device fabricated thereon.

[0073] like Figure 8C As shown, a metal nitride layer 823 may be fabricated on the adhesion layer 821. The metal nitride layer 823 may include one or more layers of one or more metal nitrides that are electronically conductive and non-reactive to switching oxides in a RRAM device fabricated on the substrate 810. The metal nitride may include, for example, TiN, TaN, etc.

[0074] like Fig.8D As shown, metal layer 825 may be fabricated on metal nitride layer 823. Metal layer 825 may include one or more layers of one or more suitable metals (also referred to as "non-reactive metals") that are electronically conductive and non-reactive to switching oxides in a RRAM device fabricated on substrate 810. Examples of the non-reactive metals may include Pt, Pd, Ir, Ru, etc.

[0075] One or more portions of the adhesion layer 821, the metal nitride layer 823, and the metal layer 825 may be selectively removed to produce one or more bottom electrodes. Fig. 8E As shown, by patterning and etching the adhesion layer 821, the metal nitride layer 823 and the metal layer 825, the first bottom electrode 820a and the second bottom electrode 820b can be respectively manufactured on the metal interconnection 811a and the metal interconnection 811b. The first bottom electrode 820a may include a first adhesion layer 821a, a first metal nitride layer 823a and a first metal layer 825a. The second bottom electrode 820b may include a second adhesion layer 821b, a second metal nitride layer 823b and a second metal layer 825b. The first adhesion layers 821a and 821b may correspond to the etched adhesion layer 821. The first metal nitride layer 823a and the second metal nitride layer 723b may correspond to the etched metal nitride layer 822. The first metal layer 825a and the second metal layer 825b may correspond to the etched metal layer 825. In some embodiments, the lateral dimensions of the bottom electrodes 820a-b may be greater than the lateral dimensions of the metal interconnections 811a-b. The first bottom electrode 820a may directly contact the metal interconnect 811a to form an ohmic contact. The second bottom electrode 820b may directly contact the metal interconnect 811b to form an ohmic contact. The first bottom electrode 820a and the second bottom electrode 820b may further contact one or more portions of the substrate 810, such as one or more portions of the surface 801 of the substrate 810 (e.g., the top surface of the substrate 810).

[0076] like Figure 8F As shown, the RRAM stack 830a and the RRAM stack 830b can be fabricated on the first bottom electrode 820a and the second bottom electrode 820b, respectively. Each of the RRAM stacks 830a and 830b can include the above-mentioned combination of Figure 3A-7 The switching oxide layer, top electrode, and one or more interface layers are described. In some embodiments, the RRAM stacks 830a and 830b may be fabricated using techniques described in US Patent Application Nos. 17 / 654,476 and 17 / 936,830, which are incorporated herein by reference.

[0077] Fig.9A Graph 900A illustrates IV (current-voltage) characteristics of an example RRAM device including a compound non-reactive electrode according to some embodiments of the present disclosure. Fig. 9B An IV curve 900B showing the simulated behavior of a RRAM device is shown. Fig. 9C Graph 900C shows device read current characteristics of an example RRAM device over time.

[0078] like Fig.9A As shown, the RRAM device provides repeatability and expected set-reset operation for multiple switching (e.g., switch 1, switch 2, and switch 3), demonstrating the stability of multiple switching behaviors. Fig. 9B As shown, the RRAM device exhibits the desired analog behavior. That is, the device resistance can be adjusted to multiple levels (or analog behavior) by controlling the current compliance, and the current is linearly proportional to the voltage (or linear behavior) in each resistance state. Fig. 9C As shown, graph 900C may represent the results of a device retention test of the RRAM device's ability to maintain a resistance level over time, and the results of a read stability test when the RRAM device is subjected to a constant read (with a read voltage of 0.2V) for its ability to maintain a resistance level over time. Fig. 9C As shown, the RRAM device exhibits desirable device read stability over time.

[0079] Fig.10 The invention shows a method for manufacturing an RRAM device (e.g. Figure 5 , Figure 6 and Figure 7 1. A flow chart of a method example 1000 of implementing the RRAM device 500, 600, and 700 shown in FIG.

[0080] In 1010, a first electrode may be fabricated on a substrate. Fabricating the first electrode may include depositing one or more layers of a metal nitride, such as TiN or TaN. For example, fabricating the first electrode may include depositing one or more layers of TiN using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a Ti reactive sputtering technique, and / or any other suitable deposition technique. Fabricating the first electrode may further include depositing one or more non-reactive metals on the metal nitride. The first electrode may be and / or include a combination of the above. Figure 4 In some embodiments, manufacturing the first bottom electrode may involve performing the following Fig.11 One or more operations described.

[0081] In 1020, an interface layer B (ILB) may be formed on the first electrode. The ILB may include a transition metal oxide (e.g., AlO) in a switching oxide layer described later. x, For example, fabricating the interface layer B may include depositing AlO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, an Al reactive sputtering technique, and / or any other suitable deposition technique. x The interface layer B may be and / or include the above combination Figure 6 Described ILB 660. In some embodiments, step 1020 may be omitted from method 1000.

[0082] In 1030, the switching oxide layer including one or more transition metal oxides may be fabricated on the interface layer B. The transition metal oxide may include, for example, HfO x For example, fabricating the switching oxide layer may include depositing HfO using an atomic layer deposition (ALD) technique, a physical vapor deposition (PVD) technique, a reactive sputtering technique of Hf, and / or any other suitable deposition technique. x The switching oxide layer may be and / or include a combination of the above Figure 6 The switching oxide layer 630 .

[0083] In 1040, an interfacial layer A (ILA) may be fabricated on the switching oxide layer. The ILA may include a metal that is more chemically stable than the transition metal oxide in the switching oxide layer, such as AlO. x , such as Al2O3. For example, manufacturing the interface layer A may include depositing AlO using atomic layer deposition (ALD) technology, physical vapor deposition (PVD) technology, Al reactive sputtering technology and / or any other suitable deposition technology. x The interface layer A may be and / or include the above combination Figure 6ILA 650 as described.

[0084] In 1050, a second electrode may be fabricated on the interface layer A. Fabricating the second electrode may involve fabricating one or more layers of one or more metallic materials that are electronically conductive and reactive to the switching oxide. For example, fabricating the second electrode may include depositing one or more Ta layers using a physical vapor deposition (PVD) technique and / or any other suitable deposition technique. The second electrode may be and / or include a combination of the above Figure 6 The second electrode 640.

[0085] Fig.11 A flowchart showing an example method 1100 for manufacturing a non-reactive electrode according to some embodiments of the present disclosure, for example, in combination with Figure 4 and Figures 8A-8F A non-reactive electrode is described.

[0086] In 1110, an adhesion layer may be fabricated on the substrate. Fabricating the adhesion layer may include depositing a metal layer, such as Ta, Ti, etc., which may enhance adhesion between the substrate and the bottom electrode and / or other components of the RRAM device fabricated on the substrate. In some embodiments, fabricating the adhesion layer may involve depositing a Ti film or a Ta film with a thickness between about 2 nm and 5 nm. The adhesion layer may be deposited using a suitable PVD technique and / or any other suitable deposition technique for depositing metals. In some embodiments, step 1110 may be omitted from method 1100.

[0087] In 1120, a metal nitride layer may be fabricated on the adhesion layer. Fabricating the metal nitride layer may involve depositing a metal nitride layer that is non-reactive to the transition metal oxide in the switching oxide layer fabricated on the bottom electrode. For example, fabricating the metal nitride layer may include depositing a layer of TiN, TaN, etc. using ALD, PVD, reactive sputtering techniques, or any other suitable deposition technique.

[0088] At 1130, a metal layer may be fabricated on the metal nitride layer. Fabricating the metal layer may include depositing one or more non-reactive metals described in the present disclosure. In some embodiments, fabricating the metal layer may include depositing Pt, Pd, Ir, Ru, etc. on the metal nitride layer using PVD technology or any other suitable deposition technology. In some embodiments, fabricating the metal layer may include depositing a Pt, Pd, Ir, Ru layer having a thickness between about 3 nm and about 10 nm.

[0089] In some embodiments, at 1140, one or more portions of the adhesion layer, the metal nitride layer, and the metal layer may be selectively removed to produce one or more bottom electrodes. For example, the adhesion layer, the metal nitride layer, and the metal layer may be patterned and etched to produce, for example, a combination of Fig. 8E The first bottom electrode 820a and the second bottom electrode 820b.

[0090] For the sake of brevity of explanation, the method of the present disclosure is depicted and described as a series of actions. However, actions according to the present disclosure can occur in various orders and / or simultaneously, and occur together with other actions that are not proposed and described in the present disclosure. In addition, not all actions of explanation can be required to realize the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can be represented as a series of mutual states via state diagrams or events alternatively.

[0091] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include a target size. Unless otherwise specified or apparent from the context, all numerical values ​​described herein are modified by the term "about."

[0092] As used herein, a range includes all values ​​within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and fractions thereof.

[0093] The present disclosure has been described in detail in the above description. However, it is obvious that the present disclosure can be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

[0094] The terms "first", "second", "third", "fourth", etc. used in this document are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

[0095] The word "example" or "exemplary" as used herein means serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be understood as being more preferred or advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means to include "or" rather than exclude "or". That is, unless otherwise specified or as can be seen from the context, "X includes A or B" means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes both A and B, then in any of the above cases, "X includes A or B" is satisfied. In addition, "a" and "an" used in this application and the appended claims should generally be understood as "one or more", unless otherwise specified or as can be clearly indicated from the context as being directed to a singular form. "One embodiment" or "an embodiment" mentioned in this specification means that a specific feature, structure or characteristic associated with the embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily all refer to the same embodiment.

[0096] As used herein, when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

[0097] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.

Claims

1. A resistive random access memory (RRAM) device, comprising: A first electrode, wherein the first electrode comprises: A metal nitride layer and a metal layer, wherein the metal nitride layer comprises at least one metal nitride, and the metal layer is manufactured on the metal nitride layer; a second electrode, the second electrode comprising a conductive material; and A switching oxide layer is located between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide, wherein the metal layer includes a metal that does not react with the at least one transition metal oxide.

2. The RRAM device according to claim 1, wherein: The metal nitride includes at least one of titanium nitride or tantalum nitride.

3. The RRAM device according to claim 1, wherein: The metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium.

4. The RRAM device according to claim 3, wherein: The metal layer is thinner than the metal nitride layer.

5. The RRAM device according to claim 4, wherein: The thickness of the metal layer is between 3 nm and 10 nm.

6. The RRAM device according to claim 5, wherein: The thickness of the metal nitride layer is between 20 nm and 50 nm.

7. The RRAM device according to claim 1, wherein: The at least one transition metal oxide comprises HfO x or TaO y At least one of , wherein x≤2.0 and y≤2.

5.

8. The RRAM device according to claim 1, wherein: The conductive material in the second electrode includes tantalum.

9. The RRAM device of claim 1, further comprising: An interfacial layer is located between the switching oxide layer and the second electrode, wherein the interfacial layer comprises aluminum oxide.

10. The RRAM device of claim 1, further comprising: An adhesion layer includes at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

11. A method of manufacturing a resistive random access memory (RRAM) device, comprising: Manufacturing a first electrode, comprising: manufacturing a metal nitride layer, wherein the metal nitride layer comprises at least one metal nitride; fabricating a metal layer over the metal nitride layer; fabricating a switching oxide layer on the first electrode, wherein the switching oxide layer comprises at least one transition metal oxide, wherein the metal layer comprises a metal that does not react with the at least one transition metal oxide; and A second electrode is fabricated on the switching oxide layer, the second electrode comprising a conductive material.

12. The method of claim 11, wherein the metal nitride comprises at least one of titanium nitride or tantalum nitride.

13. The method of claim 12, wherein: The metal that does not react with the at least one transition metal oxide includes at least one of platinum, palladium, iridium, or ruthenium. The method of claim 13 , wherein the metal layer is thinner than the metal nitride layer.

15. The method of claim 14, wherein: The thickness of the metal layer is between 3 nm and 10 nm.

16. The method of claim 15, wherein: The thickness of the metal nitride layer is between 20 nm and 50 nm.

17. The method of claim 11, wherein: The at least one transition metal oxide comprises HfO x or TaO y At least one of , wherein x≤2.0 and y≤2.

5.

18. The method of claim 11, further comprising: An interfacial layer is fabricated on the switching oxide layer, wherein the interfacial layer is located between the switching oxide layer and the second electrode, and the interfacial layer comprises aluminum oxide.

19. The method of claim 11, further comprising fabricating an adhesion layer comprising at least one of titanium or tantalum, wherein the metal nitride layer is fabricated on the adhesion layer.

20. A method for making a non-reactive electrode, comprising: producing an adhesion layer, the adhesion layer comprising at least one of titanium or tantalum; fabricating a metal nitride layer on the adhesion layer, wherein the metal nitride layer comprises at least one metal nitride, the at least one metal nitride comprising at least one of titanium nitride or tantalum nitride; and fabricating a metal layer on the metal nitride layer, the metal layer comprising a noble metal; and One or more portions of the adhesion layer, the metal nitride layer, and the metal layer are selectively removed to produce the non-reactive electrode.

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