Display substrate and display device

Abstract

The application provides a display substrate and a display device. The display substrate comprises a substrate, a first transistor, a second transistor, a third transistor, a first light shielding layer and a second light shielding layer. The first transistor is used for detecting ambient light intensity, the second transistor is used for detecting backlight intensity, and the third transistor is used for detecting temperature. The first light shielding layer is used for shielding the lower part of the first transistor and the third transistor, and the second light shielding layer is used for shielding the upper part of the second transistor and the third transistor. Therefore, the working environment parameters of the display panel can be effectively and accurately collected, so that the compensation effect on the display effect is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] In order to improve the color display accuracy of display devices such as mobile phones in different environments, the display effect of the display panel needs to be compensated in a targeted manner. In related technologies, the display effect of the display panel is compensated by detecting the brightness of the display panel using the electrical characteristics of the semiconductor layer of the transistor which is sensitive to brightness. However, for a bottom-gate display substrate, due to the structural limitations of the transistor, it is difficult to balance the external brightness test and the backlight brightness test, which affects the compensation effect of the display device. SUMMARY

[0003] Embodiments of the present application provide a display substrate and a display device to solve the problem of low brightness collection accuracy of the display panel in the prior art, which affects the compensation effect.

[0004] To solve the above problems, the present application is implemented as follows:

[0005] In a first aspect, embodiments of the present application provide a display substrate, comprising:

[0006] A substrate, comprising a display area and a peripheral area surrounding the display area;

[0007] A first transistor disposed in the peripheral area, for detecting the ambient light intensity of the display substrate;

[0008] A second transistor disposed in the peripheral area, for detecting the backlight intensity of the display substrate;

[0009] A third transistor disposed in the peripheral area, for detecting the temperature of the display substrate;

[0010] The display substrate further comprises a gate metal layer, a semiconductor layer formed on the side of the gate metal layer away from the substrate, and a source-drain metal layer formed on the side of the semiconductor layer away from the substrate;

[0011] A first light shielding layer is disposed between the semiconductor layer and the substrate, and the first light shielding layer covers the first projection of the semiconductor layer of the first transistor on the substrate and the third projection of the semiconductor layer of the third transistor on the substrate.

[0012] A second light shielding layer is disposed on the side of the semiconductor layer away from the substrate, and the second light shielding layer covers the second projection of the semiconductor layer of the second transistor on the substrate and the third projection on the substrate.

[0013] The normal projection of the metal layer on the substrate on the side of the semiconductor layer away from the substrate is not overlapped with the first normal projection.

[0014] In some embodiments, the gate metal layer is multiplexed as the first light shielding layer.

[0015] In some embodiments, each of the first transistors shares a same continuous planar gate.

[0016] In some embodiments, the gate metal layer comprises a plurality of gate metal patterns for serving as gates of the first transistors, the plurality of gate metal patterns are arranged apart from each other, and each of the gate metal patterns is for serving as a gate of one or more of the first transistors.

[0017] In some embodiments, the normal projection of the source-drain metal layer on the substrate is overlapped with the interval between the gate metal patterns.

[0018] In some embodiments, the source-drain metal layer comprises a target source-drain metal pattern whose normal projection is overlapped with the interval between the gate metal patterns.

[0019] At least two of the first transistors adjacent to each other share a same target source-drain metal pattern.

[0020] In some embodiments, among a plurality of first transistors arranged in sequence, two adjacent first transistors alternately share a target source-drain metal pattern and a gate metal pattern.

[0021] In some embodiments, the second normal projection of the semiconductor layer of the second transistor on the substrate is at least partially not overlapped with the normal projection of the gate metal layer on the substrate.

[0022] In some embodiments, the gate metal layer and the source-drain metal layer are multiplexed as the second light shielding layer.

[0023] The gate metal layer comprises a gate signal pattern and a gate relay pattern, and the source-drain metal layer comprises a source-drain signal pattern and a source-drain relay pattern.

[0024] The gate signal pattern and the source-drain relay pattern are electrically connected to transmit a gate signal of the second transistor.

[0025] The source-drain signal pattern and the gate relay pattern are electrically connected, and the gate relay pattern is electrically connected with the semiconductor layer of the second transistor to transmit a source-drain signal of the second transistor.

[0026] In some embodiments, the gate metal layer includes a gate signal pattern for transmitting a gate signal, and the source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, a normal projection of the dummy source-drain metal pattern on the substrate covers the second normal projection.

[0027] In some embodiments, the source-drain metal layer includes a source-drain signal pattern and a dummy source-drain metal pattern, a normal projection of the dummy source-drain metal pattern on the substrate covers the second normal projection.

[0028] The display substrate further includes a first electrode layer between the semiconductor layer and the source-drain metal layer, the first electrode layer includes a transfer electrode pattern, the source-drain signal pattern is electrically connected with the transfer electrode pattern, and the transfer electrode pattern is electrically connected with the semiconductor layer of the second transistor.

[0029] In some embodiments, the gate metal layer includes a gate signal pattern for transmitting a gate signal, and the gate signal pattern does not overlap with the second normal projection.

[0030] The display substrate further includes a second gate layer on a side of the source-drain metal layer away from the substrate, a normal projection of the second gate layer on the substrate overlaps with the second normal projection, and the second gate layer is electrically connected with the gate signal pattern.

[0031] In a second aspect, an embodiment of the present application provides a display device including the display substrate of any one of the first aspect.

[0032] The first transistor for detecting ambient light intensity, the second transistor for detecting backlight intensity, and the third transistor for detecting temperature are provided, and the first light shielding layer is used to shield the lower part of the first transistor and the third transistor, and the second light shielding layer is used to shield the upper part of the second transistor and the third transistor, so that the working environment parameters of the display panel can be effectively and accurately collected, and the compensation effect on the display effect is improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0034] Figure 1 is a structural schematic diagram of a display substrate in an embodiment of the present application;

[0035] Figure 2This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0036] Figure 3 This is one embodiment Figure 2 The image shows a cross-sectional view of the display substrate along line A-A'.

[0037] Figure 4 In yet another embodiment Figure 2 The image shows a cross-sectional view of the display substrate along line A-A'.

[0038] Figure 5 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0039] Figure 6 This is one embodiment Figure 5 The image shows a cross-sectional view of the display substrate along line B-B'.

[0040] Figure 7 In yet another embodiment Figure 5 The image shows a cross-sectional view of the display substrate along line B-B'.

[0041] Figure 8 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0042] Figure 9 This is one embodiment Figure 8 The image shows a cross-sectional view of the display substrate along the C-C' direction.

[0043] Figure 10 In yet another embodiment Figure 8 The image shows a cross-sectional view of the display substrate along the C-C' direction.

[0044] Figure 11 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0045] Figure 12 yes Figure 11 The image shows a cross-sectional view of the substrate along line D-D'.

[0046] Figure 13 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0047] Figure 14 yes Figure 13 The image shows a cross-sectional view of the substrate along the E-E' direction.

[0048] Figure 15 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0049] Figure 16 yes Figure 15 The image shows a cross-sectional view of the display substrate along the F-F' direction.

[0050] Figure 17 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0051] Figure 18 This is one embodiment Figure 17 The image shows a cross-sectional view of the substrate along the G-G' direction.

[0052] Figure 19 In yet another embodiment Figure 17 The image shows a cross-sectional view of the substrate along the G-G' direction.

[0053] Figure 20 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0054] Figure 21 yes Figure 20 The image shows a cross-sectional view of the display substrate along the H-H' direction.

[0055] Figure 22 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0056] Figure 23 This is one embodiment Figure 22 The image shows a cross-sectional view of the display substrate along line I-I'.

[0057] Figure 24 This is yet another embodiment. Figure 22 The image shows a cross-sectional view of the display substrate along line I-I'.

[0058] Figure 25 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0059] Figure 26 This is one embodiment Figure 25 The image shows a cross-sectional view of the substrate along line J-J'.

[0060] Figure 27 In yet another embodiment Figure 25 The image shows a cross-sectional view of the substrate along line J-J'.

[0061] Figure 28 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0062] Figure 29 yes Figure 28 The image shows a cross-sectional view of the substrate along the K-K' direction.

[0063] Figure 30 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0064] Figure 31 yes Figure 30 The image shows a cross-sectional view of the substrate along the L-L' direction.

[0065] Figure 32 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0066] Figure 33 This is a schematic diagram of the structure of the display substrate in another embodiment of the present invention;

[0067] Figure 34 Numerical curves of ambient light values ​​at different temperatures and illuminance levels;

[0068] Figure 35 This is a curve showing the backlight contrast value and the G / W relationship in one embodiment of the present invention;

[0069] Figure 36 This is a brightness detection curve under different ambient brightness conditions in one embodiment of the present invention. Detailed Implementation

[0070] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] In the embodiments of this invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Additionally, the use of "and / or" in this application indicates at least one of the connected objects, such as A and / or B and / or C, representing seven possibilities: including A alone, B alone, C alone, and the presence of both A and B, both B and C, both A and C, and the presence of A, B, and C.

[0072] This invention provides a display substrate.

[0073] In some embodiments, the display substrate is exemplarily described as a 7-mask (9-times mask exposure etching process) or a 7-mask bottom grid array substrate.

[0074] In an exemplary embodiment, the 6mask array substrate includes a substrate 101 and a gate metal layer (typically Mo) 102 and a gate insulating layer (typically SiO2 / SiN) sequentially formed on the substrate 101. x103. Semiconductor layer (Poly, low-temperature polycrystalline silicon P-Si is used in LTPS panels) 104. First electrode layer (generally the surface electrode used as the common electrode, usually indium tin oxide ITO), first insulating layer (PVX, generally SiN) x 105. Source & Drain Metal Layer (SD, typically made of titanium aluminum titanium Ti / Al / Ti) 106. Second Insulating Layer (PVX, typically made of SiN) x The first electrode layer (typically a driving electrode) and the second electrode layer (PI) 107 are added. Based on the above-mentioned 6-mask array substrate, after fabricating the source / drain metal layer 106, an insulating layer needs to be fabricated on the 7-mask array substrate.

[0075] The array substrate can be aligned with the color filter substrate to form a liquid crystal cell, in which a liquid crystal layer 108 is disposed. The color filter substrate includes a second liquid crystal alignment layer (PI) 109, a G / W color resist 110, a black matrix (black resin material) 111, and a glass cover plate 112.

[0076] In this embodiment, the substrate 101 includes a display area and a peripheral area surrounding the display area. The display area includes sub-pixels. It should be noted that, in this embodiment, any part of the structure and process of the display substrate itself that is not mentioned can be referred to the relevant technology, and will not be repeated in this application.

[0077] like Figure 1 As shown, in this embodiment, a first transistor 11 for detecting the ambient light intensity of the display substrate, a second transistor 12 for detecting the backlight intensity of the display substrate, and a third transistor 13 for detecting the temperature of the display substrate are provided in the peripheral area.

[0078] The display substrate also includes a first light-shielding layer 21 and a second light-shielding layer 22. The first light-shielding layer 21 is disposed between the semiconductor layer 104 and the substrate 101. The orthogonal projection of the first light-shielding layer 21 on the substrate 101 covers the first orthogonal projection of the semiconductor layer 104 of the first transistor 11 on the substrate 101 and the third orthogonal projection of the semiconductor layer 104 of the third transistor 13 on the substrate 101.

[0079] The second light-shielding layer 22 is disposed on the side of the semiconductor layer 104 away from the substrate 101. The orthographic projection of the second light-shielding layer 22 on the substrate 101 covers the second and third orthographic projections of the semiconductor layer 104 of the second transistor 12 on the substrate 101.

[0080] The orthographic projection of the metal layer on the side of the semiconductor layer 104 away from the substrate 101 on the display substrate does not overlap with the first orthographic projection.

[0081] It should be understood that the display substrate in this embodiment is a bottom gate display substrate, that is, the gate metal layer 102 is located between the semiconductor layer 104 and the substrate 101.

[0082] In the technical solution of this embodiment, in order to avoid the structure above the first transistor 11 blocking the semiconductor layer 104 of the first transistor 11, the orthographic projection of the metal layer above the semiconductor layer 104 on the substrate 101 does not overlap with the first orthographic projection, so that the semiconductor layer 104 can fully receive external light.

[0083] It should be understood that the liquid crystal display device is backlit by a backlight, and the backlight may have light leakage. In this embodiment, the first light-shielding layer 21 is used to block the bottom of the first transistor 11, thereby preventing the backlight from shining on the semiconductor layer 104 of the first transistor 11, and ensuring that the electrical performance of the first transistor 11 is only affected by the light from the external ambient light.

[0084] The electrical properties of the semiconductor layer 104 are sensitive to light. Thus, by shielding the backlight and avoiding the obstruction of external ambient light, this embodiment can achieve accurate detection of the brightness of the external environment by detecting the electrical properties of the first transistor 11.

[0085] It should be noted that the various directional terms in this embodiment, such as above and below, all refer to... Figure 1 In the illustrated embodiment, "above" and "below" refer to the sides of a structure that are away from the substrate 101, while "below" refers to the area between the structure and the substrate 101.

[0086] In this embodiment, a second transistor 12 is further provided. The second transistor 12 is shielded above by a second light-shielding layer 22. In this way, the electrical performance of the second transistor 12 is only affected by the light from the leaked backlight, which can improve the detection effect of backlight.

[0087] In this embodiment, a third transistor 13 is also provided. Since the lower part of the third transistor 13 is blocked by the first light-shielding layer 21 and the upper part is blocked by the second light-shielding layer 22, the electrical performance of the third transistor 13 is not affected by the backlight and ambient brightness. Its electrical performance is only affected by temperature changes. In this way, the operating temperature can be detected by detecting the electrical performance of the third transistor 13.

[0088] By combining the detection results of the first transistor 11, the second transistor 12, and the third transistor 13, it is possible to detect and calibrate temperature, backlight, and external ambient light, thereby compensating for the display effect in a targeted manner based on the detection and calibration results, which helps to improve the compensation effect.

[0089] like Figures 2 to 4 As shown, in one embodiment, the gate metal layer 102 is reused as the first light-shielding layer 21.

[0090] like Figures 2 to 4 As shown, in some embodiments, each first transistor 11 shares the same continuous planar gate.

[0091] In other words, in this embodiment, the gate of the first transistor 11 is a continuous, large-area structure, which makes its area larger and provides better blocking effect for backlight from below.

[0092] like Figures 5 to 7 As shown, in some embodiments, the gate metal layer 102 includes a plurality of gate metal patterns for serving as gates of the first transistor 11, the plurality of gate metal patterns being spaced apart from each other, and each gate metal pattern serving as a gate of one or more first transistors 11.

[0093] It should be understood that if the size of the gate metal pattern is too large, it may cause voltage instability. Therefore, in this embodiment, multiple gate metal patterns can be set, and each gate metal pattern can serve as the gate of one or more first transistors 11. In this way, voltage instability caused by the size of a single gate metal pattern being too large can be avoided.

[0094] Please continue reading. Figures 5 to 7 In some embodiments, the orthographic projection of the source / drain metal layer 106 onto the substrate 101 overlaps with the spacing between the gate metal pattern.

[0095] In this embodiment, when the gate metal pattern spacing is set, the spacing between the gate metal patterns is blocked by the source and drain metal layer 106 to avoid backlight leakage when displaying the image and affecting the display effect.

[0096] like Figures 8 to 10 As shown, in some embodiments, the source / drain metal layer 106 includes a target source / drain metal pattern whose orthographic projection overlaps with the spacing between the gate metal pattern; at least two partially adjacent first transistors 11 share the same target source / drain metal pattern.

[0097] In some embodiments, among a plurality of first transistors 11 arranged in sequence, adjacent pairs alternately share the target source-drain metal pattern and the gate metal pattern.

[0098] In this embodiment, the gap between adjacent gate metal patterns is blocked by the source / drain metal layer 106, and the interval between the source / drain metal patterns of the source / drain metal layer 106 is blocked by the gate metal layer 102. In this way, the source / drain metal layer 106 and the gate metal layer 102 work together to block the gap, which can prevent backlight leakage from affecting the display effect when displaying images.

[0099] like Figure 11 and Figure 12 As shown, in some embodiments, the second orthographic projection of the semiconductor layer 104 of the second transistor 12 onto the substrate 101 does not overlap at least partially with the orthographic projection of the gate metal layer 102 onto the substrate 101.

[0100] For the second transistor 12 used to detect backlight brightness, it is necessary to shield it from external ambient light. Furthermore, in the area corresponding to the second transistor 12, the shape of the gate metal layer 102 is adjusted to expose the area below the second transistor 12, thereby enabling backlight brightness detection.

[0101] Please continue reading. Figure 11 and Figure 12 In one embodiment, the gate metal layer 102 and the source / drain metal layer 106 are multiplexed as a second light-shielding layer 22; the gate metal layer 102 includes a gate signal pattern 1021 and a transition gate pattern 1022, and the source / drain metal layer 106 includes a source / drain signal pattern 1061 and a transition source / drain metal pattern 1062.

[0102] The gate signal pattern 1021 and the transition source-drain metal pattern 1062 are electrically connected to transmit the gate signal of the second transistor 12; the source-drain signal pattern 1061 and the transition gate pattern 1022 are electrically connected, and the transition gate pattern 1022 is electrically connected to the semiconductor layer 104 of the second transistor 12 to transmit the source-drain signal of the second transistor 12.

[0103] In the technical solution of this embodiment, the position and size of the transition source-drain metal pattern 1062 in the source-drain metal layer 106 are first adjusted so that it can effectively block the top of the semiconductor layer 104 of the second transistor 12.

[0104] Furthermore, in this embodiment, the gate signal is transferred through the source / drain metal layer 106, while the source / drain electrode signal is transferred through the gate metal layer 102. Thus, the technical solution of this embodiment cleverly utilizes a portion of the source / drain metal layer 106 located above the semiconductor layer 104 of the second transistor 12 to function as the gate of the second transistor 12, thereby freeing up the area occupied by the gate metal layer 102 and preventing obstruction of the area below the semiconductor layer 104 of the second transistor 12.

[0105] like Figure 13 andFigure 14 As shown, in some embodiments, the gate metal layer 102 includes a gate signal pattern 1021 for transmitting gate signals, and the source / drain metal layer 106 includes a source / drain signal pattern 1061 and a dummy source / drain metal pattern 1063, the orthogonal projection of the dummy source / drain metal pattern 1063 on the substrate 101 covering the second orthogonal projection.

[0106] In this embodiment, the gate of the second transistor 12 is still formed using the gate metal layer 102. During implementation, openings are made on both sides of the gate signal pattern 1021 so that the backlight can illuminate the semiconductor layer 104 of the second transistor 12. Furthermore, the portion of the source / drain metal layer 106 located above the semiconductor layer 104 of the second transistor 12 is used as a dummy source / drain metal pattern 1063 to block the light above the semiconductor layer 104 of the second transistor 12.

[0107] like Figure 15 and Figure 16 As shown, in some embodiments, the source / drain metal layer 106 includes a source / drain signal pattern 1061 and a dummy source / drain metal pattern 1063, the orthogonal projection of the dummy source / drain metal pattern 1063 on the substrate 101 covering the second orthogonal projection.

[0108] The display substrate also includes a first electrode layer located between the semiconductor layer 104 and the source / drain metal layer 106. The first electrode layer includes a transition electrode pattern 113. The source / drain signal pattern 1061 is electrically connected to the transition electrode pattern 113. The transition electrode pattern 113 is electrically connected to the semiconductor layer 104 of the second transistor 12.

[0109] In this embodiment, a transition electrode pattern 113 is fabricated during the fabrication of the first electrode layer to transmit source and drain signals through the transition electrode pattern 113.

[0110] like Figures 17 to 19 As shown, in some embodiments, the gate metal layer 102 includes a gate signal pattern 1021 for transmitting gate signals, the gate signal pattern 1021 not overlapping with the second orthographic projection.

[0111] The display substrate also includes a second gate layer 114, which is located on the side of the source / drain metal layer 106 away from the substrate 101. The orthographic projection of the second gate layer 114 on the substrate 101 overlaps with the second orthographic projection, and the second gate layer 114 is electrically connected to the gate signal pattern 1021.

[0112] In the technical solution of this embodiment, a second gate layer 114 can be further formed on the side of the source / drain metal layer 106 away from the substrate 101 as the gate of the second transistor 12. The second gate layer 114 is connected to the gate signal pattern 1021 to obtain the gate signal.

[0113] like Figure 20 and Figure 21 As shown, for the third transistor 13, it is necessary to block both its top and bottom. Therefore, the above-mentioned solutions applied to the first transistor 11 and the second transistor 12 can be combined to block the third transistor 13.

[0114] Please continue reading. Figure 20 and Figure 21 In this embodiment, the lower part of the semiconductor layer 104 of the third transistor 13 is blocked by the entire gate metal layer 102, and the upper part of the semiconductor layer 104 of the third transistor 13 is blocked by the dummy source-drain metal pattern 1063.

[0115] like Figure 22 Zhihe Figure 24 As shown, in some embodiments, the area below the semiconductor layer 104 of the third transistor 13 is shielded by a full-surface gate metal layer 102, and an additional shielding metal layer 115 is fabricated to shield the area above the semiconductor layer 104 of the third transistor 13.

[0116] like Figure 25 Zhihe Figure 27 As shown, in some embodiments, the semiconductor layer 104 of the third transistor 13 is shielded by a full-surface gate metal layer 102, and a second gate layer 114 is fabricated on the side of the source / drain metal layer 106 away from the substrate 101 as the gate of the third transistor 13. At the same time, the second gate layer 114 can also shield the semiconductor layer 104 of the third transistor 13.

[0117] like Figure 28 and Figure 29 As shown, in some embodiments, the semiconductor layer 104 of the third transistor 13 is shielded above by a dummy source-drain metal pattern 1063, and a separate light-shielding layer 115 is formed between the substrate 101 and the gate metal layer 102 to shield the semiconductor layer 104 of the third transistor 13 below.

[0118] like Figure 30 and Figure 31 As shown, in some embodiments, the semiconductor layer 104 of the third transistor 13 is shielded by the entire gate metal layer 102, and the semiconductor layer 104 of the third transistor 13 is shielded by the dummy source-drain metal pattern 1063, while the source-drain signal is transmitted by setting the transition electrode pattern 113.

[0119] like Figures 32 to 33As shown, in practice, by combining the above different blocking methods, a first transistor 11 that is blocked from the bottom and used to detect the brightness of the external environment, a second transistor 12 that is blocked from the top and used to detect the backlight intensity, and a third transistor 13 that is blocked from both the top and bottom and used to detect the temperature can be set in the peripheral area of ​​the display substrate.

[0120] In some other embodiments, the area above the second transistor 12 and the third transistor 13 may also be shielded by an ink layer on the cover glass.

[0121] Thus, in the technical solution of this embodiment, since each transistor is affected by temperature in the same way at the same temperature, by setting a third transistor 13 to measure the temperature, it is tested to work without the influence of ambient light and backlight. At this time, its electrical performance is mainly affected by temperature, and the temperature curve tends to be consistent under different ambient light levels, so that real-time temperature calibration can be achieved without turning off the backlight module.

[0122] like Figure 34 As shown, Figure 34 The figures represent ambient light values ​​at different temperatures and illuminance levels. Curve 1 is the temperature curve at 0 lux, curve 2 is the temperature curve at 500 lux before improvement, and curve 3 is the temperature curve at 500 lux after improvement according to the technical solution of this embodiment. As can be seen from the figures, the temperature curve before calibration has a large deviation, while the temperature curve after calibration has a high degree of matching under different illuminance levels.

[0123] like Figure 35 As shown, Figure 35 The horizontal axis represents the value of the backlight comparison, and the vertical axis represents the G / W (green light / white light) value, which can be understood as the ambient brightness. The upper curve is the change curve before improvement, and the lower curve is the change curve after improvement. As can be seen from the figure, the slope of the high illumination decreases significantly, from about 0.25 to about 0.04. The backlight brightness has a smaller impact on the G / W of the photosensitive area.

[0124] By blocking the top and bottom of the third transistor 13, in the absence of backlight, the temperature control group tends to show a linear trend when the ambient light changes, such as... Figure 36 As shown, Figure 36 The horizontal axis represents ambient light intensity, and the vertical axis represents the detection results of each transistor. Curve 1 represents the W / G value, which can be understood as ambient brightness. Curve 2 represents the result before improvement, and curve 3 represents the result after improvement in this embodiment. Comparing curves 2 and 3, it can be seen that the technical solution of this embodiment can effectively block ambient light. Even when the brightness increases, it can also prevent ambient light from affecting the third transistor 13, which helps to improve the accuracy of temperature acquisition.

[0125] This invention provides a display device comprising a display substrate according to any of the above-mentioned embodiments.

[0126] Since the technical solution of this embodiment includes all the technical solutions of the above-described display substrate embodiments, it can achieve at least all of the above-described technical effects, which will not be repeated here.

[0127] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, comprising: A substrate, comprising a display area and a peripheral area surrounding the display area; A first transistor is disposed in the peripheral area and is used to detect the ambient light intensity of the display substrate; A second transistor is disposed in the peripheral area and is used to detect the backlight intensity of the display substrate; A third transistor is disposed in the peripheral area and is used to detect the temperature of the display substrate; The display substrate further includes a gate metal layer, a semiconductor layer formed on the side of the gate metal layer away from the substrate, and a source / drain metal layer formed on the side of the semiconductor layer away from the substrate. A first light-shielding layer is disposed between the semiconductor layer and the substrate. The orthographic projection of the first light-shielding layer on the substrate covers the first orthographic projection of the semiconductor layer of the first transistor on the substrate and the third orthographic projection of the semiconductor layer of the third transistor on the substrate. A second light-shielding layer is disposed on the side of the semiconductor layer away from the substrate, and the orthographic projection of the second light-shielding layer on the substrate covers the second orthographic projection and the third orthographic projection of the semiconductor layer of the second transistor on the substrate. The orthographic projection of the metal layer on the side of the semiconductor layer of the display substrate away from the substrate on the substrate does not overlap with the first orthographic projection. The second orthographic projection of the semiconductor layer of the second transistor on the substrate does not overlap with the orthographic projection of the gate metal layer on the substrate at least partially; The gate metal layer and the source / drain metal layer are reused as the second light-shielding layer; The gate metal layer includes a gate signal pattern and a transition gate pattern, and the source drain metal layer includes a source drain signal pattern and a transition source drain metal pattern; The gate signal pattern and the transition source-drain metal pattern are electrically connected to transmit the gate signal of the second transistor; The source / drain signal pattern and the transition gate pattern are electrically connected, and the transition gate pattern is electrically connected to the semiconductor layer of the second transistor to transmit the source / drain signals of the second transistor.

2. The display substrate as described in claim 1, characterized in that, The gate metal layer is reused as the first light-shielding layer.

3. The display substrate as described in claim 2, characterized in that, Each of the first transistors shares the same continuous planar gate.

4. The display substrate as described in claim 3, characterized in that, The gate metal layer includes a plurality of gate metal patterns for serving as gates of the first transistor, the plurality of gate metal patterns being spaced apart from each other, and each gate metal pattern serving as a gate of one or more of the first transistors.

5. The display substrate as described in claim 4, characterized in that, The spacing between the orthographic projection of the source / drain metal layer on the substrate and the gate metal pattern overlaps.

6. The display substrate as described in claim 4 or 5, characterized in that, The source / drain metal layer includes a target source / drain metal pattern that overlaps with the orthographic projection of the gate metal pattern; At least two partially adjacent first transistors share the same target source drain metal pattern.

7. The display substrate as described in claim 6, characterized in that, In a series of first transistors arranged sequentially, adjacent pairs alternately share the target source-drain metal pattern and the gate metal pattern.

8. The display substrate as described in claim 1, characterized in that, The gate metal layer includes a gate signal pattern for transmitting gate signals, and the gate signal pattern for transmitting gate signals does not overlap with the second orthographic projection; The display substrate further includes a second gate layer, which is located on the side of the source / drain metal layer away from the substrate. The orthographic projection of the second gate layer on the substrate overlaps with the second orthographic projection, and the second gate layer is electrically connected to the gate signal pattern.

9. A display device, characterized in that, The display substrate includes any one of claims 1 to 8.

Images