ECU simulation test method, device and storage medium based on dual-core microcontroller

Abstract

The present invention relates to an ECU simulation test method, device and storage medium based on a dual-core microcontroller, wherein the method comprises: when a vehicle-mounted dedicated integrated circuit and a vehicle-mounted controller are normally connected in a vehicle-mounted ECU to be tested, recording a message frame sequence of communication; parsing all second messages, and configuring the data bits in all data messages as editable bits, obtaining a response message sequence template corresponding to each test item; selecting a corresponding response message sequence template, and generating a target response message sequence after editing all editable bits in the response message sequence template; when starting the test, cutting off the connection between the vehicle-mounted dedicated integrated circuit and the vehicle-mounted controller, the first core stores the received target response message sequence in a shared storage area, and the second core reads the target response message sequence and sends it to the vehicle-mounted controller one by one. Compared with the prior art, the present invention can simulate the output of the intra-frame mode of the vehicle-mounted dedicated integrated circuit in a software-defined manner.

Description

Technical Field

[0001] The present invention relates to ECU internal vehicle-mounted special integrated circuit simulation, and in particular to an ECU simulation test method, device and storage medium based on a dual-core microcontroller. Background Art

[0002] With the increasing degree of automotive electronics, the Electronic Control Unit (ECU) in modern vehicles has become a core electronic device. From 30 ECUs in low-end models to more than 100 ECUs in high-end models, they control a variety of functions from basic window control to safety-critical collision avoidance, airbag deployment, etc. Ensuring the functional safety and reliability of ECUs has become one of the top priorities of the automotive electronics industry.

[0003] In the hardware architecture of the ECU, the microcontroller unit (MCU) is the core processor responsible for executing control decisions. The MCU receives input through two types of communication buses: one is to communicate with other ECUs through external buses such as the controller area network (CAN), and the other is to communicate with the vehicle-mounted application-specific integrated circuit (ASIC) through on-chip buses such as the serial peripheral interface (SPI). The ASIC plays the role of a signal preprocessing unit in the ECU, responsible for processing digital signals, analog signals, and pulse signals from sensors, and transmitting the processed data to the MCU through SPI.

[0004] As shown in Table 1, the full-duplex communication interface used between the ASIC and the MCU means that each time window between the ASIC and the MCU will send a data packet to each other.

[0005] Table 1

[0006] order MCU→ASIC ASIC → MCU 1 Data_1.1 Data_2.1 2 Data_1.2 Data_2.2 3 Data_1.3 Data_2.3 4 Data_1.4 Data_2.4 5 Data_1.5 Data_2.5 6 Data_1.6 Data_2.6

[0007] The SPI communication between MCU and ASIC follows strict protocol specifications and supports two modes: intra-frame mode and extra-frame mode. In intra-frame mode, MCU sends a 32-bit request, and ASIC must immediately return a 32-bit response in the same communication cycle. The communication rate can reach 10 Mbaud, which is suitable for scenarios that require real-time response, such as airbag control. In extra-frame mode, ASIC returns a response in the next communication cycle after receiving the MCU request, providing more time for signal processing. Specifically, in extra-frame mode, data packet Data_2.2 is a response to data packet Data_1.1, and ASIC responds to the data packet of MCU in the next time slot. Therefore, after receiving data packet Data_1.1, there is enough time to parse and generate data packet Data_2.2. However, in some scenarios with high timeliness requirements, such as ignition, braking, airbag detonation, etc., intra-frame mode is often used, that is, data packet Data_2.1 is a response to data packet Data_1.1.

[0008] At present, ECU testing mainly relies on hardware-in-the-Loop (HiL) simulation test systems. This test method uses a dedicated sensor simulator to generate various sensor signals, which are processed by actual ASIC chips and transmitted to the ECU's MCU. However, each type of sensor signal requires a dedicated simulator, and ASIC chips are expensive, resulting in high overall test system costs. In addition, hardware simulators can often only generate signals within a preset range, making it difficult to simulate extreme conditions and fault scenarios. Different models of ECUs use different ASIC chips, and frequent replacement of hardware equipment also increases the complexity of the test system.

[0009] To reduce the testing cost, some technicians try to use software simulation to directly inject test data into the MCU. However, this method faces severe technical challenges: first, the intra-frame mode requires a response time of microseconds, and ordinary software cannot guarantee stable communication timing; second, SPI communication uses a complex 32-bit frame format, which includes multiple fields such as instruction identifier, status flag, data segment and CRC check, and the protocol specifications of different suppliers are different; finally, at a communication rate of 10Mbaud, the software needs to complete data parsing, status judgment and response generation in a very short time.

[0010] Although existing technologies have proposed FPGA-based solutions that meet strict timing requirements through hardware implementation, the price of FPGA is much higher than that of ordinary microcontrollers, and professional development tools and technical teams are required, with a long development cycle. More importantly, FPGA solutions are difficult to modify quickly after implementation, and adaptation to new ASIC protocols requires redevelopment, and functional expansion is also limited by hardware resources.

[0011] Therefore, how to simulate ASIC based on low-cost microcontrollers, which can not only meet the timing requirements of SPI communication, but also flexibly support the simulation of different types of sensor signals, is a technical problem that needs to be solved in this field. Successfully solving this problem will help reduce ECU testing costs, improve testing efficiency, and ultimately improve vehicle safety and reliability. Summary of the invention

[0012] The purpose of the present invention is to provide an ECU simulation test method, device and storage medium based on a dual-core microcontroller.

[0013] The purpose of the present invention can be achieved by the following technical solutions:

[0014] An ECU simulation test method based on a dual-core microcontroller comprises:

[0015] When the vehicle-mounted ASIC and the vehicle-mounted controller in the vehicle-mounted ECU to be tested are normally connected, a message frame sequence of communication between the vehicle-mounted ASIC and the vehicle-mounted controller is recorded, wherein each message frame includes a first message sent by the vehicle-mounted controller to the vehicle-mounted ASIC and a second message sent by the vehicle-mounted ASIC to the vehicle-mounted controller;

[0016] Parsing all second messages, classifying all second messages into configuration messages and data messages, and configuring data bits in all data messages as editable bits to obtain response message sequence templates corresponding to each test item;

[0017] After receiving the test instruction, determine the test item based on the test instruction, select the corresponding response message sequence template, and edit all editable bits in the response message sequence template to generate the target response message sequence;

[0018] When the test starts, the connection between the vehicle-mounted ASIC and the vehicle-mounted controller is cut off, the first core of the dual-core microcontroller stores the received target response message sequence in the shared storage area, and the second core of the dual-core microcontroller reads the target response message sequence from the shared storage area and sends it one by one to the vehicle-mounted controller.

[0019] The target response message sequence is an SPI sequence, wherein the SPI sequence is composed of a plurality of sequentially arranged SPI data strings.

[0020] The target response message sequence is sent to the first core of the dual-core microcontroller in the form of a CAN message, and a single CAN message includes:

[0021] The data segment, a total of 6 bytes, is filled with SPI sequence fragments, wherein the SPI sequence fragments are obtained by segmenting the SPI sequence.

[0022] The frame header segment consists of 2 bytes, of which 4 bits in 1 byte represent the serial number of the SPI sequence fragment, and 4 bits represent the total number of SPI sequence fragments obtained by dividing the SPI sequence.

[0023] The first core of the dual-core microcontroller confirms that all SPI sequence fragments are received according to the frame header of the CAN message, and then sorts and reassembles all SPI sequence fragments according to the sequence numbers of the SPI sequence fragments in the frame header to restore the SPI sequence.

[0024] The communication mode between the vehicle-mounted ASIC and the vehicle-mounted controller is an intra-frame mode.

[0025] The target response message sequence stored in the shared storage area adopts a first-in-first-out reading and storage mechanism.

[0026] The process in which the second core of the dual-core microcontroller reads the target response message sequence from the shared storage area and sends the target response message sequence to the vehicle controller one by one specifically includes:

[0027] Select the slave module corresponding to the vehicle-specific integrated circuit to be simulated,

[0028] The target response message sequence is read from the shared memory area, and the selected slave module sends the target response message sequence to the vehicle controller one by one according to the timing requirements of the vehicle-based ASIC to be simulated;

[0029] The slave module further includes two buffer areas, and data in one buffer area is prepared while data is transmitted in the other buffer area.

[0030] The vehicle-mounted ECU is an airbag controller, and the length of a single SPI data string is 32 bits;

[0031] When the target response message sequence simulates the acceleration sensor signal: the data bits in the data message are configured as bits 2-17 to simulate acceleration signals in different directions;

[0032] When the target reply message sequence simulates the collision sensor signal: the data bits in the data message are configured as editable bits 18-21.

[0033] An ECU simulation test device based on a dual-core microcontroller comprises a memory, a processor, and a program stored in the memory. When the processor executes the program, the above method is implemented.

[0034] A storage medium stores a program, which implements the above method when executed.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] 1. By recording the message frame sequence and parsing it to obtain a response message sequence template, a test item is subsequently given, and a target response message sequence is generated by modifying the editable bits in the response message sequence template, thereby realizing a full range of simulations such as fault injection, and combining the design of a dual-core microcontroller and a shared storage area, by disconnecting the connection between the on-board dedicated integrated circuit inside the ECU and the on-board controller, the target response message sequence can be directly sent to the on-board controller one by one in sequence. Different from the traditional simulation method outside the ECU, this application can simulate the communication between chips, effectively reduce the test cost of the ECU, improve the test efficiency, and realize the test of the intra-frame mode.

[0037] 2. Send data through CAN messages combined with the SPI sequence segmentation method, which can effectively improve the efficiency of SPI data transmission.

[0038] 3. The slave module also includes two buffer areas. By transmitting data in one buffer area while preparing data in another buffer area, uninterrupted transmission of SPI data can be achieved, thereby solving the problem of insufficient timeliness in the intra-frame communication mode.

[0039] 4. For the airbag controller, the editable bits are clarified, thus solving the problem of high testing cost of the airbag controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic flow chart of the main steps of the method of the present invention;

[0041] Figure 2 It is a principle schematic diagram of the test state of the present invention;

[0042] Among them: 1. Host computer, 2. On-board ECU, 3. Integrated circuit simulator, 4. Remote actuator, 2-1. On-board controller, 2-2. On-board dedicated integrated circuit, 2-3. CAN transceiver, 2-4. On-chip peripherals, 3-1. Second core, 3-2. First core, 3-3. Shared storage area, 2-1-1. Firmware to be tested, 2-1-2. SPI master device, 2-1-3. CAN module, 2-1-4. Output module, 3-1-1. Slave module. DETAILED DESCRIPTION

[0043] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0044] like Figure 2As shown, the present application simulates the signal processing and communication functions of the vehicle-mounted dedicated integrated circuit 2-2 by software, which can replace the multi-channel sensor simulation device in the traditional hardware-in-the-loop test, and specifically adopts a dual-core architecture. Specifically, an ECU simulation test method based on a dual-core microcontroller, such as Figure 1 As shown, including:

[0045] Step S1: When the vehicle-borne ASIC 2-2 and the vehicle-borne controller 2-1 in the vehicle-borne ECU 2 to be tested are normally connected, a message frame sequence of the communication between the vehicle-borne ASIC 2-2 and the vehicle-borne controller 2-1 is recorded, wherein each message frame includes a first message sent by the vehicle-borne controller 2-1 to the vehicle-borne ASIC 2-2 and a second message sent by the vehicle-borne ASIC 2-2 to the vehicle-borne controller 2-1;

[0046] Step S2: parsing all second messages, classifying all second messages into configuration messages and data messages, and configuring data bits in all data messages as editable bits to obtain a response message sequence template corresponding to each test item;

[0047] Step S3: After receiving the test instruction, determine the test item based on the test instruction, select the corresponding response message sequence template, and edit all editable bits in the response message sequence template to generate a target response message sequence. The target response message sequence is an SPI sequence generated by the host computer 1, wherein the SPI sequence consists of multiple sequentially arranged SPI data strings.

[0048] Step S4: When the test starts, the connection between the vehicle-mounted dedicated integrated circuit 2-2 and the vehicle-mounted controller 2-1 is cut off, the first core 3-2 of the dual-core microcontroller stores the received target response message sequence in the shared storage area 3-3, and the second core 3-1 of the dual-core microcontroller reads the target response message sequence from the shared storage area 3-3 and sends them one by one to the vehicle-mounted controller 2-1.

[0049] By recording the message frame sequence and parsing it to obtain a response message sequence template, a test item is subsequently given, and a target response message sequence is generated by modifying the editable bits in the response message sequence template, thereby realizing a full range of simulations such as fault injection, and combining the design of a dual-core microcontroller and a shared storage area 3-3, by disconnecting the connection between the on-board dedicated integrated circuit 2-2 inside the ECU and the on-board controller 2-1, the target response message sequence can be directly sent to the on-board controller 2-1 one by one in sequence. Different from the traditional simulation method outside the ECU, the present application can simulate communication between chips, effectively reduce the test cost of the ECU, improve test efficiency, and realize intra-frame mode testing.

[0050] Each vehicle-mounted ASIC 2-2 has a corresponding SPI master device 2-1-2 in the vehicle-mounted controller 2-1 to communicate with it.

[0051] like Figure 2 As shown, the present application is specifically implemented using an STM32H7 dual-core microcontroller. In the figure, two slave modules 3-1-1 correspond to two vehicle-mounted dedicated integrated circuits 2-2, respectively, so that two different sensor signals can be simulated at the same time. The first core 3-2, the second core 3-1 and the shared storage area 3-3 together constitute an integrated circuit emulator 3, which fully utilizes the advantages of its dual-core heterogeneous architecture. The focus is on the functional design of the integrated circuit emulator 3. The three major functions that need to be implemented are communication bridging, SPI processing and shared storage. Among them, the communication bridge is deployed on the Cortex-M4 core, which is responsible for processing and data exchange between the test system, including receiving CAN messages, processing data fragmentation and reorganization, decoding SPI frame format and other functions. Considering the 8-byte length of the CAN message, the length of a single SPI data string is only 32 bytes, i.e., 4 bits. In this embodiment, in order to improve efficiency, the entire SPI is generally selected to be transmitted together, but the length of the entire SPI sequence is too long, exceeding 8 bytes. Therefore, it is difficult for a single CAN message to directly transmit the complete SPI sequence, and a fragmentation transmission protocol based on a serial number and confirmation mechanism is implemented. The decoded SPI sequence is reassembled in a 32-bit frame format, each frame containing fields such as instruction identifier, status flag, data, and CRC check, and then written into the cache area of ​​the corresponding ASIC in the shared memory area 3-3.

[0052] Others such as Figure 2 As shown, the remote actuator 4 is a specific execution component, such as a heating element for detonating an airbag, etc. The on-chip peripherals 2-4 are some other peripheral devices, and the output module 2-1-4 is the output part of the vehicle controller. This application has not improved it, so it will not be traced. The firmware to be tested 2-1-1 is the specific object to be tested inside the vehicle controller 2-1, which specifically includes application software, middleware, basic software and drivers.

[0053] Specifically, the target response message sequence is sent to the first core 3-2 of the dual-core microcontroller in the form of a CAN message. A single CAN message includes:

[0054] The data segment, a total of 6 bytes, is filled with SPI sequence fragments, where the SPI sequence fragments are obtained by dividing the SPI sequence.

[0055] The frame header segment consists of 2 bytes, of which 4 bits in 1 byte represent the serial number of the SPI sequence fragment, and 4 bits represent the total number of SPI sequence fragments obtained by dividing the SPI sequence.

[0056] In addition, the vehicle-mounted ECU 2 to be tested is also equipped with a CAN transceiver 2-3 which can communicate with the host computer 1, and the corresponding CAN module 2-1-3 is integrated in the vehicle-mounted controller 2-1.

[0057] After confirming that all SPI sequence fragments are received according to the frame header of the CAN message, the first core 3-2 of the dual-core microcontroller sorts all SPI sequence fragments according to the serial numbers of the SPI sequence fragments in the frame header to restore the SPI sequence.

[0058] By sending data through CAN messages and combining the SPI sequence segmentation method, the efficiency of SPI data transmission can be effectively improved.

[0059] In this embodiment, SPI processing is deployed on the Cortex-M7 core with stronger performance. This is because the SPI communication of the vehicle-mounted ASIC 2-2 has strict real-time requirements, especially in the intra-frame mode, the interaction of requests and responses needs to be completed within the same communication cycle (up to 10 Mbaud). SPI processing realizes parallel simulation of multiple ASICs by configuring multiple groups of SPI peripherals as slave modules 3-1-1. Each slave module 3-1-1 is equipped with independent chip select control and double buffer data management mechanism, which prepares the next frame of data while the current data is being transmitted, and ensures the continuity of data transmission and the achievement of timing requirements through high priority interrupt drive.

[0060] Specifically, the target response message sequence stored in the shared storage area 3-3 adopts a first-in-first-out reading and storage mechanism.

[0061] The process of the second core 3-1 of the dual-core microcontroller reading the target response message sequence from the shared storage area 3-3 and sending it one by one to the vehicle controller 2-1 specifically includes:

[0062] Select the slave module 3-1-1 corresponding to the vehicle-mounted ASIC 2-2 to be simulated,

[0063] The target response message sequence is read from the shared storage area 3-3, and the selected slave module 3-1-1 sends them one by one to the vehicle controller 2-1 according to the timing requirements of the vehicle-specific integrated circuit 2-2 to be simulated;

[0064] The slave module 3 - 1 - 1 further includes two buffer areas, and data in one buffer area is prepared while data is transmitted in the other buffer area.

[0065] The shared memory is implemented with AXI-SRAM, which is the key bridge connecting the two cores. It also configures an independent circular buffer for each simulated ASIC, realizing a lock-free producer-consumer model based on the hardware mutual exclusion feature. The communication bridge writes data to the circular buffer as a producer, and the SPI process reads the data and performs communication as a consumer. The system updates the read and write pointers through atomic operations and implements strict interrupt priority management to ensure the reliability of data exchange. At the same time, the system also implements a complete flow control and error handling mechanism. By monitoring the buffer usage and communication status, it handles abnormal situations in a timely manner and feeds back to the test system.

[0066] In this embodiment, the vehicle-mounted ECU 2 is an airbag controller, which requires three sensors, so a total of three slave modules 3-1-1 are enabled, the length of a single SPI data string is 32 bits, and the communication mode between the vehicle-mounted dedicated integrated circuit 2-2 and the vehicle-mounted controller 2-1 is the intra-frame mode.

[0067] When the target response message sequence simulates the acceleration sensor signal: the data bits in the data message are configured as bits 2-17 to simulate acceleration signals in different directions. The specific acceleration sensor signal simulation is as follows: In the 32-bit SPI data string, bits 2-17 are the data segment used to transmit the acceleration value, of which bits 2-7 represent the X-axis acceleration, bits 8-13 represent the Y-axis acceleration, and bits 14-17 represent the Z-axis acceleration. By modifying the values ​​of these bits, the acceleration changes in the range of -16g to +16g can be simulated.

[0068] When the target reply message sequence simulates the collision sensor signal: the data bits in the data message are configured as editable bits 18-21.

[0069] Seat sensor signal simulation, 4 bits are allocated in the data segment to represent the seat resistance value, the resistance value range is from 100Ω to 100kΩ, which is used to determine the seat occupancy status. By modifying these bits, different states such as empty seat, adult occupant, child seat, etc. can be simulated.

[0070] The present application innovatively uses the STM32H7 dual-core microcontroller to simulate the vehicle-mounted ASIC 2-2, significantly reducing the cost of the test system and improving the test efficiency. Since the vehicle-mounted ASIC 2-2 is essentially an integration and preprocessing unit for multiple sensor signals, the present invention can simulate different sensor signals by modifying specific bits in the SPI sequence, simplifying the test system that originally required multiple dedicated sensor simulators to a solution that only requires one STM32H7 development board.

[0071] In terms of performance, the present invention uses a reasonable division of labor in a dual-core architecture, combined with a double buffer mechanism and an interrupt-driven callback mechanism, to enable the system to support a communication rate of up to 10Mbaud, meeting the strict real-time requirements of the vehicle-mounted ASIC 2-2. At the same time, the software-defined feature enables test engineers to flexibly configure the SPI frame format, communication parameters, and signal characteristics, not only supporting conventional functional testing of ECUs, but also enabling fault injection testing by precisely controlling specific bits in the SPI sequence, providing comprehensive testing capabilities for ECU functional verification.

[0072] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

Claims

1. An ECU simulation test method based on a dual-core microcontroller, characterized in that: include: When the vehicle-mounted ASIC and the vehicle-mounted controller in the vehicle-mounted ECU to be tested are normally connected, a message frame sequence of communication between the vehicle-mounted ASIC and the vehicle-mounted controller is recorded, wherein each message frame includes a first message sent by the vehicle-mounted controller to the vehicle-mounted ASIC and a second message sent by the vehicle-mounted ASIC to the vehicle-mounted controller; Parsing all second messages, classifying all second messages into configuration messages and data messages, and configuring data bits in all data messages as editable bits to obtain response message sequence templates corresponding to each test item; After receiving the test instruction, determine the test item based on the test instruction, select the corresponding response message sequence template, and edit all editable bits in the response message sequence template to generate the target response message sequence; When the test starts, the connection between the vehicle-mounted ASIC and the vehicle-mounted controller is cut off, the first core of the dual-core microcontroller stores the received target response message sequence in the shared storage area, and the second core of the dual-core microcontroller reads the target response message sequence from the shared storage area and sends it one by one to the vehicle-mounted controller.

2. The ECU simulation test method based on a dual-core microcontroller according to claim 1 is characterized in that: The target response message sequence is an SPI sequence, wherein the SPI sequence is composed of a plurality of sequentially arranged SPI data strings.

3. The ECU simulation test method based on a dual-core microcontroller according to claim 2 is characterized in that: The target response message sequence is sent to the first core of the dual-core microcontroller in the form of a CAN message, and a single CAN message includes: The data segment, a total of 6 bytes, is filled with SPI sequence fragments, wherein the SPI sequence fragments are obtained by segmenting the SPI sequence. The frame header segment consists of 2 bytes, of which 4 bits in 1 byte represent the serial number of the SPI sequence fragment, and 4 bits represent the total number of SPI sequence fragments obtained by dividing the SPI sequence.

4. The ECU simulation test method based on a dual-core microcontroller according to claim 3 is characterized in that: The first core of the dual-core microcontroller confirms that all SPI sequence fragments are received according to the frame header of the CAN message, and then sorts and reassembles all SPI sequence fragments according to the sequence numbers of the SPI sequence fragments in the frame header to restore the SPI sequence.

5. The ECU simulation test method based on a dual-core microcontroller according to claim 1 is characterized in that: The communication mode between the vehicle-mounted ASIC and the vehicle-mounted controller is an intra-frame mode.

6. The ECU simulation test method based on a dual-core microcontroller according to claim 1 is characterized in that: The target response message sequence stored in the shared storage area adopts a first-in-first-out reading and storage mechanism.

7. The ECU simulation test method based on a dual-core microcontroller according to claim 1 is characterized in that: The process in which the second core of the dual-core microcontroller reads the target response message sequence from the shared storage area and sends the target response message sequence to the vehicle controller one by one specifically includes: Select a slave module corresponding to the vehicle-mounted ASIC to be simulated, the slave module being included in the second core of the dual-core microcontroller, The target response message sequence is read from the shared memory area, and the selected slave module sends the target response message sequence to the vehicle controller one by one according to the timing requirements of the vehicle-based ASIC to be simulated; The slave module further includes two buffer areas, and data in one buffer area is prepared while data is transmitted in the other buffer area.

8. The ECU simulation test method based on a dual-core microcontroller according to claim 7 is characterized in that: The vehicle-mounted ECU is an airbag controller, and the length of a single SPI data string is 32 bits; When the target response message sequence simulates the acceleration sensor signal: the data bits in the data message are configured as bits 2-17 to simulate acceleration signals in different directions; When the target reply message sequence simulates the collision sensor signal: the data bits in the data message are configured as editable bits 18-21.

9. An ECU simulation test device based on a dual-core microcontroller, comprising a memory, a processor, and a program stored in the memory, characterized in that: When the processor executes the program, the method according to any one of claims 1 to 8 is implemented.

10. A storage medium having a program stored thereon, characterized in that: When the program is executed, the method according to any one of claims 1 to 8 is implemented.

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