LDO circuit

Abstract

The invention discloses an LDO circuit. The LDO circuit comprises an error amplifier; a voltage source; a current source; a power switch tube; a voltage stabilizing capacitor; an ESR resistor; the inverting input end of the error amplifier is connected with a reference voltage, the non-inverting input end of the error amplifier is connected with the voltage output end, the output end of the error amplifier is connected with the grid electrode of the power switch tube, the source electrode of the power switch tube is connected with the voltage source, and the drain electrode of the power switch tube is connected with the voltage output end. One end of the current source is connected with the voltage output end, the other end of the current source is grounded, one end of the ESR resistor is connected with the voltage output end, the other end of the ESR resistor is connected with one end of the voltage stabilizing capacitor, the ESR resistor is provided with at least one bending part, and the other end of the voltage stabilizing capacitor is grounded.

Description

Technical Field

[0001] The invention relates to a LDO circuit for a DRAM system. Background Art

[0002] In DRAM systems, complex power systems are required to implement various functions of DRAM systems. Complex power systems are also required to solve problems such as reducing chip area and ensuring power integrity. In order to realize various power domains in DRAM, LDO circuits have become an indispensable part of DRAM systems. LDO (Low Dropout Regulator) circuit is a linear regulator used to adjust the input voltage to a lower output voltage while maintaining a small voltage difference (i.e., the difference between the input voltage and the output voltage). The main feature of the LDO circuit is its low voltage difference characteristic, which allows it to work normally even when the input voltage is close to the output voltage.

[0003] At the same time, because the current load rate in the DRAM system changes all the time, it is necessary to design a variety of compensation methods to ensure that the LDO power output remains stable under different load conditions.

[0004] The system block diagram of the on-chip LDO is as follows: Figure 1 As shown. In order to prevent the LDO output from fluctuating greatly under a large instantaneous current load, a 1-2nF on-chip voltage stabilizing capacitor is generally added to the power supply output. However, as the current load increases and reaches a certain level, the output stage pole moves from the main pole to the high frequency and becomes a secondary pole. In this process, the power supply output is extremely prone to oscillation. Therefore, as Figure 1 As shown in the dotted box in the figure, a resistor of about 3 ohms is usually connected in series to the voltage stabilizing capacitor, which can provide a left half plane zero point within the normal working range of the power supply system, thereby helping to ensure the stability of the LDO circuit under different load conditions. Summary of the invention

[0005] Technical problem to be solved by the invention

[0006] Normally, in the layout of the LDO circuit, on the one hand, it is necessary to ensure that the resistance value meets the design requirements. For a resistor of 3 ohms, it is generally achieved by using a metal resistor. On the other hand, a metal resistor that is too thin and long will limit the current capacity, causing serious EM (Electron Migration) problems. The EM phenomenon means that the maximum current allowed to pass through the metal wire is limited. Excessive current will break the metal connection and cause the chip to fail. This problem is caused by excessive long-term current causing metal cations to accumulate at the positive electrode, forming hillocks or protrusions, and holes are prone to appear at the cathode. Especially under high temperature conditions, metal ions are more active, and electrons can easily promote this migration, resulting in short circuits or open circuits.

[0007] Purpose of the Invention

[0008] The present invention is completed to solve the above-mentioned problem, and its purpose is to provide an LDO circuit that can ensure a certain resistance value (such as 3 ohms) to meet the resistance requirement and has sufficient current capacity to meet the requirements of the EM rule.

[0009] Technical solutions to technical problems

[0010] A first aspect of the present invention provides an LDO circuit, comprising:

[0011] Including: error amplifier; voltage source; current source; power switch tube; voltage stabilizing capacitor; ESR resistor; voltage output terminal,

[0012] The inverting input terminal of the error amplifier is connected to the reference voltage, the non-inverting input terminal is connected to the voltage output terminal, and the output terminal of the error amplifier is connected to the gate of the power switch tube.

[0013] The source of the power switch tube is connected to the voltage source, and the drain is connected to the voltage output terminal.

[0014] One end of the current source is connected to the voltage output end, and the other end is grounded.

[0015] One end of the ESR resistor is connected to the voltage output end, and the other end is connected to one end of the voltage stabilizing capacitor. The ESR resistor has at least one bent portion.

[0016] The other end of the voltage stabilizing capacitor is grounded.

[0017] In the LDO circuit of the second aspect of the present invention, the power switch tube is a PMOS power tube.

[0018] The LDO circuit of the third aspect of the present invention comprises:

[0019] The resistance value of the ESR resistor is greater than 3 ohms.

[0020] In the LDO circuit of the fourth aspect of the present invention, the ESR resistor is connected to the voltage output terminal through a via.

[0021] In the LDO circuit of the fifth aspect of the present invention, the voltage stabilizing capacitor is 1 to 2 nF.

[0022] In the LDO circuit of the sixth aspect of the present invention,

[0023] The material of the ESR resistor is tungsten.

[0024] In the LDO circuit of the seventh aspect of the present invention,

[0025] The voltage stabilizing capacitor comprises an upper capacitor plate, two lower capacitor plates, and a special layer connected between the upper capacitor plate and the two lower capacitor plates, one lower capacitor plate is connected to an ESR resistor, and the other lower capacitor plate is grounded.

[0026] In the LDO circuit of the eighth aspect of the present invention,

[0027] An ESR resistor is connected between the lower plate of the other capacitor and ground.

[0028] In the LDO circuit of the ninth aspect of the present invention,

[0029] The ESR resistor has a plurality of bent portions.

[0030] In the LDO circuit of the tenth aspect of the present invention,

[0031] The ESR resistor is a plurality of resistors connected in parallel between the voltage stabilizing capacitor and the voltage output terminal.

[0032] Effects of the Invention

[0033] The LDO circuit according to the present invention can ensure a relatively large resistance value to meet the design requirements and also have sufficient current capacity to meet the requirements of EM regulations. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A schematic diagram showing a LDO circuit structure according to an embodiment of the present invention.

[0035] Figure 2 A schematic structural diagram of a voltage-stabilizing capacitor and an ESR resistor involved in Embodiment 1 of the present invention is shown.

[0036] Figure 3 Another structural schematic diagram of the voltage-stabilizing capacitor and the ESR resistor involved in the second embodiment of the present invention is shown.

[0037] Figure 4Shows another structural schematic diagram of the voltage stabilizing capacitor and ESR resistor involved in Embodiment 3 of the present invention.

[0038] Figure 5 Shows another structural schematic diagram of the voltage stabilizing capacitor and ESR resistor involved in Embodiment 4 of the present invention.

[0039] Figure 6 Shows a side view of the structure of the voltage stabilizing capacitor and ESR resistor involved in the embodiment of the present invention.

[0040] Label description

[0041] 100 LDO circuit

[0042] 101 Error amplifier

[0043] 102 Voltage source

[0044] 103 Current source

[0045] 104 Power switch transistor

[0046] 105 Voltage stabilizing capacitor

[0047] 1051 Upper capacitor plate

[0048] 1052 First lower capacitor plate

[0049] 1053 Second lower capacitor plate

[0050] 1054 First special layer

[0051] 1055 Second special layer

[0052] 106 ESR resistor

[0053] 1061 First straight portion

[0054] 1062 Second straight portion

[0055] 1063 Bending portion

[0056] 107 Voltage output terminal.

[0057] 108 Via hole Detailed implementation manner

[0058] <Structure of the LDO circuit>

[0059] Embodiment 1

[0060] Refer to Figure 1 、 Figure 2 、 Figure 6 to describe the structure of the LDO circuit involved in Embodiment 1 of the present invention. Figure 1 A schematic diagram showing a LDO circuit structure according to an embodiment of the present invention. Figure 2 A schematic structural diagram of a voltage-stabilizing capacitor and an ESR resistor involved in Embodiment 1 of the present invention is shown. Figure 6 A side view showing the structure of a stabilizing capacitor and an ESR resistor according to the first embodiment of the present invention.

[0061] The present invention relates to a method for realizing a special voltage-stabilizing capacitor layout in a DRAM. Figure 1 , Figure 2 , Figure 6 As shown, the LDO circuit 100 involved in the first embodiment of the present invention includes: an error amplifier 101 (EA: Error Amplifier); a voltage source 102; a current source 103; a power switch tube 104; a voltage stabilizing capacitor 105; an ESR resistor 106; and a voltage output terminal 107.

[0062] The inverting input terminal of the error amplifier 101 is connected to the reference voltage Vref, the non-inverting input terminal is connected to the voltage output terminal 107 (Vout), and the output terminal of the error amplifier 101 is connected to the gate of the power switch tube 104 .

[0063] The power switch tube 104 is a PMOS power tube, the source of the power switch tube 104 is connected to the voltage source 102 (Vdd), and the drain is connected to the voltage output terminal 107 (VOUT).

[0064] One end of the current source 103 is connected to the drain of the power switch tube 104 and the voltage output terminal 107 , and the other end is grounded.

[0065] like Figure 2 , Figure 6 As shown, the voltage-stabilizing capacitor 105 includes a capacitor upper plate 1051 , a first capacitor lower plate 1052 , a second capacitor lower plate 1053 , a first special layer 1054 , and a second special layer 1055 .

[0066] like Figure 6 As shown, the first special layer 1054 is connected between the capacitor upper plate 1051 and the first capacitor lower plate 1052, and the second special layer 1055 is connected between the capacitor upper plate 1051 and the second capacitor lower plate 1053. One end of the second capacitor lower plate 1053 away from the first capacitor lower plate 1052 is grounded. One end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053 is connected to one end of the ESR resistor 106. The other end of the ESR resistor 106 is connected to the voltage output terminal 107 through the via 108. The resistance of the ESR resistor 106 is 3 ohms.

[0067] like Figure 2As shown, the ESR resistor 106 includes a first straight portion 1061, a second straight portion 1062, and a bent portion 1063. One end of the first straight portion 1061 is connected to the voltage output terminal 107 through the via 108, and the other end of the first straight portion 1061 is connected to one end of the bent portion 1063. One end of the second straight portion 1062 is connected to one end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053, and the other end of the second straight portion 1062 is connected to the other end of the bent portion 1063. In other words, the bent portion 1063 is connected between the first straight portion 1061 and the second straight portion 1062.

[0068] According to the LDO circuit structure of Example 1 of the present invention, compared with the previous LDO circuit, the length of the ESR resistor is lengthened by the bending portion while keeping the resistor width unchanged, which can not only ensure a larger resistance value to meet the design requirements, but also have sufficient current capacity to meet the requirements of the EM rule, that is, the current capacity can reach 5 to 10 mA, making the layout design more flexible and saving the space occupied by the circuit.

[0069] Example 2

[0070] Figure 3 Another structural schematic diagram of the voltage-stabilizing capacitor and the ESR resistor involved in the second embodiment of the present invention is shown.

[0071] like Figure 3 , Figure 6 As shown, similarly to Embodiment 1, the voltage stabilizing capacitor 105 includes a capacitor upper plate 1051, a first capacitor lower plate 1052, a second capacitor lower plate 1053, a first special layer 1054, and a second special layer 1055. The first special layer 1054 is connected between the capacitor upper plate 1051 and the first capacitor lower plate 1052, and the second special layer 1055 is connected between the capacitor upper plate 1051 and the second capacitor lower plate 1053. One end of the second capacitor lower plate 1053 away from the first capacitor lower plate 1052 is grounded. One end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053 is connected to one end of the ESR resistor 106. The other end of the ESR resistor 106 is connected to the voltage output terminal 107 through the via 108.

[0072] The ESR resistor 106 includes a first straight portion 1061, a second straight portion 1062, and a bent portion 1063. One end of the first straight portion 1061 is connected to the voltage output terminal 107 through the via 108, and the other end of the first straight portion 1061 is connected to one end of the bent portion 1063. One end of the second straight portion 1062 is connected to one end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053, and the other end of the second straight portion 1062 is connected to the other end of the bent portion 1063. In other words, the bent portion 1063 is connected between the first straight portion 1061 and the second straight portion 1062.

[0073] The difference between Example 2 and Example 1 is that the ESR resistor 106 includes 7 bends. Since this embodiment can further lengthen the length of the ESR resistor through multiple bends while keeping the resistor width unchanged, and can make the current capacity reach 5-10 mA. Therefore, the LDO circuit structure according to Example 2 of the present invention can further increase the resistance value through multiple bends to meet the design requirements compared with the previous LDO circuit, and at the same time have sufficient current capacity to meet the requirements of EM rules, making the layout design more flexible and saving more circuit space.

[0074] Example 3

[0075] Figure 4 Another structural schematic diagram of the voltage-stabilizing capacitor and the ESR resistor involved in the third embodiment of the present invention is shown.

[0076] like Figure 4 , Figure 6 As shown, similarly to Embodiment 1, the voltage stabilizing capacitor 105 includes a capacitor upper plate 1051, a first capacitor lower plate 1052, a second capacitor lower plate 1053, a first special layer 1054, and a second special layer 1055. The first special layer 1054 is connected between the capacitor upper plate 1051 and the first capacitor lower plate 1052, and the second special layer 1055 is connected between the capacitor upper plate 1051 and the second capacitor lower plate 1053. One end of the second capacitor lower plate 1053 away from the first capacitor lower plate 1052 is grounded. One end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053 is connected to one end of the ESR resistor 106. The other end of the ESR resistor 106 is connected to the voltage output terminal 107 through the via 108.

[0077] The difference between Example 3 and Example 1 is that the ESR resistor 106 is 4 resistors connected in parallel between the voltage stabilizing capacitor 105 and the voltage output terminal 107. Each ESR resistor 106 includes a first straight portion 1061, a second straight portion 1062, and a bent portion 1063. One end of the first straight portion 1061 is connected to the voltage output terminal 107 through a via 108, and the other end of the first straight portion 1061 is connected to the bent portion 1063. One end of the second straight portion 1062 is connected to the first capacitor lower plate 1052, and the other end of the second straight portion 1062 is connected to the bent portion 1063. In other words, the bent portion 1063 is connected between the first straight portion 1061 and the second straight portion 1062.

[0078] Since this embodiment can further lengthen the length of the ESR resistor through the bend portion to meet the resistance requirement while keeping the resistor width unchanged, and can increase the current passing through by connecting multiple bend resistors in parallel, the current capacity can reach 5-10 mA. Therefore, compared with the previous LDO circuit, the LDO circuit structure according to the third embodiment of the present invention can meet the design requirements of the resistor while having a greater current capacity to meet the requirements of the EM rule, making the layout design more flexible and saving more circuit space.

[0079] Example 4

[0080] Figure 5 Another structural schematic diagram of the voltage-stabilizing capacitor and the ESR resistor involved in the fourth embodiment of the present invention is shown.

[0081] like Figure 5 , Figure 6 As shown, similarly to Embodiment 1, the voltage stabilizing capacitor 105 includes a capacitor upper plate 1051, a first capacitor lower plate 1052, a second capacitor lower plate 1053, a first special layer 1054, and a second special layer 1055. The first special layer 1054 is connected between the capacitor upper plate 1051 and the first capacitor lower plate 1052, and the second special layer 1055 is connected between the capacitor upper plate 1051 and the second capacitor lower plate 1053. One end of the second capacitor lower plate 1053 away from the first capacitor lower plate 1052 is grounded. One end of the first capacitor lower plate 1052 away from the second capacitor lower plate 1053 is connected to one end of the ESR resistor 106. The other end of the ESR resistor 106 is connected to the voltage output terminal 107 through the via 108.

[0082] The difference between Example 4 and Example 1 is that the ESR resistor 106 is two resistors connected in parallel between the voltage stabilizing capacitor 105 and the voltage output terminal 107 .

[0083] Each ESR resistor 106 includes a first straight portion 1061, a second straight portion 1062, and three bent portions 1063. One end of the first straight portion 1061 is connected to the voltage output terminal 107 through the via 108, and the other end of the first straight portion 1061 is connected to the bent portion 1063. One end of the second straight portion 1062 is connected to the first capacitor lower plate 1052, and the other end of the second straight portion 1062 is connected to the bent portion 1063. In other words, the bent portion 1063 is connected between the first straight portion 1061 and the second straight portion 1062.

[0084] Since the present embodiment can further lengthen the length of the ESR resistor by using multiple bending parts while keeping the resistor width unchanged so that the resistor meets the requirements, and the multiple ESR resistors are connected in parallel to increase the current passing through, the current capacity can reach 5-10 mA. Therefore, the LDO circuit structure according to the fourth embodiment of the present invention can further increase the resistance value to meet the design requirements compared with the previous LDO circuit, and at the same time have sufficient current capacity to meet the requirements of the EM rule, so that the layout design flexibility is greater and the circuit space is saved.

[0085] The power switch tube in each of the above embodiments may be a PMOS power tube or other transistors such as an IGBT transistor.

[0086] The resistance value of the ESR resistor in the above embodiments is not limited to 3 ohms, and can be greater than 3 ohms.

[0087] The voltage stabilizing capacitor in each of the above embodiments may be 1-2 nF.

[0088] The material of the ESR resistor in each of the above embodiments may be tungsten.

[0089] The material of the voltage stabilizing capacitor in each of the above embodiments may be tungsten.

[0090] The voltage output terminal in each of the above embodiments is made of metal material, which may be tungsten.

[0091] In the above-mentioned embodiments, the first capacitor lower plate 1052 and the ESR resistor 106 may be formed integrally, or the first capacitor lower plate 1052 and the ESR resistor 106 may be formed separately and then connected together by welding or the like.

[0092] In summary, the LDO circuit according to the first aspect of the present invention includes: an error amplifier; a voltage source; a current source; a power switch tube; a voltage-stabilizing capacitor; an ESR resistor; a voltage output end, the inverting input end of the error amplifier is connected to a reference voltage, the non-inverting input end is connected to the voltage output end, the output end of the error amplifier is connected to the gate of the power switch tube, the source of the power switch tube is connected to the voltage source, the drain is connected to the voltage output end, one end of the current source is connected to the voltage output end, and the other end is grounded, one end of the ESR resistor is connected to the voltage output end, and the other end is connected to one end of the voltage-stabilizing capacitor, the ESR resistor has at least one bend, and the other end of the voltage-stabilizing capacitor is grounded. Therefore, the LDO circuit of the present invention can not only ensure a larger resistance value to meet the design requirements, but also have sufficient current capacity to meet the requirements of EM rules.

[0093] According to the LDO circuit of the second aspect of the present invention, the power switch tube is a PMOS power tube.

[0094] In the LDO circuit according to the third aspect of the present invention, the resistance value of the ESR resistor is greater than 3 ohms.

[0095] According to the LDO circuit of the fourth aspect of the present invention, the ESR resistor is connected to the voltage output terminal through a via.

[0096] According to the LDO circuit of the fifth aspect of the present invention, the voltage stabilizing capacitor is 1-2 nF.

[0097] According to the LDO circuit of the sixth aspect of the present invention, the material of the ESR resistor is tungsten.

[0098] According to the LDO circuit of the seventh aspect of the present invention, the voltage-stabilizing capacitor includes an upper capacitor plate, two lower capacitor plates, and a special layer connected between the upper capacitor plate and the two lower capacitor plates, one lower capacitor plate is connected to the ESR resistor, and the other lower capacitor plate is grounded.

[0099] According to the LDO circuit of the eighth aspect of the present invention, an ESR resistor is connected between the other capacitor lower plate and the ground.

[0100] According to the LDO circuit of the ninth aspect of the present invention, the ESR resistor has a plurality of bends. Thus, the LDO circuit of the present invention can ensure a larger resistance value to meet the design requirements and have sufficient current capacity to meet the requirements of EM regulations.

[0101] According to the tenth aspect of the LDO circuit of the present invention, the ESR resistor is a plurality of resistors connected in parallel between the voltage stabilizing capacitor and the voltage output terminal. Thus, the LDO circuit of the present invention can ensure a larger resistance value to meet the design requirements and further improve the current capacity to meet the requirements of the EM rule.

[0102] So far, the LDO circuit according to the embodiment of the present disclosure is described. The market has increasingly higher requirements for the design flexibility and space saving of the LDO circuit. The present disclosure provides an LDO circuit to make the design flexibility of the LDO circuit greater and save more space occupied by the circuit.

[0103] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or their various aspects) can be used in combination with each other. In addition, without departing from the scope of the present disclosure, many modifications can be made to adapt specific conditions or materials to the teachings of the various embodiments of the present disclosure. Although the size and type of the material described herein are used to define the parameters of the various embodiments of the present disclosure, the various embodiments are not meant to be restrictive, but exemplary embodiments. In reading the above description, many other embodiments are obvious to those skilled in the art. Therefore, the scope of the various embodiments of the present disclosure should be determined with reference to the attached claims, and the full range of equivalent forms claimed by these claims.

Claims

1. An LDO circuit, characterized in that: include: Error amplifier; Voltage source; Current source; Power switch tube; Voltage stabilizing capacitor; ESR resistor; voltage output terminal, The inverting input terminal of the error amplifier is connected to the reference voltage, the non-inverting input terminal is connected to the voltage output terminal, and the output terminal of the error amplifier is connected to the gate of the power switch tube. The source of the power switch tube is connected to the voltage source, and the drain is connected to the voltage output terminal. One end of the current source is connected to the voltage output end, and the other end is grounded. One end of the ESR resistor is connected to the voltage output end, and the other end is connected to one end of the voltage stabilizing capacitor. The ESR resistor has at least one bent portion. The other end of the voltage stabilizing capacitor is grounded.

2. The LDO circuit according to claim 1, wherein: The power switch tube is a PMOS power tube.

3. The LDO circuit according to claim 1, wherein: include: The resistance value of the ESR resistor is greater than 3 ohms.

4. The LDO circuit according to claim 1, wherein: The ESR resistor is connected to the voltage output terminal through a via.

5. The LDO circuit according to claim 1, wherein: The voltage stabilizing capacitor is 1-2 nF.

6. The LDO circuit according to claim 1, wherein: The material of the ESR resistor is tungsten.

7. The LDO circuit according to claim 1, wherein: The voltage stabilizing capacitor comprises an upper capacitor plate, two lower capacitor plates, and a special layer connected between the upper capacitor plate and the two lower capacitor plates, one lower capacitor plate is connected to an ESR resistor, and the other lower capacitor plate is grounded.

8. The LDO circuit according to claim 7, wherein: An ESR resistor is connected between the lower plate of the other capacitor and ground.

9. The LDO circuit according to claim 1, wherein: The ESR resistor has a plurality of bent portions.

10. The LDO circuit according to claim 1, wherein: The ESR resistor is a plurality of resistors connected in parallel between the voltage stabilizing capacitor and the voltage output terminal.

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