Low-dropout linear voltage stabilizing circuit, chip and electronic equipment

Abstract

The invention discloses a low-dropout linear voltage stabilizing circuit, a chip and electronic equipment, and belongs to the field of semiconductor integrated circuits. The circuit comprises a voltage detection module, a first adjusting module and a second adjusting module. The voltage detection module is connected with a target output end of the circuit and is used for outputting a first control voltage according to an output voltage of the target output end; the first adjusting module is connected with the voltage detection module and the target output end and used for providing first current for the target output end according to the first control voltage. The second adjusting module is connected with the voltage detection module and the target output end and used for providing second current for the target output end according to the first control voltage. Wherein the first current and the second current are both used for stabilizing the output voltage. Under the condition that the output voltage changes, the output voltage can be recovered more quickly through the first current and the second current, the transient response of the circuit is improved, and the circuit performance is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor integrated circuits, and in particular to a low voltage difference linear voltage regulator circuit, chip and electronic device. Background Art

[0002] LDO (Low Dropout Linear Regulator) is a voltage stabilization circuit that can ensure a stable output voltage within the range of load current variation to provide power to other chips.

[0003] In the related art, if the load current changes, the output voltage of the LDO will change accordingly. The LDO itself can adjust the output voltage to keep the output voltage stable. The process of restoring the output voltage to stability is called transient response, and how to improve the transient response of the LDO has become an urgent problem to be solved. Summary of the invention

[0004] The present application provides a low voltage difference linear voltage regulator circuit, a chip and an electronic device, which can be used to solve the problems in the related art. The technical solution includes the following contents.

[0005] In a first aspect, a low voltage difference linear voltage regulator circuit is provided, characterized in that the circuit comprises a voltage detection module, a first regulation module and a second regulation module;

[0006] The voltage detection module is connected to the target output terminal of the low voltage difference linear voltage regulator circuit and is used to output a first control voltage according to the output voltage of the target output terminal;

[0007] The first regulating module is connected to the voltage detection module and the target output terminal respectively, and is used to receive the first control voltage and provide a first current to the target output terminal according to the first control voltage;

[0008] The second regulating module is connected to the voltage detection module and the target output terminal respectively, and is used to receive the first control voltage and provide a second current to the target output terminal according to the first control voltage;

[0009] Wherein, the first current and the second current are both used to stabilize the output voltage.

[0010] In a possible implementation, the first regulating module includes a first regulating unit, a first current source and a first transistor;

[0011] The first regulating unit is connected to the voltage detection module and the gate of the first transistor respectively, and is used to receive the first control voltage and provide a first target current to the gate of the first transistor according to the first control voltage;

[0012] The first current source is connected to the gate of the first transistor and is used to provide a first reference current to the gate of the first transistor;

[0013] The source of the first transistor is connected to the first input terminal, and the drain of the first transistor is connected to the target output terminal, and is used to provide the first current to the target output terminal according to a second control voltage. The first input terminal is used to provide a supply voltage, and the second control voltage is determined according to the first target current and the first reference current.

[0014] In a possible implementation, the first regulating unit includes a second transistor and a first mirror component;

[0015] The source of the second transistor is connected to the first input terminal, the drain of the second transistor is connected to the first mirror component, and the gate of the second transistor is connected to the voltage detection module, and is used to receive the first control voltage and provide a first source current to the first mirror component according to the first control voltage;

[0016] The first mirror component is connected to the gate of the first transistor, and is used for receiving the first source current and outputting the first target current to the gate of the first transistor, where the first target current is a mirror current of the first source current.

[0017] In a possible implementation, the first mirror component includes a third transistor and a fourth transistor;

[0018] The source of the third transistor is grounded, the drain of the third transistor is connected to the drain of the second transistor, and the gate of the third transistor is connected to the drain of the second transistor and the gate of the fourth transistor, and is used to receive the first source current and provide a first gate current to the fourth transistor;

[0019] The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the gate of the first transistor, for receiving the first gate current and outputting the first target current to the gate of the first transistor.

[0020] In a possible implementation, the first regulating module includes a second regulating unit, a first comparator, a fifth transistor and a first resistor, and one end of the first resistor is connected to the first input end;

[0021] The second regulating unit is connected to the voltage detection module and the first comparator respectively, and is used to receive the first control voltage and provide a first target voltage to the first comparator according to the first control voltage;

[0022] The first comparator is connected to the gate of the fifth transistor and the second input terminal, and is used to receive a first reference voltage and the first target voltage, and output a third control voltage to the gate of the fifth transistor according to the first reference voltage and the first target voltage, and the second input terminal is used to provide the first reference voltage;

[0023] The source of the fifth transistor is connected to the other end of the first resistor, and the drain of the fifth transistor is connected to the target output terminal, and is used to provide the first current to the target output terminal according to the third control voltage. The first input terminal is used to provide a supply voltage.

[0024] In a possible implementation, the second regulating unit includes: a sixth transistor and a second resistor, wherein the second resistor is grounded and connected to the drain of the sixth transistor;

[0025] The source of the sixth transistor is connected to the first input terminal, and the gate of the sixth transistor is connected to the voltage detection module, for receiving the first control voltage and providing the first target voltage to the first comparator according to the first control voltage.

[0026] In a possible implementation, the circuit further includes a third regulating module;

[0027] The third regulating module is connected to the voltage detection module, the target output terminal and the ground terminal respectively, and is used to receive the first control voltage and output a third current according to the first control voltage;

[0028] The third current is a current from the target output terminal to the ground terminal, and the third current is used to stabilize the output voltage.

[0029] In a possible implementation, the voltage detection module includes a sampling module and an error amplifier;

[0030] The sampling module is connected to the target output terminal and the error amplifier respectively, and is used to receive the output voltage and output the feedback voltage to the error amplifier according to the output voltage;

[0031] The error amplifier is connected to the third input terminal, and is used to receive the feedback voltage and the second reference voltage, and output the first control voltage according to the feedback voltage and the second reference voltage. The third input terminal is used to provide the second reference voltage.

[0032] In a possible implementation, the second regulating module includes a target transistor;

[0033] The source of the target transistor is connected to the first input terminal, the drain of the target transistor is connected to the target output terminal, and the gate of the target transistor is connected to the voltage detection module, which is used to receive the first control voltage and provide the second current to the target output terminal according to the first control voltage. The first input terminal is used to provide a supply voltage.

[0034] In a second aspect, a chip is provided, wherein the chip includes the low voltage difference linear voltage regulator circuit described in the first aspect and any possible implementation manner.

[0035] In a third aspect, an electronic device is provided, wherein the electronic device comprises the low voltage difference linear voltage regulator circuit described in the first aspect and any possible implementation manner.

[0036] The technical solution provided by this application brings at least the following beneficial effects:

[0037] In the technical solution provided by the present application, the voltage detection module can determine the first control voltage according to the output voltage of the target output terminal, the first regulation module can determine the first current provided to the target output terminal according to the first control voltage, and the second regulation module can determine the second current provided to the target output terminal according to the first control voltage. Since the first current and the second current are both used to stabilize the output voltage, when the output voltage changes, the output voltage can be restored more quickly through the first current and the second current, thereby improving the recovery speed of the output voltage, thereby improving the transient response of the circuit and improving the circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 It is a schematic diagram of a low voltage difference linear voltage regulator circuit provided by the related technology;

[0040] Figure 2 It is a waveform diagram provided by the relevant technology;

[0041] Figure 3 is a schematic diagram of a low voltage difference linear voltage stabilization circuit provided in an embodiment of the present application;

[0042] Figure 4 is a schematic diagram of another low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0043] Figure 5is a schematic diagram of another low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0044] Figure 6 is a schematic diagram of another low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0045] Figure 7 is a schematic diagram of another low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0046] Figure 8 is a schematic diagram of another low voltage difference linear voltage regulator circuit provided in an embodiment of the present application;

[0047] Fig. 9 It is a waveform diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0049] It should be noted that the terms "first", "second", etc. in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0050] In the field of semiconductor integrated circuits, LDO (Low Dropout Linear Regulator) is a common voltage stabilization circuit that can ensure the output of a stable voltage within the range of load current variation to supply power to other chips.

[0051] like Figure 1 As shown, Figure 1 It is a schematic diagram of a low voltage difference linear voltage regulator circuit provided by the related technology. The low voltage difference linear voltage regulator circuit includes an error amplifier (Error Amplifier, EA), a transistor (also called a power tube) MP, a resistor R1, a resistor R2 and a capacitor COUT. The capacitor COUT is connected to the output end of the low voltage difference linear voltage regulator circuit. The output voltage VOUT of the output end is used to power the load Rload.

[0052] exist Figure 1In the figure, the transistor MP is a PMOS (P-Channel Metal Oxide Semiconductor), which has the characteristic of low-level conduction. In practical applications, a low-voltage difference linear voltage regulator circuit can also be designed based on NMOS (N-Channel Metal Oxide Semiconductor), which will not be described here. NMOS has the characteristic of high-level conduction. The following takes the transistor MP as a PMOS as an example to explain the operating principle of the low-voltage difference linear voltage regulator circuit.

[0053] like Figure 1 As shown, when the transistor MP is a PMOS, the output end of the error amplifier EA is connected to the gate of the transistor MP, the source voltage of the transistor MP is the power supply voltage VIN, and the drain of the transistor MP is connected to the output end of the low voltage difference linear voltage regulator circuit, and is used to provide the output voltage VOUT. One end of the resistor R1 is connected to the drain of the transistor MP, the other end of the resistor R1 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded. The resistor R1 and the resistor R2 constitute a sampling module for sampling the output voltage VOUT to obtain the feedback voltage VFB. The positive input end (i.e., the in-phase input end, referred to as the positive end) of the error amplifier EA is connected to the connection node between the resistor R1 and the resistor R2, and is used to receive the feedback voltage VFB. The negative input end (i.e., the inverting input end, referred to as the negative end) of the error amplifier EA receives the reference voltage VREF. In addition, the voltage at the power supply end of the error amplifier EA is the power supply voltage VIN. One end of the capacitor COUT is connected to the resistor R1 and the drain of the transistor MP, that is, the voltage at this end is the output voltage VOUT, and the other end of the capacitor COUT is connected to the ground end GND. One end of the load Rload is connected to the resistor R1 , the drain of the transistor MP, and the capacitor COUT, that is, the voltage at this end is the output voltage VOUT, and the other end of the load Rload is connected to the ground end GND.

[0054] When the low voltage difference linear voltage regulator circuit is in a steady state, the load current of the load Rload will not change. At this time, the capacitor COUT is no longer charged or discharged, and the output voltage VOUT is in a stable state. After sampling the output voltage VOUT through resistors R1 and R2, the feedback voltage VFB is obtained and input to the error amplifier EA. The error amplifier EA generates a control voltage Vgs based on the error between the feedback voltage VFB and the reference voltage VREF. The control voltage Vgs is used to control the on-current of the transistor MP. Since the circuit is in a steady state, the value of the control voltage Vgs remains unchanged, so that the on-current of the transistor MP remains unchanged, and the output voltage VOUT will not change. At this time, the low voltage difference linear voltage regulator circuit can provide a stable output voltage VOUT for powering the load Rload.

[0055] Optionally, when the low voltage difference linear voltage regulator circuit is in a steady state, since the capacitor COUT is no longer charged or discharged, the circuit mainly provides the load current of the load Rload through the on-current of the transistor MP. In this case, the feedback voltage VFB is equal to (or approximately equal to) the reference voltage VREF. At this time, the value of the control voltage Vgs remains unchanged, and the on-current of the transistor MP remains unchanged, so that the output voltage VOUT will not change. In this case, the output voltage VOUT satisfies: VOUT=(VREF / R2)×(R1+R2). Since the reference voltage VREF, the resistor R1 and the resistor R2 remain unchanged, the output voltage VOUT will not change.

[0056] In the field of semiconductor integrated circuits, a transient increase in the load current of a load Rload is often referred to as a change from a light load to a heavy load. Conversely, a transient decrease in the load current of the load Rload is referred to as a change from a heavy load to a light load.

[0057] When the load Rload changes from light load to heavy load, the load current increases transiently. Since the low voltage difference linear voltage regulator circuit does not have time to respond, that is, the on-current of the transistor MP does not have time to increase, the capacitor COUT needs to discharge to provide the current of the load Rload. The discharge of the capacitor COUT will cause the output voltage VOUT to drop sharply. Figure 2 As shown, Figure 2 (1) shows the waveform of the output voltage VOUT. Figure 2 (2) in FIG. 1 shows the waveform of the load current, wherein the negative sign “-” in “-80.0 mA (milliamperes)” represents the direction of the load current, and the value “80.0 mA” represents the magnitude of the load current. Figure 2 It can be seen that when the load current increases from 0 to 80mA, the output voltage VOUT will drop sharply from 3.30658V (volts) to 3.30025V, a decrease of about 6.33mV (millivolts).

[0058] It is understandable that the output voltage VOUT will drop due to the influence of the load current, but the low-voltage dropout linear voltage regulator circuit has the ability to adjust and can return to a steady state after a period of adjustment. As the name implies, steady state refers to a stable state. When the low-voltage dropout linear voltage regulator circuit is in a steady state, the output voltage VOUT remains unchanged. In this example, the process of changing the low-voltage dropout linear voltage regulator circuit from one steady state to another is called transient. When the low-voltage dropout linear voltage regulator circuit is in a transient state, the output voltage VOUT will change.

[0059] When the low voltage difference linear voltage regulator circuit is in a transient state, since the load Rload changes from a light load to a heavy load (i.e., the load current transiently increases), the capacitor COUT is discharged, causing the output voltage VOUT to drop, causing the feedback voltage VFB to drop, causing the control voltage Vgs to drop, thereby increasing the on-current of the transistor MP. By continuously increasing the on-current of the transistor MP, the increased current of the load Rload is compensated by the on-current, and the capacitor COUT is charged, so that the output voltage VOUT gradually increases, and finally the low voltage difference linear voltage regulator circuit is in a steady state again, and the output voltage VOUT remains unchanged.

[0060] It should be noted that, when the load current is different, the operating point of the low voltage difference linear voltage regulator circuit is different, so that the output voltage VOUT in the steady state is also different. Optionally, in the case of a transient increase in the load current, the output voltage of the circuit in the steady state before the transient increase in the load current is higher than the output voltage of the circuit in the steady state after the transient increase in the load current. Figure 2 As shown in (1), the output voltage VOUT of the circuit in a steady state before the load current transiently increases is 3.30658V (volts), and the output voltage VOUT of the circuit in a steady state after the load current transiently increases is 3.30468V, and the output voltage VOUT decreases.

[0061] When the load Rload changes from heavy load to light load, that is, the load current decreases transiently, the low voltage drop linear regulator circuit does not have time to respond, that is, the on-current of the transistor MP does not have time to decrease. Therefore, the capacitor COUT needs to be charged to extract the current of the load Rload decrease. The charging of the capacitor COUT will cause the output voltage VOUT to rise sharply. Figure 2 As shown in the figure, when the load current decreases from 80mA to 0, the output voltage VOUT rises sharply, with an increase of about 6.26mV.

[0062] When the low voltage difference linear voltage regulator circuit is in a transient state, since the load Rload changes from a heavy load to a light load (i.e., the load current decreases transiently), the capacitor COUT is charged, causing the output voltage VOUT to rise, causing the feedback voltage VFB to rise, causing the control voltage Vgs to increase, thereby reducing the on-current of the transistor MP. By continuously reducing the on-current of the transistor MP, a smaller current is provided to the load Rload, and the capacitor COUT is discharged, causing the output voltage VOUT to gradually decrease, and finally the low voltage difference linear voltage regulator circuit is in a steady state again, and the output voltage VOUT remains unchanged.

[0063] Optionally, in the case of a transient decrease in the load current, the output voltage of the circuit in a steady state before the transient decrease in the load current is lower than the output voltage of the circuit in a steady state after the transient decrease in the load current. Figure 2As shown in (1), the output voltage VOUT of the circuit in a steady state before the load current transiently decreases is 3.30468 V, which is lower than the output voltage VOUT of the circuit in a steady state after the load current transiently decreases.

[0064] The transient response of the low voltage drop linear voltage regulator circuit in the related art is poor. Figure 2 As shown, in the process of the load current jumping from 0 to 80mA and then jumping to 0, the change amplitude of the output voltage VOUT is 6.33+6.26=12.59mV. Since the change amplitude of the output voltage VOUT is large when the low-voltage difference linear voltage regulator circuit is in a transient state, the transient response of the low-voltage difference linear voltage regulator circuit is poor. In this regard, the embodiment of the present application provides a low-voltage difference linear voltage regulator circuit, which can improve the transient response of the circuit, thereby improving the performance of the circuit.

[0065] like Figure 3 As shown, Figure 3 Schematic diagram of a low voltage difference linear voltage regulator circuit provided in an embodiment of the present application. The low voltage difference linear voltage regulator circuit includes a voltage detection module 10, a first regulation module 20 and a second regulation module 30. Among them, Figure 3 The black circle in the figure represents the output terminal, and the white circle represents the input terminal.

[0066] In an exemplary embodiment, a voltage detection module 10 is connected to a target output terminal of a low voltage difference linear voltage regulator circuit, and is used to output a first control voltage according to an output voltage of the target output terminal; a first adjustment module 20 is respectively connected to the voltage detection module 10 and the target output terminal, and is used to receive a first control voltage and provide a first current to the target output terminal according to the first control voltage; a second adjustment module 30 is respectively connected to the voltage detection module 10 and the target output terminal, and is used to receive a first control voltage and provide a second current to the target output terminal according to the first control voltage; wherein both the first current and the second current are used to stabilize the output voltage.

[0067] That is to say, Figure 4As shown, the low voltage difference linear voltage regulator circuit includes a target output terminal, and the target output terminal is used to provide an output voltage VOUT. The voltage detection module 10 is connected to the target output terminal, and is used to receive the output voltage VOUT of the target output terminal, and output the first control voltage Vgs1 according to the output voltage VOUT. Among them, the first control voltage Vgs1 is positively correlated with the output voltage VOUT. That is, when the output voltage VOUT increases, the first control voltage Vgs1 increases, and when the output voltage VOUT decreases, the first control voltage Vgs1 decreases. The first regulating module 20 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 output by the voltage detection module 10. The first regulating module 20 is also connected to the target output terminal, and is used to provide a first current I1 to the target output terminal. Among them, the first current I1 is negatively correlated with the first control voltage Vgs1. That is, when the first control voltage Vgs1 increases, the first current I1 decreases; and when the first control voltage Vgs1 decreases, the first current I1 increases. The second regulating module 30 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 output by the voltage detection module 10. The second regulating module 20 is also connected to the target output terminal, and is used to provide a second current I2 to the target output terminal. The second current I2 is negatively correlated with the first control voltage Vgs1. That is, when the first control voltage Vgs1 increases, the second current I2 decreases; and when the first control voltage Vgs1 decreases, the second current I2 increases.

[0068] The low voltage difference linear voltage regulator circuit also includes a first input terminal, which is used to provide a power supply voltage VIN. The voltage detection module 10, the first adjustment module 20 and the second adjustment module 30 are all connected to the first input terminal to receive the power supply voltage VIN provided by the first input terminal so that each module can operate normally.

[0069] The low voltage difference linear voltage regulator circuit also includes a capacitor COUT, one end of which is connected to the target output terminal so that the voltage at the end is the output voltage VOUT. The other end of the capacitor COUT can be grounded, or can be connected to other circuits or other components, etc. The other components include but are not limited to at least one of a resistor, an amplifier, a power tube, a power supply, a switch, etc. In practical applications, the low voltage difference linear voltage regulator circuit can also include other components, which will not be repeated here.

[0070] The output voltage VOUT is used to power the load Rload. Optionally, one end of the load Rload is connected to the target output end, so that the voltage of the end is the output voltage VOUT. The other end of the load Rload can be grounded, or can be connected to other circuits or other components.

[0071] In this example, when the low voltage difference linear voltage regulator circuit is in a steady state, the capacitor COUT is no longer charged or discharged. At this time, the output voltage VOUT does not change, and the output current formed by combining the first current I1 and the second current I2 is used to provide the load current of the load Rload.

[0072] When the load Rload changes from a light load to a heavy load, that is, the load current transiently increases, since the low voltage difference linear voltage regulator circuit does not have time to respond, that is, the first current I1 and the second current I2 do not have time to increase, therefore, the capacitor COUT needs to discharge to provide the load current that increases the load Rload. The discharge of the capacitor COUT will cause the output voltage VOUT to drop sharply. In this case, the low voltage difference linear voltage regulator circuit changes from a steady state to a transient state. Since the first current I1 and the second current I2 are both used to stabilize the output voltage VOUT, therefore, when the output voltage VOUT drops, the first current I1 and the second current I2 will both increase. By continuously increasing the first current I1 and the second current I2, it is achieved that the load current that increases the load Rload is provided by these two currents, and the capacitor COUT is charged, so that the output voltage VOUT gradually increases, and finally the low voltage difference linear voltage regulator circuit is in a steady state again, and the output voltage VOUT remains unchanged.

[0073] On the contrary, when the load Rload changes from heavy load to light load, that is, the load current of the load Rload decreases transiently, since the low voltage difference linear voltage regulator circuit does not have time to respond, that is, the first current I1 and the second current I2 do not have time to decrease, therefore, the capacitor COUT needs to be charged to extract the load current of the load Rload. The charging of the capacitor COUT will cause the output voltage VOUT to rise sharply. In this case, the low voltage difference linear voltage regulator circuit changes from a steady state to a transient state. Since the first current I1 and the second current I2 are both used to stabilize the output voltage VOUT, when the output voltage VOUT rises, the first current I1 and the second current I2 will both decrease. By continuously reducing the first current I1 and the second current I2, a smaller load current is provided to the load Rload, and the capacitor COUT is discharged, so that the output voltage VOUT gradually decreases, and finally the low voltage difference linear voltage regulator circuit is in a steady state again, and the output voltage VOUT remains unchanged.

[0074] In one possible implementation, Figure 5As shown, the voltage detection module 10 includes a sampling module 101 and an error amplifier EA; the sampling module 101 is respectively connected to the target output terminal and the error amplifier EA, and is used to receive the output voltage VOUT, and output a feedback voltage VFB1 to the error amplifier EA according to the output voltage VOUT; the error amplifier EA is connected to the third input terminal, and is used to receive the feedback voltage VFB and the second reference voltage VREF1, and output a first control voltage Vgs1 according to the feedback voltage VFB1 and the second reference voltage VREF1, and the third input terminal is used to provide the second reference voltage VREF1.

[0075] One end of the sampling module 101 is connected to the target output end, and is used to receive the output voltage VOUT provided by the target output end. The other end of the sampling module 101 is connected to the positive end of the error amplifier EA, and is used to output the feedback voltage VFB1 to the positive end of the error amplifier EA. The embodiment of the present application does not limit the structure of the sampling module 101. Exemplarily, the sampling module 101 is a capacitive voltage divider component, and the capacitive voltage divider component includes a capacitor and a resistor, and the capacitor is connected in series with the resistor. The output voltage VOUT can act on the capacitor, and the capacitor will store charge, thereby producing a voltage division effect, and obtaining the feedback voltage VFB1.

[0076] Alternatively, the sampling module 101 is a resistive voltage divider component, which includes a plurality of sampling resistors connected in series. After the output voltage VOUT passes through at least one sampling resistor, a feedback voltage VFB1 is obtained, and the feedback voltage VFB1 is less than the output voltage VOUT. Figure 5 As shown, the sampling module 101 includes a sampling resistor R1 and a sampling resistor R2 connected in series, one end of the sampling resistor R1 is connected to the target output end, so that the voltage at the end is the output voltage VOUT. The other end of the sampling resistor R1 is connected to one end of the sampling resistor R2. The other end of the sampling resistor R2 is connected to the ground terminal GND, so that the voltage at the end is 0. After the output voltage VOUT is divided by the sampling resistor R1, a feedback voltage VFB1 is obtained. And the feedback voltage VFB1 satisfies: In practical applications, the other end of the sampling resistor R2 may not be grounded, but may be connected to other circuits or other components, which is not limited here.

[0077] The positive terminal of the error amplifier EA is connected to the sampling module 101, for example, the positive terminal of the error amplifier EA is connected to the series node between the sampling resistor R1 and the sampling resistor R2, for receiving the feedback voltage VFB1. The negative terminal of the error amplifier EA is connected to the third input terminal, for receiving the second reference voltage VREF1 provided by the third input terminal. Optionally, the third input terminal is one end of the output voltage of the power supply circuit or one end of the output voltage of the component, for example, the third input terminal is one end of the output voltage of the capacitor or the power supply, for providing the second reference voltage VREF1. The error amplifier EA detects the error voltage between the actual output voltage and the expected output voltage by comparing the feedback voltage VFB1 (i.e., the voltage obtained by sampling the actual output voltage VOUT) with the second reference voltage VREF1. By amplifying the error voltage, the first control voltage Vgs1 is output. It can be seen that the first control voltage Vgs1 is positively correlated with the error voltage.

[0078] Optionally, the power supply terminal of the error amplifier EA is connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal, so that the error amplifier EA can operate normally. The first input terminal is an end of the output voltage of the power supply circuit or an end of the output voltage of the component, for example, the first input terminal is an end of the output voltage of the switching power supply circuit, and is used to provide the power supply voltage VIN.

[0079] In this example, when the load Rload changes from a light load to a heavy load, that is, the load current transiently increases, causing the capacitor COUT to discharge, thereby causing the output voltage VOUT to decrease. As the output voltage VOUT decreases, the feedback voltage VFB1 decreases, thereby causing the first control voltage Vgs1 to decrease. On the contrary, when the load Rload changes from a heavy load to a light load, that is, the load current transiently decreases, causing the capacitor COUT to charge, thereby causing the output voltage VOUT to increase. As the output voltage VOUT increases, the feedback voltage VFB1 increases, thereby causing the first control voltage Vgs1 to increase.

[0080] The first regulating module 20 can receive the first control voltage Vgs1, and provide the first current I1 to the target output terminal according to the first control voltage Vgs1. The first regulating module 20 satisfies: when the first control voltage Vgs1 decreases, it outputs a higher first current I1; when the first control voltage Vgs1 increases, it outputs a lower first current I1. Based on this, in practical applications, any circuit that meets this function can be used as the first regulating module 20. Several possible implementations are shown below, as shown in implementation A and implementation B, respectively.

[0081] In implementation A, if Figure 5As shown, the first regulating module 20 includes a first regulating unit 201, a first current source IREF1 and a first transistor M4. The first regulating unit 201 is connected to the voltage detection module 10 and the gate of the first transistor M4, respectively, and is used to receive the first control voltage Vgs1, and provide the first target current I3 to the gate of the first transistor M4 according to the first control voltage Vgs1; the first current source IREF1 is connected to the gate of the first transistor M4, and is used to provide the first reference current I4 to the gate of the first transistor M4; the source of the first transistor M4 is connected to the first input terminal, and the drain of the first transistor M4 is connected to the target output terminal, and is used to provide the first current I1 to the target output terminal according to the second control voltage Vgs2, the first input terminal is used to provide the power supply voltage VIN, and the second control voltage Vgs2 is determined according to the first target current I3 and the first reference current I4.

[0082] One end of the first regulating unit 201 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The other end of the first regulating unit 201 is connected to the gate of the first transistor M4, and is used to provide the first target current I3 to the gate of the first transistor M4. In addition, the first regulating unit 201 is also connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The first regulating unit 201 is also connected to the ground terminal GND, so that the voltage of the terminal is 0. By connecting to the first input terminal and the ground terminal GND, the first regulating unit 201 can operate normally.

[0083] The present embodiment does not limit the structure of the first adjustment unit 201. For example, Figure 5 As shown, the first regulating unit 201 includes a second transistor M1 and a first mirror component 202 .

[0084] Among them, the source of the second transistor M1 is connected to the first input terminal, the drain of the second transistor M1 is connected to the first mirror component 202, and the gate of the second transistor M1 is connected to the voltage detection module 10, which is used to receive the first control voltage Vgs1, and provide the first source current I5 to the first mirror component 202 according to the first control voltage Vgs1; the first mirror component 202 is connected to the gate of the first transistor M4, which is used to receive the first source current I5 and output the first target current I3 to the gate of the first transistor M4, and the first target current I3 is a mirror current of the first source current I5.

[0085] In this example, the second transistor M1 is a PMOS tube. When the actual voltage of the gate of the PMOS tube is lower than its threshold voltage, a current path can be formed between the source and drain of the PMOS tube, and the source of the PMOS tube outputs a conduction current to the drain through the current path. Moreover, the lower the actual voltage of the gate of the PMOS tube, the greater the conduction current; the higher the actual voltage of the gate of the PMOS tube, the smaller the conduction current.

[0086] Based on this, the source of the second transistor M1 is connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal, so that when the second transistor M1 is turned on (i.e., when a current path is formed between the source and the drain), a conduction current is provided. The drain of the second transistor M1 is connected to the first mirror component 202, and is used to provide the first source current I5 to the first mirror component 202. The first source current I5 is the conduction current from the source to the drain of the second transistor M1. The gate of the second transistor M1 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The first control voltage Vgs1 is used to control the magnitude of the first source current I5. Based on the working characteristics of the PMOS tube, it can be known that if the first control voltage Vgs1 decreases (equivalent to an increase in the absolute value of the first control voltage Vgs1), the first source current I5 increases; if the first control voltage Vgs1 increases (equivalent to a decrease in the absolute value of the first control voltage Vgs1), the first source current I5 decreases.

[0087] The first mirror component 202 is connected to the drain of the second transistor M1, and is used to receive the first source current I5 provided by the drain of the second transistor M1. The first mirror component 202 is also connected to the gate of the first transistor M4, and is used to output the first target current I3 to the gate of the first transistor M4. The first target current I3 is a mirror current of the first source current I5.

[0088] It should be noted that the first mirror component 202 is a mirror current source, which can mirror the input current in a certain ratio to obtain the output current. For example, when the mirror ratio is 1, the input current can be equal to the output current; when the mirror ratio is greater than 1, the input current can be less than the output current; when the mirror ratio is less than 1, the input current can be greater than the output current. Based on this, the direction of the first target current I3 is the same as the direction of the first source current I5, but the magnitude of the first target current I3 can be the same as or different from the magnitude of the first source current I5. Exemplarily, the first source current I5 is equal to the first target current I3. When the first source current I5 increases, the first target current I3 also increases; when the first source current I5 decreases, the first target current I3 also decreases. By determining the first target current I3 according to the first source current I5 by the first mirror component 202, a stable current is provided to the gate of the first transistor M4 to help the circuit reach a stable state and improve circuit performance.

[0089] In an exemplary embodiment, if Figure 5 As shown, the first mirror component 202 includes a third transistor M2 and a fourth transistor M3; the source of the third transistor M2 is grounded, the drain of the third transistor M2 is connected to the drain of the second transistor M1, and the gate of the third transistor M2 is connected to the drain of the second transistor M1 and the gate of the fourth transistor M3, and is used to receive the first source current I5 and provide the first gate current I to the fourth transistor M3. B1 The source of the fourth transistor M3 is grounded, and the drain of the fourth transistor M3 is connected to the gate of the first transistor M4 for receiving the first gate current I B1 and outputs a first target current I3 to the gate of the first transistor M4.

[0090] In this example, the third transistor M2 and the fourth transistor M3 are both NMOS tubes. When the actual voltage of the gate of the NMOS tube is higher than its threshold voltage, a current path can be formed between the source and drain of the NMOS tube, and the drain of the NMOS tube outputs a conduction current to the source through the current path. Moreover, the lower the actual voltage of the gate of the NMOS tube, the smaller the conduction current; the higher the actual voltage of the gate of the NMOS tube, the larger the conduction current.

[0091] The source of the third transistor M2 is grounded, so that the source voltage is 0. The drain and gate of the third transistor M2 are both connected to the drain of the second transistor M1, so that the drain of the second transistor M1 provides the first source current I5 to the third transistor M2, and the first source current I5 is split into two currents. Among them, one current obtained by splitting is I C0 , is the conduction current between the drain and source of the third transistor M2. The other current obtained by the diversion is 2I B , used to provide current to the gate of the third transistor M2 and to provide current to the gate of the fourth transistor M3.

[0092] The gate of the third transistor M2 is also connected to the gate of the fourth transistor M3, and the gate of the fourth transistor M3 is also connected to the drain of the second transistor M1. B is split into two currents. One of the split currents is I B0 , used to input the gate of the third transistor M2, the current I B0 The gate voltage of the third transistor M2 can be used to control the conduction current I from the drain to the source of the third transistor M2. C0 The other current obtained by shunting (i.e., the first gate current) is I B1 , used to input the gate of the fourth transistor M3. Similarly, the current I B1The gate voltage of the fourth transistor M3 can be used to control the magnitude of the conduction current from the drain to the source of the fourth transistor M3, that is, the magnitude of the first target current I3 can be controlled by the gate voltage. In other words, the third transistor M2 receives the first source current I5 and provides the first gate current I to the fourth transistor M3. B1 , the first gate current I B1 Used to control the magnitude of the first target current I3.

[0093] The source of the fourth transistor M3 is grounded so that the source voltage is 0. The drain of the fourth transistor M3 is connected to the gate of the first transistor M4, and is used to provide the first target current I3 to the gate of the first transistor M4. Optionally, the first target current I3 is equal to the first source current I5. Alternatively, the first target current I3 is greater than or less than the first source current I5.

[0094] In addition, the first regulating module 20 further includes a first current source IREF1. One end of the first current source IREF1 is connected to the gate of the first transistor M4, and is used to provide a first reference current I4 to the gate of the first transistor M4. The first current source IREF1 is a power source that can provide a constant current in the circuit, and its output current, i.e., the first reference current I4, does not change.

[0095] The gate of the first transistor M4 receives both the first reference current I4 provided by the first current source IREF1 and the first target current I3 provided by the first adjustment unit 201. In other words, the current received by the gate of the first transistor M4 is equal to the difference between the first reference current I4 and the first target current I3. The circuit can compare the first reference current I4 with the first target current I3, and determine the second control voltage Vgs2 according to the comparison result, so that the gate of the first transistor M4 receives the second control voltage Vgs2.

[0096] Optionally, the first transistor M4 is a PMOS tube. When the first target current I3 increases, the first target current I3 is greater than the first reference current I4, so that the second control voltage Vgs2 decreases. Since the first transistor M4 is a PMOS tube, and the PMOS tube has the characteristic of low-level conduction, the second control voltage Vgs2 decreases, which increases the on-current of the first transistor M4, that is, increases the first current I1. On the contrary, when the first target current I3 decreases, the first target current I3 is less than the first reference current I4, so that the second control voltage Vgs2 increases, so that the on-current of the first transistor M4 decreases, that is, the first current I1 decreases.

[0097] The first current source IREF1 can be regarded as a current mirror having a structure similar to that of the first mirror component 202, through which the first reference current I4 is generated. That is, the current mirror of the first current source IREF1 includes two transistors, and illustratively, the two transistors are both NMOS transistors or both PMOS transistors.

[0098] If the first target current I3 is reduced, the first reference current I4 is greater than the first target current I3, for example, the first reference current I4 is 2 microamperes, and the first target current I3 is less than 2 microamperes. Since the first reference current I4 is greater than the first target current I3, the first current source IREF1 operates based on the first target current I3. At this time, the transistor of the first current source IREF1 is in a linear region (the current is positively correlated to the voltage difference between the source and the drain). As the first target current I3 is reduced, the voltage difference between the source and the drain of the first current source IREF1 will decrease, that is, the voltage difference across the first current source IREF1 decreases. Since the gate voltage of the first transistor M4 is equal to the power supply voltage VIN minus the voltage difference across the first current source IREF1, the voltage difference across the first current source IREF1 decreases, causing the gate voltage of the first transistor M4 (the second control voltage Vgs2) to increase.

[0099] On the contrary, if the first target current I3 increases, the first reference current I4 is less than the first target current I3, for example, the first reference current I4 is 2 microamperes, and the first target current I3 is greater than 2 microamperes. Since the first reference current I4 is less than the first target current I3, the fourth transistor M3 operates based on the first reference current I4. At this time, the fourth transistor M3 is in the linear region. Since the fourth transistor M3 is in the linear region, the voltage difference between the source and the drain of the fourth transistor M3 is reduced. Since the gate voltage of the first transistor M4 is equal to the voltage of the ground terminal plus the voltage difference between the source and the drain of the fourth transistor M3, the voltage difference between the source and the drain of the fourth transistor M3 is reduced, which will reduce the gate voltage of the first transistor M4 (the second control voltage Vgs2).

[0100] Based on the above, it can be seen that if the first source current I5 increases, the first target current I3 increases, and at this time, the gate voltage of the first transistor M4 (the second control voltage Vgs2) decreases. Since the first transistor M4 is a PMOS tube and has the characteristic of low-level conduction, the on-current of the first transistor M4 increases, that is, the first current I1 increases. If the first source current I5 decreases, the first target current I3 decreases, and at this time, the gate voltage of the first transistor M4 increases, so that the on-current of the first transistor M4 decreases, that is, the first current I1 decreases.

[0101] By adjusting the gate voltage of the first transistor M4 through the first target current and the first reference current, the magnitude of the on-current of the first transistor M4 is controlled, that is, the magnitude of the first current is controlled. When the load current increases, the output voltage VOUT decreases, and the first control voltage Vgs1 decreases, resulting in an increase in the first source current I5. Due to the increase in the first source current I5, the first target current I3 increases, and the second control voltage Vgs2 decreases, thereby causing the first current I1 to increase. By increasing the first current I1, more load current is provided by the first current I1, which hinders the discharge of the capacitor COUT and reduces the decrease in the output voltage VOUT, thereby facilitating the recovery of the output voltage VOUT; when the load current decreases, the output voltage VOUT increases, and the first control voltage Vgs1 increases, resulting in a decrease in the first source current I5. Due to the decrease in the first source current I5, the first target current I3 decreases, and the second control voltage Vgs2 increases, thereby causing the first current I1 to decrease. By reducing the first current I1, the capacitor COUT is hindered from charging, and the increase in the output voltage VOUT is reduced, thereby facilitating the recovery of the output voltage VOUT. Based on this, the first current I1 has the function of stabilizing the output voltage VOUT.

[0102] In implementation B, if Figure 6 As shown, the first regulating module 20 includes a second regulating unit 203, a first comparator CMP1, a fifth transistor M6 and a first resistor R4, and one end of the first resistor R4 is connected to the first input end. The second regulating unit 203 is connected to the voltage detection module 10 and the first comparator CMP1 respectively, and is used to receive the first control voltage Vgs1, and provide the first target voltage VFB2 to the first comparator CMP1 according to the first control voltage Vgs1; the first comparator CMP1 is connected to the gate of the fifth transistor M6 and the second input end, and is used to receive the first reference voltage VREF2 and the first target voltage VFB2, and output the third control voltage Vgs3 to the gate of the fifth transistor M6 according to the first reference voltage VREF2 and the first target voltage VFB2, and the second input end is used to provide the first reference voltage VREF2; the source of the fifth transistor M6 is connected to the other end of the first resistor R4, and the drain of the fifth transistor M6 is connected to the target output end, and is used to provide the first current I1 to the target output end according to the third control voltage Vgs3, and the first input end is used to provide the power supply voltage VIN.

[0103] The second regulating unit 203 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The second regulating unit 203 is also connected to the first comparator CMP1, and is used to provide the first target voltage VFB2 to the first comparator CMP1. Optionally, the second regulating unit 203 is also connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The second regulating unit 203 is also connected to the ground terminal GND so that the voltage of the terminal is 0. By connecting the first input terminal and the ground terminal GND, the second regulating unit 203 can operate normally.

[0104] In practical applications, the second adjustment unit 203 may have a variety of structures, and a possible implementation is shown below. Figure 6 As shown, the second regulating unit 203 includes: a sixth transistor M5 and a second resistor R3, the second resistor R3 is grounded and connected to the drain of the sixth transistor M5; the source of the sixth transistor M5 is connected to the first input terminal, and the gate of the sixth transistor M5 is connected to the voltage detection module 10, for receiving the first control voltage Vgs1, and providing the first target voltage VFB2 to the first comparator CMP1 according to the first control voltage Vgs1.

[0105] In this example, the sixth transistor M5 is a PMOS tube. One end of the second resistor R3 is connected to the ground terminal GND so that the voltage of the terminal is 0. The other end of the second resistor R3 is connected to the drain of the sixth transistor M5. The source of the sixth transistor M5 is connected to the first input terminal for receiving the power supply voltage VIN provided by the first input terminal. The gate of the sixth transistor M5 is connected to the voltage detection module 10 for receiving the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used to control the on-current of the sixth transistor M5.

[0106] Since the sixth transistor M5 is a PMOS tube, it has the characteristic of low-level conduction. Therefore, the smaller the first control voltage Vgs1 is, the larger the on-current of the sixth transistor M5 is, and the larger the first control voltage Vgs1 is, the smaller the on-current of the sixth transistor M5 is. The voltage difference across the second resistor R3 is equal to the on-current of the sixth transistor M5 multiplied by the resistance value of the second resistor R3, and the first target voltage VFB2 is equal to the voltage of the ground terminal GND plus the voltage difference across the second resistor R3. Among them, if the first control voltage Vgs1 increases, the on-current of the sixth transistor M5 decreases, resulting in a decrease in the first target voltage VFB2. If the first control voltage Vgs1 decreases, the on-current of the sixth transistor M5 increases, resulting in an increase in the first target voltage VFB2.

[0107] The positive terminal of the first comparator CMP1 is connected to the second input terminal, and is used to receive the first reference voltage VREF2 provided by the second input terminal. The negative terminal of the first comparator CMP1 is connected to the second resistor R3 and the drain of the sixth transistor M5, and is used to receive the first target voltage VFB2. The first comparator CMP1 is used to compare the first reference voltage VREF2 with the first target voltage VFB2, and output the third control voltage Vgs3 according to the comparison result. When the first reference voltage VREF2 is greater than the first target voltage VFB2, the third control voltage Vgs3 output by the first comparator CMP1 is a high level, and when the first reference voltage VREF2 is less than the first target voltage VFB2, the third control voltage Vgs3 output by the first comparator CMP1 is a low level. Based on this, when the first target voltage VFB2 decreases, the third control voltage Vgs3 increases; when the first target voltage VFB2 increases, the third control voltage Vgs3 decreases.

[0108] The fifth transistor M6 is a PMOS tube. The gate of the fifth transistor M6 is connected to the output end of the first comparator CMP1, and is used to receive the third control voltage Vgs3 output by the first comparator CMP1. The source of the fifth transistor M6 is connected to one end of the first resistor R4, and the other end of the first resistor R4 is connected to the first input end. The source voltage of the fifth transistor M6 can be reduced by dividing the power supply voltage VIN by the first resistor R4. Since the third control voltage Vgs3 is a high level or a low level, the voltage difference between the source and the gate of the fifth transistor M6 is reduced by reducing the source voltage of the fifth transistor M6, so that the conduction current of the fifth transistor M6, that is, the first current I1, is within the desired range. The drain of the fifth transistor M6 is connected to the target output end of the low voltage difference linear voltage regulator circuit, and is used to provide the first current I1 to the target output end. Since the fifth transistor M6 is a PMOS tube and has the characteristic of being turned on at a low level, the smaller the third control voltage Vgs3 is, the larger the on-current of the fifth transistor M6 is, that is, the larger the first current I1 is; the larger the third control voltage Vgs3 is, the smaller the on-current of the fifth transistor M6 is, that is, the smaller the first current I1 is.

[0109] By adjusting the gate voltage of the fifth transistor M6 by the first target voltage and the first reference voltage, the magnitude of the on-current of the fifth transistor M6 is controlled, that is, the magnitude of the first current is controlled. When the load current increases, the output voltage VOUT decreases, the first control voltage Vgs1 decreases, and the on-current of the sixth transistor M5 increases. Due to the increase in the on-current of the sixth transistor M5, the first target voltage VFB2 increases, the third control voltage Vgs3 decreases, and the first current I1 increases. By increasing the first current I1, more load current is provided by the first current I1, the capacitor COUT is hindered from discharging, and the reduction amount of the output voltage VOUT is reduced, which is conducive to restoring the output voltage VOUT; when the load current decreases, the output voltage VOUT increases, the first control voltage Vgs1 increases, and the on-current of the sixth transistor M5 decreases. Due to the decrease in the on-current of the sixth transistor M5, the first target voltage VFB2 decreases, the third control voltage Vgs3 increases, and the first current I1 decreases. By reducing the first current I1, a smaller load current is provided by the first current I1, which hinders the charging of the capacitor COUT and reduces the increase of the output voltage VOUT, thereby facilitating the recovery of the output voltage VOUT. Based on this, the first current I1 has the function of stabilizing the output voltage VOUT.

[0110] In an exemplary embodiment, the low voltage difference linear voltage regulator circuit further includes a third regulating module. The third regulating module is connected to the voltage detection module 10, the target output terminal and the ground terminal respectively, and is used to receive the first control voltage Vgs1 and output a third current according to the first control voltage Vgs1; wherein the third current is a current from the target output terminal to the ground terminal, and the third current is used to stabilize the output voltage.

[0111] The third regulating module is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 output by the voltage detection module 10. The third regulating module is also connected to the target output terminal, and is used to output a third current. Optionally, the third regulating module is connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal, so that the module can operate normally.

[0112] When the load Rload changes from a light load to a heavy load, that is, the load current transiently increases, causing the output voltage VOUT to drop. Since the third current is used to stabilize the output voltage VOUT, and the third current is the current from the target output terminal to the ground terminal, therefore, when the output voltage VOUT drops, the third current will decrease. On the contrary, when the load Rload changes from a heavy load to a light load, that is, the load current transiently decreases, causing the output voltage VOUT to rise. Since the third current is used to stabilize the output voltage VOUT, and the third current is the current from the target output terminal to the ground terminal, therefore, when the output voltage VOUT rises, the third current will increase. Based on this, in practical applications, any circuit that meets this function can be used as a third regulation module. Several possible implementations are shown below, as shown in implementation C and implementation D, respectively.

[0113] In implementation C, if Figure 7 As shown, the third regulating module 40 includes a third regulating unit 401, a second current source IREF2 and a seventh transistor M10. The third regulating unit 401 is connected to the voltage detection module 10 and the gate of the seventh transistor M10, respectively, and is used to receive the first control voltage Vgs1, and provide the second target current I6 to the gate of the seventh transistor M10 according to the first control voltage Vgs1; the second current source IREF2 is connected to the gate of the seventh transistor M10, and is used to provide the second reference current I7 to the gate of the seventh transistor M10; the source of the seventh transistor M10 is connected to the target output terminal, and the drain of the seventh transistor M10 is grounded, and is used to output the third current I8 according to the fourth control voltage Vgs4, and the fourth control voltage Vgs4 is determined according to the second target current I6 and the second reference current I7.

[0114] One end of the third regulating unit 401 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The other end of the third regulating unit 401 is connected to the gate of the seventh transistor M10, and is used to provide the second target current I6 to the gate of the seventh transistor M10. In addition, the third regulating unit 401 is also connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The third regulating unit 401 is also connected to the ground terminal GND, so that the voltage of the terminal is 0. By connecting to the first input terminal and the ground terminal GND, the third regulating unit 401 can operate normally.

[0115] The present application embodiment does not limit the structure of the third adjustment unit 401. For example, Figure 7 As shown, the third regulating unit 401 includes an eighth transistor M7 and a second mirror component 402 .

[0116] Among them, the source of the eighth transistor M7 is grounded, the drain of the eighth transistor M7 is connected to the second mirror component 402, and the gate of the eighth transistor M7 is connected to the voltage detection module 10, which is used to receive the first control voltage Vgs1, and provide the second source current I9 to the second mirror component 402 according to the first control voltage Vgs1; the second mirror component 402 is connected to the gate of the seventh transistor M10, which is used to receive the second source current I9 and output the second target current I6 to the gate of the seventh transistor M10, and the second target current I6 is a mirror current of the second source current I9.

[0117] In this example, the eighth transistor M7 is an NMOS tube. The source of the eighth transistor M7 is grounded, so that the source voltage is 0. The drain of the eighth transistor M7 is connected to the second mirror component 402, and is used to provide the second source current I9 to the second mirror component 402. The second source current I9 is ​​the conduction current from the drain to the source of the eighth transistor M7. The gate of the eighth transistor M7 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The first control voltage Vgs1 is used to control the size of the second source current I9. Based on the characteristics of the high-level conduction of the NMOS tube, if the first control voltage Vgs1 decreases, the second source current I9 decreases; if the first control voltage Vgs1 increases, the second source current I9 increases.

[0118] The second mirror component 402 is connected to the source of the eighth transistor M7, and is used to receive the second source current I9 provided by the source of the eighth transistor M7. The second mirror component 402 is also connected to the gate of the seventh transistor M10, and is used to output the second target current I6 to the gate of the seventh transistor M10. The second target current I6 is a mirror current of the second source current I9.

[0119] It should be noted that the second mirror component 402 is a mirror current source that can mirror the input current in a certain ratio to obtain an output current. That is to say, the direction of the second target current I6 is the same as the direction of the second source current I9, but the second target current I6 and the second source current I9 can be the same size or different sizes. Exemplarily, the second source current I9 is ​​equal to the second target current I6. When the second source current I9 increases, the second target current I6 also increases; when the second source current I9 decreases, the second target current I6 also decreases. By determining the second target current I6 according to the second source current I9 through the second mirror component 402, a stable current is provided to the gate of the seventh transistor M10 to help the circuit reach a stable state and improve circuit performance.

[0120] In an exemplary embodiment, if Figure 7As shown, the second mirror component 402 includes a ninth transistor M8 and a tenth transistor M9; the source of the ninth transistor M8 is connected to the first input terminal, the drain of the ninth transistor M8 is connected to the drain of the eighth transistor M7, the gate of the ninth transistor M8 is connected to the drain of the eighth transistor M7 and the gate of the tenth transistor M9, for receiving the second source current I9 and providing the second gate current to the tenth transistor M9; the source of the tenth transistor M9 is connected to the first input terminal, the drain of the tenth transistor M9 is connected to the gate of the seventh transistor M10, for receiving the second gate current and outputting the second target current I6 to the gate of the seventh transistor M10.

[0121] In this example, the ninth transistor M8 and the tenth transistor M9 are both PMOS tubes. The source of the ninth transistor M8 is connected to the first input terminal for receiving the power supply voltage VIN provided by the first input terminal. The drain and gate of the ninth transistor M8 are both connected to the drain of the eighth transistor M7, so that the drain of the eighth transistor M7 provides a second source current I9 to the ninth transistor M8, and the second source current I9 is ​​shunted into two currents. Among them, one current obtained by shunting is the conduction current between the source and the drain of the ninth transistor M8. The other current obtained by shunting is used to provide current for the gate of the ninth transistor M8 and to provide current for the gate of the tenth transistor M9.

[0122] Among them, the gate of the ninth transistor M8 is also connected to the gate of the tenth transistor M9, and the gate of the tenth transistor M9 is also connected to the drain of the eighth transistor M7. Based on this, another current obtained by the shunting of the second source current I9 is ​​shunted into two currents. Among them, one current obtained by shunting is used to input the gate of the ninth transistor M8, and the current can correspond to the gate voltage of the ninth transistor M8, and the magnitude of the on-current from the source to the drain of the ninth transistor M8 is controlled by the gate voltage. Another current obtained by shunting (i.e., the second gate current) is used to input the gate of the tenth transistor M9. Similarly, the current can correspond to the gate voltage of the tenth transistor M9, and the magnitude of the on-current from the source to the drain of the tenth transistor M9 is controlled by the gate voltage, that is, the magnitude of the second target current I6 is controlled by the gate voltage. In other words, the ninth transistor M8 receives the second source current I9 and provides the second gate current to the tenth transistor M9, and the second gate current is used to control the magnitude of the second target current I6.

[0123] The source of the tenth transistor M9 is connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The drain of the tenth transistor M9 is connected to the gate of the seventh transistor M10, and is used to provide the second target current I6 to the gate of the seventh transistor M10. Optionally, the second target current I6 is equal to the second source current I9. Alternatively, the second target current I6 is greater than or less than the second source current I9.

[0124] In addition, the third regulating module 40 further includes a second current source IREF2. One end of the second current source IREF2 is connected to the gate of the seventh transistor M10, and is used to provide a second reference current I7 to the gate of the seventh transistor M10. The second current source IREF2 is a power source that can provide a constant current in the circuit, and its output current, i.e., the second reference current I7, does not change.

[0125] The gate of the seventh transistor M10 receives both the second reference current I7 provided by the second current source IREF2 and the second target current I6 provided by the third regulating unit 401. That is, the current received by the gate of the seventh transistor M10 is equal to the difference between the second target current I6 and the second reference current I7. The circuit can compare the second reference current I7 with the second target current I6, and determine the fourth control voltage Vgs4 according to the comparison result, so that the gate of the seventh transistor M10 receives the fourth control voltage Vgs4.

[0126] Optionally, the seventh transistor M10 is an NMOS tube. When the second target current I6 increases, the second target current I6 is greater than the second reference current I7, so that the fourth control voltage Vgs4 increases. Since the seventh transistor M10 is an NMOS tube, and the NMOS tube has the characteristic of high-level conduction, therefore, the increase of the fourth control voltage Vgs4 will increase the on-current of the seventh transistor M10, that is, increase the third current I8. On the contrary, when the second target current I6 decreases, the second target current I6 is less than the second reference current I7, so that the fourth control voltage Vgs4 decreases, so that the on-current of the seventh transistor M10 decreases, that is, the third current I8 decreases.

[0127] The second current source IREF2 can be regarded as a current mirror having a structure similar to that of the second mirror component 402, and the second reference current I7 is generated by the current mirror. That is, the current mirror of the second current source IREF2 includes two transistors, and illustratively, the two transistors are both NMOS transistors or both PMOS transistors.

[0128] If the second target current I6 is reduced, the second reference current I7 is greater than the second target current I6, for example, the second reference current I7 is 2 microamperes, and the second target current I6 is less than 2 microamperes. Since the second reference current I7 is greater than the second target current I6, the second current source IREF2 operates based on the second target current I6. At this time, the transistor of the second current source IREF2 is in a linear region (the current is positively correlated to the voltage difference between the source and the drain). As the second target current I6 is reduced, the voltage difference between the source and the drain of the second current source IREF2 will decrease, that is, the voltage difference across the second current source IREF2 is reduced. Since the gate voltage of the seventh transistor M10 is equal to the voltage of the ground terminal GND plus the voltage difference across the second current source IREF2, the voltage difference across the second current source IREF2 is reduced, so that the gate voltage of the seventh transistor M10 (that is, the fourth control voltage Vgs4) is reduced.

[0129] On the contrary, if the second target current I6 increases, the second reference current I7 is less than the second target current I6, for example, the second reference current I7 is 2 microamperes, and the second target current I6 is greater than 2 microamperes. Since the second reference current I7 is less than the second target current I6, the tenth transistor M9 operates based on the second reference current I7. At this time, the tenth transistor M9 is in the linear region. Since the tenth transistor M9 is in the linear region, the voltage difference between the source and the drain of the tenth transistor M9 is reduced. Since the gate voltage of the seventh transistor M10 is equal to the power supply voltage minus the voltage difference between the source and the drain of the tenth transistor M9, the voltage difference between the source and the drain of the tenth transistor M9 is reduced, which will increase the gate voltage of the seventh transistor M10 (i.e., the fourth control voltage Vgs4).

[0130] Based on the above, it can be seen that if the second source current I9 increases, the second target current I6 increases, and at this time, the gate voltage of the seventh transistor M10 increases. Since the seventh transistor M10 is an NMOS tube, it has the characteristic of high-level conduction, so the on-current of the seventh transistor M10 increases, that is, the third current I8 increases. If the second source current I9 decreases, the second target current I6 decreases, and at this time, the gate voltage of the seventh transistor M10 decreases, so that the on-current of the seventh transistor M10 decreases, that is, the third current I8 decreases.

[0131] By adjusting the gate voltage of the seventh transistor M10 by the second target current and the second reference current, the magnitude of the conduction current of the seventh transistor M10 is controlled, that is, the magnitude of the third current is controlled. When the load current increases, the output voltage VOUT decreases, resulting in a decrease in the first control voltage Vgs1. Since the first control voltage Vgs1 decreases, the second source current I9 decreases, and the second target current I6 decreases, resulting in a decrease in the fourth control voltage Vgs4. The fourth control voltage Vgs4 decreases, resulting in a decrease in the third current I8, thereby reducing current consumption, so that the decrease in the third current I8 can provide an increase in the load current, hinder the discharge of the capacitor COUT, and reduce the decrease in the output voltage VOUT, thereby being more conducive to restoring the output voltage VOUT. When the load current decreases, the output voltage VOUT increases, resulting in an increase in the first control voltage Vgs1. Since the first control voltage Vgs1 increases, the second source current I9 increases, and the second target current I6 increases, resulting in an increase in the fourth control voltage Vgs4. The fourth control voltage Vgs4 increases, causing the third current I8 to increase, thereby increasing current consumption to draw more load current, hindering the charging of the capacitor COUT, and reducing the increase in the output voltage VOUT, thereby being more conducive to restoring the output voltage VOUT. Based on this, the third current I8 has the function of stabilizing the output voltage VOUT.

[0132] It should be noted that Figure 7 For the description of other parts in the implementation method A, please refer to the description of the implementation method A, which will not be repeated here. In actual applications, it can also be implemented based on the implementation method B Figure 7 The rest of the parts will not be elaborated here.

[0133] In implementation D, if Figure 8 As shown, the third regulating module 40 includes a fourth regulating unit 403, a second comparator CMP2, an eleventh transistor M12 and a third resistor R6, one end of the third resistor R6 is grounded. The fourth regulating unit 403 is connected to the voltage detection module 10 and the second comparator CMP2 respectively, and is used to receive the first control voltage Vgs1, and provide the second target voltage VFB3 to the second comparator CMP2 according to the first control voltage Vgs1; the second comparator CMP2 is connected to the gate and the fourth input end of the eleventh transistor M12, and is used to receive the third reference voltage VREF3 and the second target voltage VFB3, and output the fifth control voltage Vgs5 to the gate of the eleventh transistor M12 according to the third reference voltage VREF3 and the second target voltage VFB3, and the fourth input end is used to provide the third reference voltage VREF3; the source of the eleventh transistor M12 is connected to the other end of the third resistor R6, and the drain of the eleventh transistor M12 is connected to the target output end, and is used to provide the third current I8 to the target output end according to the fifth control voltage Vgs5.

[0134] The fourth regulating unit 403 is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10. The fourth regulating unit 403 is also connected to the second comparator CMP2, and is used to provide the second target voltage VFB3 to the second comparator CMP2. Optionally, the fourth regulating unit 403 is also connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The fourth regulating unit 403 is also connected to the ground terminal GND so that the voltage of the terminal is 0. By connecting the first input terminal and the ground terminal GND, the fourth regulating unit 403 can operate normally.

[0135] In practical applications, the fourth adjustment unit 403 may have a variety of structures, and a possible implementation is shown below. Figure 6 As shown, the fourth adjustment unit 403 includes: a twelfth transistor M11 and a fourth resistor R5, the fourth resistor R5 is connected to the first input terminal and to the drain of the twelfth transistor M11; the source of the twelfth transistor M11 is grounded, and the gate of the twelfth transistor M11 is connected to the voltage detection module 10, for receiving the first control voltage Vgs1, and providing the second target voltage VFB3 to the second comparator CMP2 according to the first control voltage Vgs1.

[0136] In this example, the twelfth transistor M11 is an NMOS tube. One end of the fourth resistor R5 is connected to the first input terminal for receiving the power supply voltage VIN provided by the first input terminal. The other end of the fourth resistor R5 is connected to the drain of the twelfth transistor M11. The source of the twelfth transistor M11 is grounded so that the source voltage is 0. The gate of the twelfth transistor M11 is connected to the voltage detection module 10 for receiving the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used to control the on-current of the twelfth transistor M11.

[0137] Since the twelfth transistor M11 is an NMOS tube, it has the characteristic of high-level conduction. Therefore, the smaller the first control voltage Vgs1 is, the smaller the on-current of the twelfth transistor M11 is, and the larger the first control voltage Vgs1 is, the larger the on-current of the twelfth transistor M11 is. The voltage difference across the fourth resistor R5 is equal to the on-current of the twelfth transistor M11 multiplied by the resistance of the fourth resistor R5, and the second target voltage VFB3 is equal to the power supply voltage VIN minus the voltage difference across the fourth resistor R5. Among them, if the first control voltage Vgs1 increases, the on-current of the twelfth transistor M11 increases, resulting in a decrease in the second target voltage VFB3. If the first control voltage Vgs1 decreases, the on-current of the twelfth transistor M11 decreases, resulting in an increase in the second target voltage VFB3.

[0138] The positive terminal of the second comparator CMP2 is connected to the fourth input terminal, and is used to receive the third reference voltage VREF3 provided by the fourth input terminal. The negative terminal of the second comparator CMP2 is connected to the fourth resistor R5 and the drain of the twelfth transistor M11, and is used to receive the second target voltage VFB3. The second comparator CMP2 is used to compare the third reference voltage VREF3 and the second target voltage VFB3, and determine the fifth control voltage Vgs5 according to the comparison result. When the third reference voltage VREF3 is greater than the second target voltage VFB3, the fifth control voltage Vgs5 is at a high level, and when the third reference voltage VREF3 is less than the second target voltage VFB3, the fifth control voltage Vgs5 is at a low level. Based on this, when the second target voltage VFB3 decreases, the fifth control voltage Vgs5 increases; when the second target voltage VFB3 increases, the fifth control voltage Vgs5 decreases.

[0139] The eleventh transistor M12 is an NMOS tube. The gate of the eleventh transistor M12 is connected to the output end of the second comparator CMP2, and is used to receive the fifth control voltage Vgs5 output by the second comparator CMP2. The source of the eleventh transistor M12 is connected to one end of the third resistor R6, and the other end of the third resistor R6 is grounded. The source voltage of the eleventh transistor M12 can be increased by the third resistor R6. Since the fifth control voltage Vgs5 is a high level or a low level, the voltage difference between the source and the gate of the eleventh transistor M12 is reduced by increasing the source voltage of the eleventh transistor M12, so that the on-current of the eleventh transistor M12, that is, the third current I8, is within the desired range. The drain of the eleventh transistor M12 is connected to the target output end of the low voltage difference linear voltage regulator circuit, and is used to output the third current I8. Since the eleventh transistor M12 is an NMOS tube and has the characteristic of high-level conduction, the smaller the fifth control voltage Vgs5 is, the smaller the conduction current of the eleventh transistor M12 is, that is, the smaller the third current I8 is; the larger the fifth control voltage Vgs5 is, the larger the conduction current of the eleventh transistor M12 is, that is, the larger the third current I8 is.

[0140] It should be noted that Figure 8 For the description of other parts in the implementation method B, please refer to the description of the implementation method B, which will not be repeated here. In practical applications, it is also possible to implement the implementation method A. Figure 8 The rest of the parts will not be elaborated here.

[0141] By adjusting the gate voltage of the eleventh transistor M12 by the second target voltage and the third reference voltage, the magnitude of the on-current of the eleventh transistor M12 is controlled, that is, the magnitude of the third current is controlled. When the load current increases, the output voltage VOUT decreases, and the first control voltage Vgs1 decreases, resulting in a decrease in the on-current of the twelfth transistor M11. Due to the decrease in the on-current of the twelfth transistor M11, the second target voltage VFB3 increases, the fifth control voltage Vgs5 decreases, and the third current I8 decreases. By reducing the third current I8, the current consumption is reduced, so that the reduction in the third current I8 can provide an increase in the load current, hinder the discharge of the capacitor COUT, and reduce the reduction in the output voltage VOUT, which is more conducive to restoring the output voltage VOUT. When the load current decreases, the output voltage VOUT increases, and the first control voltage Vgs1 increases, resulting in an increase in the on-current of the twelfth transistor M11. Due to the increase in the on-current of the twelfth transistor M11, the second target voltage VFB3 decreases, the fifth control voltage Vgs5 increases, and the third current I8 increases. By increasing the third current I8 to draw more load current, the capacitor COUT is hindered from charging, and the increase in the output voltage VOUT is reduced, which is more conducive to recovering the output voltage VOUT. Based on this, the third current I8 has the function of stabilizing the output voltage VOUT.

[0142] Alternatively, if Figure 5 and Figure 6 As shown, the second regulating module 30 includes a target transistor MP. The source of the target transistor MP is connected to the first input terminal, the drain of the third transistor MP is connected to the target output terminal, the gate of the target transistor MP is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1, and provide the second current I2 to the target output terminal according to the first control voltage Vgs1, and the first input terminal is used to provide the power supply voltage VIN.

[0143] The target transistor MP is a PMOS tube. The source of the target transistor MP is connected to the first input terminal, and is used to receive the power supply voltage VIN provided by the first input terminal. The gate of the target transistor MP is connected to the voltage detection module 10, and is used to receive the first control voltage Vgs1 provided by the voltage detection module 10, and the first control voltage Vgs1 is used to control the on-current of the target transistor MP. The drain of the target transistor MP is connected to the target output terminal, and is used to provide the second current I2 to the target output terminal.

[0144] Since the target transistor MP is a PMOS tube, it has the characteristic of being turned on at a low level. Therefore, when the first control voltage Vgs1 decreases, the second current I2 increases; when the first control voltage Vgs1 increases, the second current I2 decreases.

[0145] When the load current increases, the output voltage VOUT decreases, and the first control voltage Vgs1 decreases, causing the second current I2 to increase. By increasing the second current I2, more load current is provided by the second current I2, which hinders the discharge of the capacitor COUT and reduces the decrease in the output voltage VOUT, thereby facilitating the recovery of the output voltage VOUT; when the load current decreases, the output voltage VOUT increases, and the first control voltage Vgs1 increases, causing the second current I2 to decrease. By reducing the second current I2, the capacitor COUT is hindered from charging, and the increase in the output voltage VOUT is reduced, thereby facilitating the recovery of the output voltage VOUT. Based on this, the second current I2 has the function of stabilizing the output voltage VOUT.

[0146] Based on the above content, we can know that Figure 5 For example, when the low voltage difference linear voltage regulator circuit is in a steady state, the load current will not change. At this time, the capacitor COUT is no longer charged or discharged, and the output voltage VOUT remains unchanged. After the output voltage VOUT is divided by the sampling resistor R1 and the sampling resistor R2, the feedback voltage VFB1 of the error amplifier EA is obtained. The error amplifier EA determines the first control voltage Vgs1 according to the feedback voltage VFB1 and the second reference voltage VREF1. The first control voltage Vgs1 is used to control the on-current of the target transistor MP. Since the system is in a steady state, the value of the first control voltage Vgs1 remains unchanged, and the on-current (i.e., the second current) I2 of the target transistor MP remains unchanged.

[0147] In addition, the first control voltage Vgs1 is also used to control the on-current of the second transistor M1. The fourth transistor M3 and the third transistor M2 form a first mirror component, which is used to obtain the mirrored on-current according to the on-current of the second transistor M1, that is, to obtain the first target current I3. The first current source IREF1 is used to provide a first reference current I4, and the first reference current I4 and the first target current I3 are used to determine the second control voltage Vgs2, and the second control voltage Vgs2 is used to control the on-current of the first transistor M4. Since the system is in a steady state, the value of the second control voltage Vgs2 remains unchanged, so that the on-current (i.e., the first current) I1 of the first transistor M4 remains unchanged.

[0148] Since the first current I1 and the second current I2 remain unchanged, and the capacitor COUT is no longer charged or discharged, the output voltage VOUT is stable, and the load Rload can be stably powered, and the load current of the load Rload remains unchanged.

[0149] If the load Rload changes from light load to heavy load, that is, the load current transiently increases, at this time, the capacitor COUT discharges, causing the output voltage VOUT to drop. Fig. 9 As shown, Fig. 9(1) shows the waveform of the output voltage VOUT. Fig. 9 (2) in FIG. 1 shows the waveform of the load current, where the negative sign in “-80.0mA” represents the direction of the load current, and the value “80.0mA” represents the magnitude of the load current. Fig. 9 It can be seen that when the load current increases from 0 to 80mA, the output voltage VOUT will decrease by about 1.77mV. It can be understood that the low voltage drop linear voltage regulator circuit has the ability to adjust and can return to a steady state after a period of adjustment.

[0150] When the load current transiently increases, the output voltage VOUT decreases, causing the feedback voltage VFB1 to decrease, so that the first control voltage Vgs1 decreases, thereby increasing the on-current of the target transistor MP. In addition, the first control voltage Vgs1 decreases, so that the on-current of the second transistor M1 increases, thereby increasing the on-current of the mirror. Since the first reference current provided by the first current source IREF1 remains unchanged, but the on-current of the mirror increases, the second control voltage Vgs2 decreases, so that the on-current of the first transistor M4 increases. Since the on-current of the first transistor M4 and the on-current of the target transistor MP both increase, the decrease in the output voltage VOUT can be reduced.

[0151] By increasing the on-current of the first transistor M4 and the on-current of the target transistor MP, more load current is provided, the discharge speed of the capacitor COUT is slowed down, and thus the drop range of the output voltage is reduced. Figure 8 and Figure 2 It can be seen that when the load current increases from 0 to 80mA, the output voltage VOUT of the circuit of the embodiment of the present application decreases by about 1.77mV, which is much smaller than the decrease of 6.33mV of the output voltage VOUT in the circuit of the related art. Since the output voltage of the circuit of the embodiment of the present application decreases less, the transient response of the circuit is higher and has better performance.

[0152] If the load Rload changes from heavy load to light load, the load current decreases, causing the capacitor COUT to charge, causing the output voltage VOUT to increase. Figure 8 As shown in FIG. 1 , when the load current decreases from 80mA to 0, the output voltage VOUT increases by about 1.96mV.

[0153] The output voltage VOUT rises, causing the feedback voltage VFB1 to rise, so that the first control voltage Vgs1 rises, thereby reducing the on-current of the target transistor MP. In addition, the first control voltage Vgs1 rises, causing the on-current of the second transistor M1 to decrease, thereby reducing the on-current of the mirror. Since the first reference current provided by the first current source IREF1 remains unchanged, but the on-current of the mirror decreases, the second control voltage Vgs2 rises, causing the on-current of the first transistor M4 to decrease. Since both the on-current of the first transistor M4 and the on-current of the target transistor MP decrease, the charging speed of the capacitor COUT can be slowed down, thereby reducing the increase in the output voltage VOUT.

[0154] By reducing the on-current of the first transistor M4 and the on-current of the target transistor MP, a smaller load current is provided, the charging speed of the capacitor COUT is slowed down, and thus the rise of the output voltage is reduced. Figure 8 and Figure 2 It can be seen that when the load current decreases from 80mA to 0, the output voltage VOUT of the circuit of the embodiment of the present application increases by about 1.96mV, which is much smaller than the output voltage VOUT of the circuit of the related art, which increases by 6.26mV. Since the output voltage of the embodiment of the present application increases less, the transient response of the circuit is higher and has better performance.

[0155] In the above system, the voltage detection module can determine the first control voltage according to the output voltage of the target output terminal, the first regulation module can determine the first current provided to the target output terminal according to the first control voltage, and the second regulation module can determine the second current provided to the target output terminal according to the first control voltage. Since the first current and the second current are both used to stabilize the output voltage, when the output voltage changes, the output voltage can be restored faster through the first current and the second current, and the recovery speed of the output voltage is improved, thereby improving the transient response of the circuit and improving the circuit performance.

[0156] In an exemplary embodiment, a chip is also provided, the chip comprising: Figures 4 to 7 Any of the low voltage difference linear voltage regulator circuits described above.

[0157] In an exemplary embodiment, an electronic device is also provided, the electronic device comprises the above chip, and the chip comprises the above low voltage difference linear voltage regulator circuit. Optionally, the electronic device is a terminal device or a server.

[0158] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0159] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0160] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: The circuit includes a voltage detection module, a first adjustment module and a second adjustment module; The voltage detection module is connected to the target output terminal of the low voltage difference linear voltage regulator circuit and is used to output a first control voltage according to the output voltage of the target output terminal; The first regulating module is connected to the voltage detection module and the target output terminal respectively, and is used to receive the first control voltage and provide a first current to the target output terminal according to the first control voltage; The second regulating module is connected to the voltage detection module and the target output terminal respectively, and is used to receive the first control voltage and provide a second current to the target output terminal according to the first control voltage; Wherein, the first current and the second current are both used to stabilize the output voltage.

2. The circuit according to claim 1, characterized in that The first regulating module includes a first regulating unit, a first current source and a first transistor; The first regulating unit is connected to the voltage detection module and the gate of the first transistor respectively, and is used to receive the first control voltage and provide a first target current to the gate of the first transistor (M4) according to the first control voltage; The first current source is connected to the gate of the first transistor and is used to provide a first reference current to the gate of the first transistor; The source of the first transistor is connected to the first input terminal, and the drain of the first transistor is connected to the target output terminal, and is used to provide the first current to the target output terminal according to a second control voltage. The first input terminal is used to provide a supply voltage, and the second control voltage is determined according to the first target current and the first reference current.

3. The circuit according to claim 2, characterized in that The first regulating unit includes a second transistor and a first mirror component; The source of the second transistor is connected to the first input terminal, the drain of the second transistor is connected to the first mirror component, and the gate of the second transistor is connected to the voltage detection module, and is used to receive the first control voltage and provide a first source current to the first mirror component according to the first control voltage; The first mirror component is connected to the gate of the first transistor, and is used for receiving the first source current and outputting the first target current to the gate of the first transistor, where the first target current is a mirror current of the first source current.

4. The circuit according to claim 3, characterized in that The first mirror component includes a third transistor and a fourth transistor; The source of the third transistor is grounded, the drain of the third transistor is connected to the drain of the second transistor, and the gate of the third transistor is connected to the drain of the second transistor and the gate of the fourth transistor, and is used to receive the first source current and provide a first gate current to the fourth transistor; The source of the fourth transistor is grounded, and the drain of the fourth transistor is connected to the gate of the first transistor, for receiving the first gate current and outputting the first target current to the gate of the first transistor.

5. The circuit according to claim 1, characterized in that The first regulating module includes a second regulating unit, a first comparator, a fifth transistor and a first resistor, and one end of the first resistor is connected to the first input end; The second regulating unit is connected to the voltage detection module and the first comparator respectively, and is used to receive the first control voltage and provide a first target voltage to the first comparator according to the first control voltage; The first comparator is connected to the gate of the fifth transistor and the second input terminal, and is used to receive a first reference voltage and the first target voltage, and output a third control voltage to the gate of the fifth transistor according to the first reference voltage and the first target voltage, and the second input terminal is used to provide the first reference voltage; The source of the fifth transistor is connected to the other end of the first resistor, and the drain of the fifth transistor is connected to the target output terminal, and is used to provide the first current to the target output terminal according to the third control voltage. The first input terminal is used to provide a supply voltage.

6. The circuit according to claim 5, characterized in that The second regulating unit includes: a sixth transistor and a second resistor, wherein the second resistor is grounded and connected to the drain of the sixth transistor; The source of the sixth transistor is connected to the first input terminal, and the gate of the sixth transistor is connected to the voltage detection module, for receiving the first control voltage and providing the first target voltage to the first comparator according to the first control voltage.

7. The circuit according to claim 1, characterized in that The circuit also includes a third adjustment module; The third regulating module is connected to the voltage detection module, the target output terminal and the ground terminal respectively, and is used to receive the first control voltage and output a third current according to the first control voltage; The third current is a current from the target output terminal to the ground terminal, and the third current is used to stabilize the output voltage.

8. The circuit according to claim 1, characterized in that The voltage detection module includes a sampling module and an error amplifier; The sampling module is connected to the target output terminal and the error amplifier respectively, and is used to receive the output voltage and output the feedback voltage to the error amplifier according to the output voltage; The error amplifier is connected to the third input terminal, and is used to receive the feedback voltage and the second reference voltage, and output the first control voltage according to the feedback voltage and the second reference voltage. The third input terminal is used to provide the second reference voltage.

9. The circuit according to claim 1, characterized in that The second regulating module includes a target transistor; The source of the target transistor is connected to the first input terminal, the drain of the target transistor is connected to the target output terminal, and the gate of the target transistor is connected to the voltage detection module, which is used to receive the first control voltage and provide the second current to the target output terminal according to the first control voltage. The first input terminal is used to provide a supply voltage.

10. A chip, characterized in that: The chip includes the low voltage difference linear voltage regulator circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that: The electronic device comprises the chip as claimed in claim 10.

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