Band-gap reference circuit, power management module and communication chip

Abstract

The invention relates to the technical field of power management modules, and discloses a band-gap reference circuit, a power management module and a communication chip, and the band-gap reference circuit comprises a band-gap reference core circuit which is configured to generate a band-gap reference voltage; the starting circuit is connected with the band-gap reference core circuit and is configured to generate a first sink current and stop generating the first sink current after the starting circuit reaches a preset condition; the first sink current acts on the band-gap reference core circuit to accelerate establishment of band-gap reference voltage; the band-gap reference voltage detection circuit is connected with the band-gap reference core circuit and is configured to generate a second sink current and stop generating the second sink current after the band-gap reference voltage reaches a first threshold voltage; the second sink current acts on the band-gap reference core circuit to accelerate establishment of the band-gap reference voltage. By controlling the generation and stop of the first sink current and the second sink current, the establishment speed of the band-gap reference voltage can be increased under the condition of low power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of power management modules, for example, to a bandgap reference circuit, a power management module and a communication chip. Background Art

[0002] The power management module in the communication chip is the basis of each module of the chip, providing power with different performance requirements for the receiver, transmitter, clock frequency synthesis module and digital module of the communication chip. The fundamental of the power management system is the bandgap reference voltage, which provides a stable reference voltage for each independent linear regulator, boost converter, voltage detection and other modules in the power management system. This stable reference voltage basically does not change with the power supply voltage and temperature.

[0003] In the related art, the bandgap reference voltage circuit includes a startup circuit and a bandgap reference voltage generation module. The startup circuit can provide an instantaneous startup current when the power supply is started, so that the circuit jumps out of the degenerate bias point and enters a normal working state. The bandgap reference voltage generation module utilizes the temperature characteristics of the base-emitter voltage of the bipolar transistor and the difference between the base-emitter voltages at two different current densities, and through an appropriate circuit structure, weights and sums these two voltages with opposite temperature coefficients, thereby obtaining a reference voltage with a zero temperature coefficient.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] In the application scenario of the low-power bandgap reference circuit, the bandgap reference voltage is established slowly. In order to increase the establishment speed of the bandgap reference voltage, the power consumption of the circuit needs to be increased.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a bandgap reference circuit, a power management module and a communication chip to improve the establishment speed of a bandgap reference voltage under low power consumption conditions.

[0009] In some embodiments, the bandgap reference circuit includes: a bandgap reference core circuit, configured to generate a bandgap reference voltage; a startup circuit, connected to the bandgap reference core circuit, configured to generate a first injection current, and stop generating the first injection current after the startup circuit reaches a preset condition; the first injection current acts on the bandgap reference core circuit to accelerate the establishment of the bandgap reference voltage; a bandgap reference voltage detection circuit, connected to the bandgap reference core circuit, configured to generate a second injection current, and stop generating the second injection current after the bandgap reference voltage reaches a first threshold voltage; the second injection current acts on the bandgap reference core circuit to accelerate the establishment of the bandgap reference voltage.

[0010] Optionally, the bandgap reference core circuit includes: a first current branch, a second current branch, and a core amplifier; the first current branch and the second current branch use a current mirror with a common source and common gate structure; the second current branch is provided with an output port for outputting a bandgap reference voltage; the output end of the core amplifier is connected to the gates of the common source and common gate tube and the current mirror tube; the negative input end of the core amplifier is connected to the current output end of the first current branch; the negative input end of the core amplifier is connected to the current output end of the second current branch; and the core amplifier is provided with a current injection input port.

[0011] Optionally, in the first current branch and the second current branch, the width-to-length ratio of the common-source and common-gate tubes is smaller than the width-to-length ratio of the current mirror tube, so as to increase the source-drain voltage of the current mirror tube, make the current mirror tube operate in a saturation region, and improve the accuracy of the output voltage.

[0012] Optionally, the core amplifier adopts a single-stage amplifier structure including a current mirror with a common source and common gate structure to meet the gain requirement of the amplifier under low power supply voltage conditions.

[0013] Optionally, the starting circuit includes: a first capacitor, a capacitor charging circuit, a capacitor discharging circuit, a capacitor voltage detection circuit, and a first current generating circuit; the capacitor charging circuit is configured to charge the first capacitor after the starting circuit is powered on, so that the positive plate voltage of the first capacitor gradually increases; the capacitor voltage detection circuit is configured to perform voltage detection on the positive plate voltage of the first capacitor, and when the positive plate voltage does not reach a second threshold voltage, the capacitor voltage detection circuit is turned on, and the first current generating circuit generates a first injection current; when the positive plate voltage reaches the second threshold voltage, the capacitor voltage detection circuit is turned off, and the first current generating circuit stops generating the first injection current; the capacitor discharge circuit is configured to discharge the first capacitor after the starting circuit is powered on.

[0014] Optionally, the startup circuit further includes: a self-bias current generating module; the self-bias current generating module is connected to the first capacitor and is configured to discharge the first capacitor when the power is powered on again after power failure.

[0015] Optionally, the bandgap reference voltage detection circuit includes: a comparator, a voltage-dividing resistor circuit, a latch, and a second current generating circuit; the voltage-dividing resistor circuit is configured to generate a comparison voltage according to the resistor voltage division; the comparator is configured to compare the bandgap reference voltage with the comparison voltage, and output a first level signal when the bandgap reference voltage is less than the comparison voltage; and output a second level signal when the bandgap reference voltage is greater than or equal to the comparison voltage; the latch is configured to output a control signal according to the output signal of the comparator; when the comparator outputs the first level signal, the latch outputs the first control signal; when the comparator outputs the second level signal, the latch outputs the second control signal, and locks the output signal of the latch as the second control signal; the second current generating circuit is configured to generate a second injection current under the action of the first control signal, and stop generating the injection current under the action of the second control signal.

[0016] Optionally, the latch is further configured to, when the output signal of the latch is a second control signal, turn off the voltage-dividing resistor circuit and the comparator, and clamp the output of the comparator to a second level signal.

[0017] In some embodiments, the power management module includes a bandgap reference circuit as described above.

[0018] In some embodiments, the communication chip includes a power management module as described above.

[0019] The bandgap reference circuit, power management module and communication chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] The bandgap reference circuit provided by the embodiment of the present disclosure includes a bandgap reference core circuit, a startup circuit and a bandgap reference voltage detection circuit. After the bandgap reference circuit is powered on, the startup circuit and the bandgap reference voltage detection circuit respectively generate a first injection current and a second injection current, which act together on the bandgap reference core circuit to accelerate the establishment of the bandgap reference voltage. As the startup circuit continues to work, after the startup circuit reaches a preset condition, the startup circuit will stop generating the first injection current, and at this time, the second injection current acts alone on the bandgap reference core circuit to continue to establish the bandgap reference voltage. After the bandgap reference voltage is established, that is, after the bandgap reference voltage reaches the first threshold voltage, the bandgap reference voltage detection circuit stops generating the second injection current. Therefore, through the first injection current and the second injection current, the establishment of the bandgap reference voltage can be accelerated. After the bandgap reference voltage is established, the first injection current and the second injection current are turned off to meet the low power consumption requirements of the bandgap reference circuit, thereby achieving an increase in the establishment speed of the bandgap reference voltage under low power consumption conditions. In addition, after the startup circuit reaches the preset condition, the first injection current will be stopped, which reduces the injection current flowing to the bandgap reference core circuit and can reduce the obvious overshoot of the bandgap reference voltage during the establishment process.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a circuit block diagram of a bandgap reference circuit provided by an embodiment of the present disclosure;

[0024] Figure 2 is a circuit diagram of a bandgap reference core circuit in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0025] Figure 3 is a circuit diagram of a core amplifier in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0026] Figure 4 is a circuit diagram of a startup circuit in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 is a circuit diagram of a self-bias current generating module in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0028] Figure 6 is a circuit diagram of a bandgap reference voltage detection circuit in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0029] Figure 7 is a circuit diagram of a bandgap reference circuit provided by an embodiment of the present disclosure;

[0030] Figure 8 is a circuit diagram of a latch in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0031] Fig. 9 is a circuit diagram of a comparator in a bandgap reference circuit provided by an embodiment of the present disclosure;

[0032] Fig.10 It is a schematic diagram of the change of the bandgap reference voltage of a bandgap reference circuit provided by an embodiment of the present disclosure when the power supply is powered on for the second time and the enable is turned on for the second time;

[0033] Fig.11 It is a schematic diagram showing the variation of a bandgap reference voltage established by a bandgap reference circuit provided by an embodiment of the present disclosure over time. DETAILED DESCRIPTION

[0034] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0035] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0036] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0037] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0038] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0039] Combination Figure 1 As shown, an embodiment of the present disclosure provides a bandgap reference circuit, including: a bandgap reference core circuit 10 , a startup circuit 20 and a bandgap reference voltage detection circuit 30 .

[0040] The bandgap reference core circuit 10 is configured to generate a bandgap reference voltage. The startup circuit 20 is connected to the bandgap reference core circuit 10 and configured to generate a first sink current and stop generating the first sink current after the startup circuit 20 reaches a preset condition; the first sink current acts on the bandgap reference core circuit 10 to accelerate the establishment of the bandgap reference voltage. The bandgap reference voltage detection circuit 30 is connected to the bandgap reference core circuit 10 and configured to generate a second sink current and stop generating the second sink current after the bandgap reference voltage reaches a first threshold voltage; the second sink current acts on the bandgap reference core circuit 10 to accelerate the establishment of the bandgap reference voltage.

[0041] After the bandgap reference circuit is powered on, the startup circuit 20 and the bandgap reference voltage detection circuit 30 generate a first sink current and a second sink current respectively, which act together on the bandgap reference core circuit 10 to accelerate the establishment of the bandgap reference voltage. As the startup circuit 20 continues to work, after the startup circuit 20 reaches a preset condition, the startup circuit 20 will stop generating the first sink current, and at this time, the second sink current acts alone on the bandgap reference core circuit 10 to continue the establishment of the bandgap reference voltage. After the bandgap reference voltage is established, that is, after the bandgap reference voltage reaches the first threshold voltage, the bandgap reference voltage detection circuit 30 stops generating the second sink current. Therefore, the establishment of the bandgap reference voltage can be accelerated by the first sink current and the second sink current. After the bandgap reference voltage is established, the first sink current and the second sink current are turned off to meet the low power consumption requirements of the bandgap reference circuit, thereby achieving an increase in the establishment speed of the bandgap reference voltage under low power consumption conditions. In addition, after the startup circuit 20 reaches the preset condition, it will stop generating the first sink current, reducing the sink current flowing to the bandgap reference core circuit 10, which can reduce the obvious overshoot of the bandgap reference voltage during the establishment process.

[0042] Optionally, combined Figure 2 As shown, the bandgap reference core circuit 10 includes: a first current branch 11, a second current branch 12, and a core amplifier AMP. The first current branch 11 and the second current branch 12 use a current mirror with a common source and common gate structure; the second current branch 12 is provided with an output port for outputting a bandgap reference voltage VREF. The output end of the core amplifier AMP is connected to the gates of the common source and common gate tube and the current mirror tube; the negative input end of the core amplifier AMP is connected to the current output end of the first current branch 11; the negative input end of the core amplifier AMP is connected to the current output end of the second current branch 12; the core amplifier AMP is provided with a current input port IBIAS_AMP.

[0043] Combination Figure 2 and Figure 7 As shown, in an optional embodiment, the first current branch 11 includes: a first PMOS tube PM1, a third PMOS tube PM3, a first resistor R1, a second resistor R2, a third resistor R3, and a first PNP transistor PNP1; the second current branch 12 includes: a second PMOS tube PM2, a fourth PMOS tube PM4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a second PNP transistor PNP2; the bandgap reference core circuit 10 also includes: a second capacitor C2.

[0044] The source of the first PMOS tube PM1 is connected to the power supply; the output end of the core amplifier AMP is connected to the gate of the first PMOS tube PM1, the gate of the second PMOS tube PM2, the gate of the third PMOS tube PM3, the gate of the fourth PMOS tube PM4, and the negative plate of the second capacitor C2; the drain of the first PMOS tube PM1 is connected to the source of the third PMOS tube PM3; the source of the second PMOS tube PM2 is connected to the power supply; the drain of the second PMOS tube PM2 is connected to the source of the fourth PMOS tube; the drain of the third PMOS tube PM3 is connected to the first end of the first resistor R1; the drain of the fourth PMOS tube PM4 is connected to the first end of the fourth resistor R4, serving as the output port of the bandgap reference core circuit 10, outputting the bandgap reference voltage VREF; the positive plate of the second capacitor C2 is connected to the power supply; The second end of the first resistor R1 is connected to the first end of the second resistor R2; the second end of the second resistor R2 is connected to the first end of the third resistor R3; the second end of the third resistor R3 is connected to the negative input end of the core amplifier AMP and the emitter of the first PNP transistor PNP1; the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6; the second end of the sixth resistor R6 is connected to the first end of the seventh resistor R7; the second end of the seventh resistor R7 is connected to the positive input end of the core amplifier AMP and the first end of the eighth resistor R8; the second end of the eighth resistor R8 is connected to the emitter of the second PNP transistor PNP2; the base and collector of the first PNP transistor PNP1 are grounded; the base and collector of the second PNP transistor PNP2 are grounded.

[0045] Optionally, in the first current branch 11 and the second current branch 12, the width-to-length ratio of the common-source common-gate tube is smaller than the width-to-length ratio of the current mirror tube, so as to increase the source-drain voltage of the current mirror tube, make the current mirror tube work in the saturation region, and improve the accuracy of the output voltage.

[0046] In this embodiment, the first PMOS tube PM1 and the second PMOS tube PM2 are inversely proportional tubes with relatively small width and length, and the third PMOS tube PM3 and the fourth PMOS tube PM4 are proportional tubes with relatively large width and length, so that when the power supply voltage is low, the first PMOS tube PM1, the second PMOS tube PM2, the third PMOS tube PM3 and the fourth PMOS tube PM4 can also work in the saturation region, thereby improving the accuracy of the output voltage. The first resistor R1, the second resistor R2, and the third resistor R3 are connected in series in the first current branch 11, which can not only construct the mechanism of the startup circuit 20, but also make the drain voltages of the third PMOS tube PM3 and the fourth PMOS tube PM4 as close as possible, so as to better meet the requirements of the current mirror accuracy of the first current branch 11 and the second current branch 12.

[0047] Optionally, the core amplifier AMP adopts a single-stage amplifier structure including a current mirror in a common-source common-gate structure to meet the gain requirement of the amplifier under low power supply voltage conditions.

[0048] Combination Figure 3 As shown, in an optional embodiment, the core amplifier AMP includes: a fifth PMOS tube PM5, a sixth PMOS tube PM6, a seventh PMOS tube PM7, an eighth PMOS tube PM8, a first NMOS tube NM1, a second NMOS tube NM2, a third NMOS tube NM3, and a fourth NMOS tube NM4.

[0049] The source of the fifth PMOS tube PM5 is connected to the power supply; the gate of the fifth PMOS tube PM5, the gate of the sixth PMOS tube PM6, the drain of the sixth PMOS tube PM6, the drain of the first NMOS tube NM1, the gate of the seventh PMOS tube PM7, and the gate of the eighth PMOS tube PM8 are all connected; the drain of the fifth PMOS tube PM5 is connected to the source of the sixth PMOS tube PM6; the drain of the seventh PMOS tube PM7 is connected to the source of the eighth PMOS tube PM8; the drain of the eighth PMOS tube PM8 is connected to the drain of the second NMOS tube NM2, as the core amplifier A The output end of MP; the gate of the first NMOS tube NM1 is used as the negative input end of the core amplifier AMP; the gate of the second NMOS tube NM2 is used as the positive input end of the core amplifier AMP; the source of the first NMOS tube NM1, the source of the second NMOS tube NM2, and the drain of the fourth NMOS tube NM4 are all connected; the gate of the fourth NMOS tube NM4, the gate of the third NMOS tube NM3, and the drain of the third NMOS tube NM3 are all connected as the current injection input port IBIAS_AMP; the source of the third NMOS tube NM3 and the source of the fourth NMOS tube NM4 are all grounded.

[0050] Optionally, combined Figure 4 As shown, the startup circuit 20 includes: a first capacitor C1, a capacitor charging circuit 21, a capacitor discharging circuit 22, a capacitor voltage detection circuit 23, and a first current generating circuit 24. The capacitor charging circuit 21 is configured to charge the first capacitor C1 after the startup circuit 20 is powered on, so that the positive plate voltage of the first capacitor C1 gradually increases. The capacitor voltage detection circuit 23 is configured to perform voltage detection on the positive plate voltage of the first capacitor C1. When the positive plate voltage does not reach the second threshold voltage, the capacitor voltage detection circuit 23 is turned on, and the first current generating circuit 24 generates a first injection current IBIAS1_AMP; when the positive plate voltage reaches the second threshold voltage, the capacitor voltage detection circuit 23 is turned off, and the first current generating circuit 24 stops generating the first injection current IBIAS1_AMP. The capacitor discharging circuit 22 is configured to discharge the first capacitor C1 after the startup circuit 20 is powered on.

[0051] In this embodiment, the startup circuit 20 charges the first capacitor C1 through the capacitor charging circuit 21 using the PTAT current with a positive temperature coefficient generated by the bandgap reference core circuit 10, thereby realizing the function of the startup circuit 20. When the bandgap reference voltage VREF is not established, the first capacitor C1 does not store any charge, and the positive plate voltage of the first capacitor C1 is 0. At this time, the main current branch of the bandgap reference core circuit 10 is injected through an additional current branch, breaking the initial state equilibrium point of the bandgap reference core circuit 10, and the bandgap reference voltage VREF is established. In the process of establishing the bandgap reference voltage VREF, the charge on the first capacitor C1 gradually accumulates, and the voltage of the positive plate gradually increases. When the positive plate voltage reaches the second threshold voltage, the capacitor voltage detection circuit 23 is turned off, and the first current generating circuit 24 stops generating the first injection current IBIAS1_AMP. After the startup circuit 20 is powered on, the first capacitor C1 needs to be discharged through the capacitor discharge circuit 22 to ensure that the first injection current IBIAS1_AMP can be correctly generated during the next bandgap reference voltage VREF establishment process. Therefore, a first current sink IBIAS1_AMP path for biasing the core amplifier AMP in the core circuit of the bandgap reference circuit is constructed in the startup circuit 20. That is, when the startup circuit 20 is working, the power consumption of the core amplifier AMP is increased and the response speed is improved. When the startup circuit 20 is turned off, the first current sink IBIAS1_AMP path for the core amplifier AMP is also turned off, and the power consumption of the core amplifier AMP returns to normal.

[0052] In an optional embodiment, in combination with Figure 4 and Figure 7 As shown, the capacitor charging circuit 21 includes: a ninth PMOS tube PM9, a tenth PMOS tube PM10, and a fifteenth PMOS tube PM15; the capacitor discharging circuit 22 includes: a first inverter INV1, a fifth NMOS tube NM5; the capacitor voltage detection circuit 23 includes: an eleventh PMOS tube PM11, a twelfth PMOS tube PM12, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, a sixth NMOS tube NM6, a seventh NMOS tube NM7, and a third PNP transistor PNP3; the first current generating circuit 24 includes: a sixteenth PMOS tube PM16 and a seventeenth PMOS tube PM17.

[0053] The source of the ninth PMOS tube PM9 is connected to the power supply; the gate of the ninth PMOS tube PM9, the gate of the tenth PMOS tube PM10, and the drain of the fifteenth PMOS tube PM15 are all connected to the output end of the core amplifier AMP; the drain of the ninth PMOS tube PM9 is connected to the source of the tenth PMOS tube PM10; the drain of the tenth PMOS tube PM10, the gate of the eleventh PMOS tube PM11, the gate of the twelfth PMOS tube PM12, the gate of the thirteenth PMOS tube PM13, and the gate of the fourteenth PMOS tube PM14 are connected to the output end of the core amplifier AMP; , the drain of the fifth NMOS tube NM5 is connected to the positive plate of the first capacitor C1; the source of the eleventh PMOS tube PM11 is connected to the power supply; the drain of the eleventh PMOS tube PM11 is connected to the source of the twelfth PMOS tube PM12; the drain of the twelfth PMOS tube PM12 is connected to the source of the thirteenth PMOS tube PM13; the drain of the thirteenth PMOS tube PM13 is connected to the source of the fourteenth PMOS tube PM14; the drain of the fourteenth PMOS tube PM14 is connected to the gate of the sixth NMOS tube NM6 and the gate of the sixth NMOS tube NM7. 6 and the drain of the seventh NMOS tube NM7 are connected; the source of the fifteenth PMOS tube PM15 is connected to the power supply; the gate of the fifteenth PMOS tube PM15 is connected to the circuit general enable BGR_EN; the source of the sixteenth PMOS tube PM16 is connected to the power supply; the gate of the sixteenth PMOS tube PM16 is connected to the drain of the sixteenth PMOS tube PM16, the drain of the seventh NMOS tube NM7, and the gate of the seventeenth PMOS tube PM17; the source of the seventeenth PMOS tube PM17 is connected to the power supply; the seventeenth PMOS tube PM1 The drain of the first NMOS transistor NM7 is used as the output end of the first current sink IBIAS1_AMP; the input end of the first inverter INV1 is connected to the circuit general enable BGR_EN; the output end of the first inverter INV1 is connected to the gate of the fifth NMOS transistor NM5; the source of the fifth NMOS transistor NM5 is grounded; the negative plate of the first capacitor C1 is grounded; the source of the sixth NMOS transistor NM6 is connected to the emitter of the third PNP transistor PNP3; the collector and base of the third NPN transistor are grounded; the drain of the seventh NMOS transistor NM7 is connected to the first end of the first resistor R1.

[0054] In this embodiment, the gate of the ninth PMOS tube PM9 is connected to the gate of the tenth PMOS tube PM10, and is connected to the gate of the first PMOS tube PM1 and the gate of the third PMOS tube PM3 to mirror the current branch formed by the first PMOS tube PM1 and the third PMOS tube PM3. The eleventh PMOS tube PM11, the twelfth PMOS tube PM12, the thirteenth PMOS tube PM13, and the fourteenth PMOS tube PM14 are connected in series, which is equivalent to an inverse ratio tube with a very small width-to-length ratio. The sixth NMOS tube NM6 and the seventh NMOS tube NM7 form a mirror tube, and a zero-threshold NMOS tube is used. Therefore, when the drain voltage of the seventh NMOS tube NM7 is greater than the base-emitter voltage of the third PNP transistor PNP3, the first injection current IBIAS1_AMP stops. In addition, the current flowing through the ninth PMOS tube PM9 and the tenth PMOS tube PM10 charges the first capacitor C1. When the positive plate voltage of the first capacitor C1 increases, causing the eleventh PMOS tube PM11 to be turned off, the first injection current IBIAS1_AMP stops. Both of the two shut-off mechanisms of the first current sink IBIAS1_AMP ensure that the additional first current sink IBIAS1_AMP is shut off after the bandgap reference voltage VREF is stably established, meeting the requirements of accelerated startup before the bandgap reference voltage VREF is stable and low power consumption after stabilization. When the circuit general enable BGR_EN is turned off, the charge on the first capacitor C1 is released cleanly through the fifth NMOS tube NM5, preventing the startup circuit 20 from failing due to the short working time of the startup circuit 20 after the circuit general enable BGR_EN is turned on, and the bandgap reference cannot be established normally.

[0055] Optionally, combined Figure 4 As shown, the startup circuit 20 further includes: a self-bias current generating module 25. The self-bias current generating module 25 is connected to the first capacitor C1 and is configured to discharge the first capacitor C1 when the power is turned on again after power failure.

[0056] In this embodiment, a self-bias current generating module 25 is connected in parallel to the positive plate of the first capacitor C1 to generate a weak discharge path current IBIAS1_C1, further ensuring the safety and reliability of the startup circuit 20. For example, after the bandgap reference voltage VREF output is stably established, the enable is always kept on, but when the power supply voltage is powered on again after power failure, if there is no very weak discharge path connected in parallel to the positive plate of the first capacitor C1, the bandgap reference voltage VREF cannot be established again after the power supply voltage is powered on again. By connecting a self-bias current generating module 25 to the positive plate of the first capacitor C1, combined with Fig.10As shown, after the power supply voltage is powered on for the second time or the circuit general enable BGR_EN is turned on for the second time, the first capacitor C1 will always release the charge completely, and the startup circuit 20 will automatically take effect, and the accelerated establishment of the bandgap reference voltage VREF will be started again. The startup circuit 20 provided by the embodiment of the present disclosure has high safety and reliability, and ensures that the bandgap reference circuit can be stably established in the special situation that the enable is turned on multiple times and the power supply voltage is powered on twice after power failure.

[0057] Optionally, combined Figure 5 As shown, the self-bias current generating module 25 includes: an eighteenth PMOS transistor PM18, a nineteenth PMOS transistor PM19, a twentieth PMOS transistor PM20, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a twelfth NMOS transistor, and a ninth resistor R9.

[0058] The source of the eighteenth PMOS tube PM18, the source of the nineteenth PMOS tube PM19, and the source of the twentieth PMOS tube PM20 are all connected to the power supply; the gate of the eighteenth PMOS tube PM18, the gate of the nineteenth PMOS tube PM19, the gate of the twentieth PMOS tube PM20, the drain of the eleventh NMOS tube NM11, the gate of the eleventh NMOS tube NM11, and the drain of the twelfth NMOS tube are all connected; the drain of the eighteenth PMOS tube PM18, the drain of the ninth NMOS tube NM9, the gate of the ninth NMOS tube NM9 are all connected to the power supply. The drain of the nineteenth PMOS tube PM19, the drain of the tenth NMOS tube NM10, the gate of the tenth NMOS tube NM10, the source of the eleventh NMOS tube NM11, and the gate of the twelfth NMOS tube are all connected; the source of the eighth NMOS tube NM8, the source of the ninth NMOS tube NM9, and the source of the tenth NMOS tube NM10 are all grounded; the drain of the eighth NMOS tube NM8 is connected to the positive plate of the first capacitor C1; the source of the twelfth NMOS tube is connected to the first end of the ninth resistor R9; and the second end of the ninth resistor R9 is grounded.

[0059] In this embodiment, the self-bias current generating module 25 can generate a weak discharge path current IBIAS1_C1 from the positive plate of the first capacitor C1 to the ground through the eighth NMOS tube NM8, and the magnitude is about 5 to 10nA. At this time, the total circuit current of the self-bias current generating module 25 is about 30nA. The eighteenth PMOS tube PM18, the nineteenth PMOS tube PM19, and the twentieth PMOS tube PM20 have the same size and the same current flowing through them. The width-to-length ratio of the tenth NMOS tube NM10 is K times the width-to-length ratio of the twelfth NMOS tube, the resistance value of the ninth resistor R9 is R0, the eighth NMOS tube NM8 and the second NMOS tube NM2 have the same size and are in a mirror relationship, so the pull-down current IBIAS that finally flows through the eighth NMOS tube NM8 is:

[0060]

[0061] Among them, μ n is the electron mobility of the eighth NMOS tube NM8, C OX is the gate oxide layer capacitance value, W is the channel width of the eighth NMOS transistor NM8, and L is the channel length of the eighth NMOS transistor NM8.

[0062] Optionally, combined Figure 6 As shown, the bandgap reference voltage detection circuit 30 includes: a comparator CMP, a voltage-dividing resistor circuit 31, a latch 32, and a second current generating circuit 33. The voltage-dividing resistor circuit 31 is configured to generate a comparison voltage according to the resistor voltage division. The comparator CMP is configured to compare the bandgap reference voltage VREF with the comparison voltage, and output a first level signal when the bandgap reference voltage VREF is less than the comparison voltage; and output a second level signal when the bandgap reference voltage VREF is greater than or equal to the comparison voltage. The latch 32 is configured to output a control signal according to the output signal of the comparator CMP; when the comparator CMP outputs a first level signal, the latch 32 outputs a first control signal; when the comparator CMP outputs a second level signal, the latch 32 outputs a second control signal, and locks the output signal of the latch 32 as a second control signal. The second current generating circuit 33 is configured to generate a second sink current IBIAS2_AMP under the action of the first control signal, and stop generating the second sink current IBIAS2_AMP under the action of the second control signal.

[0063] Optionally, the first level signal is a low level signal, and the second level signal is a high level signal. The first control signal is a low level control signal, and the second control signal is a high level control signal.

[0064] In this embodiment, the comparator CMP is used to compare the bandgap reference voltage VREF with the comparison voltage divided by the voltage-dividing resistor circuit 31. When the bandgap reference voltage VREF is in the initial establishment process stage, the bandgap reference voltage VREF is less than the comparison voltage, and a low-level signal is output. After passing through the latch 32, a low-level control signal is output. The low-level control signal controls the second current generating circuit 33 to generate a second sink current IBIAS2_AMP to act on the core amplifier AMP, thereby increasing the power consumption of the core amplifier AMP and increasing the loop response speed. When the bandgap reference voltage VREF is established to be greater than the comparison voltage, a high-level signal is output. After passing through the latch 32, a high-level control signal is output. The high-level control signal controls the second current generating circuit 33 to stop generating the second sink current IBIAS2_AMP. At the same time, at the rising edge moment from the low-level signal to the high-level signal, the latch 32 locks the high-level state.

[0065] Optionally, the latch 32 is further configured to, when the output signal of the latch 32 is the second control signal, turn off the voltage-dividing resistor circuit 31 and the comparator CMP, and clamp the output of the comparator CMP to the second level signal.

[0066] In this embodiment, after the latch 32 outputs a high-level control signal, the power consumption of the voltage divider resistor circuit 31 and the comparator CMP in the bandgap reference voltage detection circuit 30 is simultaneously turned off, and only the power consumption of the bandgap reference core circuit 10 is retained, thereby still ensuring the system requirement of low power consumption of the bandgap reference circuit as a whole.

[0067] In an optional embodiment, in combination with Figure 6 and Figure 7 As shown, the voltage-dividing resistor circuit 31 includes: a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and a twenty-first PMOS tube PM21; the second current generating circuit 33 includes: a twenty-second PMOS tube PM22, a twenty-third PMOS tube PM23, and a twenty-fourth PMOS tube PM24; the bandgap reference voltage detection circuit 30 also includes: a twenty-fifth PMOS tube PM25, a twenty-sixth PMOS tube PM26, a thirteenth NMOS tube NM13, a fourteenth NMOS tube NM14, a fifteenth NMOS tube NM15, a sixteenth NMOS tube NM16, a third capacitor C3, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a fifth inverter INV5.

[0068] The source of the twenty-sixth PMOS tube PM26 is connected to the power supply; the gate of the twenty-sixth PMOS tube PM26 is connected to the output end of the core amplifier AMP; the drain of the twenty-sixth PMOS tube PM26 is connected to the drain of the thirteenth NMOS tube NM13 and the gate of the fifteenth NMOS tube NM15; the gate of the thirteenth NMOS tube NM13 is connected to the bandgap reference voltage VREF; the source of the thirteenth NMOS tube NM13 is connected to the gate of the fourteenth NMOS tube NM14 and the drain of the fourteenth NMOS tube NM14; the source of the fourteenth NMOS tube NM14 is grounded; the source of the fifteenth NMOS tube NM15 is grounded; the source of the twenty-first PMOS tube PM21 is connected to the power supply; The gate of the twenty-first PMOS transistor PM21 is connected to the output of the latch 32; the drain of the twenty-first PMOS transistor PM21 is connected to the first end of the tenth resistor R10; the second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11, the drain of the fifteenth NMOS transistor NM15, and the negative input end of the comparator CMP; the second end of the eleventh resistor R11 is connected to the first end of the twelfth resistor R12 and the gate of the sixteenth NMOS transistor NM16; the second end of the twelfth resistor R12 is grounded; the positive input end of the comparator CMP is connected to the bandgap reference voltage VREF; the output end of the comparator CMP is connected to the drain of the sixteenth NMOS transistor NM16, the positive plate of the third capacitor C3, the second The drain of the fifteenth PMOS tube PM25 and the input end of the second inverter INV2 are connected; the source of the sixteenth NMOS tube NM16 is grounded; the negative plate of the third capacitor C3 is grounded; the source of the twenty-fifth PMOS tube PM25 is connected to the power supply; the input end of the fifth inverter INV5 is connected to the output end DET_OUT of the latch 32; the output of the fifth inverter INV5 is connected to the gate of the twenty-fifth PMOS tube PM25; the output end of the second inverter INV2 is connected to the input end of the third inverter INV3; the output end of the third inverter INV3 is connected to the clock input end CLK of the latch 32; the data input end D of the latch 32 is connected to the power supply end; the reset end RE of the latch 32 SET is connected to the output end of the fourth inverter INV4; the input end of the fourth inverter INV4 is connected to the circuit general enable BGR_EN; the source of the twenty-second PMOS tube PM22 is connected to the power supply; the gate of the twenty-second PMOS tube PM22 is connected to the output end of the core amplifier AMP; the drain of the twenty-second PMOS tube PM22 is connected to the source of the twenty-third PMOS tube PM23; the gate of the twenty-third PMOS tube PM23 is connected to the output end of the core amplifier AMP; the drain of the twenty-third PMOS tube PM23 is connected to the source of the twenty-fourth PMOS tube PM24; the gate of the twenty-fourth PMOS tube PM24 is connected to the output end DET_OUT of the latch 32;The drain of the twenty-fourth PMOS tube PM24 is the output terminal of the second current sink IBIAS2_AMP. ;

[0069] In this embodiment, when the bandgap reference voltage VREF is just beginning to be established, the comparator CMP outputs a low-level signal, and the output terminal DET_OUT of the latch 32 is also a low-level signal. The low-level signal is turned on by controlling the 20th PMOS tube PM20 to control the voltage-dividing resistor circuit 31, and the comparator CMP is controlled to work normally. In addition, the 22nd PMOS tube PM22, the 23rd PMOS tube PM23, and the 24th PMOS tube PM24 are also controlled to be turned on to generate a second injection current IBIAS2_AMP, and the core amplifier AMP of the bandgap reference core circuit 10 is supplemented with additional current to accelerate the establishment of the bandgap reference voltage VREF. When the bandgap reference voltage VREF is stably established, the comparator CMP outputs a high-level signal. At the moment when the comparator CMP switches from a low level to a high level, the output terminal DET_OUT of the latch 32 is locked and outputs a high-level signal. The high-level signal is turned off by controlling the 20th PMOS tube PM20 to control the voltage-dividing resistor circuit 31, and the comparator CMP is controlled to be turned off and the output of the comparator CMP is clamped to a high level through the 25th PMOS tube PM25. In addition, the twenty-second PMOS transistor PM22 , the twenty-third PMOS transistor PM23 , and the twenty-fourth PMOS transistor PM24 are controlled to be turned off, that is, the second injection current IBIAS2_AMP to the core amplifier AMP of the bandgap reference core circuit 10 is turned off.

[0070] Optionally, combined Figure 8 As shown, the latch 32 includes: a sixth inverter INV6, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, a NAND gate NAND, and a NOR gate NOR.

[0071] The data input terminal D of the latch 32 is connected to the input terminal of the first transmission gate TG1; the output terminal of the first transmission gate TG1 is connected to the output terminal of the second transmission gate TG2, as the first input signal of the NAND gate NAND; the reset terminal RESET of the latch 32 is used as the first input signal of the NOR gate NOR; the reset terminal RESET of the latch 32 is connected to the input terminal of the sixth inverter INV6; the output terminal of the sixth inverter INV6 is used as the second input signal of the NAND gate NAND; the output terminal of the NAND gate NAND is connected to the input terminals of the third transmission gate TG3 and the seventh inverter INV7; the output terminal of the seventh inverter INV7 is connected to the input terminal of the second transmission gate TG2; the output terminal of the third transmission gate TG3 is connected to the output terminal of the fourth transmission gate TG4, as the first input signal of the NOR gate NOR. The second input signal; the output end of the NOR gate NOR serves as the output end DET_OUT of the latch 32, and is connected to the input end of the eighth inverter INV8, and the output end of the eighth inverter INV8 is connected to the input end of the fourth transmission gate TG4; the clock input end CLK of the latch 32 is connected to the input end of the ninth inverter INV9; the output end of the ninth inverter INV9 is connected to the input end of the tenth inverter INV10; the output end of the tenth inverter INV10 outputs the control signal CN, and is connected to the input end of the eleventh inverter INV11; the output end of the eleventh inverter INV11 outputs the control signal CP; the control signal CN and the control signal CP serve as control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4.

[0072] Optionally, combined Fig. 9 As shown, the comparator CMP includes: a twenty-seventh PMOS tube PM27, a twenty-eighth PMOS tube PM28, a twenty-ninth PMOS tube PM29, a thirtieth PMOS tube PM30, a thirty-first PMOS tube PM31, a thirty-second PMOS tube PM32, a thirty-third PMOS tube PM33, a seventeenth NMOS tube NM17, an eighteenth NMOS tube NM18, a nineteenth NMOS tube NM19, a twentieth NMOS tube NM20, a twenty-first NMOS tube NM21, a twenty-second NMOS tube NM22, a twenty-third NMOS tube NM23, and a twenty-fourth NMOS tube NM24.

[0073] The source of the twenty-seventh PMOS tube PM27 is connected to the power supply; the gate of the twenty-seventh PMOS tube PM27 is connected to the drain of the twenty-seventh PMOS tube PM27, the drain of the eighteenth NMOS tube NM18, the drain of the thirty-second PMOS tube PM32, and the gate of the twenty-eighth PMOS tube PM28; the source of the twenty-eighth PMOS tube PM28 is connected to the power supply; the drain of the twenty-eighth PMOS tube PM28 is connected to the source of the twenty-ninth PMOS tube PM29 and the source of the thirtieth PMOS tube PM30; the gate of the twenty-ninth PMOS tube PM29 serves as the positive input terminal VIP of the comparator CMP; the gate of the twenty-ninth PMOS tube PM29 is connected to ... twenty-eighth PMOS tube PM28. The drain of the nineteenth NMOS tube NM19, the gate of the nineteenth NMOS tube NM19, and the gate of the twentieth NMOS tube NM20 are all connected; the gate of the thirtieth PMOS tube PM30 serves as the negative input terminal VIN of the comparator CMP; the drain of the thirtieth PMOS tube PM30 is connected to the drain of the twentieth NMOS tube NM20 and the drain of the thirty-third PMOS tube PM33, and serves as the output terminal COMP_OUT of the comparator CMP; the source of the thirty-first PMOS tube PM31 is connected to the second sink current IBIAS2_AMP; the gate of the thirty-first PMOS tube PM31 is connected to the ENP signal; the drain of the thirty-first PMOS tube PM31 ... The source of the twenty-first NMOS tube NM21, the drain of the seventeenth NMOS tube NM17, the gate of the seventeenth NMOS tube NM17, the drain of the twenty-fourth NMOS tube NM24, and the gate of the eighteenth NMOS tube NM18 are all connected; the source of the thirty-second PMOS tube PM32 is connected to the power supply; the gate of the thirty-second PMOS tube PM32 is connected to the ENN signal; the source of the thirty-third PMOS tube PM33 is connected to the power supply; the gate of the thirty-third PMOS tube PM33 is connected to the ENN signal; the source of the seventeenth NMOS tube NM17, the source of the eighteenth NMOS tube NM18, the source of the twenty-second NMOS tube NM22, the twenty-third NMOS The source of the S transistor NM23 and the source of the twenty-fourth NMOS transistor NM24 are both grounded; the source of the nineteenth NMOS transistor NM19 is connected to the drain of the twenty-second NMOS transistor NM22; the source of the twentieth NMOS transistor NM20 is connected to the drain of the twenty-third NMOS transistor NM23; the drain of the twenty-first NMOS transistor NM21 is connected to the second sink current IBIAS2_AMP; the gate of the twenty-first NMOS transistor NM21 is connected to the ENN signal; the gate of the twenty-second NMOS transistor NM22 is connected to the ENN signal; the gate of the twenty-third NMOS transistor NM23 is connected to the ENN signal; and the gate of the twenty-fourth NMOS transistor NM24 is connected to the ENP signal. Among them, the ENN signal is the output signal of the latch 32, and the ENP signal is the inverted signal of the output signal of the latch 32.

[0074] Combination Fig.11 As shown, the embodiment of the present disclosure divides the establishment of the bandgap reference voltage VREF into three stages: in the first stage, the startup circuit 20 generates the first injection current IBIAS1_AMP, and the bandgap reference voltage detection circuit 30 generates the second injection current IBIAS2_AMP. The first injection current IBIAS1_AMP and the second injection current IBIAS2_AMP act on the core amplifier AMP together, thereby quickly increasing the voltage value of the bandgap reference voltage VREF and accelerating the establishment of the bandgap reference power supply. In the second stage, the startup circuit 20 stops generating the first injection current IBIAS1_AMP, and the second injection current IBIAS2_AMP continues to complete the establishment of the bandgap reference voltage VREF, thereby reducing the injection current of the core amplifier AMP and reducing the obvious overshoot in the process of establishing the bandgap reference voltage VREF. In the third stage, the bandgap reference voltage detection circuit 30 stops generating the second injection current IBIAS2_AMP, and the bandgap reference voltage VREF is established. Therefore, the bandgap reference circuit provided by the embodiment of the present disclosure can accelerate the establishment of the bandgap reference voltage VREF while meeting the low power consumption requirement of the bandgap reference circuit, and can also reduce the situation where the bandgap reference voltage VREF has obvious overshoot during the establishment process.

[0075] The embodiment of the present disclosure also provides a power management module, including the bandgap reference circuit as described above.

[0076] An embodiment of the present disclosure also provides a communication chip, comprising the power management module as described above.

[0077] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

Claims

1. A bandgap reference circuit, characterized in that: include: a bandgap reference core circuit configured to generate a bandgap reference voltage; A startup circuit connected to the bandgap reference core circuit, configured to generate a first sink current, and stop generating the first sink current after the startup circuit reaches a preset condition; The first current sink acts on the bandgap reference core circuit to accelerate the establishment of the bandgap reference voltage; The bandgap reference voltage detection circuit is connected to the bandgap reference core circuit and is configured to generate a second sink current and stop generating the second sink current after the bandgap reference voltage reaches a first threshold voltage; The second current sink acts on the bandgap reference core circuit to accelerate the establishment of the bandgap reference voltage.

2. The bandgap reference circuit according to claim 1, characterized in that: The bandgap reference core circuit includes: a first current branch, a second current branch, and a core amplifier; The first current branch and the second current branch use a current mirror having a common source and common gate structure; the second current branch is provided with an output port for outputting a bandgap reference voltage; The output end of the core amplifier is connected to the gates of the common source and common gate tube and the current mirror tube; the negative input end of the core amplifier is connected to the current output end of the first current branch; the negative input end of the core amplifier is connected to the current output end of the second current branch; the core amplifier is provided with a current injection input port.

3. The bandgap reference circuit according to claim 2, characterized in that: In the first current branch and the second current branch, the width-to-length ratio of the common-source common-gate tube is smaller than the width-to-length ratio of the current mirror tube, so as to increase the source-drain voltage of the current mirror tube, make the current mirror tube work in the saturation region, and improve the accuracy of the output voltage.

4. The bandgap reference circuit according to claim 2, characterized in that: The core amplifier adopts a single-stage amplifier structure including a current mirror with a common source and common gate structure to meet the gain requirement of the amplifier under the condition of low power supply voltage.

5. The bandgap reference circuit according to claim 1, characterized in that: The startup circuit includes: a first capacitor, a capacitor charging circuit, a capacitor discharging circuit, a capacitor voltage detection circuit, and a first current generating circuit; The capacitor charging circuit is configured to charge the first capacitor after the startup circuit is powered on, so that the voltage of the positive plate of the first capacitor gradually increases; The capacitor voltage detection circuit is configured to perform voltage detection on the positive plate voltage of the first capacitor. When the positive plate voltage does not reach the second threshold voltage, the capacitor voltage detection circuit is turned on, and the first current generating circuit generates the first sink current; when the positive plate voltage reaches the second threshold voltage, the capacitor voltage detection circuit is turned off, and the first current generating circuit stops generating the first sink current. The capacitor discharge circuit is configured to discharge the first capacitor after the startup circuit is powered on.

6. The bandgap reference circuit according to claim 5, characterized in that: The startup circuit also includes: a self-bias current generating module; The self-bias current generating module is connected to the first capacitor and is configured to discharge the first capacitor when the power source is powered on again after power failure.

7. The bandgap reference circuit according to claim 1, characterized in that: The bandgap reference voltage detection circuit includes: a comparator, a voltage dividing resistor circuit, a latch, and a second current generating circuit; The voltage-dividing resistor circuit is configured to generate a comparison voltage according to a resistor voltage division; The comparator is configured to compare the bandgap reference voltage with the comparison voltage, and output a first level signal when the bandgap reference voltage is less than the comparison voltage; and output a second level signal when the bandgap reference voltage is greater than or equal to the comparison voltage; The latch is configured to output a control signal according to an output signal of the comparator; when the comparator outputs a first level signal, the latch outputs a first control signal; when the comparator outputs a second level signal, the latch outputs a second control signal and locks the output signal of the latch as the second control signal; The second current generating circuit is configured to generate a second sink current under the action of the first control signal, and stop generating the sink current under the action of the second control signal.

8. The bandgap reference circuit according to claim 7, characterized in that: The latch is further configured to, when the output signal of the latch is the second control signal, turn off the voltage-dividing resistor circuit and the comparator, and clamp the output of the comparator to a second level signal.

9. A power management module, characterized in that: Comprising the bandgap reference circuit as claimed in any one of claims 1 to 8.

10. A communication chip, characterized in that: Comprising the power management module as claimed in claim 9.

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