LDO (Low Dropout Regulator) circuit with over-temperature overload protection function and control method thereof

Abstract

The invention discloses an LDO circuit with an over-temperature overload protection function and a control method thereof. The LDO circuit comprises an error amplifier, a current biasing circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit and a current limiting circuit. The output current of the LDO is controlled by detecting the output current and the temperature, and the power of the LDO is limited by limiting the output current when soft short circuit is output, so that chip heating is reduced; if the temperature of the chip continues to rise, the value of the output current is gradually reduced; and when the set temperature threshold value is reached, the LDO output current is further limited, so that the temperature rise of the chip is reduced, and the chip is protected.

Description

Technical Field

[0001] The present invention relates to an LDO circuit and a control method thereof, in particular to an LDO circuit with over-temperature and overload protection functions and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Some high-performance DCDC chips integrate a linear low-dropout regulator LDO with external capacitor compensation, which powers the analog and digital circuits inside the DCDC chip. Under normal circumstances, this type of LDO will produce large conduction losses when the output and output voltage difference is too large and the output current is output at the same time. This situation generally occurs when the LDO output is short-circuited. Traditional technology solves this problem by detecting the LDO output voltage, and hard-turning off the LDO when the output voltage is lower than a certain threshold. However, if the LDO output is soft-shorted, that is, the LDO output is not short-circuited to the output short-circuit protection threshold, the output current is also very large at this time. Due to the large output and output voltage difference and the large output current at the same time, heat will slowly accumulate, and finally thermal damage will occur, especially in high-temperature environment applications, such heat accumulation causes more thermal damage to the chip. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide an LDO circuit with over-temperature and overload protection function and a control method thereof, so as to reduce the temperature rise of the chip and protect the chip.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is: An LDO circuit with over-temperature and overload protection function comprises an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit and a current limiting circuit. The LDO circuit comprises a PMOS tube MP7, a resistor R6, a resistor R7 and a capacitor COUT. The source of the PMOS tube MP7 is connected to a power supply VIN, the gate of the PMOS tube MP7 is connected to the output end of the current bias circuit and the input end of the current sampling circuit, the drain of the PMOS tube MP7 is connected to one end of the resistor R6, one end of the capacitor COUT and the second input end of the voltage sampling circuit, the other end of the resistor R6 is connected to one end of the resistor R7 The first input terminal of the error amplifier is connected to the feedback voltage FB, the second input terminal of the error amplifier is connected to the reference voltage VREF1, the output terminal of the error amplifier is connected to the input terminal of the current bias circuit and the output terminal of the current limiting circuit, the output terminal of the current sampling circuit is connected to the input terminal of the voltage sampling circuit and generates a sampling current ISNS, the output terminal of the voltage sampling circuit generates a sampling voltage VSNS, the first input terminal of the current limiting circuit is connected to the reference voltage VREF2, the second input terminal of the current limiting circuit is connected to the sampling voltage VSNS, and the third input terminal of the current limiting circuit is connected to a reference source VBG with a zero temperature coefficient.

[0005] Furthermore, the error amplifier comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3 and a resistor R1, the source of the PMOS tube MP1 and the source of the PMOS tube MP4 are connected to a power supply VDDPRE, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP4 are connected to a bias voltage Vbias, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2 and the source of the PMOS tube MP3, and the gate of the PMOS tube MP2 serves as a first input terminal of the error amplifier and is connected to a feedback voltage FB The gate of the PMOS tube MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1. The drain of the PMOS tube MP2 is connected to the drain of the NMOS tube MN1 and the gate of the NMOS tube MN1. The drain of the PMOS tube MP3 is connected to the drain of the NMOS tube MN2, the gate of the NMOS tube MN2, one end of the resistor R1 and the gate of the NMOS tube MN3. The drain of the PMOS tube MP4 and the other end of the resistor R1 and the drain of the NMOS tube MN3 are connected to the node A and serve as the output terminal of the error amplifier. The source of the NMOS tube MN1, the source of the NMOS tube MN2 and the source of the NMOS tube MN3 are grounded.

[0006] Furthermore, the current bias circuit includes a PMOS tube MP5, a resistor R3, an NMOS tube MN5, an NMOS tube MN4 and a resistor R2, the source of the PMOS tube MP5 is connected to the power supply VIN, the gate of the PMOS tube MP5 is connected to the drain of the PMOS tube MP5 and one end of the resistor R3 and serves as the output end of the current bias circuit, the other end of the resistor R3 is connected to the drain of the NMOS tube MN5, the gate of the NMOS tube MN5 is connected to the power supply VDDPRE, the source of the NMOS tube MN5 is connected to the drain of the NMOS tube MN4, the gate of the NMOS tube MN4 serves as the input end of the current bias circuit, the source of the NMOS tube MN4 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0007] Furthermore, the current sampling circuit includes a PMOS tube MP6, the source of the PMOS tube MP6 is connected to the power supply VIN, the gate of the PMOS tube MP6 serves as the input end of the current sampling circuit, and the drain of the PMOS tube MP6 serves as the output end of the current sampling circuit and generates a sampling current ISNS.

[0008] Furthermore, the voltage sampling circuit includes a transistor Q1, a transistor Q2, a resistor R4 and a resistor R5, the emitter of the transistor Q1 serves as a first input end of the voltage sampling circuit, the emitter of the transistor Q2 serves as a second input end of the voltage sampling circuit, the base of the transistor Q1 is connected to the base of the transistor Q2, the collector of the transistor Q2 and one end of the resistor R5, the collector of the transistor Q1 is connected to one end of the resistor R4 and serves as an output end of the voltage sampling circuit to generate a sampling voltage VSNS, and the other end of the resistor R4 and the other end of the resistor R5 are grounded.

[0009] Furthermore, the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, and the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP5 is k2.

[0010] Further, the current limiting circuit comprises a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a capacitor C1, a resistor R8, a resistor R9, a resistor R10, a triode Q3 and a triode Q4, a source of the PMOS tube MP8 is connected to a power supply VDDPRE, a gate of the PMOS tube MP8 is connected to a bias voltage Vbias, a drain of the PMOS tube MP8 is connected to a source of the PMOS tube MP9 and a source of the PMOS tube MP10, a gate of the PMOS tube MP9 serves as a first input terminal of the current limiting circuit and is connected to a reference voltage VREF2, a gate of the PMOS tube MP10 serves as a second input terminal of the current limiting circuit and is connected to a sampling voltage VSNS, a drain of the PMOS tube MP9 is connected to the NMOS tube MP9, and a gate of the PMOS tube MP10 serves as a second input terminal of the current limiting circuit and is connected to a sampling voltage VSNS. The drain of the OS transistor MN6, the gate of the NMOS transistor MN6 and the gate of the NMOS transistor MN7 are connected, the drain of the PMOS transistor MP10 and the drain of the NMOS transistor MN7, one end of the capacitor C1, the collector of the transistor Q4 and the gate of the PMOS transistor MP11 are connected to the node B, the source of the PMOS transistor MP11 serves as the output end of the current limiting circuit, the base of the transistor Q4 is connected to one end of the resistor R9 and one end of the resistor R10, the other end of the resistor R9 and the emitter of the transistor Q3 are connected to the node C, the base of the transistor Q3 is connected to the reference source VBG with a zero temperature coefficient, the collector of the transistor Q3 is connected to the source of the NMOS transistor MN8, the gate of the NMOS transistor MN8 is connected to the power supply VDDPRE, the drain of the NMOS transistor MN8 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the power supply VIN.

[0011] A control method for an LDO circuit with an over-temperature and overload protection function comprises the following steps: When the circuit runs stably, the current flowing through the PMOS tube MP6 is the sampling current ISNS. Since the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, the output current IOUT flowing through the PMOS tube MP7 is k1*ISNS; the current flowing through the resistor R4 is the sampling current ISNS, and the sampling voltage VSNS is ISNS*R4; since the current limiting circuit, current bias circuit, current sampling circuit, and voltage sampling circuit constitute a current closed-loop control, VSNS=VREF2, and IOUT=k1*ISNS=k1*VSNS / R4= k1* VREF2 / R4; When the circuit starts, when the output current IOUT flowing through the PMOS tube MP7 gradually reaches k1* VREF2 / R4, the voltage of node B gradually decreases, and the voltage of node A also gradually decreases. Since the voltage of node A controls the current flowing through the NMOS tube MN4, it controls the current of the PMOS tube MP7. When the temperature gradually increases, the voltage at node C gradually increases, and the voltage at node D also gradually increases. At this time, the voltage at node B will further decrease, and thus the voltage at node A will further decrease. If the temperature continues to rise, the voltage at node A will be clamped at a value close to the gate-source voltage VGS4 of the NMOS tube MN4; the minimum value of the voltage at node A is approximately equal to the gate-source voltage VGS11 of the PMOS tube MP11, and the minimum value of the output current of the LDO circuit is clamped at k2*(VGS11-VGS4) / R2, making k2*(VGS11-VGS4) / R2 greater than the static current of the DCDC chip itself.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an LDO circuit with over-temperature and overload protection function and a control method thereof, the output current of the LDO is controlled by detecting the output current and the temperature, and the power of the LDO is limited by limiting the output current when the output is soft short-circuited, thereby reducing the heat generation of the chip; if the chip temperature continues to rise, the value of the output current will be gradually reduced; when the set temperature threshold is reached, the LDO output current is further limited, thereby reducing the temperature rise of the chip and protecting the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of an LDO circuit with over-temperature and overload protection function of the present invention. DETAILED DESCRIPTION

[0014] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0015] like Figure 1 As shown, an LDO circuit with over-temperature and overload protection function of the present invention comprises an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit and a current limiting circuit. The LDO circuit comprises a PMOS tube MP7, a resistor R6, a resistor R7 and a capacitor COUT. The source of the PMOS tube MP7 is connected to a power supply VIN, the gate of the PMOS tube MP7 is connected to the output end of the current bias circuit and the input end of the current sampling circuit, the drain of the PMOS tube MP7 is connected to one end of the resistor R6, one end of the capacitor COUT and the second input end of the voltage sampling circuit, the other end of the resistor R6 is connected to the gate of the resistor R7, and the drain of the PMOS tube MP7 is connected to one end of the resistor R6, one end of the capacitor COUT and the second input end of the voltage sampling circuit. One end is connected to and generates a feedback voltage FB, the first input end of the error amplifier is connected to the feedback voltage FB, the second input end of the error amplifier is connected to the reference voltage VREF1, the output end of the error amplifier is connected to the input end of the current bias circuit and the output end of the current limiting circuit, the output end of the current sampling circuit is connected to the input end of the voltage sampling circuit and generates a sampling current ISNS, the output end of the voltage sampling circuit generates a sampling voltage VSNS, the first input end of the current limiting circuit is connected to the reference voltage VREF2, the second input end of the current limiting circuit is connected to the sampling voltage VSNS, and the third input end of the current limiting circuit is connected to a reference source VBG with a zero temperature coefficient.

[0016] The error amplifier includes a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3 and a resistor R1. The source of the PMOS tube MP1 and the source of the PMOS tube MP4 are connected to a power supply VDDPRE, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP4 are connected to a bias voltage Vbias, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2 and the source of the PMOS tube MP3, the gate of the PMOS tube MP2 is used as the first input terminal of the error amplifier and is connected to a feedback voltage FB, and the PMOS The gate of the S transistor MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN1 and the gate of the NMOS transistor MN1; the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN2, one end of the resistor R1 and the gate of the NMOS transistor MN3; the drain of the PMOS transistor MP4, the other end of the resistor R1 and the drain of the NMOS transistor MN3 are connected to the node A and serve as the output terminal of the error amplifier; the source of the NMOS transistor MN1, the source of the NMOS transistor MN2 and the source of the NMOS transistor MN3 are grounded.

[0017] The function of the resistor R1 is to clamp the voltage of the node A of the gate of the NMOS transistor MN4 through the NMOS transistor MN2 when the LDO circuit is started, thereby achieving the purpose of limiting the startup output current and eliminating the startup circuit. At the same time, the resistor R1 is equivalent to reducing the AC impedance of the node A, so that the main pole of the LDO circuit is at the output position of the LDO circuit, and the system is easier to compensate.

[0018] The current bias circuit includes a PMOS tube MP5, a resistor R3, an NMOS tube MN5, an NMOS tube MN4 and a resistor R2. The source of the PMOS tube MP5 is connected to a power source VIN, the gate of the PMOS tube MP5 is connected to a drain of the PMOS tube MP5 and one end of the resistor R3 and serves as an output end of the current bias circuit, the other end of the resistor R3 is connected to a drain of the NMOS tube MN5, the gate of the NMOS tube MN5 is connected to a power source VDDPRE, the source of the NMOS tube MN5 is connected to a drain of the NMOS tube MN4, the gate of the NMOS tube MN4 serves as an input end of the current bias circuit, the source of the NMOS tube MN4 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0019] The current sampling circuit includes a PMOS tube MP6, the source of the PMOS tube MP6 is connected to the power supply VIN, the gate of the PMOS tube MP6 serves as the input end of the current sampling circuit, and the drain of the PMOS tube MP6 serves as the output end of the current sampling circuit and generates a sampling current ISNS.

[0020] The voltage sampling circuit includes a transistor Q1, a transistor Q2, a resistor R4 and a resistor R5. The emitter of the transistor Q1 serves as a first input end of the voltage sampling circuit, the emitter of the transistor Q2 serves as a second input end of the voltage sampling circuit, the base of the transistor Q1 is connected to the base of the transistor Q2, the collector of the transistor Q2 and one end of the resistor R5, the collector of the transistor Q1 is connected to one end of the resistor R4 and serves as an output end of the voltage sampling circuit to generate a sampling voltage VSNS, and the other end of the resistor R4 and the other end of the resistor R5 are grounded.

[0021] The PMOS tube MP5, the PMOS tube MP6 and the PMOS tube MP7 form a current mirror circuit. Among them, the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, and the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP5 is k2. The PMOS tube MP5, the PMOS tube MP6 and the PMOS tube MP7 and the NMOS tube MN5 and the NMOS tube MN8 are all high-voltage MOS tubes with source-drain high-voltage resistance.

[0022] The current limiting circuit includes a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a capacitor C1, a resistor R8, a resistor R9, a resistor R10, a triode Q3 and a triode Q4, a source of the PMOS tube MP8 is connected to a power supply VDDPRE, a gate of the PMOS tube MP8 is connected to a bias voltage Vbias, a drain of the PMOS tube MP8 is connected to a source of the PMOS tube MP9 and a source of the PMOS tube MP10, a gate of the PMOS tube MP9 is used as a first input terminal of the current limiting circuit and is connected to a reference voltage VREF2, a gate of the PMOS tube MP10 is used as a second input terminal of the current limiting circuit and is connected to a sampling voltage VSNS, a drain of the PMOS tube MP9 is connected to a source of the NMOS tube MP9, and a drain of the PMOS tube MP9 is connected to a source of the NMOS tube MP10. The drain of MN6, the gate of NMOS tube MN6 and the gate of NMOS tube MN7 are connected, the drain of PMOS tube MP10 and the drain of NMOS tube MN7, one end of capacitor C1, the collector of transistor Q4 and the gate of PMOS tube MP11 are connected to node B, the source of PMOS tube MP11 serves as the output end of the current limiting circuit, the base of transistor Q4 is connected to one end of resistor R9 and one end of resistor R10, the other end of resistor R9 and the emitter of transistor Q3 are connected to node C, the base of transistor Q3 is connected to a reference source VBG with a zero temperature coefficient, the collector of transistor Q3 is connected to the source of NMOS tube MN8, the gate of NMOS tube MN8 is connected to the power supply VDDPRE, the drain of NMOS tube MN8 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the power supply VIN.

[0023] Wherein, capacitor C1 is the compensation capacitor of the current limiting circuit.

[0024] A control method for an LDO circuit with an over-temperature and overload protection function comprises the following steps: When the circuit runs stably, the current flowing through the PMOS tube MP6 is the sampling current ISNS. Since the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, the output current IOUT flowing through the PMOS tube MP7 is k1*ISNS; the current flowing through the resistor R4 is the sampling current ISNS, and the sampling voltage VSNS is ISNS*R4; since the current limiting circuit, current bias circuit, current sampling circuit, and voltage sampling circuit constitute a current closed-loop control, VSNS=VREF2, and IOUT=k1*ISNS=k1*VSNS / R4= k1* VREF2 / R4.

[0025] When the circuit starts, when the output current IOUT flowing through the PMOS tube MP7 gradually reaches k1* VREF2 / R4, the voltage of node B gradually decreases, and the voltage of node A also gradually decreases. Since the voltage of node A controls the current flowing through the NMOS tube MN4, it controls the current of the PMOS tube MP7.

[0026] When the temperature gradually increases, the voltage at the node C gradually increases, and the voltage at the node D also gradually increases. At this time, the voltage at the node B will further decrease, and thus the voltage at the node A will further decrease.

[0027] If the temperature continues to rise, the voltage at node A will be clamped at a value close to the gate-source voltage VGS4 of the NMOS tube MN4; the minimum value of the voltage at node A is approximately equal to the gate-source voltage VGS11 of the PMOS tube MP11, and the minimum value of the output current of the LDO circuit is clamped at k2*(VGS11-VGS4) / R2, making k2*(VGS11-VGS4) / R2 greater than the static current of the DCDC chip itself.

[0028] The present invention provides an LDO circuit with over-temperature and overload protection function and a control method thereof. The output current of the LDO is controlled by detecting the output current and the temperature. When the output is soft short-circuited, the power of the LDO is limited by limiting the output current, thereby reducing the heat generation of the chip. If the chip temperature continues to rise, the value of the output current will be gradually reduced. When the set temperature threshold is reached, the LDO output current is further limited, thereby reducing the temperature rise of the chip and protecting the chip.

[0029] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. An LDO circuit with over-temperature and overload protection function, characterized in that: The invention comprises an error amplifier, a current bias circuit, a current sampling circuit, a voltage sampling circuit, an LDO circuit and a current limiting circuit. The LDO circuit comprises a PMOS tube MP7, a resistor R6, a resistor R7 and a capacitor COUT. The source of the PMOS tube MP7 is connected to a power supply VIN, the gate of the PMOS tube MP7 is connected to the output end of the current bias circuit and the input end of the current sampling circuit, the drain of the PMOS tube MP7 is connected to one end of the resistor R6, one end of the capacitor COUT and the second input end of the voltage sampling circuit, the other end of the resistor R6 is connected to one end of the resistor R7 and generates a feedback voltage FB, the first input end of the error amplifier is connected to the feedback voltage FB, the second input end of the error amplifier is connected to a reference voltage VREF1, the output end of the error amplifier is connected to the input end of the current bias circuit and the output end of the current limiting circuit, the output end of the current sampling circuit is connected to the input end of the voltage sampling circuit and generates a sampling current ISNS, the output end of the voltage sampling circuit generates a sampling voltage VSNS, the first input end of the current limiting circuit is connected to the reference voltage VREF2, the second input end of the current limiting circuit is connected to the sampling voltage VSNS, and the third input end of the current limiting circuit is connected to a reference source VBG with a zero temperature coefficient.

2. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The error amplifier comprises a PMOS tube MP1, a PMOS tube MP2, a PMOS tube MP3, a PMOS tube MP4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3 and a resistor R1, the source of the PMOS tube MP1 and the source of the PMOS tube MP4 are connected to a power supply VDDPRE, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP4 are connected to a bias voltage Vbias, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2 and the source of the PMOS tube MP3, the gate of the PMOS tube MP2 serves as the first input terminal of the error amplifier and is connected to a feedback voltage FB, The gate of the OS transistor MP3 serves as the second input terminal of the error amplifier and is connected to the reference voltage VREF1; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN1 and the gate of the NMOS transistor MN1; the drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN2, the gate of the NMOS transistor MN2, one end of the resistor R1 and the gate of the NMOS transistor MN3; the drain of the PMOS transistor MP4 and the other end of the resistor R1 and the drain of the NMOS transistor MN3 are connected to the node A and serve as the output terminal of the error amplifier; the source of the NMOS transistor MN1, the source of the NMOS transistor MN2 and the source of the NMOS transistor MN3 are grounded.

3. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The current bias circuit comprises a PMOS tube MP5, a resistor R3, an NMOS tube MN5, an NMOS tube MN4 and a resistor R2, the source of the PMOS tube MP5 is connected to a power source VIN, the gate of the PMOS tube MP5 is connected to a drain of the PMOS tube MP5 and one end of the resistor R3 and serves as an output end of the current bias circuit, the other end of the resistor R3 is connected to a drain of the NMOS tube MN5, the gate of the NMOS tube MN5 is connected to a power source VDDPRE, the source of the NMOS tube MN5 is connected to a drain of the NMOS tube MN4, the gate of the NMOS tube MN4 serves as an input end of the current bias circuit, the source of the NMOS tube MN4 is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

4. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The current sampling circuit includes a PMOS tube MP6, the source of the PMOS tube MP6 is connected to the power supply VIN, the gate of the PMOS tube MP6 serves as the input end of the current sampling circuit, and the drain of the PMOS tube MP6 serves as the output end of the current sampling circuit and generates a sampling current ISNS.

5. The LDO circuit with over-temperature and overload protection function according to claim 4, characterized in that: The voltage sampling circuit includes a transistor Q1, a transistor Q2, a resistor R4 and a resistor R5. The emitter of the transistor Q1 serves as a first input end of the voltage sampling circuit, the emitter of the transistor Q2 serves as a second input end of the voltage sampling circuit, the base of the transistor Q1 is connected to the base of the transistor Q2, the collector of the transistor Q2 and one end of the resistor R5, the collector of the transistor Q1 is connected to one end of the resistor R4 and serves as an output end of the voltage sampling circuit to generate a sampling voltage VSNS, and the other end of the resistor R4 and the other end of the resistor R5 are grounded.

6. The LDO circuit with over-temperature and overload protection function according to claim 5, characterized in that: The width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, and the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP5 is k2.

7. The LDO circuit with over-temperature and overload protection function according to claim 1, characterized in that: The current limiting circuit comprises a PMOS tube MP8, a PMOS tube MP9, a PMOS tube MP10, a PMOS tube MP11, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, a capacitor C1, a resistor R8, a resistor R9, a resistor R10, a triode Q3 and a triode Q4, a source of the PMOS tube MP8 is connected to a power supply VDDPRE, a gate of the PMOS tube MP8 is connected to a bias voltage Vbias, a drain of the PMOS tube MP8 is connected to a source of the PMOS tube MP9 and a source of the PMOS tube MP10, a gate of the PMOS tube MP9 is used as a first input terminal of the current limiting circuit and is connected to a reference voltage VREF2, a gate of the PMOS tube MP10 is used as a second input terminal of the current limiting circuit and is connected to a sampling voltage VSNS, a drain of the PMOS tube MP9 is connected to a NMOS The drain of transistor MN6, the gate of NMOS transistor MN6 and the gate of NMOS transistor MN7 are connected, the drain of PMOS transistor MP10 and the drain of NMOS transistor MN7, one end of capacitor C1, the collector of transistor Q4 and the gate of PMOS transistor MP11 are connected to node B, the source of PMOS transistor MP11 serves as the output end of the current limiting circuit, the base of transistor Q4 is connected to one end of resistor R9 and one end of resistor R10, the other end of resistor R9 and the emitter of transistor Q3 are connected to node C, the base of transistor Q3 is connected to a reference source VBG with a zero temperature coefficient, the collector of transistor Q3 is connected to the source of NMOS transistor MN8, the gate of NMOS transistor MN8 is connected to the power supply VDDPRE, the drain of NMOS transistor MN8 is connected to one end of resistor R8, and the other end of resistor R8 is connected to the power supply VIN.

8. A control method for an LDO circuit with over-temperature and overload protection function according to any one of claims 1 to 7, characterized in that The following steps are involved: When the circuit runs stably, the current flowing through the PMOS tube MP6 is the sampling current ISNS. Since the width-to-length ratio of the PMOS tube MP7 and the PMOS tube MP6 is k1, the output current IOUT flowing through the PMOS tube MP7 is k1*ISNS; the current flowing through the resistor R4 is the sampling current ISNS, and the sampling voltage VSNS is ISNS*R4; since the current limiting circuit, current bias circuit, current sampling circuit, and voltage sampling circuit constitute a current closed-loop control, VSNS=VREF2, and IOUT=k1*ISNS=k1*VSNS / R4= k1*VREF2 / R4; When the circuit starts, when the output current IOUT flowing through the PMOS tube MP7 gradually reaches k1* VREF2 / R4, the voltage of node B gradually decreases, and the voltage of node A also gradually decreases. Since the voltage of node A controls the current flowing through the NMOS tube MN4, it controls the current of the PMOS tube MP7. When the temperature gradually increases, the voltage at node C gradually increases, and the voltage at node D also gradually increases. At this time, the voltage at node B will further decrease, and thus the voltage at node A will further decrease. If the temperature continues to rise, the voltage at node A will be clamped at a value close to the gate-source voltage VGS4 of the NMOS tube MN4; the minimum value of the voltage at node A is approximately equal to the gate-source voltage VGS11 of the PMOS tube MP11, and the minimum value of the output current of the LDO circuit is clamped at k2*(VGS11-VGS4) / R2, making k2*(VGS11-VGS4) / R2 greater than the static current of the DCDC chip itself.

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