NAND flash firmware adaptation system and method

Abstract

The invention provides a firmware adaptation system and method of NAND flash, a flash API (Application Program Interface) layer is used for responding to an increase operation, and a first flash driving module corresponding to first NAND flash is added in the flash API layer; the deleting module is also used for responding to the deleting operation and deleting the second flash driving module corresponding to the second NAND flash; the system can manage and adapt to different NAND flash based on one set of firmware control unit, when the NAND flash needs to be newly added, deleted or modified, only the corresponding flash driving module needs to be added, deleted or modified in the flash API layer, the iteration master control does not need to be updated after the NAND flash is updated each time, the number of the flash driving modules is reduced, and the system is simple and convenient to operate. And the compatibility and the maintenance convenience are improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a NAND flash firmware adaptation system and method. Background Art

[0002] In SSD (Solid State Disk) and other products that use NAND flash as storage media, with the rapid development of NAND flash, different NAND flashes have different programming methods, and different NAND flashes use slightly different NAND flash command sequences. Therefore, when designing a storage controller based on different models of NAND flash, it is necessary to adapt different programming methods and command sequences according to the changes in NAND flash. This results in the use of different NAND flashes in a product involving the replacement of the controller and the need to update related hardware. This method has poor compatibility and poor maintenance convenience. Summary of the invention

[0003] The object of the present invention is to provide a NAND flash firmware adaptation system and method to improve compatibility and convenience of maintenance.

[0004] The present invention provides a NAND flash firmware adaptation system, which includes a firmware control unit and at least one NAND flash connected to the firmware control unit. The firmware control unit is provided with a flash API layer; the flash API layer includes flash driver modules corresponding to each NAND flash respectively; the flash API layer is used to respond to an add operation of adding a first NAND flash and add a first flash driver module corresponding to the first NAND flash in the flash API layer; the flash API layer is used to respond to a delete operation of deleting a second NAND flash and delete a second flash driver module corresponding to the second NAND flash in the flash API layer; the flash API layer is used to respond to a modify operation of modifying the third NAND flash and modify a third flash driver module corresponding to the third NAND flash in the flash API layer.

[0005] Furthermore, the firmware control unit also includes an FTL layer, and the FTL layer is connected to each flash driver module in the flash API layer.

[0006] Furthermore, the flash API layer has a public input interface; the FTL layer is connected to each flash driver module in the flash API layer through the public input interface.

[0007] Furthermore, the system also includes: a host, a main control interface module, a cache control module, an NFC, and a flash memory interface module that are communicatively connected in sequence, the cache control module is communicatively connected to the FTL layer through the front-end module, the flash memory interface module is connected to each NAND flash, and each flash driver module is also connected to the cache control module; the host is used to send a data processing request, and sends the data processing request to the FTL layer through the main control interface module, the cache control module and the front-end module; the FTL layer is used to map the physical address of the FTL layer according to the logical address of the host, map the physical address of the specified NAND flash according to the pre-configured mapping relationship between the physical address of the FTL layer and the physical address of the NAND flash, determine the specified flash driver module corresponding to the specified NAND flash according to the physical address of the specified NAND flash, and establish a communication connection with the specified flash driver module; generate first information based on the data processing request, and send the first information to the specified flash driver module; the specified flash driver module is used to generate first information based on the first information, the instructions for use of NFC and the specified NAND The instructions for use of the flash generate a target command sequence and send the target command sequence to the cache control module; the cache control module is used to enable the specified NAND flash to perform operations corresponding to the data processing request through the NFC and flash memory interface module based on the target command sequence.

[0008] Furthermore, the designated flash driver module is further used to obtain the execution result corresponding to the designated NAND flash execution data processing request, and return the execution result to the FTL layer.

[0009] Further, the designated flash driver module includes: an information acquisition submodule and a write operation submodule; the FTL layer is used to generate an operation sequence number according to the data write request if the received data processing request is a data write request, and send the operation sequence number to the information acquisition submodule; wherein the data write request carries the data to be written; the information acquisition submodule is used to output the second information according to the operation sequence number, and return the second information to the FTL layer; wherein the second information includes: page address information, Fine Program information and the amount of data that can be written to each word line; the FTL layer is used to generate the third information according to the second information, and send the third information to the write operation submodule; wherein the third information includes: the physical address of the FTL layer, the first data storage address, the amount of data to be written, the Fine Program information and the XLC operation information; the write operation submodule is used to generate the first command sequence based on the third information, the instructions for use of NFC, and the instructions for use of the designated NAND flash, and send the first command sequence to the cache control module; the cache control module is used to write the data to be written in the designated NAND flash through the NFC and the flash memory interface module based on the first command sequence.

[0010] Furthermore, the second information records the location information corresponding to the operation sequence number.

[0011] Furthermore, the designated flash driver module includes: an erase operation submodule; the FTL layer is used to generate a data erase instruction if a data write request is received, generate fourth information according to the data erase instruction, and send the fourth information to the erase operation submodule; wherein the fourth information includes: a physical address of the FTL layer, the number of storage blocks to be erased, and XLC operation information; the erase operation submodule is used to generate a second command sequence based on the fourth information, NFC usage instructions, and designated NAND flash usage instructions, and send the second command sequence to the cache control module; the cache control module is used to erase the data requested to be erased by the data erase instruction in the designated NAND flash through NFC and the flash memory interface module based on the second command sequence.

[0012] Further, the flash driver module is specified to include: a read operation submodule; the FTL layer is used to generate fifth information according to the data read request if the received data processing request is a data read request, and send the fifth information to the read operation submodule; wherein the fifth information includes: a physical address of the FTL layer, a second data storage address, a data amount of the data to be read, and XLC operation information;

[0013] The read operation submodule is used to generate a third command sequence based on the fifth information, the instructions for use of NFC, and the instructions for use of the specified NAND flash, and send the third command sequence to the cache control module;

[0014] The cache control module is used to read the data requested by the data read request from the specified NAND flash through the NFC and flash memory interface module based on the third command sequence.

[0015] The present invention provides a NAND flash firmware adaptation method, wherein a flash API layer is provided in a firmware control unit; the flash API layer includes flash driver modules corresponding to each NAND flash respectively; the method comprises: in response to an adding operation of adding a first NAND flash, the flash API layer adds a first flash driver module corresponding to the first NAND flash in the flash API layer; in response to a deleting operation of deleting a second NAND flash, the flash API layer deletes a second flash driver module corresponding to the second NAND flash in the flash API layer; in response to a modifying operation of modifying a third NAND flash, the flash API layer modifies a third flash driver module corresponding to the third NAND flash in the flash API layer.

[0016] The present invention provides a firmware adaptation system and method for NAND flash. The system includes a firmware control unit and at least one NAND flash connected to the firmware control unit. The firmware control unit is provided with a flash API layer. The flash API layer includes flash driver modules corresponding to each NAND flash. The flash API layer is used to respond to an add operation of adding a first NAND flash and add a first flash driver module corresponding to the first NAND flash in the flash API layer. The flash API layer is used to respond to a delete operation of deleting a second NAND flash and delete a second flash driver module corresponding to the second NAND flash in the flash API layer. The flash API layer is used to respond to a modify operation of modifying a third NAND flash and modify a third flash driver module corresponding to the third NAND flash in the flash API layer. The system can manage and adapt different NAND flashes based on a set of firmware control units. When it is necessary to add, delete or modify a NAND flash, it is only necessary to add, delete or modify the corresponding flash driver module in the flash API layer. It is not necessary to update the iterative master control every time the NAND flash is updated, thereby improving compatibility and convenience of maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of a NAND flash firmware adaptation system provided by an embodiment of the present invention;

[0019] Figure 2 A schematic diagram of a NAND flash firmware adaptation system provided by an embodiment of the present invention;

[0020] Figure 3 A schematic diagram of the structure of a flash driver module provided by an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of data interaction provided by an embodiment of the present invention;

[0022] Figure 5A schematic diagram of another data interaction provided by an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the interaction between an FTL layer and a flash API layer provided in an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of another data interaction provided by an embodiment of the present invention;

[0025] Figure 8 A schematic diagram of another data interaction provided by an embodiment of the present invention;

[0026] Fig. 9 A schematic diagram of another data interaction provided by an embodiment of the present invention;

[0027] Fig.10 A schematic diagram of another data interaction provided by an embodiment of the present invention;

[0028] Fig.11 A flowchart of a NAND flash firmware adaptation method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] In SSD and other products using NAND flash as storage medium, with the rapid development of NAND flash, different NAND flashes have different programming methods. The current XLC compiler usually adopts one pass (one-time compilation) programming or two pass (twice compilation) programming during the compilation process; different NAND flash blocks have mixed SLC (Single-Level Cell), MLC (Multi-Level Cell), and QLC (Quad-Level Cell); and the NAND flash command sequences used by different NAND flashes are slightly different. Therefore, when designing a storage master controller based on different models of NAND flash, it is necessary to adapt different programming methods and command sequences according to the changes of NAND flash, which results in that in a product, the use of different NAND flashes will involve the replacement of the master controller and the need to update related hardware. This method has poor compatibility and poor maintenance convenience. Based on this, an embodiment of the present invention provides a firmware adaptation system and method for NAND flash, which can be applied to application scenarios that require adaptation of multiple NAND flashes.

[0031] To facilitate understanding of this embodiment, firstly, a NAND flash firmware adaptation system disclosed in an embodiment of the present invention is introduced. Figure 1As shown, the system includes a firmware control unit and at least one NAND flash connected to the firmware control unit. The firmware control unit is provided with a flash API (Application Programming Interface) layer; the flash API layer includes flash driver modules corresponding to each NAND flash; NAND flash is a type of flash memory, which has the advantages of large capacity and fast rewrite speed, and is suitable for storing a large amount of data; the flash API layer can be understood as a flash operation interface layer; the flash driver module can be represented by flash DRV, for example, when it is necessary to read and write NAND flash, a corresponding flash driver module is required to connect the upper layer and the bottom layer. In actual implementation, one NAND flash can be set according to the design requirements of the main control, or multiple different NAND flashes can be set; each NAND flash has its own corresponding flash driver module, and each flash driver module is included in the flash API layer. It should be noted that the firmware control unit described above connected to at least one NAND flash corresponds to a physical connection. In actual applications, when the firmware control unit is running, only one NAND flash will be selected to run, and other NAND flashes will not run.

[0032] The flash API layer is used to respond to an add operation of adding a first NAND flash, and add a first flash driver module corresponding to the first NAND flash in the flash API layer; during the maintenance and management process, if a new first NAND flash is to be added, a code corresponding to the first NAND flash can be added in the flash API layer, and the flash API layer responds to the add operation, and can add the first flash driver module corresponding to the first NAND flash in the flash API layer.

[0033] The flash API layer is used for responding to a deletion operation of deleting the second NAND flash, and deleting the second flash driver module corresponding to the second NAND flash in the flash API layer; in the maintenance and management process, if the existing second NAND flash is to be deleted, the code corresponding to the second NAND flash in the flash API layer can be deleted, and the flash API layer responds to the deletion operation, and the second flash driver module corresponding to the second NAND flash can be deleted in the flash API layer.

[0034] The flash API layer is used to respond to the modification operation of modifying the third NAND flash, and modify the third flash driver module corresponding to the third NAND flash in the flash API layer. In the maintenance and management process, if the existing third NAND flash needs to be modified, the code corresponding to the third NAND flash in the flash API layer can be modified, and the flash API layer responds to the modification operation, and the third flash driver module corresponding to the third NAND flash can be modified in the flash API layer.

[0035] The firmware adaptation system of the NAND flash can manage and adapt different NAND flashes based on a set of firmware control units. When it is necessary to add, delete or modify the NAND flash, it is only necessary to add, delete or modify the corresponding flash driver module in the flash API layer. It is not necessary to update the iterative main control every time the NAND flash is updated, thereby improving compatibility and convenience of maintenance.

[0036] Furthermore, the firmware control unit also includes an FTL (Flash Translation Layer) layer, and the FTL layer is connected to each flash driver module in the flash API layer. The above FTL layer can be used to complete the mapping of the host HOST logical address space to the flash physical address space; the FTL layer is connected to each flash driver module in the flash API layer, and the connection described here represents a physical connection. In actual applications, since only one NAND flash will be selected to run when the firmware control unit is running, accordingly, the FTL layer will only establish communication with one flash driver module, and will not establish communication with other flash driver modules.

[0037] Furthermore, the flash API layer has a public input interface; the FTL layer is connected to each flash driver module in the flash API layer through the public input interface.

[0038] The above-mentioned public input interface can be understood as a public external operation interface of the flash API layer. In this embodiment, the FTL layer can call the flash API layer through the public input interface, and can call different flash driver modules according to different NAND flashes. In this way, calling the upper layer only needs to call the public input interface to uniformly manage different NAND flashes, thereby improving the efficiency and convenience of maintenance and management.

[0039] Furthermore, the system also includes: a host, a main control interface module, a cache control module, an NFC (NAND Flash Controller), and a flash memory interface module that are sequentially connected in communication, the cache control module is connected in communication with the FTL layer through the front-end module, the flash memory interface module is connected to each NAND flash, and each flash driver module is also connected to the cache control module; Figure 2 The schematic diagram of a firmware adaptation system for NAND flash is shown in the figure. The host HOST can be any computer connected to the internet, etc.; the main control interface module can also be called a high-speed storage main control interface module, which is mainly responsible for communication and data transmission with the host; the cache control module can also be called an adjustable cache and control module, which is mainly responsible for managing and optimizing the process of data storage and reading, and improving the overall storage performance by adaptively configuring and optimizing the cache and processing architecture; the NFC is mainly used to manage and control the data read and write operations of the NAND flash storage device. The flash memory interface module is mainly responsible for communicating and exchanging data with the NAND flash. The flash memory interface module usually interacts directly with the NAND flash to realize data reading and writing, etc. The front-end module can be represented by FE (Front End), which is mainly responsible for communicating with the host HOST and realizing various protocols, etc. It should be noted that the flash memory interface module is connected to each NAND flash, and the connection here represents a physical connection. In actual applications, when the firmware control unit is running, only one NAND flash will be selected to run, and other NAND flashes will not run, that is, the flash memory interface module will only establish communication with one NAND flash, and will not establish communication with other NAND flashes. Another public connection interface may be provided for the flash API layer, and each flash driver module is connected to the cache control module via the public connection interface.

[0040] The host is used to send data processing requests, and sends the data processing requests to the FTL layer through the main control interface module, the cache control module and the front-end module; the data processing request can be a data write request, etc.; in actual implementation, the user can send the above data processing request through the host, and send the data processing request to the FTL layer through the main control interface module, the cache control module and the front-end module in turn.

[0041] The FTL layer is used to map the physical address of the FTL layer according to the logical address of the host, map the physical address of the specified NAND flash according to the pre-configured mapping relationship between the physical address of the FTL layer and the physical address of the NAND flash, determine the specified flash driver module corresponding to the specified NAND flash according to the physical address of the specified NAND flash, and establish a communication connection with the specified flash driver module; generate first information based on the data processing request, and send the first information to the specified flash driver module;

[0042] In actual implementation, the FTL layer records the mapping relationship between the logical address of the host and the physical address of the FTL layer. When the FTL layer receives a data processing request, it can map the physical address of the FTL layer according to the logical address of the host and the mapping relationship between the logical address of the host and the physical address of the FTL layer. The FTL layer obtains good blocks, but NAND flash has bad blocks. Therefore, there is also a mapping relationship between the physical address of the FTL layer and the physical address of the NAND flash. Therefore, the physical address of the specified NAND flash can be mapped according to the mapping relationship between the physical address of the FTL layer and the physical address of the NAND flash and the physical address of the FTL layer. Since the NAND flash and the flash driver module are one-to-one corresponding, the specified flash driver module corresponding to the specified NAND flash can be determined in the flash API layer, and the FTL layer can establish a communication connection with the specified flash driver module. After establishing the communication connection with the specified flash driver module, the FTL layer can generate first information according to the data processing request and send it to the specified flash driver module; usually, the first information corresponding to different data processing requests will be different.

[0043] The designated flash driver module is used to generate a target command sequence based on the first information, the NFC usage instructions and the designated NAND flash usage instructions, and send the target command sequence to the cache control module; the NFC usage instructions can be expressed as "NFC usage spec" to describe the usage of NFC; the designated NAND flash usage instructions can be expressed as "designated NAND flash usage spec" to describe the usage of the designated NAND flash; in actual applications, the assembly command sequence is a command sequence for constructing the identification of the NAND flash; there will be differences according to different operations and different NAND flashes.

[0044] For example, the read operation of Intel N38B QLC:

[0045] ① For single plane operation, the command sequence to be sent for the particle spec is Cmd(00h)+2byteColumn address+4byte Row address+Cmd(30h)+Cmd(70h)-ReadStatus+Cmd(06h)+2byteColumn address+Cmd(E0h)+DMA;

[0046] ② How to construct commands so that NFC can send commands / addresses needs to be determined based on the current NFC usage spec.

[0047] Cmd---refers to the command, and the command sequence refers to the command and timing of the operation that conforms to the usage spec of the specified NAND flash. This embodiment adopts the method of the firmware layer, and the flash API layer is a module in the firmware control unit. The flash API layer needs to operate the hardware NFC to interact with the specified NAND flash. Therefore, the flash API layer will combine the usage spec of NFC and the usage spec of the specified NAND flash, which is equivalent to a bridge. Specifically, the specified flash driver module in the flashAPI layer can generate a target command sequence based on the first information, the usage instructions of NFC and the usage instructions of the specified NAND flash.

[0048] The cache control module is used to enable the designated NAND flash to perform operations corresponding to the data processing request based on the target command sequence through the NFC and flash interface modules. The designated flash driver module can send the generated target command sequence to the cache control module. Since the target command sequence contains the instructions for using NFC and the instructions for using the designated NAND flash, NFC can recognize the target command sequence, and then enable the designated NAND flash to perform operations corresponding to the data processing request, such as write operations, read operations, etc., through the flash interface module.

[0049] The generation and assembly of the command sequence corresponding to each NAND flash is performed by the corresponding flash driver module. The array operation and non-array operation commands of different NAND flashes are constructed by the interface operation of the corresponding flash driver module in the flash API layer to conform to the command sequence of the corresponding NAND flash.

[0050] Furthermore, the designated flash driver module is also used to obtain the execution result corresponding to the designated NAND flash execution data processing request, and return the execution result to the FTL layer. In actual implementation, the designated flash driver module can also monitor the process of the designated NAND flash execution data processing request. After monitoring the execution result, the execution result can be obtained and returned to the FTL layer. For example, the execution result can be execution success or execution failure, etc. The execution result can be returned to the host through the FTL layer so that the user can understand the execution status in a timely manner.

[0051] Further, such as Figure 3 The schematic diagram of the structure of a flash driver module shown in FIG. mainly includes array operations of erase, write and read, and other operations such as Identify Operations, Feat Operations, etc. Figure 3 As shown, the designated flash driver module includes: an information acquisition submodule and a write operation submodule; the FTL layer is used to generate an operation sequence number according to the data write request if the received data processing request is a data write request, and send the operation sequence number to the information acquisition submodule; wherein the data write request carries the data to be written; the information acquisition submodule is used to output the second information according to the operation sequence number, and return the second information to the FTL layer; wherein the second information includes: page address information, FineProgram information and the amount of data that can be written to each word line; the above-mentioned page address information can be represented by "PageAddr", which can be understood as the page address information required for programming returned by the designated flash driver module; the Fine Program information can be represented by "FineProgram Tag", which is used to indicate whether it is a Fine Program. Usually, the particles of the Two-pass programming method call the first pass a coarse program and the second pass a fine program. program; the above-mentioned writable data volume of each word line can be understood as the writable data volume of each WL (WordLine) in the current operation; in actual implementation, if the user sends a data write request carrying data to be written through the host, the FTL layer can generate an operation sequence number order according to the data write request, and the operation sequence number order can be used to indicate the number of data write requests executed by the FTL layer; different data write requests correspond to different operation sequence numbers order; Figure 4 As shown in the schematic diagram of a data interaction, the FTL layer can send the operation sequence number order to the information acquisition submodule. The information acquisition submodule can return the second information such as page address information, Fine Program information and the amount of data that can be written to each word line to the FTL layer according to the operation sequence number.

[0052] The FTL layer is used to generate the third information according to the second information, and send the third information to the write operation submodule; wherein the third information includes: the physical address of the FTL layer, the first data storage address, the amount of data to be written, the FineProgram information and the XLC operation information; the first data storage address can be understood as the buf (buffer) address of the data, that is, the buf address of the prepared data storage; the XLC operation information is usually determined by the FTL layer, and there may be SLC operation and XLC operation in NAND flash. The XLC operation information here is used to indicate whether it is an XLC operation, and is used to distinguish whether the particle needs to be operated by SLC or XLC, wherein XLC is a synonym for MLC, TLC (Triple-Level Cell, three-layer unit storage), and QLC; such as Figure 5 In another data interaction diagram shown in FIG. 1 , the FTL layer can generate third information such as the physical address of the FTL layer, the first data storage address, the amount of data to be written, the Fine Program information, and the XLC operation information according to the received second information such as the page address information, the Fine Program information, and the amount of data that can be written to each word line, and send the generated third information to the write operation submodule. The physical address of the FTL layer usually includes the page address information; the amount of data to be written usually includes the amount of data that can be written to each word line.

[0053] The write operation submodule is used to generate a first command sequence based on the third information, the instructions for use of NFC, and the instructions for use of the specified NAND flash, and send the first command sequence to the cache control module; the cache control module is used to write the data to be written in the specified NAND flash through the NFC and flash interface module based on the first command sequence. In actual implementation, since the first command sequence combines the instructions for use of NFC and the instructions for use of the specified NAND flash, NFC can recognize the first command sequence, and then write the above-mentioned data to be written to the specified NAND flash through the flash interface module; it should be noted that the continuity of data must be guaranteed when a single command is executed.

[0054] Furthermore, the second information records the position information corresponding to the operation sequence number. By recording the position information corresponding to the operation sequence number at the end, it can be clearly indicated that the second information has been output.

[0055] For ease of understanding, take the program (write) operation as an example. Figure 6The diagram of the interaction between the FTL layer and the flash API layer is shown. When the FTL layer needs to send a write operation, the first step is to call the "information acquisition submodule" to obtain: ① page address information (corresponding to the above page address information); ② Fine Program information; ③ the amount of data that can be written to each WL in the current operation (corresponding to the amount of data that can be written to each word line in the above). The "information acquisition submodule" aims to establish a programming method relationship table corresponding to the NAND flash spec inside the flash driver module of each different NAND flash. The programming method relationship table contains the above three types of information. The FTL layer does not perceive the change of the current programming sequence. The end position of the programming can be recorded in the operation sequence number order. The second step is to call "program operation" and input: ① the buf address of the data, that is, the buf address where the prepared data is stored (corresponding to the above first data storage address); ② the physical address of the FTL layer, which will be converted into the physical address of the NAND flash by the flash API layer again; ③ the amount of data to be written; ④ Fine Program information, that is, whether it is a fine Program; ⑤ XLC operation information. After obtaining the execution result, the FTL layer can complete the program operation. When the FTL layer records the last programming location, it does not need to be aware of which page address is currently being written, and can record it in the order of the operation sequence number.

[0056] Further, the flash driver module is specified to include: an erase operation submodule; the FTL layer is used to generate a data erase instruction if a data write request is received, generate fourth information according to the data erase instruction, and send the fourth information to the erase operation submodule; wherein the fourth information includes: a physical address of the FTL layer, the number of storage blocks to be erased, and XLC operation information;

[0057] like Figure 7 As shown in the schematic diagram of another data interaction, the number of storage blocks to be erased can be expressed as "BlockCnt to be erased"; in actual implementation, if the user sends a data write request through the host, the FTL layer will usually determine whether there is data that needs to be erased. If so, a data erase instruction can be generated. The fourth information such as the physical address of the FTL layer, the number of storage blocks to be erased and the XLC operation information can be generated according to the data erase instruction and sent to the erase operation submodule.

[0058] The erase operation submodule is used to generate a second command sequence based on the fourth information, the instructions for use of NFC, and the instructions for use of the specified NAND flash, and send the second command sequence to the cache control module; the cache control module is used to erase the data requested to be erased by the data erase instruction in the specified NAND flash through the NFC and flash memory interface module based on the second command sequence.

[0059] In actual implementation, since the second command sequence combines the instructions for using NFC and the instructions for using the specified NAND flash, NFC can recognize the second command sequence, and then erase the data requested to be erased by the data erase instruction from the specified NAND flash through the flash memory interface module; it should be noted that the execution of a single command must ensure the continuity of the data.

[0060] Furthermore, the specified flash driver module includes: a read operation submodule; the FTL layer is used to generate fifth information according to the data read request if the received data processing request is a data read request, and send the fifth information to the read operation submodule; wherein the fifth information includes: the physical address of the FTL layer, the second data storage address, the data amount of the data to be read and the XLC operation information.

[0061] like Figure 8 As shown in the schematic diagram of another data interaction, the above-mentioned second data storage address can be understood as the buf address of data storage, that is, the buf address of data read from the array; in actual implementation, if the user sends a data read request through the host, the FTL layer can generate the fifth information such as the physical address of the FTL layer, the second data storage address, the amount of data to be read and the XLC operation information according to the data read request, and send it to the read operation submodule.

[0062] The read operation submodule is used to generate a third command sequence based on the fifth information, the instructions for use of NFC, and the instructions for use of the specified NAND flash, and send the third command sequence to the cache control module; the cache control module is used to read the data requested by the data read request from the specified NAND flash through the NFC and flash memory interface module based on the third command sequence. In actual implementation, since the third command sequence combines the instructions for use of NFC and the instructions for use of the specified NAND flash, NFC can recognize the third command sequence, and then read the data requested by the data read request from the specified NAND flash through the flash memory interface module; it should be noted that the continuity of the data must be guaranteed for a single command execution.

[0063] The above data processing request may also include other operations, such as Identify Operations, Feat Operations, etc. Here, Read Id and Set feat are taken as examples. Fig. 9 Another data interaction diagram is shown in FIG. 1 . In the Read Id operation, the input provided by the FTL layer is: ① lgLunIdx, where logical LunIdx refers to the logical numbering of all Luns on a disk; ② data is stored in the buf address, and the read id data is stored in the buf address. Fig.10 Another schematic diagram of data interaction is shown. In the Set feat operation, the input provided by the FTL layer is ①LgLunIdx, where logical LunIdx refers to the logical numbering of all Luns on a disk; ②feat option, which feat option to use.

[0064] The firmware adaptation system of the above-mentioned NAND flash adds a flash API layer in the firmware control unit, and uses the flash API layer to adapt the differences between different NAND flashes. The upper layer's perception of NAND flash is reduced, which guarantees the adaptability and compatibility of the code to a greater extent. Using code to manage and distinguish different NAND flashes is less costly than hardware management, and compared with the existing hardware module management, this solution has stronger variability and portability. In addition, after the system adds the flash API layer, the upper layer of the firmware has less perception of NAND flash when optimizing performance, reducing the restrictions on performance optimization. With this system, the master control can adapt to different NAND flashes more quickly and conveniently to the maximum extent under the supported NAND flash interface protocol, thereby improving the adaptability and compatibility of the master control.

[0065] The firmware adaptation system of the above-mentioned NAND flash can manage and adapt different NAND flashes with a set of firmware and master control. The firmware does not perceive changes in NAND flash, and the master control does not need to be updated and iterated every time a new NAND flash is added. Under the NAND flash interface protocol supported by the master control, it can be compatible with all changes in NAND flash characteristics (such as programming methods and block WL changes) to the greatest extent possible. When it is necessary to add / delete / modify NAND flash, it is only necessary to add / delete / modify the corresponding flash driver module, which has lower maintenance costs, stronger portability, and can achieve faster and more convenient management and maintenance. The system uses code to be compatible with the differences between different NAND flashes. The added flash API layer can maximize the guarantee of all particles adapted under the NAND flash interface protocol supported by the master control without affecting the use of the upper layer.

[0066] The embodiment of the present invention also provides a NAND flash firmware adaptation method, wherein a flash API layer is provided in the firmware control unit; the flash API layer includes a flash driver module corresponding to each NAND flash; Fig.11 As shown, the method comprises the following steps:

[0067] Step S1101, in response to an adding operation of adding a first NAND flash, the flash API layer adds a first flash driver module corresponding to the first NAND flash in the flash API layer;

[0068] Step S1102, in response to the deletion operation of deleting the second NAND flash, the flash API layer deletes the second flash driver module corresponding to the second NAND flash in the flash API layer;

[0069] Step S1103: the flash API layer modifies a third flash driver module corresponding to the third NAND flash in the flash API layer in response to the modification operation of modifying the third NAND flash.

[0070] The firmware adaptation method of the NAND flash can manage and adapt different NAND flashes based on a set of firmware control units. When it is necessary to add, delete or modify the NAND flash, it is only necessary to add, delete or modify the corresponding flash driver module in the flash API layer. It is not necessary to update the iterative master control every time the NAND flash is updated, thereby improving compatibility and convenience of maintenance.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A NAND flash firmware adaptation system, characterized in that: The system includes a firmware control unit and at least one NAND flash connected to the firmware control unit, wherein a flash API layer is provided in the firmware control unit; the flash API layer includes a flash driver module corresponding to each of the NAND flashes; The flash API layer is used to respond to an adding operation of adding a first NAND flash, and to add a first flash driver module corresponding to the first NAND flash in the flash API layer; The flash API layer is used to delete a second flash driver module corresponding to the second NAND flash in the flash API layer in response to a deletion operation of deleting the second NAND flash; The flash API layer is used to modify a third flash driver module corresponding to the third NAND flash in the flash API layer in response to a modification operation of modifying the third NAND flash.

2. The system according to claim 1, characterized in that The firmware control unit also includes an FTL layer, and the FTL layer is connected to each flash driver module in the flash API layer.

3. The system according to claim 2, characterized in that The flash API layer has a public input interface; The FTL layer is connected to each flash driver module in the flash API layer through the common input interface.

4. The system according to claim 2, characterized in that The system further comprises: a host, a main control interface module, a cache control module, an NFC, and a flash memory interface module which are sequentially connected in communication, wherein the cache control module is connected in communication with the FTL layer through the front-end module, the flash memory interface module is connected with each of the NAND flashes, and each of the flash driver modules is also connected with the cache control module; The host is used to send a data processing request, and sends the data processing request to the FTL layer through the main control interface module, the cache control module and the front-end module; The FTL layer is used to map the physical address of the FTL layer according to the logical address of the host, map the physical address of the specified NAND flash according to the pre-configured mapping relationship between the physical address of the FTL layer and the physical address of the NAND flash, determine the specified flash driver module corresponding to the specified NAND flash according to the physical address of the specified NAND flash, and establish a communication connection with the specified flash driver module; generate first information based on the data processing request, and send the first information to the specified flash driver module; The designated flash driver module is used to generate a target command sequence based on the first information, the NFC usage instructions and the designated NAND flash usage instructions, and send the target command sequence to the cache control module; The cache control module is used to enable the designated NAND flash to execute the operation corresponding to the data processing request through the NFC and the flash memory interface module based on the target command sequence.

5. The system according to claim 4, characterized in that The designated flash driver module is further used to obtain an execution result corresponding to the data processing request executed by the designated NAND flash, and return the execution result to the FTL layer.

6. The system according to claim 4, characterized in that The designated flash driver module includes: an information acquisition submodule and a write operation submodule; The FTL layer is used for generating an operation sequence number according to the data writing request if the received data processing request is a data writing request, and sending the operation sequence number to the information acquisition submodule; wherein the data writing request carries the data to be written; The information acquisition submodule is used to output second information according to the operation sequence number, and return the second information to the FTL layer; wherein the second information includes: page address information, Fine Program information and the amount of data that can be written to each word line; The FTL layer is used to generate third information according to the second information, and send the third information to the write operation submodule; wherein the third information includes: a physical address of the FTL layer, a first data storage address, a data amount of the data to be written, Fine Program information and XLC operation information; The write operation submodule is used to generate a first command sequence based on the third information, the NFC usage instructions, and the specified NAND flash usage instructions, and send the first command sequence to the cache control module; The cache control module is used to write the to-be-written data in the designated NAND flash through the NFC and the flash memory interface module based on the first command sequence.

7. The system according to claim 6, characterized in that The second information records the location information corresponding to the operation sequence number.

8. The system according to claim 6, characterized in that The designated flash driver module includes: an erase operation submodule; The FTL layer is used to generate a data erase instruction if the data write request is received, generate fourth information according to the data erase instruction, and send the fourth information to the erase operation submodule; wherein the fourth information includes: a physical address of the FTL layer, the number of storage blocks to be erased, and XLC operation information; The erase operation submodule is used to generate a second command sequence based on the fourth information, the usage instructions of the NFC, and the usage instructions of the specified NAND flash, and send the second command sequence to the cache control module; The cache control module is used to erase the data requested to be erased by the data erase instruction in the specified NAND flash through the NFC and the flash memory interface module based on the second command sequence.

9. The system according to claim 4, characterized in that The designated flash driver module includes: a read operation submodule; The FTL layer is used for generating fifth information according to the data read request if the received data processing request is a data read request, and sending the fifth information to the read operation submodule; wherein the fifth information includes: a physical address of the FTL layer, a second data storage address, a data amount of the data to be read, and XLC operation information; The read operation submodule is used to generate a third command sequence based on the fifth information, the NFC usage instructions, and the specified NAND flash usage instructions, and send the third command sequence to the cache control module; The cache control module is used to read the data requested by the data read request from the specified NAND flash through the NFC and the flash memory interface module based on the third command sequence.

10. A method for adapting firmware of NAND flash, characterized in that: A flash API layer is provided in the firmware control unit; The flash API layer includes a flash driver module corresponding to each NAND flash; the method includes: The flash API layer adds a first flash driver module corresponding to the first NAND flash in the flash API layer in response to an adding operation of adding the first NAND flash; The flash API layer deletes a second flash driver module corresponding to the second NAND flash in the flash API layer in response to a deletion operation of deleting the second NAND flash; The flash API layer modifies a third flash driver module corresponding to the third NAND flash in the flash API layer in response to a modification operation of modifying the third NAND flash.

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