DDR controller exception processing method and apparatus, and storage medium

Abstract

The application discloses a DDR controller exception processing method, which belongs to the technical field of DDR controllers and improves the stability and reliability of the DDR controller and reduces system crashes and data loss caused by abnormal conditions. Through dynamic adjustment strategy and error recovery mechanism, high data read-write efficiency and accuracy can be maintained under abnormal conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of DDR controller, and particularly relates to a DDR controller exception processing method. BACKGROUND

[0002] As the core component of embedded system storage management, DDR controller accurately regulates and controls the data flow between CPU and DDR SDRAM, ensuring efficient read and write of data and smooth operation of the system. However, in the actual complex operating environment, DDR controller will also face many challenges, such as read and write errors and timing mismatches caused by factors such as voltage fluctuations, signal interference and temperature changes. Once these problems occur, they will directly threaten the integrity of the stored data and the stability of the system operation. Especially in embedded systems with extremely high stability requirements, SDRAM as the core storage medium of programs and data, once encountering read and write errors, may trigger abnormal behavior of MCU, such as program runaway, system crash, etc., and further cause the collapse of the entire system. Therefore, building a comprehensive and efficient DDR controller exception processing flow is not only responsible for data security, but also an important guarantee for the stable operation of embedded systems. This flow should cover multiple links such as rapid diagnosis, intelligent decision and recovery, and log recording, to ensure that exceptions can be accurately captured and effectively processed at the first time of occurrence, thereby minimizing system failures and improving the reliability and user experience of the overall system. SUMMARY

[0003] In order to overcome the above technical deficiencies, the present application provides an exception processing method for improving the stability and reliability of DDR controller.

[0004] The technical scheme adopted by the present application to overcome the technical problems is:

[0005] A DDR controller exception processing method, comprising:

[0006] S1. The MCU is started, and the command read data is sent to the DDR controller according to the requirements;

[0007] S2. After the DDR controller receives the command read data sent by the MCU, the command read data is parsed and executed;

[0008] S3. The exception detection module detects whether the command read data received by the DDR controller from the MCU is abnormal, and if so, step S6 is executed, and if not, step S4 is executed;

[0009] S4. The DRAM receives the command read data parsed by the DDR controller;

[0010] S5. The anomaly detection module detects whether the DRAM receiving the command read data parsed by the DDR controller is abnormal, and if so, step S6 is executed, and if not, step S7 is executed;

[0011] S6. The anomaly detection module triggers a hardware interrupt, and after the interrupt signal is transmitted to the MCU, step S9 is executed;

[0012] S7. The DRAM returns the command read data to the DDR controller;

[0013] S8. The anomaly detection module detects whether the DRAM returning the command read data to the DDR controller is abnormal, and if so, step S6 is executed, and if not, the DDR controller returns the command read data to the MCU;

[0014] S9. After the MCU receives the interrupt signal, the address of the executed program is jumped, and the DDR controller exception handling program on the SRAM is transferred;

[0015] S10. After the MCU terminates the current DRAM data transmission, the reason for the occurrence of the exception is obtained from the register of the DDR controller, and it is judged whether it is a data transmission error, and if so, step S12 is executed, and if not, step S11 is executed;

[0016] S11. The MCU records the DDR controller error information to the SRAM, and then restarts the DDR controller;

[0017] S12. DRAM data verification is performed, read-write test is performed on the address where the error occurs, and it is judged whether the error is reproduced, and if so, step S11 is returned, and if not, step S13 is executed;

[0018] S13. The DDR controller error information is recorded, and the anomaly detection module notifies the MCU to resend the read command, and then returns to step S2.

[0019] Further, in step S1, the MCU sends the command read data to the DDR controller through the bus.

[0020] Further, in step S3, when the anomaly detection module detects that the DDR controller receiving the command sent by the MCU has a timeout error, it is determined to be abnormal.

[0021] Further, in step S5, when the anomaly detection module detects that the DRAM receiving the command read data parsed by the DDR controller has a timeout error, it is determined to be abnormal.

[0022] Further, in step S8, when the anomaly detection module detects that the DRAM returning the command read data to the DDR controller has a timeout error, it is determined to be abnormal.

[0023] Further, the DDR controller in step S11 restarts to recover the data of the DRAM from the external backup device.

[0024] In another aspect, the present application also relates to a DDR controller exception processing device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; wherein:

[0025] The memory is used for storing a computer program.

[0026] The processor is used for executing the following steps by running the program stored in the memory:

[0027] S1. The MCU starts and sends a command to read data to the DDR controller according to requirements;

[0028] S2. The DDR controller receives the command to read data sent by the MCU, parses and executes the command to read data;

[0029] S3. The exception detection module detects whether the command to read data received by the DDR controller from the MCU is abnormal, if yes, step S6 is executed, and if not, step S4 is executed;

[0030] S4. The DRAM receives the command to read data parsed by the DDR controller;

[0031] S5. The exception detection module detects whether the command to read data received by the DRAM from the DDR controller is abnormal, if yes, step S6 is executed, and if not, step S7 is executed;

[0032] S6. The exception detection module triggers a hardware interrupt, and after the interrupt signal is transmitted to the MCU, step S9 is executed;

[0033] S7. The DRAM returns the command to read data to the DDR controller;

[0034] S8. The exception detection module detects whether the command to read data returned by the DRAM to the DDR controller is abnormal, if yes, step S6 is executed, and if not, the DDR controller returns the command to read data to the MCU;

[0035] S9. The MCU jumps to the address of the program after receiving the interrupt signal, and is transferred to the SRAM to execute the DDR controller exception processing program;

[0036] S10. The MCU acquires the cause of the exception from the register of the DDR controller after terminating the current DRAM data transmission, and judges whether the cause is a data transmission error, if yes, step S12 is executed, and if not, step S11 is executed;

[0037] S11. The MCU records the DDR controller error information to the SRAM and restarts the DDR controller;

[0038] S12. The DRAM data is checked, the read-write test is performed on the error address, and it is judged whether the error is reproduced or not. If yes, the step S11 is returned to be executed, and if no, the step S13 is executed.

[0039] S13. The DDR controller error information is recorded, and the MCU is informed by the abnormality detection module to resend the read command and then the step S2 is returned to be executed.

[0040] On the other hand, the application also relates to a storage medium, and a computer program is stored on the computer readable storage medium, and the computer program is executed by a processor to realize:

[0041] S1. The MCU is started, and the command is sent to read data to the DDR controller according to the requirement;

[0042] S2. The DDR controller receives the command read data sent by the MCU, analyzes and executes the command read data;

[0043] S3. The abnormality detection module detects whether the DDR controller receives the command read data sent by the MCU is abnormal or not. If yes, the step S6 is executed, and if no, the step S4 is executed.

[0044] S4. The DRAM receives the command read data analyzed by the DDR controller;

[0045] S5. The abnormality detection module detects whether the DRAM receives the command read data analyzed by the DDR controller is abnormal or not. If yes, the step S6 is executed, and if no, the step S7 is executed.

[0046] S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is transmitted to the MCU, and then the step S9 is executed.

[0047] S7. The DRAM returns the command read data to the DDR controller;

[0048] S8. The abnormality detection module detects whether the DRAM returns the command read data to the DDR controller is abnormal or not. If yes, the step S6 is executed, and if no, the DDR controller returns the command read data to the MCU;

[0049] S9. The MCU receives the interrupt signal, jumps to the address of the executed program, and is transferred to the SRAM to execute the DDR controller abnormality processing program;

[0050] S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed.

[0051] S11. The MCU records the DDR controller error information in SRAM and restarts the DDR controller.

[0052] S12 performs DRAM data verification, performs read and write tests on the address where the error occurs, and determines whether the error recurs. If so, returns to step S11, if not, executes step S13;

[0053] S13. Record the DDR controller error information. The abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

[0054] The present invention improves the stability and reliability of the DDR controller and reduces system crashes and data loss caused by abnormal situations. Dynamically adjusting policies and error recovery mechanisms ensure high data read and write efficiency and accuracy even in abnormal situations. Detailed logging and reporting capabilities are provided to facilitate user understanding of the DDR controller's operating status and troubleshooting. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Flow chart of the method of the present invention. DETAILED DESCRIPTION

[0056] The following is combined with Figure 1 The present invention is further described.

[0057] Example 1

[0058] A DDR controller exception handling method, comprising:

[0059] S1. MCU starts and sends commands to read data to the DDR controller as required.

[0060] S2. After receiving the data read command from the MCU, the DDR controller parses and executes the command to read the data.

[0061] S3. The abnormality detection module detects whether the data read by the DDR controller after receiving the command sent by the MCU is abnormal. If so, step S6 is executed; otherwise, step S4 is executed.

[0062] S4. DRAM receives the command parsed by the DDR controller and reads the data.

[0063] S5. The anomaly detection module detects whether the command read data received by the DRAM is abnormal, and if so, step S6 is executed, and if not, step S7 is executed.

[0064] S6. The anomaly detection module triggers a hardware interrupt, and after passing the interrupt signal to the MCU, step S9 is executed.

[0065] S7. The DRAM returns the command read data to the DDR controller.

[0066] S8. The anomaly detection module detects whether the command read data returned by the DRAM to the DDR controller is abnormal, and if so, step S6 is executed, and if not, the DDR controller returns the command read data to the MCU.

[0067] S9. After receiving the interrupt signal, the MCU jumps to the address of the program to be executed, and transfers to the SRAM to execute the DDR controller anomaly processing program.

[0068] S10. After the MCU terminates the current DRAM data transmission, the reason for the anomaly is obtained from the register of the DDR controller, and it is determined whether the data transmission is erroneous, and if so, step S12 is executed, and if not, step S11 is executed.

[0069] S11. After the MCU records the DDR controller error information to the SRAM, the DDR controller is restarted.

[0070] S12. DRAM data verification is performed, read-write testing is performed on the address where the error occurred, and it is determined whether the error is reproducible, and if so, step S11 is returned, and if not, step S13 is executed.

[0071] S13. The DDR controller error information is recorded, and the anomaly detection module notifies the MCU to resend the read command, and then step S2 is returned.

[0072] The program and data required by the MCU in normal operation are stored on the SDRAM, when the DDR controller has an exception, the exception detection module detects the exception information, and then triggers the DDR controller hardware interrupt immediately, and transmits the information to the MCU in the form of a hardware signal, after the MCU receives the information, the MCU terminates the data stream of DRAM access immediately, and then jumps to the storage body such as SRAM and the like where the DDR controller exception processing code is stored, and executes the corresponding exception processing program, in the exception processing program, the registers of the DDR controller are accessed to obtain the current state, and the reason for the exception is analyzed, then whether the DDR controller can recover to normal and whether the SDRAM data can be recovered are judged according to the analysis result, and the error record is recorded in the SRAM, after the DDR controller recovers to normal, the MCU can read the record in the SRAM to detect the historical state of the DRAM, and potential problems can be found in time.

[0073] In this embodiment, the MCU reads the command data to the DDR controller through the bus in step S1.

[0074] In this embodiment, the exception detection module determines that there is an exception when the DDR controller receives the command sent by the MCU and a timeout error occurs in step S3.

[0075] In this embodiment, the exception detection module determines that there is an exception when the DRAM receives the command read data parsed by the DDR controller and a timeout error occurs in step S5.

[0076] In this embodiment, the exception detection module determines that there is an exception when the DRAM returns the command read data to the DDR controller and a timeout error occurs in step S8.

[0077] In this embodiment, the DDR controller recovers the data of the DRAM from the external backup device after restarting in step S11.

[0078] Embodiment 2

[0079] A DDR controller exception processing device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus;

[0080] The memory is used for storing a computer program.

[0081] The processor is used for executing the following steps by running the program stored in the memory:

[0082] S1. The MCU is started, and sends a command to read data to the DDR controller according to the requirement.

[0083] S2. The DDR controller receives the command read data sent by the MCU, parses and executes the command read data.

[0084] S3. The anomaly detection module detects whether the DDR controller receives the command read data sent by the MCU abnormally, if yes, step S6 is executed, if not, step S4 is executed.

[0085] S4. The DRAM receives the command read data parsed by the DDR controller.

[0086] S5. The anomaly detection module detects whether the DRAM receives the command read data parsed by the DDR controller abnormally, if yes, step S6 is executed, if not, step S7 is executed.

[0087] S6. The anomaly detection module triggers a hardware interrupt, and after the interrupt signal is transmitted to the MCU, step S9 is executed.

[0088] S7. The DRAM returns the command read data to the DDR controller.

[0089] S8. The anomaly detection module detects whether the DRAM returns the command read data to the DDR controller abnormally, if yes, step S6 is executed, if not, the DDR controller returns the command read data to the MCU.

[0090] S9. After the MCU receives the interrupt signal, the address of the program is jumped to execute, and the DDR controller exception processing program on the SRAM is executed.

[0091] S10. After the MCU terminates the current DRAM data transmission, the reason of the anomaly is obtained from the register of the DDR controller, and it is judged whether the data transmission error is caused, if yes, step S12 is executed, if not, step S11 is executed.

[0092] S11. The MCU records the DDR controller error information to the SRAM, and then restarts the DDR controller.

[0093] S12. DRAM data verification is performed, read-write test is performed on the address where the error occurs, and it is judged whether the error is reproduced, if yes, step S11 is returned, if not, step S13 is executed.

[0094] S13. The DDR controller error information is recorded, the anomaly detection module notifies the MCU to resend the read command, and then step S2 is returned.

[0095] Embodiment 3

[0096] A storage medium, a computer readable storage medium stores a computer program, the computer program is executed by a processor to realize:

[0097] S1. MCU starts and sends a command to read data to the DDR controller according to the requirement.

[0098] S2. The DDR controller receives the command to read data sent by the MCU, parses and executes the command to read data.

[0099] S3. The anomaly detection module detects whether the DDR controller receiving the command to read data sent by the MCU is abnormal, if yes, step S6 is executed, if not, step S4 is executed.

[0100] S4. The DRAM receives the command to read data parsed by the DDR controller.

[0101] S5. The anomaly detection module detects whether the DRAM receiving the command to read data parsed by the DDR controller is abnormal, if yes, step S6 is executed, if not, step S7 is executed.

[0102] S6. The anomaly detection module triggers a hardware interrupt, and after the interrupt signal is transmitted to the MCU, step S9 is executed.

[0103] S7. The DRAM returns the command to read data to the DDR controller.

[0104] S8. The anomaly detection module detects whether the DRAM returning the command to read data to the DDR controller is abnormal, if yes, step S6 is executed, if not, the DDR controller returns the command to read data to the MCU.

[0105] S9. The MCU jumps to the address of the program after receiving the interrupt signal, and transfers to the SRAM to execute the DDR controller exception handling program.

[0106] S10. The MCU acquires the cause of the exception from the register of the DDR controller after terminating the current DRAM data transmission, and judges whether it is a data transmission error, if yes, step S12 is executed, if not, step S11 is executed.

[0107] S11. The MCU records the DDR controller error information to the SRAM, and restarts the DDR controller.

[0108] S12. DRAM data verification is performed, read-write test is performed on the address where the error occurs, and it is judged whether the error is reproduced, if yes, step S11 is returned, if not, step S13 is executed.

[0109] S13. The DDR controller error information is recorded, and the anomaly detection module notifies the MCU to resend the reading command, and step S2 is returned.

[0110] Finally, it should be noted that the above only describes the preferred embodiments of the present application and is not intended to limit the present application. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that the technical solutions described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalent ones. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A DDR controller exception handling method, characterized in that: include: S1. MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the data read command from the MCU, the DDR controller parses and executes the command to read the data. S3 abnormality detection module detects whether the DDR controller receives a command sent by the MCU to read the data abnormality, if so, step S6 is executed, if otherwise, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller and reads data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed, and if not, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then executes step S9; S7. DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM command to read data is returned to the DDR controller. If so, step S6 is executed. Otherwise, the DDR controller sends the command to read data back to the MCU. S9. After receiving the interrupt signal, the MCU jumps to the execution program address and transfers to the SRAM to execute the DDR controller exception handler; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed. S11. The MCU records the DDR controller error information in SRAM and restarts the DDR controller. S12 performs DRAM data verification, performs read and write tests on the address where the error occurs, and determines whether the error recurs. If so, returns to step S11, if not, executes step S13; S13. Record the DDR controller error information. The abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

2. The DDR controller exception handling method according to claim 1, wherein: In step S1, the MCU sends a command to read data to the DDR controller via the bus.

3. The DDR controller exception handling method according to claim 1, wherein: In step S3, when the abnormality detection module detects that a timeout error occurs when the DDR controller receives a command sent by the MCU, it is determined to be abnormal.

4. The DDR controller exception handling method according to claim 1, wherein: In step S5, when the abnormality detection module detects that a timeout error occurs when the DRAM receives the command parsed by the DDR controller to read data, it is determined to be abnormal.

5. The DDR controller exception handling method according to claim 1, wherein: In step S8 , when the abnormality detection module detects that a timeout error occurs when the DRAM returns the command to read data to the DDR controller, it is determined to be abnormal.

6. The DDR controller exception handling method according to claim 1, wherein: In step S11 , the DDR controller recovers the DRAM data from the external backup device after restarting.

7. A DDR controller exception handling device, characterized in that: include: A processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus; wherein: The memory is used to store computer programs; The processor is configured to execute, by running the program stored in the memory: S1. MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the data read command from the MCU, the DDR controller parses and executes the command to read the data. S3 abnormality detection module detects whether the DDR controller receives a command sent by the MCU to read the data abnormality, if so, step S6 is executed, if otherwise, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller and reads data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed, and if not, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then executes step S9; S7. DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM command to read data is returned to the DDR controller. If so, step S6 is executed. Otherwise, the DDR controller sends the command to read data back to the MCU. S9. After receiving the interrupt signal, the MCU jumps to the execution program address and transfers to the SRAM to execute the DDR controller exception handler; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed. S11. The MCU records the DDR controller error information in SRAM and restarts the DDR controller. S12 performs DRAM data verification, performs read and write tests on the address where the error occurs, and determines whether the error recurs. If so, returns to step S11, if not, executes step S13; S13. Record the DDR controller error information. The abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

8. A storage medium, characterized in that: A computer program is stored on a computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements: S1. MCU starts and sends commands to read data to the DDR controller as required; S2. After receiving the data read command from the MCU, the DDR controller parses and executes the command to read the data. S3 abnormality detection module detects whether the DDR controller receives a command sent by the MCU to read the data abnormality, if so, step S6 is executed, if otherwise, step S4 is executed; S4. DRAM receives the command parsed by the DDR controller and reads data; S5. The abnormality detection module detects whether the DRAM receives an abnormal command from the DDR controller to read the data. If so, step S6 is executed, and if not, step S7 is executed; S6. The abnormality detection module triggers a hardware interrupt, and the interrupt signal is passed to the MCU and then executes step S9; S7. DRAM returns the command read data to the DDR controller; S8. The abnormality detection module detects whether the DRAM command to read data is returned to the DDR controller. If so, step S6 is executed. Otherwise, the DDR controller sends the command to read data back to the MCU. S9. After receiving the interrupt signal, the MCU jumps to the execution program address and transfers to the SRAM to execute the DDR controller exception handler; S10. After terminating the current DRAM data transmission, the MCU obtains the cause of the exception from the register of the DDR controller and determines whether it is a data transmission error. If so, step S12 is executed; otherwise, step S11 is executed. S11. The MCU records the DDR controller error information in SRAM and restarts the DDR controller. S12 performs DRAM data verification, performs read and write tests on the address where the error occurs, and determines whether the error recurs. If so, returns to step S11, if not, executes step S13; S13. Record the DDR controller error information. The abnormality detection module notifies the MCU to resend the read command and then returns to step S2.

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