System for reading, writing and verifying data

Abstract

A system for reading, writing, and verifying data is provided, where the system for reading data includes: a code cache; and a memory controller connected to the code cache and configured to: receive a read command for reading requested data from a location in a main memory connected to the memory controller through a first interface; reading the first data stored in the position from the main memory; reading a code corresponding to data of a request associated with the read command from the code cache or from an auxiliary memory connected to the memory controller through a second interface different from the first interface; performing error detection and / or correction based on the first data and the code; selecting second data based on a result of the error detection and / or correction; and outputting the second data for the requested data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 537,407, filed on September 8, 2023, entitled “OUT-OF-DIMM ECC FOR ENABLING ERRORRESILIENCE IN NON-ECC DIMMS,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of one or more embodiments of the present disclosure relate to systems and methods for verifying data stored in a memory. Background Art

[0004] Error correction codes (ECC) are designed to detect and / or correct errors in data stored in memory by storing ECC information (such as parity bits or ECC codes) together with the data. However, storing ECC information may introduce additional storage costs and / or may affect memory performance.

[0005] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] One or more embodiments of the present disclosure are directed to verifying data stored in a main memory based on corresponding codes (eg, error detection codes) stored in a secondary memory and / or a cache of a memory controller.

[0007] According to one or more embodiments of the present disclosure, a system for verifying data in a memory includes: a code cache and a memory controller, wherein the memory controller is connected to the code cache and is configured to: receive a read command for reading requested data from a location in a main memory connected to the memory controller via a first interface; read first data stored in the location from the main memory; read a code corresponding to the requested data associated with the read command from the code cache or from an auxiliary memory connected to the memory controller via a second interface different from the first interface; perform error detection and / or correction based on the first data and the code; select second data based on a result of the error detection and / or correction; and output the second data for the requested data.

[0008] In some embodiments, the memory controller is further configured to: determine that the first data is erroneous based on error detection and / or correction; and select the second data by selecting third data as the second data based on the determination that the first data is erroneous, wherein the third data is different from the first data.

[0009] In some embodiments, the third data includes corrected data generated based on the first data and the code through error detection and / or correction.

[0010] In some embodiments, the third data includes an error indicator indicating that the first data is erroneous.

[0011] In some embodiments, the memory controller is further configured to output first data and an indication that the first data is speculative for requested data before error detection and / or correction is completed, wherein the third data includes a reliability flag indicating whether the first data is correct or erroneous.

[0012] In some embodiments, the system also includes a processor that is communicatively connected to the memory controller and is configured to: receive first data and the indication that the first data is speculative from the memory controller; store the first data and the value of a speculative bit associated with the first data in a load-store queue, the value of the speculative bit corresponding to the indication that the first data is speculative; receive third data including a reliability tag from the memory controller; based on a determination that the reliability tag is a first reliability tag indicating that the first data is correct, change the value of the speculative bit to indicate that the first data is correct; and based on a determination that the reliability tag is a second reliability tag indicating that the first data is erroneous, perform an error speculation process associated with a command for reading requested data.

[0013] In some embodiments, the memory controller is further configured to: determine, based on error detection and / or correction, that the first data is correct; and select the second data by selecting the first data as the second data in accordance with the determination that the first data is correct.

[0014] In some embodiments, the second interface comprises a cache coherent interconnect.

[0015] In some embodiments, the code comprises an error correction code (ECC) or a message authentication code (MAC).

[0016] According to one or more embodiments of the present disclosure, a system for verifying data in a memory includes: a code cache and a memory controller, wherein the memory controller is connected to the code cache and is configured to: receive a request for writing data to a main memory, wherein the request includes the data; generate a code corresponding to the data based on the data; store the data in a main memory connected to the memory controller via a first interface; store the code in an auxiliary memory connected to the memory controller via a second interface; and store the code in the code cache.

[0017] In some embodiments, the code comprises an error correction code (ECC) or a message authentication code (MAC).

[0018] In some embodiments, the second interface comprises a cache coherent interconnect.

[0019] In some embodiments, the memory controller is further configured to store, in the code cache along with the code, an indication of a location of the data in the main memory.

[0020] In some embodiments, the system further comprises a processor connected to a last level cache (LLC), the LLC connected to the memory controller, wherein the memory controller is configured to receive the request via the LLC.

[0021] In some embodiments, the system further comprises: a primary memory and a secondary memory.

[0022] According to one or more embodiments of the present disclosure, a system for verifying data in a memory includes: a code cache and a memory controller connected to the code cache, wherein the memory controller includes: an error detection (ED) code generator configured to generate a code based on data associated with a write request for writing data received by the memory controller; and error checking logic configured to detect an error in data read from a main memory by the memory controller during a read instruction based on the code generated by the code generator and stored in the code cache.

[0023] In some embodiments, the system further comprises: a last level cache (LLC) coupled to the memory controller; and a processor coupled to the LLC, wherein the processor comprises a load-store queue and a reorder buffer, wherein the load-store queue is used to store the instructions in the order in which the instructions will be committed, and the reorder buffer is configured to store instructions speculatively executed by the processor, wherein the processor is configured to read and write memory access instructions to the LLC.

[0024] In some embodiments, the memory controller is connected to the primary memory via a first interface and to the secondary memory via a second interface different from the first interface.

[0025] In some embodiments, the error checking logic is configured to detect errors in data read from the main memory based on the code retrieved from the code cache or the auxiliary memory.

[0026] In some embodiments, the first interface includes an interface controller connected to a memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram of a memory system according to one or more embodiments of the present disclosure.

[0029] Figure 2 is a block diagram of a memory system for verifying data in a memory according to one or more embodiments of the present disclosure.

[0030] Figure 3 is a flow chart of an example method of performing a write process according to some embodiments of the present disclosure.

[0031] Figure 4 is a flow chart of an example method of performing a read process according to some embodiments of the present disclosure.

[0032] Figure 5 is a block diagram of a memory system for verifying data in a memory according to one or more embodiments of the present disclosure.

[0033] Figure 6 is a flow chart of an example method of performing a read process according to some embodiments of the present disclosure.

[0034] Figure 7 is a flow chart of an example method of performing a read process according to some embodiments of the present disclosure.

[0035] Figure 8 is a flowchart of a method of performing a reading process according to some embodiments of the present disclosure.

[0036] Fig. 9 is a flowchart of a method of performing a write process according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always refer to the same elements. However, the present disclosure may be embodied in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully conveyed to those skilled in the art. Therefore, processes, elements and techniques that are unnecessary for a complete understanding of the aspects and features of the present disclosure for those of ordinary skill in the art may not be described. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their redundant descriptions may not be repeated.

[0038] Error correction code (ECC) can detect and / or correct errors in data stored in memory by indicating ECC information (such as parity bits or ECC codes) that can be stored in the memory device. However, additional capacity may be required to store ECC information, which may increase costs. For example, for DRAM, eight memory chips can be used to store data, and the ninth memory chip can be used to store ECC information for detecting and correcting errors in the data. In addition, the memory for storing ECC information may be constrained to operate at a clock speed slower than the clock speed of other memory devices. Therefore, some computing systems may rely on memory devices that do not store ECC information (e.g., ECC codes), for example, due to their lower cost and / or higher clock speed. However, such memory devices may not provide error detection and / or correction capabilities. In addition, a memory device that stores ECC information (e.g., ECC codes) may do so in a single form of error detection and correction code, so that it may not support other types of error detection and / or correction codes.

[0039] However, according to one or more embodiments of the present disclosure, error detection and / or correction may be implemented for the main memory by storing a corresponding code (e.g., an error detection and / or correction code) with the data. For example, in some embodiments, the corresponding code may be stored in an auxiliary memory (e.g., separate from the data stored in the main memory). In this case, when the memory controller writes data to the main memory, the memory controller may generate a corresponding code (e.g., such as an ECC code or another type of error detection and / or correction code) and write it to the auxiliary memory. When the memory controller subsequently reads data from the main memory, the memory controller may also read the corresponding code from the auxiliary memory and perform error detection and / or correction on the data using the corresponding code to determine whether the retrieved data is erroneous, and in some cases, correct the retrieved data as needed or desired.

[0040] Thus, the codes stored in the auxiliary memory may be used for subsequent error detection and / or correction processes (e.g., for memory devices that do not store ECC codes), or an additional layer of redundancy may be provided (e.g., for memory devices that already store ECC codes). In this way, error resilience may be provided, and flexible selection of error detection and / or correction schemes may also be implemented depending on the requirements of the application using the memory. For example, depending on the application needs or the desired reliability level, a suitable error detection and / or correction process may be selected to implement, for example, single error correction for 1-bit correction, double error detection (SECDED) codes, double error correction for 2-bit correction, triple error detection (DECTED) codes, and / or message authentication codes (MACs) for detecting row hammer attacks. In other words, the systems and methods described herein may provide support for different types of error detection and / or correction.

[0041] In some cases, reading codes (e.g., error detection and / or correction codes) from auxiliary memory may increase the read latency of the corresponding data because retrieving the data and code may take longer than retrieving only the data. Thus, the memory controller may wait to return data (e.g., to the CPU) until the error detection and / or correction process is complete.

[0042] However, according to one or more embodiments of the present disclosure, in order to reduce the frequency of long read wait times associated with retrieving codes from auxiliary memory, when the memory controller writes data to the main memory, the memory controller may store the corresponding code (e.g., ECC code, MAC, or other type of error detection and / or correction code) in a code cache (e.g., SRAM) on the memory controller. In this case, when the memory controller receives a subsequent request to read the data, the memory controller may first check the code cache to determine whether the corresponding code is contained in the cache. If the corresponding code is contained in the code cache, the additional read wait time associated with retrieving the corresponding code from the auxiliary memory may be avoided. In some embodiments, the memory controller may access the code cache immediately after the read request is inserted into the read queue of the memory controller. In this case, most code cache misses (if they occur) may be hidden because the miss wait time overlaps with the sum of: (1) the time the read request waits in the read queue of the memory controller, (2) the main memory scheduling time, and (3) the completion time of the read operation to read the data from the main memory.

[0043] In some cases, for example, where the code is not cached, it may be desirable to further mitigate the additional read latency. According to one or more embodiments of the present disclosure, the memory controller may forward retrieved data (e.g., data read from the main memory) to a load-store queue of the CPU (e.g., via a last-level cache) before completing an error detection and / or correction process. In some embodiments, when the memory controller forwards data to the load-store queue before the error detection and / or correction process is completed, the memory controller may mark the data as speculative (e.g., by sending an indication to the load-store queue that the data is speculative). In this way, the CPU may be enabled to speculatively execute subsequent instructions using data read from the main memory while waiting for the memory controller to determine whether the data is erroneous. In this case, in some embodiments, the CPU may maintain the corresponding load instruction (e.g., a read instruction requesting data) in a reorder buffer (ROB) until the CPU receives an indication from the memory controller whether the data forwarded by the memory controller is erroneous. In some embodiments, after the memory controller completes error detection and / or correction of the data, the memory controller may send an indication of the result of the error detection and / or correction to the CPU (e.g., an indication of whether the previously forwarded data is correct or incorrect). In some embodiments, if the memory controller sends an indication that the data is correct (e.g., not erroneous), the load instruction can be retired from the ROB, and the data and / or results generated by the CPU based on the data can be committed (e.g., saved in registers and / or memory so that the data and / or results are architecturally visible). In some examples, if the memory controller sends an indication that the data is erroneous, the load instruction can be flushed from the ROB along with subsequent instructions, and any results generated based on the erroneous data can be reversed (e.g., not committed). Thus, in some embodiments, CPU features that support out-of-order execution and speculative execution can be utilized to support the use of speculative data.

[0044] The above and / or other aspects and features of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0045] Figure 1 is a block diagram of a memory system 100 according to one or more embodiments of the present disclosure.

[0046] The system 100 includes a CPU (e.g., a host processor) 102 having one or more processing units (e.g., processors or other processing circuits) configured to execute instructions (e.g., stored in memory), such as read / write memory access instructions and other instructions. In some embodiments, the CPU 102 is configured to perform out-of-order and / or speculative execution of instructions, and includes a load-store queue 104 and a reorder buffer (ROB) 106 to support these features. For example, the CPU 102 can be configured to perform speculative execution of instructions by preemptively executing some instructions before it is determined that the instructions will be needed (e.g., by predicting branch results), so that the results are available more quickly. If the CPU 102 subsequently determines that the speculatively executed instructions are needed (e.g., the predicted branch is taken), the CPU 102 commits the results of the speculatively executed instructions. If the CPU 102 subsequently determines that the speculatively executed instructions are not needed (e.g., a different branch is taken), the CPU 102 rolls back (e.g., reverses) the results of the speculatively executed instructions.

[0047] The CPU 102 may be a processing circuit, such as a general purpose processor or central processing unit core, such as a subsystem or device 123. The CPU 102 may be connected to other components via an address bus, a control bus, a data bus, etc. The CPU 102 may execute instructions stored in a memory (e.g., a main memory 116) to perform various operations described herein and / or cause such operations to be performed by other components, such as a memory controller 110, an LLC 108, an interface controller 114, and / or other components. For example, the CPU 102 may execute one or more system processes and background processes (which are described in more detail below), which may be copied from a persistent storage device (e.g., a storage device, a read-only memory (ROM), etc.) to a memory as needed or desired (e.g., at boot time, at execution time, in an interrupt routine, etc.).

[0048] The load-store queue 104 is configured as a queue that stores load and / or store instructions (e.g., instructions for reading or writing data) in the order in which the results of the instructions are to be committed. Such instructions may include, for example, an operation to be performed (e.g., read or write), a memory address (e.g., a memory address of data to be read), and / or data (e.g., data to be written to memory). The ROB 106 is configured to temporarily store instructions and corresponding data in the ROB 106 until the instructions are committed.

[0049] The CPU 102 is electrically coupled to a last level cache (LLC) 108, which is used to cache instructions and / or data to reduce the frequency of access to memory (e.g., main memory 116 or other memory, such as external memory). For example, the CPU 102 writes memory access instructions and / or data to the LLC 108 and / or reads data from the LLC 108. In some embodiments, the LLC 108 is a 64-bit cache. In some embodiments, one or more additional caches may be coupled between the CPU 102 and the LLC 108 to implement a multi-level cache hierarchy, where the LLC 108 is the last (e.g., highest) cache level before the memory controller 110 is used to access the memory. In this case, the CPU 102 may be electrically coupled to the LLC 108 via one or more additional caches.

[0050] The memory controller 110 is connected to the main memory 116 via the first memory interface 124. In some embodiments, the main memory 116 may be composed of any suitable memory device (e.g., non-ECC memory) that does not store ECC codes, and may include, for example, one or more DRAM chips without a separate chip for storing ECC codes. In some embodiments, the main memory 116 may be composed of any suitable memory device including a separate chip for storing ECC codes. In some embodiments, the main memory 116 may include (or may be) a volatile memory, such as a dynamic random access memory (DRAM), which may be directly connected to a memory slot of a motherboard of the CPU 102 via the first memory interface 124. In this case, the first memory interface 124 (e.g., a connector and its protocol) may conform to a dual in-line memory module (DIMM) to facilitate communication between the main memory 116 and the CPU 102 (e.g., via the CPU OS / kernel), so that the main memory 116 may be a DIMM memory connected to the DIMM slot of the CPU 102. For example, main memory 116 may be or may include a DIMM that includes multiple (e.g., eight or a different number) DRAM chips (e.g., chip 118) or modules. However, the present disclosure is not limited thereto, and main memory 116 may include (or may be) any suitable high-performance primary memory replacement for CPU 102 as known to those skilled in the art. For example, in other embodiments, main memory 116 may be a relatively high-performance non-volatile memory such as NAND flash memory, phase change memory (PCM), resistive RAM, spin transfer torque RAM (STTRAM), any suitable memory based on PCM technology, memristor technology, and / or resistive random access memory (ReRAM), and may include, for example, chalcogenides, etc.

[0051] The memory controller 110 is responsible for scheduling and executing data transfers between the CPU 102 and memory devices (e.g., via the LLC 108), such as data transfers between the CPU 102 and the main memory 116. For example, the memory controller 110 stores data in the main memory 116 (e.g., in response to receiving a request to write data), and reads data from the main memory 116 (e.g., in response to receiving a read command). The memory controller 110 may include at least one processing component embedded thereon for interfacing with the CPU 102 and the main memory 116. The processing component may include, for example, a digital circuit (e.g., a microcontroller, a microprocessor, a digital signal processor, or a logic device (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.)) that is capable of executing memory access instructions (e.g., via firmware and / or software) to provide access to and from data stored in the main memory 116 according to the memory access instructions. In some embodiments, CPU 102 , LLC 108 , memory controller 110 , and interface controller 114 are included in a subsystem or device 123 (eg, a single integrated subsystem or device) such as a circuit board or system on a chip (SOC).

[0052] In a brief overview, and as referenced below Figure 2 In more detail, the memory controller 110 generates codes (e.g., error detection and / or correction codes) corresponding to data read from or written to the main memory 116. The memory controller 110 is connected to a code cache (e.g., error detection and / or correction code cache) 112, which is used to cache the codes to reduce the latency associated with retrieving the codes. In some embodiments, the memory controller 110 includes the code cache 112 (e.g., as part of a single chip), such as Figure 1 As shown. In other embodiments, code cache 112 is external to memory controller 110. The code may include, for example, an ECC code, such as a block code or a convolutional code, a SECDED code, a DECTED code, a MAC, and / or any other suitable type of code that may be used for error detection and / or error correction (e.g., for detecting and / or correcting errors in corresponding data retrieved from main memory 116). In some embodiments, code cache 112 may be implemented using a high-speed volatile memory, such as a static random access memory (SRAM).

[0053] The memory controller 110 is coupled (e.g., electrically connected) to an interface controller 114 for accessing the auxiliary memory 120. The interface controller 114 formats information for transmission and parses received information according to a communication protocol or standard (such as Compute Express Link (CXL)) or on a Peripheral Component Interconnect (PCI). In some embodiments, the interface controller 114 may include at least one processing component embedded thereon for interfacing with the memory controller 110 and the auxiliary memory 120. The processing component may include, for example, a digital circuit (e.g., a microcontroller, a microprocessor, a digital signal processor, or a logic device (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.)) that is capable of executing instructions (e.g., via firmware and / or software) to provide access to and from code stored in the auxiliary memory 120.

[0054] The auxiliary memory 120 may be comprised of any suitable memory device (such as DRAM) for storing the code 122 generated by the memory controller 110. In some embodiments, the interface controller 114 is connected to the auxiliary memory 120 via a second memory interface 126 that is different from the first memory interface 124. For example, the second memory interface 126 may be based on a communication protocol that is different from the communication protocol of the first memory interface 124, and / or may use a conductive path that is different from the conductive path of the first memory interface 124. In some embodiments, the interface controller 114 may be a cache coherent controller (e.g., a CXL controller or other suitable cache coherent controller), and the second memory interface 126 (e.g., a connector and its protocol) may include (e.g., conform to) a cache coherent interconnect (e.g., CXL or other suitable cache coherent interconnect built on Peripheral Component Interconnect Express (PCIe)) to facilitate communication between the interface controller 114 and the auxiliary memory 120. In other embodiments, the second storage interface 126 (e.g., a connector and its protocol) may include (or may conform to) Small Computer System Interface (SCSI), Non-Volatile Memory Express (NVMe), Peripheral Component Interconnect Express (PCIe), Remote Direct Memory Access (RDMA) over Ethernet, Serial Advanced Technology Attachment (SATA), Fibre Channel, Serial Attached SCSI (SAS), NVMe over Fabric (NVMe-oF), etc. In other embodiments, the second storage interface 126 (e.g., a connector and its protocol) may include (or may conform to) various general purpose interfaces, such as, for example, Ethernet, Universal Serial Bus (USB), etc.

[0055] The auxiliary memory 120 may include one or more memory devices, such as one or more CXL memory devices. In some embodiments, the auxiliary memory 120 includes a disaggregated CXL memory pool including a plurality of different types of CXL memory devices, which may generally include volatile memory, such as DRAM, for example, from DDR3, DDR4, DDR5, low power, high power, low profile, PMEM, HBM, SSD with DRAM, etc. However, the present disclosure is not limited thereto, and the auxiliary memory 120 may include (or may be) any suitable type of memory known to those skilled in the art.

[0056] For example, in some embodiments, the auxiliary memory 120 may be implemented with a suitable storage device to persistently store data and / or code accessible to the CPU 102 and / or the memory controller 110. In this context, the auxiliary memory 120 may include (or may be) a relatively slow memory compared to the high-performance main memory 116. For example, in some embodiments, the auxiliary memory 120 may be a solid-state drive (SSD). However, the present disclosure is not limited thereto, and in other embodiments, the auxiliary memory 120 may include (or may be) any suitable storage device, for example, such as a magnetic storage device (e.g., a hard disk drive (HDD)), an optical storage device (e.g., a Blu-ray disc drive, a compact disc (CD) drive, a digital versatile disc (DVD) drive, etc.), other kinds of flash memory devices (e.g., a USB flash drive, etc.), etc. In various embodiments, the auxiliary memory 120 may conform to a large form factor standard (e.g., a 3.5-inch hard disk drive form factor), a small form factor standard (e.g., a 2.5-inch hard disk drive form factor), an M.2 form factor, an E1.S form factor, etc. In other embodiments, secondary storage 120 may conform to any suitable or desired derivative of these form factors.

[0057] Figure 2 is a block diagram of a memory system 200 for verifying data in a memory according to one or more embodiments of the present disclosure.

[0058] System 200 includes a memory controller 201, which may be referred to above. Figure 1 The system 200 may also include LLC 108, code cache 112 (eg, in memory controller 201), interface controller 114, main memory 116, and auxiliary memory 120, as described above with reference to Figure 1 Described. Figure 2 In the drawings, dashed directional lines depict communication paths through which codes are communicated between elements, and solid directional lines depict communication paths through which data and / or instructions are communicated between elements.

[0059] Memory controller 201 receives data from LLC 108 (which is itself electrically coupled to the load / store queues, as described above with reference to Figure 1 The memory access controller 100 receives read (load) commands and write requests and manages memory accesses associated with the read commands and write requests (eg, memory accesses required to write data associated with a write request or to read data requested by a read command).

[0060] exist Figure 2 In an example of , the memory controller 201 includes a code generator 202 for generating a code (e.g., an error detection and / or correction code) based on data received in a write request (e.g., from LLC 108). The code generator 202 includes processing circuits and / or commands for generating a code based on the data. For example, the code generator 202 can implement ECC code generation by generating a single error correction (SEC) code, a SECDEC code, a DECTED code, a MAC code, or another suitable type of error detection and / or correction code, which can then be used by the memory controller 201 to detect and / or correct errors in the data. As described above, the memory controller 201 stores the generated code in the code cache 112 of the memory controller 201 and writes the code to the auxiliary memory 120 (e.g., via the interface controller 114 and the second memory interface 126). In some embodiments, the memory controller 201 stores a memory address associated with the corresponding data (e.g., an address in the main memory 116 where the corresponding data is stored) and the code so that the memory controller can retrieve the appropriate code when it reads the corresponding data from the main memory 116.

[0061] The memory controller 201 includes a write queue 204, a read queue 206, and a scheduler 208 for scheduling the reading and writing of data to the main memory 116 (e.g., to optimize memory access time). For example, the memory controller 201 stores write requests received from the LLC 108 in the write queue 204 until the scheduler 208 determines an appropriate time to execute the write request. Similarly, the memory controller 201 stores read commands in the read queue 206 until the scheduler 208 determines an appropriate time to execute the read command. Figure 2 In the example of FIG. 2 , the memory controller 201 further includes a buffer 212 for buffering data associated with read commands and write requests.

[0062] The memory controller 201 includes error checking logic 210 for verifying data read from the main memory 116. The error checking logic 210 includes circuits and / or instructions for verifying the data using (e.g., based on) the data and a corresponding code read from the code cache 112 and / or the auxiliary memory 120 (e.g., a code generated based on the data when the data is written to the main memory 116). For example, when the memory controller 201 receives a read command requesting data in the main memory 116, the memory controller 201 reads the requested data from the main memory 116 and retrieves (e.g., reads) the corresponding code associated with the requested data from the code cache 112 (if the corresponding code exists in the code cache 112) or from the auxiliary memory 120 (if the corresponding code does not exist in the code cache 112). In some examples, the code corresponding to the data is associated with (e.g., stored with) a memory address of the data so that the corresponding code can be retrieved based on the memory address when the data at the memory address is retrieved. In some embodiments, when the code is not present in the code cache 112 (eg, such as in a cache miss), the memory controller 201 writes the code to the code cache 112 after reading the code from the auxiliary memory 120 , thereby updating the code cache 112 with the most recently used code.

[0063] Memory controller 201 provides the data and the corresponding code to error checking logic 210, and error checking logic 210 performs error detection and / or correction based on the code and the data, such as by generating a second code based on the data, and comparing the second code with the code retrieved from auxiliary memory 120 or code cache 112 to determine whether the codes match (e.g., whether the data is correct). In some embodiments, error checking logic 210 determines whether the data read from main memory 116 is correct or erroneous based on the error detection and / or correction. In some embodiments, based on the determination that the data is correct, error checking logic 210 outputs the data and / or outputs an indication that the data is correct (e.g., via communication path 218).

[0064] In some embodiments, based on determining that the data is erroneous and correctable (e.g., the data can be corrected during error detection and correction, such as when the error is a single-bit error), error checking logic 210 corrects the data to generate corrected data, and outputs the corrected data (e.g., via communication path 218). In some embodiments, based on determining that the data is erroneous and uncorrectable (e.g., such as when the error is a multi-bit error or error checking logic 210 does not include error correction capabilities), error checking logic 210 outputs an error indicator indicating that the data is erroneous (e.g., via communication path 218).

[0065] exist Figure 2In an example of , the memory controller 201 includes a multiplexer 216 for selecting data read from the main memory 116 (e.g., provided to the multiplexer 216 via the communication path 220) or the output of the error checking logic 210 (e.g., provided to the multiplexer 216 via the communication path 218) to be provided to the LLC 108 (optionally, via the response queue 214). For example, if the error checking logic 210 determines that the data is correct (e.g., not erroneous), the memory controller 201 may cause the multiplexer 216 to select the data read from the main memory 116 to be provided to the LLC 108. For example, if the error checking logic 210 determines that the data is erroneous and outputs the corrected data or an indication that the data is erroneous, the memory controller 201 may cause the multiplexer 216 to select the corrected data or the indication that the data is erroneous to be provided to the LLC 108.

[0066] Figure 3 is a flowchart of an example method 300 of performing a write process according to some embodiments. In some embodiments, the method 300 is respectively referred to above Figure 1 and Figure 2 The system 100 and / or system 200 described above are performed. However, the present disclosure is not limited thereto, and the operations shown in the method 300 may be performed by any suitable one or any suitable combination of those components and elements of one or more example embodiments described above. In addition, the present disclosure is not limited to Figure 3 The order or number of operations of the method 300 shown in the figure may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 300 may include fewer operations or additional operations.

[0067] refer to Figure 3 At operation 302, an LLC (e.g., LLC 108) writes a cache line including data to be written to a main memory (e.g., main memory 116) to memory. In some embodiments, the LLC writes a cache line (e.g., a line of the LLC) to memory when the cache line is evicted from the cache to make room for other portions (e.g., when a load instruction requires that the corresponding data be brought to the LLC). In some embodiments, the LLC writes the cache line to memory by sending a request to a memory controller (e.g., memory controller 110 or 201). For example, in some embodiments, the LLC queues the request to the write queue 204.

[0068] At operation 304, the memory controller receives the cache line from the LLC and generates a code (e.g., using the code generator 202). For example, the memory controller provides the data received in the cache line from the LLC to the code generator 202, and the code generator 202 generates a code (e.g., an error detection and / or correction code) corresponding to the data.

[0069] At operation 306, the memory controller writes the cache line to the main memory and sends an acknowledgement to the LLC. For example, the memory controller writes the data included in the cache line to the main memory at a memory address determined by the memory controller. In some embodiments, the memory controller writes the cache line to the main memory by sending the data (e.g., along with the address and write request) to the main memory via a first memory interface (such as memory interface 124) to cause the main memory to store the data in the main memory.

[0070] At operation 308 (which may be performed concurrently with operation 306 or at least partially overlapped in time with operation 306), the memory controller writes the code to a code cache (e.g., code cache 112). For example, the memory controller writes the code to the code cache by causing the code to be stored in a row of the code cache, optionally together with an indication of the location where the corresponding data is stored in the main memory. In some embodiments, the memory controller may determine whether the row of code corresponding to the data already exists in the code cache, and if so (e.g., upon a cache hit), the code may be written (e.g., the code may be overwritten) in the corresponding row of the code cache. In some embodiments, if the code corresponding to the data is being stored in the code cache for the first time or a previously stored cache row has been evicted from the cache, the memory controller (e.g., via interface controller 114) may obtain the appropriate row for the code from the auxiliary memory (e.g., auxiliary memory 120) and may write the code to the corresponding row in the code cache.

[0071] Figure 4 is a flowchart of an example method 400 of performing a read process according to some embodiments. In some embodiments, the method 400 can be respectively referred to above Figure 1 and Figure 2 The system 100 and / or system 200 described above are performed. However, the present disclosure is not limited thereto, and the operations shown in the method 400 may be performed by any suitable one or any suitable combination of those components and elements in one or more of the example embodiments described above. In addition, the present disclosure is not limited to Figure 4The order or number of operations of the method 400 shown in the figure may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 400 may include fewer operations or additional operations.

[0072] At operation 402, the LLC (e.g., LLC 108) requests data from a memory controller (e.g., memory controller 110 or 201). In some embodiments, the LLC requests data from the memory controller in response to receiving an instruction to read data from a CPU (e.g., CPU 102) (e.g., an instruction including an indication of a read operation and a memory address associated with the data). The LLC requests data from the memory controller by sending a read command to the memory controller for reading the data. For example, in some embodiments, the LLC queues the read command to the read queue 206. The read command includes a memory address at which the data is stored in the main memory.

[0073] At operation 404, in response to receiving the read command from the LLC, the memory controller reads data from a main memory (eg, main memory 116). In some embodiments, the memory controller reads (eg, receives) data from the main memory via a first memory interface (such as memory interface 124).

[0074] At operation 406 (which may be performed concurrently with operation 404 or at least partially overlapped in time with operation 404), in response to receiving a request to read data from the LLC, the memory controller requests a corresponding code from a code cache (e.g., code cache 112). The corresponding code may be a code generated based on the data when the data is stored, such as the code described above with reference to Figure 3 as described in operation 304 .

[0075] At operation 408 , the memory controller determines whether there is a code cache hit (eg, yes at operation 408 ) by determining whether the corresponding code is present in the code cache or not present in the code cache (eg, a cache miss).

[0076] At operation 410 , in response to determining that there is a code cache hit (eg, the code is present in the code cache), the memory controller reads the code from the code cache.

[0077] At operation 412, based on determining that there is no code cache hit (e.g., the code is not present in the code cache, or in other words, a cache miss), the memory controller (e.g., via the interface controller 114) reads the code from the auxiliary memory, such as the auxiliary memory 120. In some embodiments, the memory controller reads the code from the auxiliary memory via a second memory interface different from the first memory interface, such as the second memory interface 126.

[0078] At operation 414, based on determining that there is no code cache hit (e.g., the code is not present in the code cache), and after reading the code from the auxiliary memory (e.g., via the interface controller 114), the memory controller (or the interface controller 114) writes the code to the code cache. In some embodiments, the memory controller reads the code from the code cache (e.g., similar to operation 410 described above). In other embodiments, the memory controller may use the code read from the auxiliary memory (e.g., via the interface controller 114) for error detection and / or correction, and may concurrently or subsequently write the code to the code cache.

[0079] At operation 416, after reading the data from the main memory, the memory controller determines whether the code has been read (e.g., whether the code has been read from the code cache or from the auxiliary memory and can be used to perform error detection and / or correction). Based on determining at operation 416 that the code has not been read (e.g., no at operation 416), the memory controller can wait until the code has been read.

[0080] Based on determining at operation 416 that the code has been read (e.g., yes at operation 416), at operation 418, the memory controller performs error detection and / or correction based on the data read from the main memory and the corresponding code read from the code cache (at operation 410) or from the auxiliary memory (at operation 412). For example, the error checking logic 210 of the memory controller performs error detection and / or correction based on the data and the corresponding code.

[0081] At operation 420 , the memory controller determines whether an error is detected during the error detection and / or correction process. For example, the error checking logic 210 of the memory controller may determine at operation 420 whether an error is detected during the error detection and / or correction process.

[0082] Based on the determination that no errors were detected at operation 420 (e.g., the data read from the main memory at operation 404 is correct and not erroneous), at operation 422, the memory controller returns the data read from the main memory at operation 404 (e.g., as is). For example, the memory controller may return the data by writing the data to the response queue 214 or to the LLC 108 (optionally via a multiplexer such as the multiplexer 216).

[0083] Based on the determination that an error was detected at operation 420 (e.g., the data read from the main memory at operation 404 is incorrect or erroneous), at operation 424, the memory controller may correct the data (if possible) and return the corrected data, or if the error is uncorrectable (e.g., the error checking logic 210 cannot correct the detected error), the memory controller may return an error code indicating that the data is erroneous. For example, if the error checking logic 210 detects an uncorrectable error (or does not implement error correction capabilities), the error checking logic 210 outputs an error code indicating that the data is erroneous, and the memory controller provides the error code to, for example, the response queue 214 or the LLC 108 (optionally, via a multiplexer such as the multiplexer 216).

[0084] Figure 5 5 is a block diagram of a memory system 500 for verifying data in a memory according to one or more embodiments of the present disclosure. The system 500 includes a memory controller 501 and the memory controller 502 described above. Figure 2 Many of the same or substantially the same elements (eg, as indicated by the same reference numerals) described above with respect to the system 200 may be used. The memory controller 501 may be the same or substantially the same elements (eg, as indicated by the same reference numerals) as described above with respect to the system 200. Figure 1 Another example implementation of the memory controller 110 is described.

[0085] refer to Figure 5 , memory controller 501 is similar to memory controller 201 in that it is configured to read data from and write data to main memory 116, generate and store codes, and verify data based on the stored codes, as described above with reference to Figure 3 and Figure 4As described above. However, the memory controller 501 may implement additional functionality relative to the memory controller 201. In more detail, waiting until the error detection and / or correction process is completed before returning (e.g., outputting) the data read from the main memory 116 to, for example, the response queue 214 or the LLC 108 may incur additional read latency in the event that the code is not present in the code cache 112 and the code must be read from the auxiliary memory 120. Thus, in some embodiments, the memory controller 501 may be configured to return the data read from the main memory 116 when the data is read from the main memory 116 (e.g., in response to reading the data from the main memory 116), without waiting for the code to be read from the auxiliary memory 120 and / or without waiting for the error detection and / or correction process to be completed. For example, the memory controller 501 may return the data read from the main memory 116 to the response queue 214 via the communication path 220 and the multiplexer 216.

[0086] For example, the memory controller 501 may include error checking and forwarding logic 504. The error checking and forwarding logic 504 includes the above reference Figure 3 1. The error checking logic 210, code availability logic 508, and speculative data marking logic 506 described above are described above. In some embodiments, the code availability logic 508 and / or the speculative data marking logic 506 are included in the error checking logic 210. In some embodiments, the code availability logic 508 and / or the speculative data marking logic 506 are implemented using circuits and / or instructions separate from the error checking logic 210. The code availability logic 508 is configured to determine whether the corresponding code is ready for use in error detection and / or correction performed by the error checking logic 210 during a read operation (e.g., when the memory controller 501 is executing a read instruction to read data from the main memory 116). In some embodiments, the code availability logic 508 determines that the code is ready based on determining that the code has been read from the auxiliary memory 120 or from the code cache 112. In some embodiments, the code availability logic 508 is included in the error checking logic 210. In some embodiments, based on the determination that the code is ready, the error checking logic 210 performs error detection and / or correction based on the code and the data read from the main memory 116.

[0087] In some embodiments, if the data read from the main memory 116 is returned to the response queue 214 or LLC 108 before the code is read and / or before the error detection and / or correction process is completed, the speculative data marking logic 506 outputs an indication that the data is speculative. For example, the speculative data marking logic 506 can output one or more bits that are set to a first value (e.g., "1") if the data is speculative and set to a second value (e.g., "0") if the data is not speculative (e.g., if error detection and / or correction has been completed). In some embodiments, the memory controller 501 outputs the data and the indication that the data is speculative (e.g., concurrently or simultaneously) as part of a single output record. For example, the indication that the data is speculative can be appended to the data, and the data with the appended indication can be provided to the multiplexer 216. In some embodiments, memory controller 501 outputs the indication that the data is speculative separately from the output of the data (e.g., outputs the indication that the data is speculative so that it is temporally or logically separate from the data, such as by providing the indication that the data is speculative to multiplexer 216 before or after providing the data to multiplexer 216). In some embodiments, LLC 108 receives the data and the indication that the data is speculative from memory controller 501 and stores the data and the indication that the data is speculative in LLC 108.

[0088] In some embodiments, after the error checking and forwarding logic 504 outputs the data with an indication that the data is speculative, the error checking and forwarding logic 504 waits until the code is ready (e.g., the code has been read from the auxiliary memory 120 or the code cache 112), and then performs an error detection and / or correction process based on the data read from the main memory 116 and the corresponding code to determine whether the data read from the main memory 116 is correct or erroneous. In some embodiments, after completing the error detection and / or correction process, the error checking logic 210 outputs a reliability flag (e.g., via the communication path 218) indicating whether the data previously returned to the response queue 214 is correct or erroneous. The reliability flag may include one or more bits that are set to a first value (e.g., "1") based on the error checking logic 210 determining that the data is correct, and are set to a second value (e.g., "0") based on the error checking logic 210 determining that the data is erroneous.

[0089] In some embodiments, when the code is present in the code cache 112 (and therefore, the additional read latency is minimized or reduced), the memory controller 501 functions in a manner similar to that described above with reference to the memory controller 201. For example, the memory controller 501 performs an error detection and / or correction process (e.g., using the error checking logic 210) based on the code retrieved from the code cache 112 and the data read from the main memory 116. The memory controller 501 then uses the multiplexer 216 to select the data read from the main memory 116 or the output of the error checking logic 210 to provide to the response queue 214 based on the determination of whether the data read from the main memory 116 is correct or erroneous.

[0090] In some embodiments, when the code does not exist in the code cache 112 (and therefore, the memory controller 501 may incur additional latency to read the code from the auxiliary memory 120), the memory controller 501 outputs data with an indication that the data is speculative, performs an error detection and / or correction process upon reading the code from the auxiliary memory 210, and outputs a reliability flag based on the output of the error detection and / or correction process, as described above. In some embodiments, when the code does not exist in the code cache 112, the memory controller 501 writes the code to the code cache after reading the ED code from the auxiliary memory 120, thereby updating the code cache with the most recently used code.

[0091] Figure 6 is a flowchart of an example method 600 of performing a read process according to some embodiments of the present disclosure. In some embodiments, the method 600 may be performed by referring to Figure 1 and Figure 5 The system 100 and / or system 500 described herein are performed. However, the present disclosure is not limited thereto, and the operations shown in the method 600 may be performed by any suitable component and element or any suitable combination of components and elements of the components and elements of one or more of the example embodiments described above. In addition, the present disclosure is not limited to Figure 6 The order or number of operations of the method 600 shown in the embodiment of the present invention may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 600 may include fewer operations or additional operations.

[0092] refer to Figure 6At operation 602, the LLC (e.g., LLC 108) requests data from a memory controller (e.g., memory controller 110 or 501). In some embodiments, the LLC requests data from the memory controller in response to receiving a command (e.g., an instruction including an indication of a read operation and a memory address associated with the data) from a CPU (e.g., CPU 102) to read the data. In some embodiments, the LLC requests data from the memory controller by sending a read command (e.g., via read queue 206) to the memory controller. In some embodiments, the read command includes a memory address at which the data is stored in the main memory.

[0093] At operation 604, in response to receiving the read command from the LLC, the memory controller reads data from a main memory (eg, main memory 116). In some embodiments, the memory controller reads (eg, receives) data from the main memory via a first memory interface (such as memory interface 124).

[0094] At operation 606 (which may be performed concurrently with operation 604 or at least overlapped in time with operation 604), in response to receiving a request to read data from the LLC, the memory controller requests a corresponding code from a code cache (e.g., code cache 112). The corresponding code is a code generated based on the data when the data is stored, such as the code described above with reference to Figure 3 as described in operation 304 .

[0095] At operation 608 , the memory controller determines whether there is a code cache hit by determining whether the corresponding code is present in the code cache or not in the code cache.

[0096] At operation 610 , in response to determining that there is a code cache hit (eg, the code is present in the code cache), the memory controller reads the code from the code cache.

[0097] At operation 612, based on determining that there is no code cache hit, or in other words, a cache miss (e.g., the code is not present in the code cache), the memory controller (e.g., via the interface controller 114) reads the code from the auxiliary memory, such as the auxiliary memory 120. In some embodiments, the memory controller reads the code from the auxiliary memory via a second memory interface different from the first memory interface, such as the second memory interface 126.

[0098] At operation 614, the memory controller writes the code to the code cache based on determining that there is no code cache hit (e.g., the code is not present in the code cache) and after reading the code from the auxiliary memory (e.g., via the interface controller 114). For example, the memory controller writes the code to the code cache prior to, concurrently with, or subsequent to an error detection and / or correction process described in more detail below.

[0099] At operation 616 , after reading the data from the main memory, the memory controller determines whether the code has been read (eg, whether the code has been read from a code cache or from auxiliary memory and is available to perform an error detection and / or correction process).

[0100] Based on determining at operation 616 that the code has not been read (e.g., no at operation 616), at operation 618, the memory controller (e.g., the error checking and forwarding logic 504 of the memory controller 501) returns the data read at operation 604 and an indication that the data is speculative. The memory controller then waits until the code has been read (e.g., from the auxiliary memory 120 or the code cache 112) to proceed to operation 620.

[0101] Based on determining at operation 616 that the code has been read (or after performing operation 618 and waiting for the code to be read), at operation 620, the memory controller performs error detection and / or correction based on the data read from the main memory and the corresponding code read from the code cache (e.g., at operation 610) or from the auxiliary memory (e.g., at operation 612). For example, the error checking logic 210 of the memory controller performs the error detection and / or correction process based on the data and the corresponding code.

[0102] At operation 622, the memory controller determines whether an error was detected during the error detection and / or correction performed at operation 620. For example, the error checking logic 210 of the memory controller determines whether an error was detected during the error detection and / or correction. In some embodiments, based on a determination that a correctable error was detected (e.g., yes at operation 622), the error checking logic corrects the data and outputs the corrected data. In some embodiments, based on a determination that an uncorrectable error was detected, the error checking logic outputs an error indicator or may return data with an error flag (e.g., an error flag or bit set to true).

[0103] Based on the determination that no errors were detected at operation 622 (e.g., the data read from the main memory at operation 604 is correct and not erroneous), at operation 624, the memory controller returns a first reliability flag (e.g., a reliability flag indicating that the data returned at operation 618 is correct, as described above with reference to Figure 5), and / or returns the data read from the main memory at operation 604 (e.g., if operation 618 is not performed because the code is determined to be available at operation 616). For example, the memory controller may return the data and / or the first reliability tag by writing the data and / or the first reliability tag to the response queue 214 or the LLC 108 (optionally, via a multiplexer such as the multiplexer 216).

[0104] Based on a determination that an error was detected at operation 622 (e.g., the data read from the main memory at operation 604 was incorrect or erroneous), at operation 626, the memory controller returns a second reliability flag (e.g., a reliability flag indicating that the data returned at operation 618 was erroneous, as described in reference to FIG. Figure 5 ), or returns an error code (e.g., if operation 618 is not performed because the code is determined to be available at operation 616, and if an uncorrectable error is detected at operation 620), or returns corrected data (e.g., if operation 618 is not performed because the code is determined to be available at operation 616, and if a correctable error is detected at operation 620). For example, the memory controller may return the second reliability tag, error code, and / or corrected data by writing the second reliability tag, error code, and / or corrected data to the response queue 214 or LLC 108 (optionally, via a multiplexer such as multiplexer 216).

[0105] Figure 7 is a flow chart of an example method 700 of performing a read process according to some embodiments of the present disclosure. In some embodiments, Figure 7 The operation may be performed by a CPU including a load-store queue and a reorder buffer (such as the one referenced above). Figure 1 However, the present disclosure is not limited thereto, and the operations shown in method 700 may be performed by any suitable one or combination of those components and elements of one or more of the exemplary embodiments described above. Figure 7 The order or number of operations of the method 700 shown in the figure may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 700 may include fewer operations or additional operations.

[0106] refer to Figure 7At operation 702, the CPU receives speculative data and stores the speculative data in an entry of a load-store queue (e.g., load-store queue 104). For example, the CPU receives data and an indication that the data is speculative (e.g., as described above with reference to FIG. 1 ) from a memory controller (e.g., memory controller 110 or 501). Figure 6 as described above), and stores the data in an entry of a load-store queue.

[0107] At operation 704, the CPU sets a speculative bit associated with the load-store queue entry having the data stored at operation 702 (e.g., a speculative bit associated with the data received at operation 702). For example, the CPU sets the speculative bit in the load-store queue entry to a first value (e.g., "1" or another value) based on receiving an indication from a memory controller that the data is speculative. In some embodiments, the speculative bit is included in the load-store queue entry having the data. In some embodiments, the speculative bit is stored in the load-store queue separately from the load-store queue entry having the data.

[0108] At operation 706, the CPU receives a reliability tag associated with the data received at operation 702. For example, the CPU receives the reliability tag from the memory controller, such as by receiving the above referenced Figure 6 The first reliability flag or the second reliability flag described. The reliability flag indicates whether the data received at operation 702 is correct or erroneous.

[0109] At operation 708, the CPU determines whether the data stored at operation 702 is error-free (e.g., whether the data is correct or incorrect). In some embodiments, the CPU determines whether the data stored at operation 702 is correct or incorrect based on the reliability mark received at operation 706. For example, if the CPU receives a first reliability mark indicating that the data is correct, the CPU determines that the data is correct based on the first reliability mark. If the CPU receives a second reliability mark indicating that the data is incorrect, the CPU determines that the data is incorrect based on the second reliability mark.

[0110] Based on determining that the data is error-free (e.g., the data is correct), at operation 710, the CPU unsets the speculative bit associated with the load-store queue entry stored at operation 702 to indicate that the data is no longer speculative. For example, the CPU changes the value of the speculative bit from a first value to a second value to indicate that the data is no longer speculative, such as by changing the value from "1" to "0" or from "0" to "1". In some examples, the CPU commits the data (e.g., makes the data visible at a level, such as by storing the data in a register or memory) based on the determination that the speculative bit indicates that the data is not speculative.

[0111] Based on determining that the data is not error-free (e.g., the data is erroneous), at operation 712, the CPU performs a misspeculation (recovery) process (e.g., a typical misspeculation or recovery process known to those of ordinary skill in the art), for example, by rolling back the load (e.g., the read command for reading the data received at operation 702) and subsequent instructions in the reorder buffer. For example, the CPU performs a recovery process similar to the recovery process performed when the CPU speculatively executes the branch if the branch is not subsequently selected (e.g., by predicting which path of the conditional branch instruction will ultimately be taken). For example, the CPU removes the read instruction from the reorder buffer along with any subsequent (e.g., subsequent) instructions that use the results of the read instruction, and discards the results of the subsequent instructions without committing them.

[0112] Figure 8 is a flowchart of a method 800 for performing a read process according to some embodiments of the present disclosure. The method 800 may be performed by a memory controller (e.g., the memory controller 110, 201, and / or 501) or by a system including a memory controller (e.g., the system 100, 200, and / or 500 or the subsystem or device 123). For example, the memory controller may be configured to perform the method 800 by executing instructions to perform the method 800 and / or using programmable or non-programmable hardware configured to perform the method 800. However, the present disclosure is not limited thereto, and the operations shown in the method 800 may be performed by any suitable one of those components and elements or any suitable combination of components and elements of one or more of the example embodiments described above. Furthermore, the present disclosure is not limited to Figure 8 The order or number of operations of the method 800 shown in the figure may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 800 may include fewer operations or additional operations.

[0113] refer to Figure 8 At operation 802, a memory controller receives a read command for reading requested data from a location (e.g., a memory address or other type of location) in a main memory. For example, the memory controller receives the read command from an LLC (e.g., LLC 108) or from a CPU (e.g., CPU 102). In some embodiments, the read command for reading the data includes a memory address associated with the data, such as a memory address at which the data is stored in the main memory (e.g., in a memory chip 118 of the main memory 116).

[0114] At operation 804, the memory controller reads the first data stored in the location from the main memory. For example, in response to receiving a read command for reading data at operation 802, the memory controller sends a read request including a memory address associated with the requested data to the main memory, and receives the first data from the main memory. The first data may be data stored at the memory address. In some embodiments, the memory controller reads the data from the main memory using a first memory interface (e.g., first memory interface 124).

[0115] At operation 806, the memory controller reads a code corresponding to the requested data associated with the read command from the code cache or from the auxiliary memory. For example, the memory controller uses the memory address associated with the data to retrieve the corresponding code from the code cache (e.g., if the ED code exists in the code cache) or from the auxiliary memory (e.g., if the code does not exist in the code cache). For example, in response to receiving a read command for reading the requested data at operation 802, and based on determining that the code does not exist in the code cache (e.g., a cache miss), the memory controller sends a read request including the memory address associated with the data to the auxiliary memory, and receives the corresponding code from the auxiliary memory (e.g., via a second interface). In some embodiments, the auxiliary memory or the code cache uses the memory address associated with the data to find the corresponding code.

[0116] At operation 808, the memory controller performs error detection and / or correction based on the first data and code. In some embodiments, the memory controller performs an error detection and correction process, such as an ECC process, which detects and in some cases corrects errors in the first data (e.g., 1-bit errors, 2-bit errors, or other errors). In some embodiments, the memory controller performs an error detection process, such as a MAC process, that detects errors but does not correct the detected errors. In some embodiments, if the error detection and / or correction detects that the first data is correct, the error detection and / or correction outputs the first data and / or outputs an indication that the first data is correct. In some embodiments, if the error detection and / or correction detects an uncorrectable error in the first data (e.g., an error that the error detection and / or correction cannot correct), the error detection and / or correction outputs an error indicator indicating that the first data is wrong. In some embodiments, if the error detection and / or correction detects a correctable error in the first data (e.g., an error that the error detection and / or correction can correct), the error detection and / or correction corrects the first data to generate corrected data and outputs the corrected data.

[0117] At operation 810, the memory controller selects the second data based on the result of the error detection and / or correction. In some embodiments, the memory controller uses a multiplexer (such as multiplexer 216) to select the second data. In some embodiments, based on a determination that the result of the error detection and / or correction includes an indication that the first data is correct, the memory controller selects the first data as the second data (e.g., the memory controller outputs the data read from the main memory). In some embodiments, based on a determination that the output of the error detection and / or correction includes corrected data, the memory controller selects the corrected data as the second data (e.g., the memory controller outputs the corrected data). In some embodiments, based on a determination that the output of the error detection and / or correction includes an error indicator, the memory controller selects the error indicator as the second data (e.g., the memory controller outputs the error indicator).

[0118] At operation 812, the memory controller outputs second data for the requested data (e.g., the memory controller outputs the second data in response to receiving a command to read the requested data). In some embodiments, the memory controller outputs the second data by writing the second data to a response queue (e.g., response queue 214) or an LLC (e.g., LLC 108).

[0119] Fig. 9 is a flowchart of a method for performing a write process according to some embodiments of the present disclosure. Method 900 may be performed by a memory controller (e.g., memory controller 110, 201, and / or 501) or by a system including a memory controller (e.g., system 100, 200, and / or 500 or subsystem or device 123). For example, the memory controller may be configured to perform method 900 by executing instructions to perform method 900 and / or using programmable or non-programmable hardware configured to perform method 900. However, the present disclosure is not limited thereto, and the operations shown in method 900 may be performed by any suitable one of those components and elements or any suitable combination of components and elements of one or more of the example embodiments described above. Furthermore, the present disclosure is not limited to Fig. 9 The order or number of operations of the method 900 shown in the embodiment of the present invention may be changed to any desired order or number of operations as recognized by those of ordinary skill in the art. For example, in some embodiments, the order may be changed, or the method 900 may include fewer operations or additional operations.

[0120] refer to Fig. 9At operation 902, the memory controller receives a request to write data to the main memory. In some embodiments, the request includes the data. For example, the memory controller receives the request from an LLC (e.g., LLC 108) or from a CPU (e.g., CPU 102). In some embodiments, the request to write the data includes the data.

[0121] At operation 904, the memory controller generates a code corresponding to the data based on the data. For example, the code generator 202 of the memory controller generates the code by encoding the data (optionally with additional bits) using an ECC algorithm or another suitable kind of algorithm.

[0122] At operation 906, the memory controller stores the data in a main memory (eg, main memory 116). In some embodiments, the memory controller stores the data in the main memory using a first memory interface (eg, first memory interface 124).

[0123] At operation 908, the memory controller stores the code in the auxiliary memory (e.g., the auxiliary memory 120). In some embodiments, the memory controller stores the code in the auxiliary memory using a second memory interface (e.g., the second memory interface 126) and / or an interface controller (e.g., the interface controller 114). In some embodiments, the memory controller stores the memory address (e.g., the memory address at which the data is stored in the main memory) and the code associated with the data stored in the main memory at operation 906 in the auxiliary memory so that the code can be subsequently retrieved from the auxiliary memory when the data is retrieved from the main memory.

[0124] At operation 910, the memory controller stores the code in a code cache (e.g., code cache 112). In some embodiments, the memory controller stores the memory address associated with the data stored in the main memory at operation 906 (e.g., the memory address at which the data is stored in the main memory) and the code in the code cache so that the code can be subsequently retrieved from the code cache when the data is retrieved from the main memory.

[0125] According to one or more embodiments of the present disclosure described above, when a memory controller stores data in a main memory, the memory controller generates a corresponding code and stores it in an auxiliary memory, which can then be used to verify the data when reading the data back from the main memory. In order to reduce the frequency of the additional read latency associated with retrieving the code from the auxiliary memory, in some embodiments, the memory controller also stores the code in a code cache on the memory controller. In some embodiments, the memory controller mitigates the read latency associated with reading the code from the auxiliary memory by forwarding the data read from the main memory and an indication that the data is speculative before completing the error detection and / or correction process (e.g., when there is a code cache miss). In this case, the CPU can be enabled to continue to speculatively execute instructions that depend on the forwarded data. When the error detection and / or correction process is completed, the memory controller outputs a reliability mark indicating whether the previously forwarded data is correct or wrong. If the data is wrong, the CPU rolls back (e.g., reverses) the read operation associated with the data and any speculatively executed instructions that depend on the data.

[0126] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the order opposite to the described order.

[0127] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0128] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there can be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected to one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can also be one or more intervening elements or layers.

[0129] Any functionality described herein, including any functionality that may be implemented by systems 100, 200, and 500, subsystem or device 123, CPU 102, memory controller 110, main memory 116, and / or auxiliary memory 120, and the above descriptions of Figure 1 , Figure 2 and Figure 5 Any functions described in the illustrated embodiments may be implemented by any suitable hardware, software, firmware, or any suitable combination thereof that executes instructions stored in any type of memory, including, for example, hardware and / or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as DRAM and / or SRAM), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory), memory with body resistance change, PCM, etc., and / or any combination thereof, CPLD, FPGA, ASIC, CPU including CISC processor and / or RISC processor, GPU, NPU, TPU, DPU, etc. In some embodiments, one or more components may be implemented as a system on chip (SOC).

[0130] Any CPU 102 and / or any subsystem or device 123 disclosed herein that can implement any functionality described herein related to the intermediate format and / or language can be implemented with any component or combination of components including one or more of a client device, a server, a storage node, a CPU, a personal computer, a tablet computer, a smart phone, etc.

[0131] Any computing device disclosed herein (including CPU 102, memory controller 110, 201 and / or 501, etc.) can be implemented in any form factor (such as 3.5 inches, 2.5 inches, 1.8 inches, M.2, Enterprise and Data Center Standard Form Factor (EDSFF), NF1, etc.) using any connector configuration (such as Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), U.2, etc.). Any computing device disclosed herein can be implemented and / or used in conjunction with, in whole or in part, a server chassis, a server rack, a data room, a data center, an edge data center, a mobile edge data center, and / or any combination thereof.

[0132] Any communication connections and / or communication interfaces disclosed herein, including interfaces 124 and / or 126, may be implemented using any type of interface and / or protocol utilizing one or more interconnects, one or more networks, a network of networks (eg, the Internet), etc., or a combination thereof. Examples may include Peripheral Component Interconnect Express (PCIe), NVMe, NVMe-oF, Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Direct Memory Access (DMA), Remote DMA (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel, InfiniBand, Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), iWARP, Compute Express Link (CXL) and / or coherency protocols (such as CXL.mem, CXL.cache, CXL.IO, etc.), Gen-Z, Open Coherent Accelerator Processor Interface (OpenCAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc., Advanced Extensible Interface (AXI), any generation of wireless networks including 2G, 3G, 4G, 5G, 6G, etc., any generation of Wi-Fi, Bluetooth, Near Field Communication (NFC), etc., or any combination thereof.

[0133] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "comprising", "includes", "including", "has", "have" and "having" specify the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. For example, the statement "A and / or B" means A, B or A and B. Statements such as "at least one of ...", when following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list. For example, the expressions "at least one of a, b or c", "at least one of a, b and c", and "at least one selected from the group consisting of a, b and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0134] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent variations in measurements or calculations that one of ordinary skill in the art will recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0135] Any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware may be utilized to implement the electronic or electrical devices and / or any other related devices or components according to the embodiments of the present disclosure described herein. For example, the various components of these devices may be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program commands, and interact with other system components for performing the various functions described herein. The computer program commands are stored in a memory that may be implemented in a computing device using a standard memory device such as, for example, a random access memory (RAM). The computer program commands may also be stored in other non-transitory computer-readable media such as, for example, a CD-ROM, a flash drive, and the like. In addition, those skilled in the art should recognize that, without departing from the spirit and scope of the exemplary embodiments of the present disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed on one or more other computing devices.

[0136] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0137] Although some embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications are possible in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific embodiments disclosed herein, and that various modifications to the disclosed embodiments and other example embodiments are intended to be included within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. A system for reading data, comprising: Code cache; as well as a memory controller connected to the code cache and configured to: receiving a read command for reading requested data from a location in a main memory connected to the memory controller via a first interface; reading first data stored in the location from the main memory; reading a code corresponding to the requested data associated with the read command from the code cache or from an auxiliary memory connected to the memory controller through a second interface different from the first interface; performing error detection and / or correction based on the first data and the code; selecting second data based on a result of the error detection and / or correction; as well as The second data is outputted for the requested data.

2. The system according to claim 1, wherein: The memory controller is further configured to: Based on the error detection and / or correction, determining that the first data is erroneous; and According to the determination that the first data is erroneous, the second data is selected by selecting third data as the second data, the third data being different from the first data.

3. The system according to claim 2, wherein: The third data includes corrected data generated based on the first data and the code through the error detection and / or correction.

4. The system according to claim 2, wherein: The third data includes an error indicator indicating that the first data is erroneous.

5. The system according to claim 2, wherein: The memory controller is further configured to output the first data and an indication that the first data is speculative for the requested data before the error detection and / or correction is completed, and The third data includes a reliability mark indicating whether the first data is correct or wrong.

6. The system of claim 5, further comprising a processor communicatively connected to the memory controller and configured to: receiving, from the memory controller, the first data and the indication that the first data is speculative; storing the first data and a value of a speculative bit associated with the first data in a load-store queue, the value of the speculative bit corresponding to the indication that the first data is speculative; receiving the third data including the reliability flag from the memory controller; Based on a determination that the reliability flag is a first reliability flag indicating that the first data is correct, changing the value of the speculative bit to indicate that the first data is correct; and Based on a determination that the reliability flag is a second reliability flag indicating that the first data is erroneous, a mis-speculation process associated with the command for reading the requested data is performed.

7. The system according to claim 1, wherein: The memory controller is further configured to: determining, based on the error detection and / or correction, that the first data is correct; and Based on the determination that the first data is correct, the second data is selected by selecting the first data as the second data.

8. The system according to claim 1, wherein: The second interface comprises a cache coherent interconnect.

9. The system according to claim 1, wherein: The code includes an error correction code ECC or a message authentication code MAC.

10. A system for writing data, comprising: Code cache; as well as a memory controller connected to the code cache and configured to: receiving a request to write data to a main memory, wherein the request includes the data; generating a code corresponding to the data based on the data; storing the data in the main memory connected to the memory controller via a first interface; storing the code in an auxiliary memory connected to the memory controller via a second interface; and The codes are stored in the code cache.

11. The system according to claim 10, wherein: The code includes an error correction code ECC or a message authentication code MAC.

12. The system according to claim 10, wherein: The second interface comprises a cache coherent interconnect.

13. The system according to claim 10, wherein: The memory controller is further configured to: An indication of the location of the data in the main memory is stored in the code cache along with the code.

14. The system of claim 10, further comprising: a processor connected to a last level cache LLC, the LLC connected to the memory controller, The memory controller is configured to receive the request via the LLC.

15. The system of claim 10, further comprising: the main memory; as well as The auxiliary memory.

16. A system for verifying data, comprising: Code cache; as well as a memory controller connected to the code cache, wherein the memory controller comprises: an error detection ED code generator configured to generate a code based on the data associated with a request received by the memory controller to write data; and Error checking logic is configured to detect errors in data read from a main memory by the memory controller during a read instruction based on the code generated by the ED code generator and stored in the code cache.

17. The system of claim 16, further comprising: A last level cache LLC, the LLC being connected to the memory controller; as well as a processor coupled to the LLC, wherein the processor includes a load-store queue and a reorder buffer, the load-store queue being configured to store instructions in the order in which they will be committed, the reorder buffer being configured to store instructions speculatively executed by the processor, The processor is configured to read and write memory access instructions to the LLC.

18. The system of claim 16, wherein: The memory controller is connected to the primary memory via a first interface and to an auxiliary memory via a second interface different from the first interface.

19. The system of claim 18, wherein: The error checking logic is configured to detect the error in the data read from the main memory based on a code retrieved from the code cache or the secondary memory.

20. The system of claim 18, wherein: The first interface includes an interface controller connected to the memory controller.

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