System including plurality of hosts and plurality of memory devices and method of operating same

Abstract

A system includes: a plurality of memory devices, each of the plurality of memory devices including a plurality of memory regions; a host configured to communicate with the plurality of memory devices; and a switching circuit configured to store mapping information of a memory area allocated to a host among a plurality of memory areas among the plurality of memory devices, in which a first memory device among the plurality of memory devices is configured to receive at least a portion of the mapping information from the switching circuit, and to switch the first memory device based on the at least a portion of the mapping information. A refresh operation is performed on a plurality of first memory regions in a first memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0119817 filed on September 8, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a computing system, and more particularly, to a system including a plurality of hosts and a plurality of storage devices. Background Art

[0004] A device configured to process data performs various operations by accessing a memory. For example, the device may process data read from the memory, or write processed data to the memory. Due to the performance and functionality required by the system, the system may include various devices that communicate with each other via links that provide high bandwidth and low latency. The memory included in the system is shared and accessed by two or more devices. Therefore, the performance of the system depends not only on the operating speed of each device, but also on the communication efficiency between the devices and the time required for memory access. Summary of the invention

[0005] One or more example embodiments provide a computing system that selectively performs a refresh operation between a plurality of memory devices.

[0006] According to an aspect of an example embodiment, a system includes: a plurality of memory devices, each of the plurality of memory devices including a plurality of storage areas; a host configured to communicate with the plurality of memory devices; and a switch circuit configured to store mapping information of a storage area assigned to the host among a plurality of storage areas in the plurality of memory devices, wherein a first memory device among the plurality of memory devices is configured to receive at least a portion of the mapping information from the switch circuit, and based on at least a portion of the mapping information, perform a refresh operation on a plurality of first storage areas in the first memory device.

[0007] According to one aspect of an example embodiment, a method for operating a system includes: generating allocation information between a plurality of hosts and a plurality of storage devices; providing a first storage device among the plurality of storage devices with partial allocation information in the allocation information related to the first storage device, the first storage device including a plurality of storage areas; based on the partial allocation information, performing a refresh operation on a storage area among the plurality of storage areas in the first storage device that is allocated to at least one of the plurality of hosts; and based on the partial allocation information, skipping a refresh operation on a storage area among the plurality of storage areas in the first storage device that is not allocated to the plurality of hosts.

[0008] According to one aspect of an example embodiment, a system includes: a plurality of hosts; a plurality of storage devices configured to communicate with the plurality of hosts, each of the plurality of storage devices including a plurality of storage areas; and a switch circuit configured to store mapping information about storage areas among the plurality of storage areas in the plurality of storage devices that are assigned to at least one of the plurality of hosts, wherein a first storage device among the plurality of storage devices is configured to receive at least a portion of the mapping information from the switch circuit, and based on at least a portion of the mapping information, perform a refresh operation on the plurality of first storage areas in the first storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and / or other aspects will be more clearly understood through the following detailed description of example embodiments in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a computing system for an application storage system according to one or more embodiments;

[0011] Figure 2 is a block diagram of components of a computing system according to one or more embodiments;

[0012] Figure 3 is a block diagram of a computing system according to one or more embodiments;

[0013] Figure 4 is a diagram for illustrating an H2M mapping table according to one or more embodiments;

[0014] Figure 5 is a block diagram of a computing system according to one or more embodiments;

[0015] Figure 6 is a diagram for illustrating an H2M mapping table according to one or more embodiments;

[0016] Figure 7 is a diagram of a memory chip according to one or more embodiments;

[0017] Figure 8 is a flow chart of a method of operating a memory device according to one or more embodiments;

[0018] Fig. 9 is a circuit diagram for describing the structure of a refresh manager according to one or more embodiments;

[0019] Fig. 10A , Fig. 10B and Fig. 10C is a diagram for describing a method of skipping a refresh operation by using a write flag according to an embodiment;

[0020] Fig.11A and Fig. 11Bis a diagram for describing a write flag of each memory bank according to an embodiment;

[0021] Fig.12 is a block diagram of a computing system according to one or more embodiments;

[0022] Fig.13 is a block diagram of a computing system according to one or more embodiments; and

[0023] Fig.14 is a block diagram of a computing system according to one or more embodiments. DETAILED DESCRIPTION

[0024] Various embodiments of the present disclosure are described below in conjunction with the accompanying drawings.

[0025] It will be understood that although the terms "first", "second", "third", "fourth", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be referred to as a second element, component, region, layer or part.

[0026] It will be understood that when an element or layer is referred to as being "on," "over," "up," "below," "under," "below," "connected to," or "coupled to" another element or layer, it can be directly on, over, over, under, under, below, directly connected to or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "over," "up," "below," "under," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0027] Figure 1 is a block diagram of a computing system 100 to which a storage system is applied according to one or more embodiments.

[0028] Reference Figure 1, computing system 100 may include host 101, multiple storage devices 102a and 102b, storage device 110, and memory 120. In one or more examples, storage device 110 may be a Computer Express Link (CXL) storage device, and memory 120 may be a CXL memory. In one or more examples, CXL is an industry standard interface for high-speed interconnection for communication between processors, accelerators, memory, storage devices, and other IO devices. CXL improves efficiency by allowing composability, scalability, and flexibility of heterogeneous and distributed computing architectures.

[0029] In one or more embodiments, computing system 100 may be included in user devices (e.g., laptops, servers, media players, and digital cameras), or automotive devices (e.g., navigation devices, black boxes, and automotive electronics). In one or more examples, computing system 100 may include a mobile phone, a smart phone, a tablet personal computer, a wearable device, a healthcare device, or a mobile system such as an Internet of Things (IoT) device.

[0030] The host 101 may control the overall operation of the computing system 100. In one or more embodiments, the host 101 may include one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and a data processing unit (DPU). In one or more embodiments, the host 101 may include a single-core processor or a multi-core processor.

[0031] The plurality of memory devices 102a and 102b may be used as a main memory or a system memory of the computing system 100. In one or more embodiments, each of the plurality of memory devices 102a and 102b may include a dynamic random access memory (RAM) (DRAM) device and may have a form factor of a dual in-line memory module (DIMM). However, the scope of the embodiments of the present disclosure is not limited thereto, and the plurality of memory devices 102a and 102b may include a non-volatile memory such as a flash memory, a phase change RAM (PRAM), a resistive RAM (RRAM), and a magnetic RAM (MRAM).

[0032] The plurality of memory devices 102a and 102b may communicate directly with the host 101 via a double data rate (DDR) interface. In one or more embodiments, the host 101 may include a memory controller configured to control the plurality of memory devices 102a and 102b. However, the scope of the embodiments of the present disclosure is not limited thereto, and the plurality of memory devices 102a and 102b may communicate with the host 101 via various interfaces.

[0033] The CXL storage device 110 may include a CXL storage device controller 111 and a non-volatile memory NVM. The CXL storage device controller 111 may store data in the non-volatile memory NVM or transmit data stored in the non-volatile memory NVM to the host 101 according to the control of the host 101. In one or more embodiments, the non-volatile memory NVM may include a NAND flash memory. However, the scope of the embodiments of the present disclosure is not limited thereto.

[0034] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may store data in the buffer memory BFM or transmit data stored in the buffer memory BFM to the host 101 according to the control of the host 101. In one or more embodiments, the buffer memory BFM may include a DRAM, but the scope of the embodiments of the present disclosure is not limited thereto.

[0035] In one or more embodiments, the host 101, the CXL storage device 110, and the CXL memory 120 may be configured to share the same interface. For example, the host 101, the CXL storage device 110, and the CXL memory 120 may communicate with each other via the CXL interface IF_CXL. In one or more embodiments, the CXL interface IF_CXL may support dynamic protocol multiplexing of consistency, memory access, and input / output (I / O) protocols, and may refer to a low-latency and high-bandwidth link that enables various connections between accelerators, memory devices, or various electronic devices.

[0036] In one or more embodiments, the CXL storage device controller 111 may manage data stored in the nonvolatile memory NVM by using mapping data. The mapping data may include information about the relationship between the logical block addresses managed by the host 101 and the physical block addresses of the nonvolatile memory NVM.

[0037] In one or more embodiments, the CXL memory device 110 may not include a separate buffer memory for storing or managing mapping data. In this case, a buffer memory for storing or managing mapping data may be required. In one or more embodiments, at least a portion of the area of ​​the CXL memory 120 may be used as a buffer memory of the CXL memory device 110. In this case, a mapping table managed by the CXL memory device controller 111 of the CXL memory device 110 may be stored in the CXL memory 120. For example, at least a portion of the area of ​​the CXL memory 120 may be allocated by the host 101 as a buffer memory of the CXL memory device 110 (e.g., a dedicated area for the CXL memory device 110). In one or more examples, the portion of the area of ​​the CXL memory 120 may be continuous or discontinuous. For example, the CXL memory 120 may be divided into a plurality of pages, wherein the allocated portion of the area may consist of a group of continuous pages, or a group of pages in which at least one page is discontinuous with other pages in the group of pages.

[0038] In one or more embodiments, the CXL memory device 110 may access the CXL memory 120 via the CXL interface IF_CXL. For example, the CXL memory device 110 may store the mapping table in an allocated area among the areas of the CXL memory 120 or read the stored mapping table. The CXL memory 120 may store data (e.g., mapping data) in the buffer memory BFM or send data (e.g., mapping data) stored in the buffer memory BFM to the CXL memory device 110 according to the control of the CXL memory device 110.

[0039] The CXL storage device controller 111 of the CXL storage device 110 may communicate with the host 101 and the CXL memory 120 (e.g., a buffer memory) via the CXL interface IF_CXL. In one or more examples, the CXL storage device controller 111 of the CXL storage device 110 may communicate with the host 101 and the CXL memory 120 via a homogeneous interface or a common interface, and may use a partial area of ​​the CXL memory 120 as a buffer memory.

[0040] In the following, for ease of description, it is assumed that the host 101, the CXL storage device 110, and the CXL memory 120 communicate with each other via the CXL interface IF_CXL. However, the scope of the embodiments of the present disclosure is not limited thereto, and the host 101, the CXL storage device 110, and the CXL memory 120 may communicate with each other based on various computing interfaces (e.g., GEN-Z protocol, NVLink protocol, Cache Coherent Interconnect for Accelerators (CCIX) protocol, Open Coherent Accelerator Processor Interface (CAPI) protocol, or any other suitable interface known to those of ordinary skill in the art).

[0041] In one or more embodiments of the embodiments of the present disclosure, the CXL memory controller 121 may include a refresh manager 122. The refresh manager 122 may manage refresh operations on a plurality of memories included in the buffer memory BFM. Some of the plurality of memories included in the buffer memory BFM may be allocated to the host 101, and the remaining memories of the plurality of memories may not be allocated to the host 101. The refresh manager 122 may control the buffer memory BFM so that a refresh operation is performed on the memory allocated to the host 101. In addition, the refresh manager 122 may control the buffer memory BFM so that a refresh operation is not performed on the memory not allocated to the host 101. The refresh manager 122 may be implemented as hardware or software, but one or more embodiments are not limited thereto.

[0042] According to one or more embodiments of the present disclosure, since a refresh operation is performed only on a memory allocated to the host 101, power consumed for maintaining data stored in a memory included in the buffer memory BFM may be reduced.

[0043] Figure 2 is a block diagram of components of computing system 100 according to one or more embodiments. Figure 2 yes Figure 1 Detailed block diagram of components of computing system 100 . Figure 2 You can refer to Figure 1 Description will be made and repeated description thereof will be omitted.

[0044] Reference Figure 2 The computing system 100 may include a CXL switch SW_CXL, a host 101 , a CXL storage device 110 , and a CXL memory 120 .

[0045] The CXL switch SW_CXL may include components included in the CXL interface IF_CXL. The CXL switch SW_CXL may be configured to mediate communications between the host 101, the CXL storage device 110, and the CXL memory 120. For example, when the host 101 communicates with the CXL storage device 110, the CXL switch SW_CXL may be configured to send information such as requests, data, replies, and signals sent by the host 101 to the CXL storage device 110 or by the CXL storage device 110 to the host 101. When the host 101 communicates with the CXL memory 120, the CXL switch SW_CXL may be configured to send information such as requests, data, replies, and signals sent by the host 101 to the CXL memory 120 or by the CXL memory 120 to the host 101. When the CXL memory device 110 communicates with the CXL memory 120, the CXL switch SW_CXL may be configured to transmit information such as requests, data, replies, and signals sent from the CXL memory device 110 to the CXL memory 120 or from the CXL memory 120 to the CXL memory device 110. The host 101 may include a CXL host interface (CXL_H I / F) circuit 101a. The CXL_H I / F circuit 101a may communicate with the CXL memory device 110 or the CXL memory 120 via the CXL switch SW_CXL.

[0046] According to one or more embodiments, the CXL storage device 110 may include a CXL storage device controller 111 and a non-volatile memory NVM. The CXL storage device controller 111 may include a CXL storage device interface (CXL_S I / F) circuit 111a, a processor 111b, a RAM 111c, a flash translation layer (FTL) 111d, an error correction code (ECC) engine 111e, and a NAND I / F circuit 111f.

[0047] The CXL_S I / F circuit 111 a may be connected to the CXL switch SW_CXL. The CXL_S I / F circuit 111 a may communicate with the host 101 or the CXL memory 120 via the CXL switch SW_CXL.

[0048] The processor 111 b may be configured to control the overall operation of the CXL storage controller 111. The RAM 111 c may be used as an operation memory or a buffer memory of the CXL storage controller 111.

[0049] The FTL 111d may perform various management operations to effectively use the non-volatile memory NVM. For example, based on the mapping data (or mapping table), the FTL 111d may perform an address conversion between a logical block address managed by the host 101 and a physical block address used by the non-volatile memory NVM. The FTL 111d may perform a bad block management operation on the non-volatile memory NVM. The FTL 111d may perform a wear leveling operation on the non-volatile memory NVM. The FTL 111d may perform a garbage collection operation on the non-volatile memory NVM. In one or more examples, bad block management may include: detecting and marking bad blocks, replacing unusable blocks with reserved extra capacity, and preventing data from being written to bad blocks, thereby improving the reliability of the memory. In one or more examples, the wear leveling operation may be a process for extending the life of a storage device (e.g., NAND flash memory) to ensure that all storage blocks reach their maximum endurance limit specified by the manufacturer. For example, a wear leveling operation may balance the distribution of program / erase operations across all free blocks by writing all new or updated data to free blocks and then erasing blocks containing old data and making the erased blocks available in a pool of free blocks.

[0050] In one or more embodiments, the FTL 111d may be implemented as software, hardware, firmware, or a combination thereof. When the FTL 111d is implemented as software or firmware, program codes associated with the FTL 111d may be stored in the RAM 111c and may be driven by the processor 111b. When the FTL 111d is implemented as hardware, hardware components configured to perform the above-described various management operations may be implemented in the CXL storage device controller 111.

[0051] The ECC engine 111e may perform error detection and correction operations on data stored in the nonvolatile memory NVM. For example, the ECC engine 111e may generate parity bits for user data UD to be stored in the nonvolatile memory NVM, and the generated parity bits may be stored in the nonvolatile memory NVM together with the user data UD. When the user data UD is read from the nonvolatile memory NVM, the ECC engine 111e may detect errors in the user data UD and correct the errors using the parity bits read from the nonvolatile memory NVM along with the read user data UD.

[0052] The NAND I / F circuit 111f can control the nonvolatile memory NVM so that data is stored in the nonvolatile memory NVM or data is read from the nonvolatile memory NVM. In one or more embodiments, the NAND I / F circuit 111f can be implemented to comply with standard practices, such as a switching interface and an open NAND flash memory interface (ONFI). For example, the nonvolatile memory NVM may include multiple NAND flash memories, and when the NAND I / F circuit 111f is implemented based on a switching interface, the NAND I / F circuit 111f can communicate with multiple NAND flash memory devices via multiple channels. Multiple NAND flash memory devices can be connected to multiple channels via a multi-channel-multiplexing structure.

[0053] The nonvolatile memory NVM may store or output user data UD according to the control of the CXL storage device controller 111. The nonvolatile memory NVM may store or output mapping data MD according to the control of the CXL storage device controller 111. In one or more embodiments, the mapping data MD stored in the nonvolatile memory NVM may include mapping information corresponding to all user data UD stored in the nonvolatile memory NVM. The mapping data MD stored in the nonvolatile memory NVM may be stored in the CXL memory 120 at the time of the initialization operation of the CXL storage device 110.

[0054] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may include a CXL memory interface CXL_M I / F circuit 121 a , a processor 121 b , a memory manager 121 c , and a buffer memory I / F circuit 121 d .

[0055] The CXL_M I / F circuit 121 a may be connected to the CXL switch SW_CXL. The CXL_M I / F circuit 121 a may communicate with the host 101 or the CXL memory device 110 via the CXL switch SW_CXL.

[0056] The processor 121b may be configured to control the overall operation of the CXL memory controller 121. The memory manager 121c may be configured to manage the buffer memory BFM. For example, the memory manager 121c may be configured to convert a memory address (e.g., a logical address or a virtual address) accessed from the host 101 or the CXL memory device 110 into a physical address of the buffer memory BFM. In one or more embodiments, the memory address may be an address for managing a storage area of ​​the CXL memory 120, and may be a logical address or a virtual address specified and managed by the host 101.

[0057] The buffer memory I / F circuit 121d may control the buffer memory BFM so that data is stored in the buffer memory BFM or data is read from the buffer memory BFM. In one or more embodiments, the buffer memory I / F circuit 121d may be implemented to comply with standard conventions, such as a DDR interface and a low power DDR (LPDDR) interface.

[0058] The buffer memory BFM may store data or output the stored data according to the control of the CXL memory controller 121. In one or more embodiments, the buffer memory BFM may be configured to store mapping data MD used by the CXL memory device 110. In an initialization operation of the computing system 100 or in an initialization operation of the CXL memory device 110, the mapping data MD may be transferred from the CXL memory device 110 to the CXL memory 120.

[0059] As described above, the CXL storage device 110 according to one or more embodiments may store mapping data MD required for managing the nonvolatile memory NVM via the CXL switch SW_CXL or the CXL interface IF_CXL in the CXL memory 120 connected thereto. Thereafter, when the CXL storage device 110 performs a read operation according to a request of the host 101, the CXL storage device 110 may read at least a portion of the mapping data MD from the CXL memory 120 via the CXL switch SW_CXL or the CXL interface IF_CXL, and perform the read operation based on the read mapping data MD. In one or more examples, when the CXL storage device 110 performs a write operation according to a request of the host 101, the CXL storage device 110 may perform a write operation in the nonvolatile memory NVM and update the mapping data MD. In this case, the updated mapping data MD may be first stored in the RAM 111c of the CXL storage device controller 111, and the mapping data MD stored in the RAM 111c may be transferred to the buffer memory BFM of the CXL memory 120 via the CXL switch SW_CXL or the CXL interface IF_CXL and may be updated.

[0060] In one or more embodiments, a portion of the buffer memory BFM of the CXL memory 120 may be allocated as a dedicated area of ​​the CXL memory device 110 , and the remaining unallocated area may be used as an area accessible to the host 101 .

[0061] In one or more embodiments, the host 101 and the CXL storage device 110 may communicate with each other by using an input / output (I / O) protocol CXL.io. The I / O protocol CXL.io may have an inconsistent I / O protocol based on Peripheral Component Interconnect Express (PCIe). The host 101 and the CXL storage device 110 may transmit and receive user data or various information to and from each other by using the I / O protocol CXL.io.

[0062] In one or more embodiments, the CXL storage device 110 and the CXL memory 120 may communicate with each other by using the memory access protocol CXL.mem. The memory access protocol CXL.mem may include a memory access protocol supporting memory access. By using the memory access protocol CXL.mem, the CXL storage device 110 may access a partial area of ​​the CXL memory 120 (e.g., an area storing mapping data MD, or a CXL storage device dedicated area).

[0063] In one or more embodiments, the host 101 and the CXL memory 120 may communicate with each other by using the memory access protocol CXL.mem. By using the memory access protocol CXL.mem, the host 101 may access the remaining areas of the CXL memory 120 (e.g., the remaining areas except the area storing the mapping data MD or the remaining areas except the CXL memory device dedicated area).

[0064] The above access types (CXL.io, CXL.mem, or any other suitable access type) are merely examples, and the scope of embodiments of the present disclosure is not limited in this regard.

[0065] In one or more embodiments, the CXL storage device 110 and the CXL memory 120 may be installed on a physical port based on a CXL interface (e.g., a PCIe physical port). In one or more embodiments, the CXL storage device 110 and the CXL memory 120 may be implemented based on a form factor (e.g., E1.S, E1.L, E3.S, E3.L, and PCIe AIC (CEM)). In one or more examples, the CXL storage device 110 and the CXL memory 120 may be implemented based on a U.2 form factor, an M.2 form factor, or a form factor based on various other types of PCI2, or various other types of small form factors. The CXL storage device 110 and the CXL memory 120 may support hot-swap that can be installed on or removed from a physical port. Fig.13 Give a detailed description of the hot-swap functionality.

[0066] According to one or more embodiments of the present disclosure, the CXL memory controller 121 may include a refresh manager 122. The refresh manager 122 may control a refresh operation of the buffer memory BFM. The refresh manager 122 may control the buffer memory BFM so as to perform a refresh operation on a memory allocated to the host 101 among a plurality of memories included in the buffer memory BFM, and not perform a refresh operation on the remaining memories (e.g., unallocated memories).

[0067] Figure 3 is a block diagram of a computing system 200 according to one or more embodiments.

[0068] In the embodiments of the present disclosure, the computing system 200 may be referred to as a system. Figure 3 , the computing system 200 may correspond to Figure 2 A computing system 100 is provided. Figure 3 The computing system 200 may include first to j-th hosts (host 1) 210_1 to 210_j (for example, j is an integer of 2 or more), a CXL switch SW_CXL, and first to k-th storage devices (storage device 1) 230_1 to 230_k (for example, k is an integer of 2 or more). In this case, the number of hosts 1 210_1 to 210_j may be different from the number of storage devices 1 230_1 to 230_k. Figure 3 Each of the illustrated memory device 1 230_1 through memory device k 230 — k may correspond to the CXL memory 120 or a peripheral device that communicates via the CXL interface IF_CXL and performs a refresh operation.

[0069] Host 1 210_1 - host j 210_j may be configured to communicate with memory device 1 230_1 - memory device k 230_k via CXL switch SW_CXL. A host requiring memory allocation may send a memory allocation request to the CXL switch SW_CXL.

[0070] Figure 3 The CXL switch SW_CXL in can correspond to Figure 1 In the embodiment of the present disclosure, the CXL switch SW_CXL may be referred to as a switch or a switch circuit. The CXL switch SW_CXL may be configured to provide connections between the host 1 210_1 to the host j 210_j and the memory device 1 230_1 to the memory device k 230_k.

[0071] The CXL switch SW_CXL may include a fabric manager 221. The fabric manager 221 may allocate storage devices 1 230_1 to storage devices k 230_k to hosts 1 210_1 to hosts j 210_j in response to memory allocation requests received from hosts 1 210_1 to hosts j 210_j. For example, the fabric manager 221 may allocate storage devices to hosts based on category information of applications executed by the hosts, performance information required by the hosts, and the like.

[0072] When storage devices 1 230_1 to 230_k are connected to the CXL switch SW_CXL, fabric manager 221 may allocate storage devices 1 230_1 to 230_k to hosts 1 210_1 to 210_j based on device information received from storage devices 1 230_1 to 230_k. In one or more embodiments, the device information may be referred to as device status information, state information, or health information.

[0073] The fabric manager 221 may manage mapping between the host and the storage device based on the host-memory mapping table 222_1. The fabric manager 221 may be implemented as software, hardware, firmware, or a combination thereof.

[0074] The memory device 1 230_1 may include a memory controller 231 and a memory pool 232, and the memory pool 232 may correspond to a buffer memory BFM. The memory pool 232 may include a plurality of memory blocks. The memory block may be a unit that logically divides the memory pool 232. For example, the memory block may correspond to Figure 7 The memory chip 500 and one of the first to fourth memory bank arrays 700a to 700d.

[0075] In an embodiment of the present disclosure, allocating a storage device to a host may refer to allocating at least one storage block included in a memory pool of the storage device to the host.

[0076] exist Figure 3 , storage device 1 230_1 and storage device 2 230_2 may be assigned to host 1 210_1, and storage device 3 230_3 and storage device 4 230_4 may be assigned to host 2 210_2. Storage device 5 230_5 to storage device k 230_k may not be assigned to host 3 210_3 to host j 230_j. Storage device k 230_k may not be assigned to host 1 210_1 to host j 210_j. As will be understood by those skilled in the art, these assignments are merely examples.

[0077] Figure 4is a diagram for explaining an H2M mapping table according to one or more embodiments. Figure 4 You can refer to Figure 3 to describe.

[0078] Reference Figure 4 , the H2M mapping table may include information of the host to which the storage device is assigned. For example, storage device 1 230_1 and storage device 2 230_2 may be assigned to host 1 210_1, and storage device 3 230_3 and storage device 4 230_4 may be assigned to host 2 210_2. Figure 3 As described, storage device k 230_k may not be assigned to any other host.

[0079] In some embodiments, the H2M mapping table may include information about an allocation flag. The allocation flag may indicate whether a storage device is allocated to a host. For example, when a storage device is allocated to a host, the allocation flag of the corresponding storage device may be "1", but when the storage device is not allocated to a host, the allocation flag of the corresponding storage device may be "0".

[0080] However, one or more embodiments are not limited thereto, and the H2M mapping table may not include an allocation flag.

[0081] Figure 5 2 is a block diagram of a computing system 200 according to one or more embodiments. The description of memory device 1 230_1 may also be applied to memory device 2 230_2 through memory device k 230_k.

[0082] Reference Figure 5 , the memory pool 232 may include the first memory chip M_CHIP1 to the sixth memory chip M_CHIP6. The number of memory chips included in the memory pool 232 is not limited thereto. The first memory chip M_CHIP1 and the second memory chip M_CHIP2 may be assigned to the host 1 210_1. The fourth memory chip M_CHIP4 and the fifth memory chip M_CHIP5 may be assigned to the host 2 210_2. The third memory chip M_CHIP3 and the sixth memory chip M_CHIP6 may be in a state of not being assigned to any host.

[0083] The refresh manager 233 may generate an internal refresh command so that refresh operations are performed on the first to fifth memory chips M_CHIP1 , M_CHIP2 , M_CHIP4 , and M_CHIP5 , and refresh operations are not performed on the third to sixth memory chips M_CHIP3 and M_CHIP6 .

[0084] Figure 6is a diagram for explaining an H2M mapping table according to one or more embodiments. Figure 5 describe Figure 6 .

[0085] Reference Figure 6 , the H2M mapping table may include information of hosts to which multiple memory devices are assigned. For example, the first memory chip M_CHIP1 and the second memory chip M_CHIP2 may be assigned to the host 1 210_1, and the fourth memory chip M_CHIP4 and the fifth memory chip M_CHIP5 may be assigned to the host 2 210_2. Figure 5 As described above, the third memory chip M_CHIP3 and the sixth memory chip M_CHIP6 may not be allocated to any host. The third memory chip M_CHIP3 may be in an allocation released state, and the sixth memory chip M_CHIP6 may be in an unallocated history state.

[0086] In some embodiments, the H2M mapping table may include information about an allocation flag. The allocation flag may indicate whether a memory chip is allocated to a host. For example, when a memory chip is allocated to a host, the allocation flag of the corresponding memory chip may be "1", but when the memory chip is not allocated to a host, the allocation flag of the corresponding memory chip may be "0".

[0087] However, one or more embodiments are not limited thereto, and the H2M mapping table may not include an allocation flag.

[0088] Figure 7 is a diagram of a memory chip 500 according to one or more embodiments.

[0089] Reference Figure 7 , the memory chip 500 may include a control logic circuit 510, an address buffer 520, a bank control logic circuit 530, a row address (RA) multiplexer (MUX) (RA MUX) 540, a column address (CA) latch (CA latch) 550, a row decoder 560, a column decoder 570, a memory cell array 600, a sense amplifier (AMP) 585, an input / output (I / O) gating circuit 590, a data I / O buffer 595, and a refresh counter 545. In an embodiment of the present disclosure, a memory block or a memory chip may be referred to as a memory region.

[0090] The memory cell array 600 may include first to fourth memory cell arrays 600a to 600d. In one or more examples, the row decoder 560 may include first to fourth memory cell row decoders 560a to 560d connected to the first to fourth memory cell arrays 600a to 600d, respectively, the column decoder 570 may include first to fourth memory cell column decoders 570a to 570d connected to the first to fourth memory cell arrays 600a to 600d, respectively, and the sense AMP 585 may include first to fourth memory cell sense AMPs 585a to 585d connected to the first to fourth memory cell arrays 600a to 600d, respectively.

[0091] The first memory bank array 600a to the fourth memory bank array 600d, the first memory bank sense AMP 585a to the fourth memory bank sense AMP 585d, the first memory bank column decoder 570a to the fourth memory bank column decoder 570d, and the first memory bank row decoder 560a to the fourth memory bank row decoder 560d may each constitute the first memory bank to the fourth memory bank. Each of the first memory bank array 600a to the fourth memory bank array 600d may include a plurality of word lines and a plurality of bit lines, and a plurality of memory cells formed at points where the word lines and the bit lines intersect.

[0092] Figure 7 An example of a memory chip 500 including four memory banks is shown in FIG. 5 , but according to one or more embodiments, the memory chip 500 may include any number of memory banks.

[0093] The address buffer 520 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 231. The address buffer 520 may provide the received bank address BANK_ADDR to the bank control logic circuit 530, provide the received row address ROW_ADDR to the RA MUX 540, and provide the received column address COL_ADDR to the CA latch 550.

[0094] The bank control logic circuit 530 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, a bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 560a to the fourth bank row decoder 560d may be activated, and a bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 570a to the fourth bank column decoder 570d may be activated.

[0095] The RAM MUX 540 may receive a row address ROW_ADDR from the address buffer 520 and may receive a refresh row address REF_ADDR from the refresh counter 545. The RA MUX 540 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output by the RA MUX 540 may be applied to each of the first to fourth bank row decoders 560a to 560d.

[0096] The bank row decoders activated by the bank control logic circuit 530 among the first bank row decoders 560a to the fourth bank row decoders 560d may decode the row address RA output by the RA MUX 540 and activate a word line corresponding to the row address RA. For example, the activated bank row decoders may apply a word line drive voltage to the word line corresponding to the row address RA. The activated bank row decoders may generate a word line drive voltage by using the power supply voltage VDD and may provide the word line drive voltage to the corresponding word line.

[0097] The CA latch 550 may receive a column address COL_ADDR from the address buffer 520 and may temporarily store the received column address COL_ADDR or the mapped column address MCA. In one or more examples, the CA latch 550 may gradually increase the received column address COL_ADDR in a burst mode. The CA latch 550 may apply the column address COL_ADDR, which may be temporarily stored or gradually increased, to each of the first to fourth bank column decoders 570a to 570d.

[0098] The bank column decoders activated by the bank control logic circuit 530 among the first to fourth bank column decoders 570 a to 570 d may activate a sense AMP corresponding to the bank address BANK_ADDR and the column address COL_ADDR via the I / O gating circuit 590 .

[0099] The I / O gating circuit 590 may include a circuit for gating I / O data, a read data latch for storing data output by the first to fourth memory bank arrays 600a to 600d, and a write driver for writing data into the first to fourth memory bank arrays 600a to 600d.

[0100] Data read from one bank array among the first to fourth bank arrays 600 a to 600 d may be sensed by a sense amplifier corresponding to the one bank array and stored in a read data latch.

[0101] The data stored in the read data latch may be provided to the memory controller 231 via the data I / O buffer 595. Data to be written to one of the first to fourth memory bank arrays 600a to 600d may be provided to the data I / O buffer 595 from the memory controller 231. The data provided to the data I / O buffer 595 may be provided to the I / O gating circuit 590.

[0102] The control logic circuit 510 may control the operation of the memory chip 500. For example, the control logic circuit 510 may generate a control signal so that the memory chip 500 performs a write operation or a read operation. The control logic circuit 510 may include a command decoder 511 for decoding a command CMD received by the memory controller 231, and a mode register 512 for setting an operation mode of the memory chip 500.

[0103] When a refresh command (eg, Figure 8 , the memory chip 500 may perform a refresh operation on the memory cell array corresponding to the refresh address REF_ADDR when the first internal refresh command in the refresh address REF_ADDR is executed. The refresh operation may include an automatic refresh operation and a self-refresh operation. The automatic refresh operation may generate a refresh address REF_ADDR in response to a refresh command applied periodically, and may refresh a memory cell row corresponding to the refresh address REF_ADDR. The self-refresh operation may correspond to an operation of entering a self-refresh mode in response to a self-refresh entry command, and in the self-refresh mode, a memory cell row is refreshed by using a built-in timer.

[0104] Figure 8 is a flow chart of an operating method of a memory device according to one or more embodiments. Figure 5 describe Figure 8 .

[0105] The memory controller 231 included in the memory device 1 230_1 may obtain a portion of the H2M mapping information from the CXL switch SW_CXL (S810). Figure 6The memory controller 231 may obtain information about the host to which the memory device 1230_1 has been assigned by the H2M mapping table. According to the H2M mapping information obtained by the memory device 1 230_1, the first memory chip M_CHIP1 and the second memory chip M_CHIP2 may be assigned to the host 1 210_1, the fourth memory chip M_CHIP4 and the fifth memory chip M_CHIP5 may be assigned to the host 2 210_2, and the third memory chip M_CHIP3 and the sixth memory chip M_CHIP6 may be in a state of not being assigned to any host. The memory controller 231 may obtain an allocation flag. In some embodiments, the memory controller 231 may receive information about the allocation flag from the CXL switch SW_CXL. In some embodiments, the memory controller 231 may generate an allocation flag based on the mapping information between the memory chip and the host.

[0106] The memory controller 231 may generate a refresh command for requesting a refresh operation of at least one of the first to sixth memory chips M_CHIP1 to M_CHIP6 included in the memory device 1 230_1 (S820). The refresh command may be generated at preset time intervals.

[0107] When the allocation flag corresponding to the memory chip is "1", the memory device 1 230_1 may perform a refresh operation on the corresponding memory chip (S840). The memory controller 231 may provide a refresh command to the memory chip whose allocation flag is "1" (eg, S830=Y), and the memory chip having received the refresh command may perform a refresh operation.

[0108] When the allocation flag corresponding to the memory chip is "0" (e.g., S830=N), the memory device 1 230_1 may skip the refresh operation on the corresponding memory chip (S850). The memory controller 231 may not provide a refresh command to the memory chip whose allocation flag is "0". However, the embodiment is not limited thereto, and although the memory controller 231 may provide a refresh command to the memory chip whose allocation flag is "0", the memory controller 231 may also skip the refresh operation inside the memory chip.

[0109] Fig. 9 2 is a circuit diagram for describing the structure of the refresh manager 233 according to one or more embodiments. Figure 5 describe Fig. 9 .

[0110] Reference Fig. 9The refresh manager 233 may receive the refresh command and generate first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6. The first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6 may be provided to the first to sixth memory chips M_CHIP1 to M_CHIP6, respectively.

[0111] The refresh manager 233 may include first to sixth AND gates 911 to 916. The first to sixth AND gates 911 to 916 may receive a refresh command in common and receive first to sixth allocation flags ALLOC_FLAG1 to ALLOC_FLAG6, respectively. The first to sixth AND gates 911 to 916 may output first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6, respectively. Each of the first to sixth AND gates 911 to 916 may perform an AND operation on a refresh command and an allocation flag corresponding to the refresh command, and output a corresponding internal refresh command. In an embodiment of the present disclosure, the AND gate may be referred to as a selection circuit.

[0112] For example, Figure 5 As shown, when the first memory chip M_CHIP1 is assigned to the host 1210_1, the first allocation flag may be "1", and the first internal refresh command INT_REF_CMD1 may be the same as the refresh command. On the other hand, because the third memory chip M_CHIP3 is not assigned to the host, the third allocation flag ALLOC_FAG3 may be "0", and the third internal refresh command INT_REF_CMD3 may be maintained at a logic low.

[0113] Fig. 10A , Fig. 10B and Fig. 10C 2 is a diagram for describing a method for skipping a refresh operation by using a write flag according to an embodiment. Figure 5 describe Fig. 10A .

[0114] Reference Fig. 10A , the refresh manager 233 may store write information. The write information may indicate whether a write operation has been performed on the first to sixth memory chips M_CHIP1 to M_CHIP6.

[0115] When a write operation is performed on the memory chip, the write flag WR_FLAG corresponding to the corresponding memory chip may be '1', and when a write operation is not performed on the memory chip, the write flag WR_FLAG corresponding to the corresponding memory chip may be '0'.

[0116] Reference Fig. 10B , the refresh manager 233 may generate first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6 based on the first to sixth write flags WR_FLAG1 to WR_FLAG6. The first to sixth write flags WR_FLAG1 to WR_FLAG6 may correspond to the first to sixth memory chips M_CHIP1 to M_CHIP6, respectively. The first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6 may be provided to the first to sixth memory chips M_CHIP1 to M_CHIP6, respectively.

[0117] The refresh manager 233 may include first to sixth AND gates 1011 to 1016. The first to sixth AND gates 1011 to 1016 may receive a refresh command in common and receive first to sixth write flags WR_FLAG1 to WR_FLAG6, respectively. The first to sixth AND gates 1011 to 1016 may output first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6, respectively. Each of the first to sixth AND gates 1011 to 1016 may perform an AND operation on a refresh command and a write flag corresponding to the refresh command, and output a corresponding internal refresh command.

[0118] For example, Fig. 10A As shown, when the first memory chip M_CHIP1, the second memory chip M_CHIP2, the fourth memory chip M_CHIP4 and the fifth memory chip M_CHIP5 are in a state where a write operation has been performed, the first write flag WR_FLAG1, the second write flag WR_FLAG2, the fourth write flag WR_FLAG4 and the fifth write flag WR_FLAG5 can be "1", and the first internal refresh command INT_REF_CMD1, the second internal refresh command INT_REF_CMD2, the fourth internal refresh command INT_REF_CMD4 and the fifth internal refresh command INT_REF_CMD5 can be the same as the refresh command. On the other hand, when the third memory chip M_CHIP3 and the sixth memory chip M_CHIP6 are in a state where a write operation has not been performed, the third write flag WR_FLAG3 and the sixth write flag WR_FLAG6 can be "0", and the third internal refresh command INT_REF_CMD3 and the sixth internal refresh command INT_REF_CMD6 can be maintained at a logic low.

[0119] When allocation of the first memory device or the first to sixth memory chips M_CHIP1 to M_CHIP6 is released, the refresh manager 233 may skip a refresh operation of the memory chip whose allocation is released by resetting the write flag to '0'.

[0120] Reference Fig. 10C , the refresh manager 233 may generate first to sixth internal refresh commands INT_REF_CMD1 to INT_REF_CMD6 based on the first to sixth allocation flags ALLOC_FLAG1 to ALLOC_FLAG6 and the first to sixth write flags WR_FLAG1 to WR_FLAG6, respectively.

[0121] The refresh manager 233 may include first to sixth AND gates 1111 to 1116. The first to sixth AND gates 1111 to 1116 may receive a refresh command. Each of the first to sixth AND gates 1111 to 1116 may perform an AND operation on the refresh command, a write flag corresponding to the refresh command, and a write flag corresponding to the refresh command, and output an internal refresh command corresponding to the result of the operation.

[0122] Fig.11A and Fig. 11B 2 is a diagram for describing a write flag WR_FLAG_BK of each memory bank according to an embodiment. Figure 7 describe Fig.11A and Fig. 11B .

[0123] Reference Figure 7 and Fig.11A , the control logic circuit 510 may store the bank write information BANK WRITE INFO. The bank write information BANK WRITE INFO may include a bank write flag WR_FLAG_BK indicating whether a write operation has been performed on the first bank array 600a to the fourth bank array 600d. For example, when a write operation has been performed on the first bank array 600a and the second bank array 600b, the first bank write flag WR_FLAG_BK1 and the second bank write flag WR_FLAG_BK2 are "1", and when a write operation has not been performed on the third bank array 600c and the fourth bank array 600d, the third bank write flag WR_FLAG_BK3 and the fourth bank write flag WR_FLAG_BK4 may be "0".

[0124] exist Fig.11A In the figure, only the information included in the storage device 1 ( Figure 5The bank write information of the first memory chip M_CHIP1 in the memory device 230_1) is stored, but one or more embodiments are not limited thereto. Any memory chip included in the memory device 2 230_2 to the memory device k 230_k may store the bank write information.

[0125] Reference Fig. 11B , the memory chip 500 may receive the first internal refresh command INT_REF_CMD1, and based on the first to fourth bank refresh control signals REF_BK1 to REF_BK4, the memory chip 500 may control refresh operations on the first to fourth bank arrays 600a to 600d.

[0126] The memory chip 500 may include first to fourth AND gates 1211 to 1214. The first to fourth AND gates 1211 to 1214 may receive the first internal refresh command INT_REF_CMD1 together, and may receive the first to fourth memory write flags WR_FLAG_BK1 to WR_FLAG_BK4, respectively. The first to fourth AND gates 1211 to 1214 may generate first to fourth memory refresh control signals REF_BK1 to REF_BK4, respectively. Each of the first to fourth AND gates 1211 to 1214 may generate a corresponding memory refresh control signal by executing the first internal refresh command INT_REF_CMD1 and performing an AND operation on the first internal refresh command INT_REF_CMD1 and the memory write flag corresponding to the first internal refresh command INT_REF_CMD1. In some embodiments, the first to fourth AND gates 1211 to 1214 may be included in the memory control logic circuit 530. The bank control logic circuit 530 may control the row decoder 560 and the column decoder 570 so that a bank array corresponding to a result of the AND operation of “1” is activated.

[0127] Fig.12 1 is a block diagram of a computing system 1200 according to one or more embodiments. Hereinafter, for convenience of description, detailed descriptions of repeated components are omitted.

[0128] Reference Fig.12 , the computing system 1200 may include a host 1201 , a plurality of storage devices 1202 a and 1202 b , a CXL switch SW_CXL, a plurality of CXL storage devices 1210_1 to 1210 — m , and a plurality of CXL memories 1220_1 to 1220 — n .

[0129] The host 1201 may be directly connected to the plurality of storage devices 1202a and 1202b. The host 1201, the plurality of CXL storage devices 1210_1 to 1210_m, and the plurality of CXL memories 1220_1 to 1220_n may be connected to a CXL switch SW_CXL, and each of them may communicate with each other via the CXL switch SW_CXL.

[0130] In one or more embodiments, the host 1201 may manage the plurality of CXL storage devices 1210_1 to 1210_m as a storage device cluster, and may manage the plurality of CXL memories 1220_1 to 1220_n as a storage cluster. The host 1201 may allocate some areas of the storage cluster as dedicated areas with respect to the one storage device cluster (e.g., areas for storing mapping data of the storage device cluster). In one or more examples, the host 1201 may allocate each area of ​​the plurality of CXL memories 1220_1 to 1220_n as a dedicated area with respect to the plurality of CXL storage devices 1210_1 to 1210_m.

[0131] Fig.13 13 is a block diagram of a computing system 1300 according to one or more embodiments. Hereinafter, for convenience of description, detailed descriptions of repeated components are omitted.

[0132] Reference Fig.13 , the computing system 1300 may include a host 1301 , a plurality of storage devices 1302 a and 1302 b , a CXL switch SW_CXL, a plurality of CXL storage devices 1310_1 , 1310_2 , and 1310_3 , and a plurality of CXL memories 1320_1 , 1320_2 , and 1320_3 .

[0133] The host 1301 may be directly connected to the plurality of storage devices 1302a and 1302b. The host 1301, the plurality of CXL storage devices 1310_1 and 1310_2, and the plurality of CXL memories 1320_1 and 1320_2 may be connected to the CXL switch SW_CXL, and each of them may communicate with each other via the CXL switch SW_CXL. Similar to the description given above, some areas of the plurality of CXL memories 1320_1 and 1320_2 may be allocated as dedicated areas of the plurality of CXL storage devices 1310_1 and 1310_2.

[0134] In one or more embodiments, when the computing system 1300 is operating, some regions of the plurality of CXL storage devices 1310_1 and 1310_2 or some regions of the plurality of CXL memories 1320_1 and 1320_2 may be connected or hot-removed from the CXL switch SW_CXL. In one or more examples, when the computing system 1300 is operating, a portion of the CXL storage device 1310_3 or a portion of the CXL memory 1320_3 may be connected or hot-added to the CXL switch SW_CXL. In this case, the host 1301 may perform memory allocation again by performing an initialization operation again on the device connected to the CXL switch SW_CXL using a reset operation or a hot-plug operation. In one or more examples, the CXL storage device and the CXL memory according to one or more embodiments of the embodiments of the present disclosure may support a hot-plug function and expand the storage device capacity and the memory capacity of the computing system by using various connections.

[0135] Fig.14 1400 according to one or more embodiments. Detailed descriptions of repeated components are omitted hereinafter for convenience of description.

[0136] Reference Fig.14 The computing system 1400 may include a first CPU CPU#1 1510 , a second CPU CPU#2 1520 , a GPU 1530 , an NPU 1540 , a CXL switch SW_CXL, a CXL storage device 1610 , a CXL memory 1620 , a PCIe device 1710 , and an accelerator (CXL device) 1720 .

[0137] The first CPU CPU#1 1510, CPU#2 1520, GPU 1530, NPU 1540, CXL switch SW_CXL, CXL storage device 1610, CXL memory 1620, PCIe device 1710, and accelerator (CXL device) 1720 may be commonly connected to the CXL switch SW_CXL, and each of them may communicate with each other via the CXL switch SW_CXL.

[0138] In one or more embodiments, each of CPU#1 1510, CPU#2 1520, GPU 1530, and NPU 1540 may include a reference Figures 1 to 8 described hosts, and each of them can be directly connected to a separate storage device.

[0139] In one or more embodiments, CXL memory 1620 may include reference Figures 1 to 11BThe CXL memory described above can allocate at least some areas of the CXL memory 1620 as a dedicated area of ​​the CXL storage device 1610 by using any one or more of the CPU #1 1510, the CPU #2 1520, the GPU 1530, and the NPU 1540. In one or more examples, the CXL storage device 1610 and the CXL memory 1620 can be used as a storage space STR of the computing system 1400.

[0140] In one or more embodiments, the CXL switch SW_CXL may be connected to a PCIe device 1710 or an accelerator (CXL device) 1720 configured to support various functions, and the PCIe device 1710 or the accelerator (CXL device) 1720 may communicate with each of the CPU #1 1510 , the CPU #2 1520 , the GPU 1530 , and the NPU 1540 via the CXL switch SW_CXL, or access a storage space STR including the CXL storage device 1610 and the CXL memory 1620 .

[0141] In one or more embodiments, the CXL switch SW_CXL may be connected to an external network or fabric, and may be configured to communicate with an external server via the external network or fabric.

[0142] While embodiments of the present disclosure have been particularly shown and described with reference thereto, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A system for selectively performing a refresh operation between a plurality of memory devices, comprising: a plurality of storage devices, each of the plurality of storage devices comprising a plurality of storage areas; a host configured to communicate with the plurality of storage devices; as well as a switch circuit configured to store mapping information of a storage area allocated to the host among the plurality of storage areas in the plurality of storage devices, A first storage device among the plurality of storage devices is configured to receive at least a portion of the mapping information from the switch circuit, and perform a refresh operation on a plurality of first storage regions in the first storage device based on the at least a portion of the mapping information.

2. The system according to claim 1, wherein: The first storage device is further configured as: performing the refresh operation on a first storage area allocated to the host among the plurality of first storage areas, and The refresh operation on a first storage area that is not allocated to the host among the plurality of first storage areas is skipped.

3. The system according to claim 1, wherein: The first storage device includes a memory controller configured to provide a refresh command to the plurality of first storage areas based on an allocation flag indicating whether the plurality of first storage areas are allocated to the host.

4. The system according to claim 3, wherein: The memory controller includes a plurality of first selection circuits, each of the plurality of first selection circuits corresponding to a respective storage area of ​​the plurality of first storage areas, The plurality of first selection circuits receive the refresh command together, and Among them, each of the multiple first selection circuits is configured to: generate an internal refresh command based on the refresh command and the allocation flag indicating whether the corresponding first storage area among the multiple first storage areas is allocated to the host, and output the internal refresh command to the corresponding first storage area.

5. The system according to claim 4, wherein: Each of the plurality of first selection circuits is further configured to generate the internal refresh command based on a write flag indicating whether a write operation has been performed in the corresponding first storage area, and output the internal refresh command to the corresponding first storage area.

6. The system according to claim 5, wherein: Based on the allocation between at least one first storage area among the plurality of first storage areas and the host being released, the write flag of the at least one first storage area whose allocation is released is reset.

7. The system according to claim 4, wherein: The corresponding first storage area includes: a plurality of memory arrays, each of the plurality of memory arrays comprising memory cells; and A plurality of second selection circuits, each of the plurality of second selection circuits being configured to generate a control signal for controlling the refresh operation on the corresponding memory array based on the internal refresh command and a write flag indicating whether a write operation has been performed on the corresponding memory array.

8. The system according to claim 7, wherein: Based on the allocation between the corresponding first storage area and the host being released, the write flags of the plurality of memory arrays are reset.

9. A method for operating a system for selectively performing a refresh operation between a plurality of memory devices, the method comprising: generating allocation information between a plurality of hosts and a plurality of storage devices; providing a portion of the allocation information related to the first storage device to a first storage device among the plurality of storage devices, the first storage device including a plurality of storage areas; performing a refresh operation on a storage area among the plurality of storage areas in the first storage device that is allocated to at least one of the plurality of hosts based on the partial allocation information; as well as The refresh operation on a storage area that is not allocated to the plurality of hosts among the plurality of storage areas in the first storage device is skipped based on the partial allocation information.

10. The operating method according to claim 9, wherein: Performing the refresh operation includes providing a refresh command to at least one of the plurality of storage areas based on an allocation flag indicating whether the plurality of storage areas have been allocated to at least one of the plurality of hosts.

11. The operating method according to claim 10, wherein: Providing the refresh command to the plurality of storage areas comprises: generating an internal refresh command based on the refresh command and the allocation flag; and The internal refresh command is provided to a first storage area among the plurality of storage areas that is allocated to at least one host among the plurality of hosts.

12. The operating method according to claim 11, wherein: Generating the internal refresh command includes generating the internal refresh command based on a write flag indicating whether a write operation has been performed on the plurality of storage areas.

13. The operating method according to claim 12, further comprising: Based on the allocation between at least one storage area among the plurality of storage areas and at least one host among the plurality of hosts being released, the write flag of the at least one storage area whose allocation is released is reset.

14. The operating method according to claim 11, further comprising: A control signal for controlling a refresh operation on the plurality of memory arrays in the first storage area is generated based on the internal refresh command and a write flag indicating whether a write operation has been performed on the plurality of memory arrays in the first storage area.

15. The operating method according to claim 14, further comprising: Based on allocation between the first storage area and the plurality of hosts being released, the write flags of the plurality of memory arrays are reset.

16. A system for selectively performing a refresh operation between a plurality of memory devices, comprising: Multiple hosts; a plurality of storage devices configured to communicate with the plurality of hosts, each of the plurality of storage devices comprising a plurality of storage areas; as well as a switch circuit configured to store mapping information about a storage area among the plurality of storage areas in the plurality of storage devices that is allocated to at least one of the plurality of hosts, A first storage device among the plurality of storage devices is configured to receive at least a portion of the mapping information from the switch circuit, and perform a refresh operation on a plurality of first storage regions in the first storage device based on the at least a portion of the mapping information.

17. The system of claim 16, wherein: The first storage device is further configured as: performing the refresh operation on a first storage area among the plurality of first storage areas that is allocated to at least one host among the plurality of hosts; as well as The refresh operation on a first storage area that is not allocated to the plurality of hosts among the plurality of first storage areas is skipped.

18. The system of claim 16, wherein: The first storage device includes a memory controller configured to provide a refresh command to the plurality of first storage regions based on an allocation flag indicating whether the plurality of first storage regions have been allocated to at least one of the plurality of hosts.

19. The system of claim 18, wherein: The memory controller includes a plurality of first selection circuits, each of the plurality of first selection circuits corresponding to a respective storage area of ​​the plurality of first storage areas, The plurality of first selection circuits receive the refresh command together, and Wherein, each of the multiple first selection circuits is configured to: generate an internal refresh command based on the refresh command and the allocation flag indicating whether the corresponding first storage area among the multiple first storage areas has been allocated to the host, and output the internal refresh command to the corresponding first storage area.

20. The system of claim 19, wherein: Each of the plurality of first selection circuits is further configured to generate an internal refresh command based on a write flag indicating whether a write operation has been performed in the corresponding first storage region, and output the internal refresh command to the corresponding first storage region.

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