Processing method and device for obtaining environment, verification method, equipment and storage medium

Abstract

The invention provides an acquisition environment processing method and device, a verification method, equipment and a storage medium. The processing method comprises the steps that a first verification intellectual property module used for a to-be-tested object is acquired, and the first verification intellectual property module comprises one or more verification intellectual property modules based on general verification methodology; classifying the first verification intellectual property module to obtain a classified second verification intellectual property module; and performing generalization processing based on the second verification intellectual property module to realize integration of the verification intellectual property module for different levels of verification environments. According to the method and the device, the intellectual property verification module is classified and then universalized, so that corresponding integration can be carried out according to the application scene of the intellectual property verification module, and the method and the device have good inheritance and good expandability.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method and apparatus for obtaining a processing environment, a verification method, a device, and a storage medium. Background Art

[0002] As semiconductor processes and application computing power requirements continue to increase, the scale and complexity of chip design continue to increase. Verification work needs to match the design. In order to cope with increasingly complex designs, the verification environment has also changed from a simple environment to an increasingly complex verification environment. The time and difficulty required to build a complete verification environment are also increasing.

[0003] System-on-a-chip (SOC) contains many standardized functional design modules and bus protocols. As the protocol standards are constantly updated, the design of IP (Intellectual Property) modules and verification environments need to be synchronized with the standards, which poses a greater challenge to the timely delivery of chips. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a method for obtaining a processing environment, comprising: obtaining a first verification intellectual property module for an object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; classifying the first verification intellectual property module to obtain a classified second verification intellectual property module; and performing generalization processing based on the second verification intellectual property module to achieve integration of verification intellectual property modules for verification environments of different levels.

[0005] For example, in a processing method provided by at least one embodiment of the present disclosure, obtaining a first verification intellectual property module for the object to be tested includes: obtaining the first verification intellectual property module of the object to be tested in a first verification environment, wherein the first verification environment is the initial environment of the object to be tested.

[0006] For example, in a processing method provided by at least one embodiment of the present disclosure, obtaining a first verification intellectual property module for an object to be tested includes: obtaining at least one of a first top-level module, a first object to be tested encapsulation module, a first test case layer module, a first master or slave device-side environment layer module, a first master or slave device-side configuration module, and a first interface module to obtain the first verification intellectual property module, wherein the first master or slave device-side environment module includes a library, an agent, a sequencer, and a scoreboard.

[0007] For example, in a processing method provided by at least one embodiment of the present disclosure, the first verification intellectual property module is classified to obtain the classified second verification intellectual property module, including: obtaining at least one of a second top-level module, a second object encapsulation module, a second test case layer module, a second master or slave device-side environment and configuration module, a second interface module, and an encryption library and a non-encryption library module to obtain the second verification intellectual property module, wherein the second top-level module is configured to be obtained based on the first top-level module, the second object encapsulation module is configured to be obtained based on the first object encapsulation module, the second test case layer module is configured to be obtained based on the first test case layer module, the second master or slave device-side environment and configuration module is configured to be obtained based on the first master or slave device-side environment layer module and the first master or slave device-side configuration module, the second interface module is configured to be obtained based on the first interface module, and the encryption library and the non-encryption library module are configured to be obtained based on the library for classification.

[0008] For example, in a processing method provided by at least one embodiment of the present disclosure, obtaining a first verification intellectual property module for an object to be tested also includes: obtaining a first coverage module to obtain the first verification intellectual property module; classifying the first verification intellectual property module to obtain the classified second verification intellectual property module, and also includes: obtaining a second coverage module to obtain the second verification intellectual property module, wherein the second coverage module is configured to be obtained based on the first coverage module.

[0009] For example, in a processing method provided by at least one embodiment of the present disclosure, generalized processing is performed based on the second verification intellectual property module to realize the integration of verification intellectual property modules for verification environments of different levels, including: generalized processing is performed based on the second verification intellectual property module to obtain the integration of verification intellectual property modules for at least one level of module-level verification environment, subsystem-level verification environment, and system-on-chip level verification environment.

[0010] For example, in a processing method provided by at least one embodiment of the present disclosure, general processing is performed based on the second verification intellectual property module to realize the integration of verification intellectual property modules for verification environments of different levels, including at least one of the following: based on the encryption library and the non-encryption library module, common components are obtained, and the common components are packaged and encapsulated; the first type of interface signal of the object under test is connected to the second interface module, and the second type of interface signal of the object under test is classified, packaged and encapsulated into the second interface module, wherein the first type of interface signal is a standard interface signal, and the second type of interface signal is a non-standard interface signal other than the standard interface signal; in response to the different levels of verification environment, the corresponding different levels of the second object under test encapsulation module are instantiated to the second top-level module, and the second main or The slave device-side environment and configuration module, the second test case layer module, and the second interface module are instantiated to the second top-level module to connect the object to be tested and the second verification intellectual property module; in response to the different levels of verification environment, the corresponding different levels of objects to be tested are instantiated to the second object to be tested encapsulation module, and the object to be tested is set to undergo a hierarchical replacement process so that the second verification intellectual property module can be connected to different objects to be tested; the second test case layer module is set to undergo a hierarchical replacement process according to the levels of the different levels of verification environment so as to implement the use of test cases; the connection relationship between the internal signals of the object to be tested and the interface signals in the second interface module related to the object to be tested is maintained; and parameter configuration is performed based on the second master or slave device-side environment and configuration module and the different levels of verification environment.

[0011] For example, in a processing method provided in at least one embodiment of the present disclosure, generalized processing is performed based on the second verification intellectual property module to achieve verification intellectual property module integration for verification environments of different levels, and also includes: mapping the second coverage module from the module level to the subsystem level and the system-on-chip level.

[0012] For example, in a processing method provided by at least one embodiment of the present disclosure, the setting for performing hierarchical replacement processing on the object to be tested includes: the hierarchy of the object to be tested is defined using macros, wherein the hierarchy of the object to be tested corresponds one-to-one to the hierarchy of the verification environments of different levels.

[0013] For example, in a processing method provided by at least one embodiment of the present disclosure, the setting of performing hierarchical replacement processing on the second test case layer module according to the hierarchy of the different levels of verification environment includes: macro definition of the second test case layer module according to the hierarchy of the different levels of verification environment to realize the replacement of test case layers with each other at the module level, subsystem level, and system-on-chip level.

[0014] At least one embodiment of the present disclosure further provides a processing device for acquiring an environment, comprising: an acquisition module, configured to acquire a first verification intellectual property module for an object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; an extraction module, configured to perform a classification operation on the first verification intellectual property module to acquire a classified second verification intellectual property module; and a generalization processing module, configured to perform generalization processing based on the second verification intellectual property module to achieve integration of verification intellectual property modules for verification environments of different levels.

[0015] At least one embodiment of the present disclosure further provides a verification method, comprising: acquiring a current verification environment based on a processing method as described in any one of the above, and performing simulation operation based on the current verification environment to implement the verification method.

[0016] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processing method described in any one of the above items is implemented.

[0017] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the processing method described in any of the above examples is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A flowchart of a processing method for environment integration proposed in some embodiments of the present disclosure;

[0020] Figure 2 A schematic diagram of an object to be tested and a verification intellectual property module proposed in some embodiments of the present disclosure;

[0021] Figure 3 A schematic diagram of a general verification intellectual property module provided for some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram of a general verification intellectual property module extraction provided for some embodiments of the present disclosure;

[0023] Figure 5A schematic diagram of the integration of a universal verification intellectual property module provided for some embodiments of the present disclosure;

[0024] Figure 6 A flowchart of an execution process of step S3 provided in some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram of a PCIE VIP provided for some embodiments of the present disclosure;

[0026] Figure 8 A schematic diagram of PCIE VIP extraction provided for some embodiments of the present disclosure;

[0027] Fig. 9 A schematic diagram of PCIE VIP integration provided for some embodiments of the present disclosure;

[0028] Fig.10 A schematic diagram of a processing device for acquiring an environment provided in some embodiments of the present disclosure;

[0029] Fig.11 A schematic diagram of the structure of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present disclosure explicitly define such meanings.

[0032] The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0033] At present, the construction of the existing verification environment is based on UVM (Universal Verification Methodology, UVM for short) to create an environment (env), create new agents (Agents) according to different modules or functions, create interface(s) for different interfaces, and then integrate them into the environment (env). In order to save time and complete the verification task with lower risk, electronic design automation manufacturers have launched a more efficient and reliable VIP (Verification Intellectual Propertγ, verification intellectual property, also known as verification IP or verification template or verification module or verification component). The efficient integration of the VIP environment can accelerate the construction of the verification environment, save a lot of manpower and time costs, and accelerate the convergence of verification.

[0034] Specifically, VIP can also be called universal VIP. VIP provides an interface based on SystemVerilog and UVM verification methodology. In other words, universal VIP is a specification suite that can be used on the UVM platform to verify different protocols. Users can directly introduce VIP into their own verification environment for use, imitate the protocol of specific needs through VIP and create corresponding incentives for verification, so as to achieve connection and inspection for protocol standards and interfaces. Therefore, citing a reliable VIP can greatly reduce the verification work of chip verification personnel, improve verification efficiency, and speed up project progress. For example, in the process of building a verification environment for a system-level chip such as SOC, it is necessary to connect VIP to the object to be tested (Design Under Test, DUT), and build test cases and complete the result comparison of all test cases.

[0035] The inventors of the present disclosure discovered that in system chip-level verification, since different levels (different Levels, also called different layers) of verification environments focus on different protocols, it becomes difficult to efficiently integrate VIP into the chip's module-level (IP level), subsystem-level (Subsystem level), and system chip-level (i.e., SOC level, also called system-on-chip level) verification environments, support the synchronization of VIP version updates and verification components, and fully reuse VIP components to expand verification scenarios.

[0036] The inventors of the present disclosure also found that there are generally two purposes of reusability, one is component reusability, and the other is use case reusability. There are two corresponding reuse technologies discovered so far. One is for components, which generally reloads the agent from active mode to passive mode; the other is for use cases, modifying the configuration to reuse the VIP test case. In this way, the vertical reuse of the environment is achieved by using these two methods, but the inventors of the present disclosure have found that this method has great limitations. First, this will place high demands on the components and test cases of VIP, and there must be a mode that supports reuse; second, the workload is large, and a series of components such as sequencer and configuration (Cfg) need to be iterated again; third, the flexibility is poor, for example, the test case may be modified at the module level, subsystem, SOC level configuration and integration steps; thus, it is necessary to maintain multiple sets of environments, and a lot of redundant work will be done.

[0037] The inventors of the present disclosure have discovered that in order to facilitate reuse from the module level to the subsystem and SOC level, it is necessary to reuse subsets of verification components and test cases as much as possible, but current reuse technology can only reuse a small number of components and has poor scalability, inheritance and maintainability.

[0038] In this regard, at least one embodiment of the present disclosure provides an environment integration processing method, including: obtaining a first verification intellectual property module for an object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; classifying the first verification intellectual property module to obtain a classified second verification intellectual property module; and performing generalization processing based on the second verification intellectual property module to achieve integration of verification intellectual property modules for verification environments of different levels.

[0039] At least one embodiment of the present disclosure further provides a verification method including the above processing method.

[0040] The environment integration processing method of the above-mentioned embodiment of the present invention can quickly and conveniently integrate the universal VIP into the module-level, subsystem-level, and SOC-level environments according to the development process of the integrated circuit, support the synchronization of VIP version updates and verification components in the environment, support test case integration and non-encryption component modifications, and save environmental maintenance costs.

[0041] The embodiments and examples of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A flowchart of an environment integration processing method proposed in some embodiments of the present disclosure.

[0043] For example, Figure 1 As shown, at least one embodiment of the present disclosure provides a method for obtaining an environment, including steps S1 to S3.

[0044] Step S1: Acquire a first verification intellectual property module for the object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology.

[0045] Step S2: classify the first verification intellectual property module to obtain the classified second verification intellectual property module.

[0046] Step S3: Perform generalization processing based on the second verification intellectual property module to achieve integration of verification intellectual property modules for verification environments of different levels.

[0047] In the embodiments of the present disclosure, the “verification intellectual property module” refers to VIP (Verification Intellectual Property), which may also be referred to as a verification component in this article.

[0048] For example, in step S1, the first verification intellectual property module can be recorded as the first VIP, which is a concept of a summary or collection of multiple verification components. For example, the first VIP can be a PCIE (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) VIP, as described below. For example, in step S2, the second verification intellectual property module can be recorded as the second VIP, which is a concept of a summary or collection of multiple common verification components after extraction.

[0049] In the embodiments of the present disclosure, the processing method for obtaining the environment refers to a processing method for integrating the verification component into different levels of verification environments (such as module-level, subsystem-level or SOC-level environments). In some examples, the processing method for obtaining the environment of the present disclosure refers to a specific environment integration method (also referred to as a VIP integration method or a method for integrating a VIP environment) used to form a verification environment in a corresponding scenario to achieve verification of the object under test (Design Under Test, DUT, also referred to as the design under test).

[0050] In some examples, the DUT of the embodiments of the present disclosure may be a storage module, a data processing module, an interconnection module, etc. in an integrated circuit, or a SOC chip, etc. For example, when the DUT is a storage module, the processing method of the acquisition environment disclosed in the present disclosure may be used to implement VIP integration of a module-level verification environment; for another example, when the DUT is a SOC chip, the processing method of the acquisition environment disclosed in the present disclosure may be used to implement VIP integration of a subsystem-level verification environment and / or VIP integration of a SOC-level verification environment. The embodiments of the present disclosure do not limit the specific type of the DUT.

[0051] The embodiment of the present disclosure can implement corresponding integration according to the application scenario of VIP by classifying VIP and then performing generalization processing, such as bottom-up integration, with good inheritance and scalability.

[0052] Figure 2 A schematic diagram of an object to be tested and a verification intellectual property module proposed in some embodiments of the present disclosure.

[0053] For example, in step S1, the first VIP is based on various VIPs of UVM, which may include a VIP of the Master end (i.e., the master device end) (i.e., the VIP of the Master end is the Master relative to the DUT, such as Figure 2 The VIP of the slave end (i.e., the VIP of the slave end is a slave relative to the DUT, such as Master0, Master1, and Master2) can also be included. Figure 2 Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0054] For example, for Master, it may represent an access initiating module (i.e., the party that actively initiates the access operation), which may be implemented as a data processing device such as a CPU core, etc. For example, for Slave, it may represent an access response module (i.e., the party that passively receives or responds), which may be implemented as a communication module or a storage controller, etc. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0055] In some examples, obtaining the first VIP for the DUT in step S1 may include the following process or steps: obtaining the first VIP of the DUT in the first verification environment, that is, the first VIP in step S1 refers to the common VIP of the corresponding DUT in the first verification environment. The first verification environment is the initial environment of the DUT. The initial environment may also be referred to as the original environment, that is, the original environment refers to the integrated initial environment.

[0056] In some examples, for VIP integration of different levels of verification environments, each level of verification has a corresponding initial environment for initializing the verification of DUTs at different levels. For example, when the DUT is a module-level design under test, the first verification environment refers to the initial environment at the module level; for another example, when the DUT is a subsystem-level design under test, the first verification environment refers to the initial environment at the subsystem level; for another example, when the DUT is a SOC chip, the first verification environment refers to the initial environment at the SOC level.

[0057] The environment integration of the embodiments of the present disclosure can make some processing and improvements for the verification environment integration at the subsystem level and SOC level, while paying attention to whether the verification components of the original environment can work normally and not affecting the existing environment characteristics, so as to more efficiently improve the verification quality of the entire verification process.

[0058] In some embodiments of the present disclosure, the classification operation of the first VIP in step S2 refers to the classification processing according to different verification components in the verification environment, that is, the second VIP is based on the first VIP and is extracted one by one according to the functions of the verification components in the environment. The embodiments of the present disclosure do not specifically limit the specific operations of the classification processing, which can be determined according to the types and functions of each verification component in the environment. For example, the classification processing can include a merging operation, and can also include the category remaining unchanged, and can also include operations such as division into multiple categories, which will not be exhaustively listed and repeated here.

[0059] In some embodiments of the present disclosure, the generalized processing based on the second VIP in step S3 refers to processing each verification component of the environment separately. As a general step for integrating the VIP environment, a general processing method is given to the integration of the general VIP, thereby achieving the purpose of the general integration step. The verification components in the environment can be integrated into various levels of verification environments. For example, the verification components in the environment can be integrated from the module level to the subsystem level and then to the SOC level, which solves the problem that the initialization process in the existing solution is different due to the integration of different levels. That is to say, even if the embodiments of the present disclosure use the integration of verification environments of different levels, the initialization process of the DUT can be implemented by inheriting the base class of the DUT testcase. The embodiments of the present disclosure have good inheritance and good scalability.

[0060] In some examples, the generalization processing based on the second VIP in step S3 to achieve verification intellectual property module integration for different levels of verification environments includes the following processes or steps: generalization processing based on the second VIP to obtain verification intellectual property module integration for at least one level of module-level verification environment, subsystem-level verification environment, and SOC-level verification environment.

[0061] The embodiments of the present disclosure classify VIPs and then perform general processing, so as to realize bottom-up integration according to the application scenarios of VIPs (such as integration from module level to subsystem level and then to SOC level). Of course, the embodiments of the present disclosure are not limited to this. Not only can they be integrated in sequence from bottom to top according to the hierarchy (such as bottom-up according to IP->Subsystem->SOC), but they can also be directly integrated according to their respective levels. For example, SOC-level integration can be directly performed without having to go through all the steps of subsystem-level integration in sequence (that is, the IP-level environment is directly integrated into the SOC-level environment to realize direct SOC usage instantiation), or when the actual DUT only includes module-level designs to be tested and subsystem-level designs to be tested, only module-level and from module-level to subsystem-level integration can be realized. This can also be determined according to the actual situation. The embodiments of the present disclosure are more flexible and will not be repeated here.

[0062] Figure 3 A schematic diagram of a general verification intellectual property module provided for some embodiments of the present disclosure. Figure 4 A schematic diagram of a general verification intellectual property module extraction provided for some embodiments of the present disclosure. Figure 5 A schematic diagram of the integration of a universal verification intellectual property module provided in some embodiments of the present disclosure, Figure 5 It mainly demonstrates the integration from module level to subsystem level and SOC level.

[0063] For example, in step S1, the first VIP may include various general VIPs of a typical or mainstream UVM verification platform, and the general VIP refers to at least one verification intellectual property module (also referred to as at least one verification component) based on a UVM methodology architecture.

[0064] For example, Figure 3 As shown, the first VIP 300 includes: a top layer Tb_top 310, a DUT wrapper 320, a test case layer Tests (Testcase) 330, a master or slave device environment layer Rc / Ep env 340, a master or slave device configuration Rc / Ep env_cfg 350 and interfaces 360. Figure 3As shown, the master or slave device environment layer Rc / Epenv 340 includes a library Libs 341 , an agent Agents 342 , a sequence generator 343 (generally referred to as Sequencer 343 , used to send a sequence; abbreviated as seqrs in the figure herein) and a scoreboard Scoreboard 344 .

[0065] It should be noted that the protection scope of the embodiments of the present disclosure is not limited by the naming or identification of each component or module, but is subject to the technical solution described in this document. Figure 4 Interface 460 in the diagram may also be labeled as Interfaces 460, or as a DUT wrapper and Interface of a VIP component.

[0066] For example, Figure 3 As shown, the first VIP 300 can be recorded as RC / EP VIP, where RC (or Rc) refers to the universal RC (Root Complex), EP (or Ep) refers to the universal EP (EndPoint), and RC / EP in the embodiments of the present disclosure refers to RC or EP, and RC / EP indicates whether the VIP is a master or a slave. The embodiments of the present disclosure may include the case of RC-side integration and the case of EP-side integration.

[0067] For example, in Figure 3 In the environment structure of the general RC / EP VIP: DUT wrapper 320 can be used to instantiate DUT. Sequences are sequences called by Tests through seqrs; seqrs refers to Sequencer 343, which is used to send sequences. Tests 330 refers to the test cases of the generated environment. The test case layer Tests 330 is responsible for executing the test and associating the sequence with Sequencer 343. The env in the embodiment of the present disclosure refers to the environment (which is an environment layer used to bring together all verification components around a certain DUT (module level or subsystem level or system level, etc.). For example, the environment layer combines the related verification components together and encapsulates all verification components for the DUT, that is, the environment layer is used to instantiate specific verification components). Rc / Ep env 340 indicates that there are both Rc env and Ep env in the environment. Rc / Ep env_cfg350 refers to the configuration file for Rc / Ep env 340, which indicates the configuration of the environment. Interfaces360 refers to the environment interface.

[0068] Figure 6A flowchart of an execution process of step S3 provided in some embodiments of the present disclosure. Figure 7 A schematic diagram of a PCIE VIP provided for some embodiments of the present disclosure. Figure 8 A schematic diagram of PCIE VIP component extraction provided in some embodiments of the present disclosure, wherein: Figure 8 is based on Figure 7 Component extraction diagram of . Fig. 9 A schematic diagram of PCIEVIP integration provided for some embodiments of the present disclosure. Figure 7-Figure 9 In the example, it mainly takes PCIE VIP as an example to illustrate the reusable solution for integrating the PCIE VIP environment.

[0069] For example, Figure 7 As shown, the first VIP 300 may include Figure 7 PCIE EP / PHY VIP700 in the example, Figure 7 An example is the case where the DUT is a PCIE DUT.

[0070] For example, Figure 7 As shown, App layer refers to application layer; pl refers to physical layer; d1 refers to data-link layer; t1 refers to transaction layer; these layers all correspond to the various layers of the PCIE protocol and are all contained in the environment layer module Env (which can be regarded as an example of the above-mentioned Rc / Ep env).

[0071] For example, Figure 7 As shown, EP / PHY refers to EP or PHY. EP can refer to the above Figure 3 Description of the example; PHY is the abbreviation of Physical, which means the physical port layer; the general verification intellectual property model includes the MAC layer and the PHY layer. The MAC layer and the PHY layer are two different layers in the OSI model, corresponding to the data link layer and the physical port layer respectively; RC / EP indicates whether the VIP is a master or a slave.

[0072] exist Figure 7In the example, Vip_port_if is regarded as an example of the interface module Interfaces 360 mentioned above, and Vip_port_if may include a Serial interface signal (Serial_if) and / or a PIPE interface signal (Pipe_if). The Serial interface of the embodiment of the present disclosure is a serial interface, also known as a serial communication interface or a serial communication interface, usually referred to as a serial port. This interface adopts a serial communication method, that is, data is transmitted sequentially one bit at a time. The PIPE interface is part of the PCIE physical layer. It defines a unified interface between the media layer and the physical coding sublayer in the physical layer. Thus, through the PIPE interface, the MAC layer can effectively exchange and control data with the PHY layer to ensure the normal operation of the PCIE device and the accuracy of data transmission. It should be noted that the embodiment of the present disclosure Figure 7 For other modules such as PCIE_agent, EP / PHYTests and EP / PHY_env_cfg, please refer to the above Figure 3 For the sake of clarity and brevity of this article, the descriptions of Agents 342, Tests 330, Rc / Ep env_cfg350, etc. are not repeated here.

[0073] In some examples, obtaining the first VIP in step S1 may include the following process or steps: obtaining the first top-level module (such as Figure 3 Tb_top in), the first object under test encapsulation module (such as Figure 3 DUT wrapper in the first test case layer module (such as Figure 3 Tests in the first master or slave device environment layer module (such as Figure 3 Rc / Ep env in), the first master or slave device configuration module (such as Figure 3 Rc / Ep env_cfg in), the first interface module (such as Figure 3 In the Interfaces) to obtain the first VIP 300. For example, the first master or slave device side environment module includes a library (such as Figure 3 Libs in ), agents (such as Figure 3 Agents in ), sequence generators (such as Figure 3 seqrs in ) and scoreboards (such as Figure 3 in the Scoreboard).

[0074] For example, Figure 3 As shown, the first VIP 300 may further include a coverage module Coverage 370, wherein the coverage module Coverage 370 refers to a component for collecting coverage in an environment.

[0075] In some examples, obtaining the first VIP in step S1 may also include the following process or steps: obtaining a first coverage module (such as Figure 3 Coverage 370) in order to obtain the first VIP.

[0076] For example, Figure 4 As shown, Figure 4 is based on Figure 3 The second VIP is obtained by classifying and extracting the verification components one by one according to their functions in the environment. Figure 4 It is equivalent to extracting and abstracting Figure 3 .

[0077] For example, Figure 3-Figure 4 As shown, the classification operation for the first VIP may include the following: Figure 3 The library Libs 341 shown in the figure was extracted and divided into Figure 4 The encryption library and non-encryption library shown in Figure 3 The master or slave side environment layer Rc / Ep env 340 and the master or slave side configuration Rc / Ep env_cfg 350 shown in Figure 4 The master or slave device side environment and configuration module VIP env / env_cfg440 shown in Figure 3 The top layer Tb_top 310 shown in FIG. Figure 4 The top VIP Tb_top 410 shown in FIG. 4 (ie, Tb_top remains unchanged) is Figure 3 The test cases shown in the layer Tests330 are categorized as Figure 4 VIP RC / EP Tests 430, as shown in Figure 3 The DUT wrapper 320 shown in FIG. 1 is mapped to Figure 4 The DUT wrapper 420 shown in FIG. 1 (ie, the DUT wrapper remains unchanged) and Figure 3 The interfaces shown in Interfaces 360 are categorized as Figure 4 The interface 460 shown in (for the interface of the embodiment of the present disclosure, one VIP corresponds to one protocol of the Interface, so if the VIP is fixed, the Interface is fixed). In the embodiment of the present disclosure, Tests is generally a full set, with test cases for different levels of RC / EP / PHY, so it is generally unchanged. This is only exemplary and is not a limitation of the embodiment of the present disclosure.

[0078] In some examples, the classification operation of the first verification intellectual property module may also include: Figure 3 The coverage module Coverage 370 shown in the figure is mapped to Figure 4 The coverage module Coverage 470 shown in (equivalent to the Coverage part remains unchanged).

[0079] In some examples, the classification operation of the first verification intellectual property module in step S2 to obtain the classified second verification intellectual property module may include the following process or steps: obtaining the second top-level module (such as Figure 4 VIPTb_top 410 in the second test object encapsulation module (such as Figure 4 DUT wrapper 420 in ), the second test case layer module (such as Figure 4 VIP RC / EP Tests 430 in the second master or slave device environment and configuration module (such as Figure 4 VIP env / env_cfg440 in the second interface module (such as Figure 4 Interface 460 in ), encryption library and non-encryption library modules (such as Figure 4 At least one of the encrypted library and the non-encrypted library 450) in the library to obtain a second verification intellectual property module.

[0080] For example, in step S2, the second top-level module (such as Figure 4 VIP Tb_top 410 in 410 is configured as a first top-level module (such as Figure 3 The second object to be tested encapsulation module (such as Figure 4 The DUT wrapper 420 in FIG. 1 is configured as a first DUT encapsulation module (eg, Figure 3 The DUT wrapper in the second test case layer module is as follows: Figure 4 VIP RC / EP Tests 430) is configured based on the first test case layer module (such as Figure 3 Tests in the second master or slave device environment and configuration module (such as Figure 4 VIP env / env_cfg440) is configured based on the first master or slave device side environment layer module (such as Figure 3 Rc / Ep env in) and the first master or slave device configuration module (such as Figure 3 Rc / Epenv_cfg in the second interface module (such as Figure 4 Interface 460 in is configured as a first interface module (such as Figure 3Interfaces in the library) to obtain the encryption library and non-encryption library modules (such as Figure 4 The encrypted library and the non-encrypted library 450 in are configured as libraries (such as Figure 3 Libs in the classification acquisition. In some embodiments of the present disclosure, due to Figure 3 The Rc / Ep env340 shown includes library Libs 341, agent Agents 342, sequencer Sequencer 343 and scoreboard Scoreboard 344, so that after extraction, these sub-module parts are all included in VIP env / env_cfg440.

[0081] In some examples, the classification operation of the first verification intellectual property module in step S2 to obtain the classified second verification intellectual property module also includes the following process or step: obtaining the second coverage module (such as Figure 4 470) to obtain a second verification intellectual property module, wherein the second coverage module is configured based on the first coverage module (such as Figure 3 Obtained from Coverage 370).

[0082] For example, Figure 8 As shown, the second VIP 400 may include Figure 8 PCIE EP / PHY VIP 800 in the example, Figure 8 is based on Figure 7 The results are obtained by classifying and extracting the functions of the verification components in the environment one by one. Figure 8 It is equivalent to extracting and abstracting Figure 7 .

[0083] For example, Figure 8 As shown, the standard Serial and PIPE interfaces in the PCIE DUT can be connected to the Serial_if and Pipe_if interfaces respectively. Figure 8 The DUT internalif in the DUT internalif refers to the internal signal interface related to the DUT, through which the internal signal of the DUT can be connected and placed in Vip_port_if. It should be noted that the embodiment of the present disclosure Figure 8 For other modules such as PCIEVIPTb_top, PCIE VIPenv / env_cfg, PCIE VIP EP / PHY Tests, please refer to the above Figure 3 , Figure 4 and Figure 7For the sake of clarity and conciseness of this article, the descriptions of VIP Tb_top 410, VIP env / env_cfg440, VIP RC / EP Tests, etc. are not repeated here.

[0084] The embodiments of the present disclosure can implement a reusable PCIE VIP solution, can better inherit the initialization process of the original PCIE DUT environment, can reduce duplication of verification work, and improve verification quality.

[0085] For example, Figure 4 As shown in FIG. 1 , it illustrates the module-level classification and extraction of verification components. Figure 4 , if the DUT is a module-level design under test, then Figure 4 It can also be used as a block diagram to illustrate the VIP integration at the module level (for example, Figure 4 The DUT wrapper in the example can refer to the case of instantiating the module-level DUT. Figure 4 VIP env / env_cfg in can represent module-level env / env_cfg as well as Figure 4 VIP RC / EP Tests in the example may represent VIP IP Tests). For another example, if some embodiments of the present disclosure need to be integrated upward from the module level to the subsystem level and SOC level, then the process from Figures 4 to 5 Steps, that is, Figure 5 To illustrate the situation where the module level is integrated upward to the subsystem level and the SOC level. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. The processing method of the embodiments of the present disclosure is an example of a general process, which can not only be integrated sequentially from bottom to top according to the levels, but also can be directly integrated according to the respective levels to achieve the integration of verification environments at different levels.

[0086] For example, Figure 5 As shown, when integrating upward from the module level to the subsystem level: Subsystem top is instantiated in VIPtb_top, and other VIP modules are similar (for example, Subsystem dut is instantiated in DUT wrapper, Subsystemenv / env_cfg is instantiated in VIP env / env_cfg), and Subsystem base test is instantiated in VIP basetest, and the environment also has VIP Subsystem tests for the subsystem level and the corresponding second interface module Interface. VIP base test inherits base tests of different levels according to the level, and can be used for DUT initialization, etc. Figure 5In the example, VIP base test refers to the base test (i.e., basic test case) of the SOC or Subsystem environment, which is used to initialize the two. Figure 5 In the example, Subsystemdut refers to the subsystem-level test DUT.

[0087] For example, Figure 5 As shown, when integrating from the subsystem level upward to the SOC level: SOC top is instantiated in VIP tb_top, and other VIP modules are similar (for example, SOC dut is instantiated in DUT wrapper, SOC env / env_cfg is instantiated in VIP env / env_cfg), and SOC base test is instantiated in VIP base test, and the environment also has VIP SOC tests for the SOC level and the corresponding second interface module Interface. Figure 5 In the example, SOC dut refers to the SOC level test DUT. VIP Subsystem tests or VIP SOC tests include VIP Rc / Ep tests 430, and VIP Subsystem tests and VIP SOC tests can be understood as test case layer modules for subsystem level and SOC level, respectively. Figure 5 In the example, VIP Subsystem tests or VIP SOC tests are inherited from the corresponding Subsystembase test or SOC base test.

[0088] In the embodiments of the present disclosure, Figure 5 The subsystem integration and SOC level integration in the example may refer to the case where each is directly integrated separately. In the embodiment of the present disclosure, Fig. 9 An example of is a diagram of an environment integration that is normalized in order, as shown below.

[0089] In the embodiments of the present disclosure, the integration from the module level to the subsystem level and from the subsystem level to the SOC level will map the second coverage module from the module level to the subsystem level and the SOC level, so that the coverage can be better viewed from multiple dimensions.

[0090] The embodiments of the present disclosure can make corresponding improvements on the subsystem-level and SOC-level verification environment integration based on the traditional verification environment integration. The environments can be integrated from bottom to top in a more inherited manner according to their respective characteristics, which can more efficiently improve the verification quality of the entire verification process.

[0091] For example, Figure 6 As shown, the generalization processing based on the second verification intellectual property module in step S3 to realize the integration of verification intellectual property modules for verification environments of different levels includes at least one of the following processes or steps:

[0092] Step S31: Based on the encryption library and the non-encryption library modules, obtain the common components, and package the common components.

[0093] Step S32, connecting the first type of interface signal of the DUT to the second interface module, and classifying, packaging and encapsulating the second type of interface signal of the DUT into the second interface module, wherein the first type of interface signal is a standard interface signal, and the second type of interface signal is a non-standard interface signal other than the standard interface signal.

[0094] Step S33, in response to different levels of verification environment, instantiate the corresponding second object under test encapsulation modules of different levels to the second top-level module, and instantiate the second master or slave device side environment and configuration module, the second test case layer module, and the second interface module to the second top-level module, connecting the DUT and the second verification intellectual property module.

[0095] Step S34, in response to different levels of verification environments, instantiate corresponding different levels of DUTs into the second DUT encapsulation module, and perform level replacement processing on the DUTs so that the second verification intellectual property module is connected to different DUTs.

[0096] Step S35, performing a hierarchical replacement process on the second test case layer module according to the hierarchies of different levels of verification environments to implement the use of test cases.

[0097] Step S36: Maintain the connection relationship between the internal signal of the DUT and the interface signal in the second interface module related to the DUT.

[0098] Step S37: perform parameter configuration based on the second master or slave device environment and the configuration module and different levels of verification environments.

[0099] The embodiments of the present disclosure have good inheritance for the original environment, solve the problem that the initialization process is different due to different levels of integration, have good scalability, can save manpower for maintaining multiple environments, and improve the efficiency of environment reuse.

[0100] The embodiment of the present disclosure does not limit the sequence of the various processes or steps in this example. For example, the embodiment of the present disclosure does not limit the sequence of steps S31 to S37.

[0101] For example, Figure 3-Figure 6As shown, in step S31, based on the encryption library and non-encryption library modules, obtaining common components can mean that after extracting the encryption library and non-encryption library modules 450, the verification components in the environment that are not affected by the integration mode are used as common components. Here, "not affected by the integration mode" means that regardless of module-level environment integration, subsystem-level environment integration, or SOC-level environment integration, such components do not need to be modified and can be extracted as common components (i.e., common verification components).

[0102] For example, in step S31, for the encryption library module, what is generally encrypted is the underlying code, for example, it can be an encryption library obtained for the key code in Sequence, Agents, and Libs; in the embodiments of the present disclosure, the underlying code can be instantiated in the top layer and the environment layer one level at a time.

[0103] The embodiments of the present disclosure can extract common components based on the encryption and non-encryption characteristics of VIP components, and make them more flexible to use through targeted special processing.

[0104] In some examples, regarding the encrypted library components (i.e., VIP Lib encrypted components) and the non-encrypted library components (i.e., VIP Lib non-encrypted components) in the encrypted library and non-encrypted library module 450 in the embodiments of the present disclosure, this is due to the fact that VIP generally has intellectual property rights, its key code will be encrypted and non-key code will not be encrypted, so the library can be divided into an encrypted library and a non-encrypted library. For example, for Figure 7-Figure 8 In the case of extracting PCIE VIP libraries, some libraries are C compiled code encapsulated encrypted libraries (meaning that this code becomes an encapsulated and unreadable code after being compiled by C, and the function is that this code cannot be modified after encryption), while others are non-encrypted libraries. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0105] The embodiments of the present disclosure may implement general processing from module level to subsystem level and to SOC level verification library through specialized library processing.

[0106] For example, in step S31, the embodiment of the present disclosure packages at least a part of the encryption library and non-encryption library modules (i.e., the encryption library and non-encryption library modules extracted at the module level) into a package (declaration package), and iterates layer by layer through the import (import class) method to the scenario where this package is needed at a higher level. For example, the encryption library verification component at the module level can be packaged and packaged into a package. If it is needed at the subsystem level, it is imported into the subsystem level package, so that the subsystem level can use the verification component in the package, and the subsystem level package contains the module level package. In addition, the embodiment of the present disclosure can similarly package the verification component corresponding to the subsystem into a package, and then import it into the SOC level package, so that the SOC level can use the verification component in the package, and the SOC level package contains the subsystem level package. It should be noted that the embodiments of the present disclosure can not only package and encapsulate the module-level encryption library verification component, but also package the module-level non-encryption library verification component; in some embodiments of the present disclosure, the encryption library verification component and the non-encryption library verification component are packaged separately, and the packaged content of the non-encryption library verification component can be modified, while the packaged content of the encryption library verification component cannot be modified, the non-encryption library verification component can be flexibly integrated, and the encryption library verification component can only be called as a benchmark package. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0107] Therefore, the embodiments of the present disclosure can realize an inherited bottom-up integrated environment, and can more efficiently improve the verification quality of the entire verification process.

[0108] The embodiments of the present disclosure are integrated by means of package and import, which is very convenient, especially when integrating upwards, there is no need to instantiate and use each component one by one. The embodiments of the present disclosure adopt different processing methods for encryption libraries and non-encryption libraries, which can be used more flexibly. For example, non-encryption libraries can be modified and can be modified flexibly, while encryption libraries cannot be modified, and the two are processed separately.

[0109] For example, in step S32, the first type of interface signal is a standard interface signal. For example, for the example of PCIE DUT, the standard interface signal may include a standard Serial interface and a PIPE interface. In step S32, the second interface module may be recorded as vip_port_if. The second type of interface signal may refer to other interface signals in the DUT except the standard interface signal, such as other interface signals of the internal state machine, so that the sequence in the VIP will wait for these DUT signals and know the state of the DUT, so that other interface signals in the DUT can be classified, packaged and encapsulated into multiple groups of interface signals and placed in Vip_port_if for easy use. Therefore, the embodiments of the present disclosure can connect the internal signals of the DUT and place them in Vip_port_if.

[0110] For example, in step S32, combined with Figure 7-Figure 9 For example, for the first type of interface signal of the DUT to be connected to the second interface module, it can include: the standard Serial and PIPE interfaces in the PCIE DUT can be connected to the Serialif and Pipe_if interfaces respectively. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0111] For example, in step S33, different levels of verification environments may include verification environments at the module level, the subsystem level, and the SOC level, and for different levels of verification environments, the DUTs at each level are different, the DUT wrappers are also different, and the DUT wrappers are used to instantiate the DUTs and the DUT wrappers are included in the top-level module. Thus, regarding the processing of the second top-level module of some embodiments of the present disclosure, it is as follows: for different levels of verification environments, different second object under test encapsulation modules DUT wrapper420 are instantiated in the second top-level module VIP Tb_top 410, and other verification components (such as the second master or slave device end environment and configuration module VIP env / env_cfg440, the second test case layer module VIP RC / EP Tests430, the second interface module Interface 460) are also instantiated in the second top-level module VIP Tb_top 410, and the DUT and the second VIP are connected through an interface (such as Serial or Pipe Interface). For example, the communication connection between the DUT and the second VIP is realized by connecting the DUT interface and the corresponding VIP interface.

[0112] For example, the setting of the level replacement processing for the DUT in step S34 includes the following process or steps: the level of the DUT is defined using a macro, wherein the level of the DUT corresponds one-to-one to the levels of verification environments at different levels.

[0113] The embodiments of the present disclosure use macro definitions to implement the generalized processing of DUTwrapper required for verification environments of different levels, which has good maintainability and portability, strong reusability, and improves the running efficiency of the program. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, the hierarchical replacement processing method can also be other processing methods such as inline functions, as long as the same or similar functions and effects as the macro definitions can be achieved, which will not be repeated here.

[0114] For example, in step S34, different levels of verification environments may include module level, subsystem level and SOC level, and for different levels of verification environments, the DUTs of each level are different, and the SOC-level DUT includes the subsystem-level DUT and the subsystem-level DUT includes the module-level DUT. Therefore, regarding the processing of the second object under test encapsulation module of some embodiments of the present disclosure, it is as follows: for different levels of verification environments, the DUTs of different levels (such as the DUT is a PCIE DUT) are instantiated into the second object under test encapsulation module DUT wrapper 420, the hierarchical levels are replaced by macros, and the inheritance of different levels is redefined as the corresponding macros. In this way, the embodiments of the present disclosure can realize the connection between the interface and different objects under test by replacing the macros of different levels.

[0115] For example, the setting of performing hierarchical replacement processing on the second test case layer module according to the hierarchy of different levels of verification environment in step S35 may include the following process or steps: macro definition of the second test case layer module according to the hierarchy of different levels of verification environment to realize the replacement of test case layers with each other at module level, subsystem level, and system-on-chip level.

[0116] For example, in step S35, the processing of the macro definition of the second test case layer module in some embodiments of the present disclosure includes: redefining the macro of base test according to tests of different levels, that is, replacing the macro definition of base test of different levels of environment inherited by VIP base test, so that it can be compatible with the base class of the legacy environment (Legacy environment) and facilitate expansion, and the test case list should contain test cases of all levels, so that VIP Rc / Ep tests can be used directly without re-modification according to different levels; and for test cases, different levels of situations can be reused according to application scenarios. In other words, in the embodiments of the present disclosure, for base test, macro definition can be used to replace Module or Subsystem base test with SOC base test, so that the SOC initialization process can be automatically used; and VIP Rc / Ep tests can be reused at the SOC level and subsystem level. In the embodiments of the present disclosure, testcases are inherited from base test, and the name of base test is a macro definition, then Module or Subsystem base test can be replaced with the name of SOC base test, so that the process of initializing DUT using verification environments of different levels is realized.

[0117] In some examples, the generalization processing based on the second verification intellectual property module in step S3 is performed to achieve verification intellectual property module integration for verification environments of different levels, and also includes: mapping the second coverage module from the module level to the subsystem level and the system-on-chip level. For example, the module-level coverage of the embodiment of the present disclosure can be mapped to the subsystem level and the SOC level through a map, which can better view the coverage from multiple dimensions. For this mapping (map), it allows the coverage data to be associated with a specific code unit or module. By using a mapping, multiple small coverage data sets can be merged into a larger, more comprehensive coverage report.

[0118] In some examples, step S36 of the embodiment of the present disclosure is a general processing for the internal signal of the DUT to pull the signal out to the interface, that is, step S36 is a general processing process for interface processing. In some examples, step S37 of the embodiment of the present disclosure is a general processing process for VIP env / env_cfg440.

[0119] For example, in step S36, if Sequence implements interaction with DUT, it is necessary to call the interface signal associated with DUT encapsulated in the second interface module (such as Vip_port_if). Sequence here refers to the sequence driven by the DUT port signal. Therefore, the embodiment of the present disclosure has a file for maintaining the connection relationship between the internal signal of DUT and the interface signal associated with DUT in Vip_port_if, that is, the file includes the connection relationship between the internal signal of DUT and the interface signal.

[0120] For example, in step S37, the above parameter configuration includes the following: Regarding whether the parameters related to the configuration process are reused, generally the subsystem level and the SOC level use the same parameters, and if they are different, the overload function overwrites them.

[0121] For example, Fig. 9 As shown, it is based on Figure 8 Illustration of VIP integration implemented on the component extraction of . Fig. 9 In the example, Macro replace SOC top means that the top is changed during SOC integration, and the macro needs to be replaced with the SOC top path. SOC dut means SOC-level test DUT. Import SOC env package means that the SOC env package needs to be imported into PCIE VIPenv. Extend ffrom SOC base test means that VIP tests need to inherit from SOC base test in order to initialize SOC DUT. It should be noted that the embodiments of the present disclosure Fig. 9 For more information about other modules in the integration, please refer to Figure 5 as well as Figure 7-Figure 8 , for the sake of clarity and conciseness of this article, it will not be repeated here.

[0122] The embodiments of the present disclosure provide an effective solution to the consistency problem of universal VIP (such as VIP version update) at the module level, subsystem level, and SOC level. The solutions of the embodiments of the present disclosure are universal, can better inherit the initialization process of the original DUT environment, and can reuse various components, thereby improving the verification quality and reducing duplication of verification work.

[0123] Fig.10 A schematic diagram of a processing device for acquiring an environment provided in some embodiments of the present disclosure.

[0124] For example, Fig.10As shown, the processing device 900 for acquiring an environment according to an embodiment of the present disclosure includes an acquisition module 910, a classification module 920, and a generalization processing module 930. The acquisition module 910 is configured to acquire a first verification intellectual property module for an object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology. The classification module 920 is configured to perform a classification operation on the first verification intellectual property module to acquire a second verification intellectual property module after classification. The generalization processing module 930 is configured to perform generalization processing based on the second verification intellectual property module to realize the integration of verification intellectual property modules for verification environments of different levels.

[0125] The processing device for acquiring the environment in the above-mentioned embodiment of the present invention can quickly and conveniently integrate the general VIP into the module-level, subsystem-level, and SOC-level environments according to the development process of the integrated circuit, support the synchronization of VIP version updates and verification components in the environment, support test case integration and non-encryption component modifications, and save environmental maintenance costs.

[0126] It should be noted that in the embodiments of the present disclosure, the processing device for acquiring the environment may include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific configuration of each module is not limited.

[0127] Each module in the above embodiment can be configured as software, hardware, firmware or any combination of the above items to perform specific functions. For example, these modules can correspond to a dedicated integrated circuit, or to pure software code, or to a module combining software and hardware.

[0128] It should be noted that although the processing device for acquiring the environment is divided into modules for respectively performing corresponding processing when describing the processing device for acquiring the environment, those skilled in the art are aware that the processing performed by each module can also be performed without any specific module division or without clear boundaries between the modules.

[0129] In the embodiments of the present disclosure, the specific implementation and technical effects of the processing device for acquiring the environment can also refer to the environment integration processing method provided in the above embodiments of the present disclosure.

[0130] At least one embodiment of the present disclosure also provides a verification method, which may include: obtaining a current verification environment based on a processing method as described in any one of the above, and performing a simulation run based on the current verification environment to implement the verification method. The specific implementation and technical effects of the verification method can also refer to the processing method for obtaining the environment provided in the above embodiment of the present disclosure. It should be noted that in the embodiments of the present disclosure, the focus is on explaining the processing method for obtaining the environment. Regarding other processes or steps in the chip verification method, it can refer to the relevant prior art. For the clarity and conciseness of the description in this article, it will not be repeated here.

[0131] Reference below Fig.11 , which shows a schematic diagram of the structure of an electronic device (such as a terminal device or a server) 600 suitable for implementing the embodiment of the present disclosure. The terminal device in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.11 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0132] like Fig.11 As shown, the electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage device 606 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0133] Typically, the following devices may be connected to the I / O interface 605: an input device 606 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 607 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 606 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 609. The communication device 609 may allow the electronic device 600 to communicate with other devices wirelessly or by wire to exchange data. Although Fig.11 The electronic device 600 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0134] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 609, or installed from a storage device 606, or installed from a ROM 602. When the computer program is executed by the processing device 601, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0135] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0136] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0137] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0138] The above-mentioned computer-readable medium carries one or more programs. When the above-mentioned one or more programs are executed by the electronic device, the electronic device: obtains a first verification intellectual property module for the object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; classifies the first verification intellectual property module to obtain the classified second verification intellectual property module; and performs generalization processing based on the second verification intellectual property module to realize the integration of verification intellectual property modules for verification environments of different levels.

[0139] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0140] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0141] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a unit does not limit the unit itself in some cases. For example, a classification module may also be described as a "module for performing classification operations on the first verification intellectual property module."

[0142] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0143] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0144] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0145] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0146] There are a few points to note:

[0147] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0148] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0149] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for obtaining an environment, comprising: Acquire a first verification intellectual property module for the object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; Classifying the first verification intellectual property module to obtain the classified second verification intellectual property module; Based on the second verification intellectual property module, generalization processing is performed to achieve verification intellectual property module integration for verification environments of different levels.

2. The processing method according to claim 1, wherein: Obtaining a first verification intellectual property module for the object to be tested, including: The first verification intellectual property module of the object under test in a first verification environment is obtained, wherein the first verification environment is an initial environment of the object under test.

3. The processing method according to claim 1 or 2, wherein: Obtaining a first verification intellectual property module for the object to be tested, including: Obtain at least one of a first top-level module, a first object encapsulation module, a first test case layer module, a first master or slave device-side environment layer module, a first master or slave device-side configuration module, and a first interface module to obtain the first verification intellectual property module, wherein the first master or slave device-side environment module includes a library, an agent, a sequencer, and a scoreboard.

4. The processing method according to claim 3, wherein: Classifying the first verification intellectual property module to obtain the classified second verification intellectual property module includes: Obtain at least one of a second top-level module, a second object encapsulation module, a second test case layer module, a second master or slave device end environment and configuration module, a second interface module, an encryption library and a non-encryption library module to obtain the second verification intellectual property module, Among them, the second top-level module is configured to obtain based on the first top-level module, the second object encapsulation module is configured to obtain based on the first object encapsulation module, the second test case layer module is configured to obtain based on the first test case layer module, the second master or slave device-side environment and configuration module is configured to obtain based on the first master or slave device-side environment layer module and the first master or slave device-side configuration module, the second interface module is configured to obtain based on the first interface module, and the encryption library and non-encryption library module is configured to obtain by classification based on the library.

5. The processing method according to claim 4, wherein: Acquiring a first verification intellectual property module for the object to be tested further includes: acquiring a first coverage module to acquire the first verification intellectual property module; The first verification intellectual property module is classified to obtain the classified second verification intellectual property module, and further includes: obtaining a second coverage module to obtain the second verification intellectual property module, wherein the second coverage module is configured to be obtained based on the first coverage module.

6. The processing method according to claim 1, wherein: Based on the second verification intellectual property module, general processing is performed to realize the integration of verification intellectual property modules for verification environments of different levels, including: Based on the second verification intellectual property module, general processing is performed to obtain a verification intellectual property module integration for at least one level of module-level verification environment, subsystem-level verification environment, and system-on-chip level verification environment.

7. The processing method according to claim 6, wherein: Based on the second verification intellectual property module, generalization processing is performed to realize the integration of verification intellectual property modules for verification environments of different levels, including at least one of the following: Based on the encryption library and the non-encryption library modules, obtain common components, and package the common components; Connecting the first type of interface signal of the object to be tested to the second interface module, and classifying and packaging the second type of interface signal of the object to be tested and encapsulating it into the second interface module, wherein the first type of interface signal is a standard interface signal, and the second type of interface signal is a non-standard interface signal other than the standard interface signal; In response to the different levels of verification environment, instantiate the corresponding different levels of the second object under test encapsulation module to the second top-level module, and instantiate the second master or slave device end environment and configuration module, the second test case layer module, and the second interface module to the second top-level module, and connect the object under test and the second verification intellectual property module; In response to the different levels of verification environment, instantiate the corresponding different levels of the objects to be tested into the second object to be tested encapsulation module, and perform a level replacement process on the objects to be tested, so that the second verification intellectual property module is connected to different objects to be tested; Performing a level replacement process on the second test case layer module according to the levels of the different levels of verification environments to implement the use of the test case; Maintaining a connection relationship between an internal signal of the object to be tested and an interface signal in the second interface module related to the object to be tested; Parameter configuration is performed based on the second master or slave device side environment and the configuration module and the different levels of verification environment.

8. The processing method according to claim 5 or 7, wherein: Based on the second verification intellectual property module, general processing is performed to realize the integration of verification intellectual property modules for verification environments of different levels, and further includes: The second coverage module is mapped from module level to subsystem level and system-on-chip level.

9. The processing method according to claim 7, wherein: The setting of performing a hierarchical replacement process on the object to be tested includes: The level of the object under test is defined using a macro, wherein the level of the object under test corresponds one-to-one to the levels of the verification environments at different levels.

10. The processing method according to claim 7, wherein: The setting of performing level replacement processing on the second test case layer module according to the levels of the different levels of verification environments includes: The second test case layer module is macro-defined according to the hierarchy of the different levels of verification environment to achieve replacement of test case layers at module level, subsystem level, and system-on-chip level.

11. A processing device for acquiring an environment, comprising: An acquisition module configured to acquire a first verification intellectual property module for the object to be tested, wherein the first verification intellectual property module includes one or more verification intellectual property modules based on a general verification methodology; A classification module, configured to classify the first verification intellectual property module to obtain a classified second verification intellectual property module; The universal processing module is configured to perform universal processing based on the second verification intellectual property module to achieve integration of verification intellectual property modules for verification environments of different levels.

12. A verification method, comprising: A current verification environment is obtained based on the processing method according to any one of claims 1 to 10, and a simulation operation is performed based on the current verification environment to implement the verification method.

13. An electronic device comprising: processor and memory, Wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the processing method described in any one of claims 1 to 10 is implemented.

14. A computer-readable storage medium, wherein: The storage medium stores a computer program, and when the computer program is executed by a processor, the processing method according to any one of claims 1 to 10 is implemented.

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