A method, apparatus, device and medium for on-chip firmware security protection

Abstract

The application provides a method, device, equipment and medium for on-chip firmware security protection, the method comprising: generating a target protection mode corresponding to a protection requirement level of a chip to be processed according to the protection requirement level; wherein the target protection mode comprises a plurality of different levels of sub-protection modes; when a target operation on the chip to be processed is detected, detecting the target operation using the target protection mode; when the target operation passes the verification of each sub-protection mode in the target protection mode in turn, executing the target operation on the chip to be processed. The embodiment of the application adds protection to the chip to be processed, and the processing operation on the chip to be processed needs to be verified before the processing operation is performed, and the processing operation on the chip to be processed can be performed only when the verification is passed, thereby avoiding chip damage caused by abnormal operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip protection technical field, in particular, relates to a kind of on-chip firmware security protection method, device, equipment and medium. BACKGROUND

[0002] At present, nonvolatile memory in chip, almost all are designed and realized by direct programming (write) operation and erase operation, erase and programming (write) operation, wherein, programming operation, directly to address write, erase operation is realized by writing corresponding erase command.

[0003] Nonvolatile memory, such as FLASH or OTP, as chip internal storage unit, the information stored is mainly customer's program, or important chip calibration information.If no corresponding protection measures are taken on chip design, in chip debugging or application, it is extremely possible to cause storage information to be rewritten due to misoperation or system anomaly. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a kind of on-chip firmware security protection method, device, equipment and medium to overcome the problems in the prior art.

[0005] In the first aspect, the present application provides a kind of on-chip firmware security protection method, the method comprises:

[0006] According to the protection requirement level of the chip to be processed, the target protection mode corresponding to the protection requirement level is generated;Wherein, the target protection mode includes multiple different levels of sub-protection mode;

[0007] When detecting the target operation on the chip to be processed, the target operation is detected using the target protection mode;

[0008] When the target operation passes the verification of each sub-protection mode in the target protection mode in turn, the target operation is executed on the chip to be processed.

[0009] In some technical solutions of the present application, the above-mentioned chip to be processed includes a first protection area;The protection requirement level of the chip to be processed is low-level protection requirement;

[0010] According to the protection requirement level of the chip to be processed, the target protection mode corresponding to the protection requirement level is generated;Wherein, the target protection mode includes multiple different levels of sub-protection mode, including:

[0011] According to the low-level protection requirement of the to-be-processed chip, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, and the third-level protection mode is sub-operation enable protection of the register.

[0012] In some technical solutions of the present application, the to-be-processed chip includes a first protection area; the register of the to-be-processed chip includes a plurality of sub-areas, and the protection requirement level of the to-be-processed chip is a medium-level protection requirement;

[0013] According to the protection requirement level of the to-be-processed chip, a target protection mode corresponding to the protection requirement level is generated; wherein, the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0014] According to the medium-level protection requirement of the to-be-processed chip, a first-level protection mode, a second-level protection mode, a third-level protection mode and a fourth-level protection mode are generated in the first protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, the third-level protection mode is sub-operation enable protection of the register, and the fourth-level protection mode is sub-area lock protection.

[0015] In some technical solutions of the present application, the to-be-processed chip includes a first protection area and a second protection area; the protection requirement level of the to-be-processed chip is a high-level protection requirement;

[0016] According to the protection requirement level of the to-be-processed chip, a target protection mode corresponding to the protection requirement level is generated; wherein, the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0017] According to the high-level protection requirement of the to-be-processed chip, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area, and a fifth-level protection mode is generated in the second protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, the third-level protection mode is sub-operation enable protection of the register, and the fifth-level protection mode is overall area lock protection.

[0018] In some technical solutions of the present application, the to-be-processed chip includes a first protection area and a second protection area; the protection requirement level of the to-be-processed chip is a high-level protection requirement;

[0019] The target protection mode corresponding to the protection requirement level is generated according to the protection requirement level of the chip to be processed; wherein the target protection mode includes a plurality of different levels of sub-protection modes, including:

[0020] The first level protection mode, the second level protection mode, the third level protection mode and the fourth level protection mode are generated in the first protection region according to the higher level protection requirement of the chip to be processed; the fifth level protection mode is generated in the second protection region; wherein the first level protection mode is register access protection, the second level protection mode is overall operation enable protection of the register, the third level protection mode is sub-operation enable protection of the register, the fourth level protection mode is sub-region locking protection, and the fifth level protection mode is overall region locking protection.

[0021] In some technical solutions of the present application, when the target operation is verified by each sub-protection mode in the target protection mode in turn, the target operation is performed on the chip to be processed, including:

[0022] The first identification bit, the second identification bit, the third identification bit and the fourth identification bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode and the fourth level protection mode are read from the first protection region;

[0023] The fifth identification bit of the fifth level protection mode is read from the second protection region;

[0024] The first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit are verified in turn, and when all identification bits pass the verification, the target operation is performed on the chip to be processed.

[0025] In some technical solutions of the present application, the method further includes:

[0026] If any one of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit fails to pass the verification, subsequent verification is not performed, and the target operation is not performed on the chip to be processed.

[0027] In a second aspect, the embodiments of the present application provide a device for on-chip firmware security protection, the device comprising:

[0028] The generation module is configured to generate a target protection mode corresponding to a protection requirement level of a chip to be processed according to the protection requirement level; wherein the target protection mode includes a plurality of different levels of sub-protection modes;

[0029] The detection module is configured to, when a target operation on the chip to be processed is detected, detect the target operation using the target protection mode.

[0030] The verification module is configured to, when the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, execute the target operation on the chip to be processed.

[0031] In a third aspect, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor. When the processor executes the computer program, the steps of the on-chip firmware security protection method described above are implemented.

[0032] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program. When the computer program is run by a processor, the steps of the on-chip firmware security protection method described above are executed.

[0033] The technical solutions provided by the embodiments of the present application can include the following beneficial effects:

[0034] The method provided by the present application includes generating a target protection mode corresponding to a protection requirement level of a chip to be processed according to the protection requirement level; the target protection mode includes multiple sub-protection modes of different levels; when a target operation on the chip to be processed is detected, the target operation is detected using the target protection mode; and when the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, the target operation is executed on the chip to be processed. The embodiments of the present application increase the protection of the chip to be processed. Before a processing operation is performed on the chip to be processed, the processing operation needs to be verified. Only when the verification is passed, the chip to be processed can be processed, thereby avoiding damage to the chip caused by abnormal operation.

[0035] In order to make the above objectives, features and advantages of the present application more apparent, the following will describe preferred embodiments in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0037] Figure 1A flowchart of a method for on-chip firmware security protection is shown.

[0038] Figure 2 A schematic diagram of a specific read operation and write operation process is shown.

[0039] Figure 3 A schematic diagram of a device for on-chip firmware security protection is shown.

[0040] Figure 4 A structural schematic diagram of an electronic device is provided. DETAILED DESCRIPTION

[0041] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in detail with reference to the accompanying drawings of the embodiments of the present application. It should be understood that the accompanying drawings in the present application only serve the purpose of description and illustration, and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowchart shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowchart or removed from the flowchart under the guidance of the content of the present application by those skilled in the art.

[0042] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0043] It should be noted that the term “comprises” will be used in the embodiments of the present application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0044] At present, the non-volatile memory inside the chip is almost designed and implemented through direct programming (write) operation and erase operation. The erase and programming (write) operations are implemented, wherein the programming operation directly writes to the address, and the erase operation is implemented by writing the corresponding erase command.

[0045] Non-volatile memory, such as FLASH or OTP, is used as a chip internal storage unit to store information, mainly the customer's program or important chip calibration information. If no corresponding protection measures are taken in chip design, the stored information may be overwritten due to misoperation or system exception during chip debugging or application.

[0046] Based on this, the embodiment of the application provides a method, device, equipment and medium for on-chip firmware security protection, which are described below through embodiments.

[0047] Figure 1 A flowchart of a method for on-chip firmware security protection provided by the embodiment of the application is shown, wherein the method comprises steps S101-S103; specifically:

[0048] S101, generating a target protection mode corresponding to a protection requirement level of a to-be-processed chip according to the protection requirement level; wherein the target protection mode comprises a plurality of different level sub-protection modes;

[0049] S102, detecting a target operation on the to-be-processed chip using the target protection mode;

[0050] S103, executing the target operation on the to-be-processed chip when the target operation passes the verification of each sub-protection mode in the target protection mode in turn.

[0051] The embodiment of the application adds protection to the to-be-processed chip, and the processing operation on the to-be-processed chip needs to be verified before the processing operation is performed, and the to-be-processed chip can only be processed when the verification is passed, thereby avoiding chip damage caused by abnormal operation.

[0052] Some embodiments of the application are described in detail below. In the case of no conflict, the embodiments described below and the features in the embodiments can be combined with each other.

[0053] The chip to be processed in the embodiments of the present application is referred to as a to-be-processed chip. The target protection mode is set for the to-be-processed chip, thereby improving the security of the to-be-processed chip. When the target protection mode is set for the to-be-processed chip, the embodiments of the present application mainly consider the protection requirement level of the to-be-processed chip. Different target protection modes are set according to different protection requirement levels. The protection requirement level of the to-be-processed chip can be determined according to the specific service executed by the to-be-processed chip. For example, the protection requirement level of the to-be-processed chip is low when the to-be-processed chip executes service A, and the protection requirement level of the to-be-processed chip is higher when the to-be-processed chip executes service B. In the specific implementation, the embodiments of the present application divide the protection requirement level of the to-be-processed chip into low-level protection requirement, medium-level protection requirement, high-level protection requirement, and higher-level protection requirement. That is, the embodiments of the present application set a target protection mode for the to-be-processed chip with low-level protection requirement, set a target protection mode for the to-be-processed chip with medium-level protection requirement, set a target protection mode for the to-be-processed chip with high-level protection requirement, and set a target protection mode for the to-be-processed chip with higher-level protection requirement.

[0054] The target protection mode in the embodiments of the present application includes a plurality of different levels of sub-protection modes. The specific difference of the target protection mode lies in the included sub-protection modes when the target protection mode is set. The different levels of sub-protection modes include a first-level protection mode, a second-level protection mode, a third-level protection mode, a fourth-level protection mode, and a fifth-level protection mode. The first-level protection mode, the second-level protection mode, the third-level protection mode, and the fourth-level protection mode are set on the first protection region of the to-be-processed chip, and the fifth-level protection mode is set on the second protection region of the to-be-processed chip.

[0055] Specifically, the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of a register, the third-level protection mode is sub-operation enable protection of a register, the fourth-level protection mode is sub-region lock protection, and the fifth-level protection mode is overall region lock protection. The first protection region is a FLASH region, and the second protection region is an OTP (One Time Programmable) region. The FLASH region is a chip flash memory, also known as a non-volatile random access memory, which is a storage technology embedded in an integrated circuit (IC) and is mainly used for long-term data storage, even if the power is off, the content can be maintained. OTP (One Time Programmable) is a type of memory for a single-chip microcomputer, which means one-time programmable: the program is burned into the single-chip microcomputer and cannot be changed and cleared again.

[0056] In the setting of the target protection mode, the correspondence with the protection requirement level is: according to the low-level protection requirement of the to-be-processed chip, generating the first-level protection mode, the second-level protection mode and the third-level protection mode in the first protection area; according to the medium-level protection requirement of the to-be-processed chip, generating the first-level protection mode, the second-level protection mode, the third-level protection mode and the fourth-level protection mode in the first protection area; according to the high-level protection requirement of the to-be-processed chip, generating the first-level protection mode, the second-level protection mode and the third-level protection mode in the first protection area; generating the fifth-level protection mode in the second protection area; according to the higher-level protection requirement of the to-be-processed chip, generating the first-level protection mode, the second-level protection mode, the third-level protection mode and the fourth-level protection mode in the first protection area; generating the fifth-level protection mode in the second protection area.

[0057] After the setting of the target protection mode is completed, the to-be-processed chip is monitored. When the target operation of the to-be-processed chip is detected, the target operation is detected using the target protection mode, and when the target operation passes the verification of each sub-protection mode in the target protection mode in turn, the target operation is executed on the to-be-processed chip.

[0058] For the to-be-processed chip with the low-level protection requirement, the target operation needs to pass the verification of the first-level protection mode, the second-level protection mode and the third-level protection mode. For the to-be-processed chip with the medium-level protection requirement, the target operation needs to pass the verification of the first-level protection mode, the second-level protection mode, the third-level protection mode and the fourth-level protection mode. For the to-be-processed chip with the high-level protection requirement, the target operation needs to pass the verification of the first-level protection mode, the second-level protection mode, the third-level protection mode and the fifth-level protection mode. For the to-be-processed chip with the higher-level protection requirement, the target operation needs to pass the verification of the first-level protection mode, the second-level protection mode, the third-level protection mode, the fourth-level protection mode and the fifth-level protection mode.

[0059] In the specific verification, the first identification bit, the second identification bit, the third identification bit, the fourth identification bit corresponding to the first protection mode, the second protection mode, the third protection mode and the fourth protection mode are read from the first protection area; the fifth identification bit of the fifth protection mode is read from the second protection area; the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit are verified in turn, and when all the identification bits pass the verification, the target operation is performed on the chip to be processed. If any one of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit fails to pass the verification, the subsequent verification is not performed, and the target operation is not performed on the chip to be processed.

[0060] In an optional embodiment, the write and erase operations of the FLASH need to be enabled by configuring the related registers of the FLASH before the write and erase operations of the FLASH can be performed.

[0061] The first protection mode is FLASH register access protection, and all FLASH registers are protected by eallow, that is, eallow must be configured before the FLASH registers can be configured, and if eallow is not opened, the FLASH cannot be enabled.

[0062] The second protection mode is FLASH enable protection (overall operation enable protection), when the FLASH enable is closed, the FLASH ignores all write and erase instructions, and the third protection mode cannot be effective.

[0063] The third protection mode is FLASH operation protection (sub-operation enable protection), and the write and erase of the FLASH have separate write operation enable and erase operation enable, and when the corresponding enable is not opened, the write and erase action will not be performed.

[0064] The fourth protection mode is lock protection (sub-region lock protection), and different regions (sectors) of the FLASH are locked. The lock function can only be written from 0 to 1, and cannot be re-written from 1 to 0, and the reset domain is power-on reset, that is, only when the chip is powered on, the register will be reset to 0, and the rest of the reset cannot be reset. That is, after the production test is completed, the code can be protected by lock programming region to ensure that the program of the chip will not be rewritten incorrectly during normal operation. It should be noted that if the flash region is locked, the chip cannot unlock the lock without power-off. That is, the locked region cannot be updated during online updating.

[0065] Fifth level protection mode: permanent protection mechanism (overall area lock protection), in the OTP area, define a control lockflag of FLASH. If the corresponding lockflag is effective, the full chip erase of FLASH, and the sector erase and write of the corresponding sector cannot be executed. It should be noted that if the flash area of the OTP flag is locked, the corresponding FLASH area of the chip will be permanently locked.

[0066] In an optional embodiment, as shown in Figure 2 for FLASH write operation: configure eallow register, allow write operation on FLASH operation register; configure FLASH enable valid, allow FLASH to perform erase and write operation;

[0067] Configure FLASH write enable, i.e. flash_write_enable valid, allow flash to perform write operation; judge whether the sector of the current write address is lock wr_lock or not, if lock, the operation is not allowed (FLASH write lock: each sector has its own lock flag bit, which can be locked individually, if lock, the write is not allowed); if there is no write lock, execute read lockflag flag from OTP, see if the flag is lock or not, if lock, the write cannot be executed, if not lock, write data into FLASH.

[0068] For the FLASH erase operation: configure the eallow register to allow write operation on the FLASH operation register; configure the FLASHenable valid to allow the FLASH to perform erase and write operation; configure the FLASH erase enable, i.e., flash erase enable valid, at this time, the FLASH is allowed to execute the erase command; if the whole flash is erased, it is necessary to judge whether all sector erase locks are 0, i.e., all sectors are allowed to be erased, if all are allowed, the erase is executed, otherwise it is not allowed to execute; if part of the flash is erased, it is necessary to judge whether the sector erase lock to be erased is 0, if allowed (lock = 0), the erase is executed, otherwise it is not allowed to execute; the lock flag is read from the otp, and the subsequent process is judged; if there is no lock, the corresponding data is erased. Other descriptions, if the FLASH erase and write enable is turned on, the erase or write operation process is completed, and the enable is automatically turned off through the hardware circuit. That is, the enable of the second level protection mode of the FLASH will be automatically turned off, so that the enable of the third level protection mode will also be turned off; further avoid the risk of data damage caused by the developer forgetting to turn off the enable after programming or erasing due to misoperation.

[0069] Figure 3 A structure diagram of a device for on-chip firmware security protection is shown, and the device comprises:

[0070] A generating module is configured to generate a target protection mode corresponding to a protection requirement level of a to-be-processed chip according to the protection requirement level; the target protection mode comprises a plurality of sub-protection modes of different levels;

[0071] A detecting module is configured to detect a target operation on the to-be-processed chip using the target protection mode when the target operation is detected;

[0072] A verifying module is configured to execute the target operation on the to-be-processed chip when the target operation passes the verification of each sub-protection mode in the target protection mode in turn.

[0073] The to-be-processed chip comprises a first protection region; the protection requirement level of the to-be-processed chip is a low-level protection requirement;

[0074] The target protection mode corresponding to the protection requirement level of the to-be-processed chip is generated according to the protection requirement level; the target protection mode comprises a plurality of sub-protection modes of different levels, which comprises:

[0075] According to the low-level protection requirement of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, and the third-level protection mode is sub-operation enable protection of the register.

[0076] The chip to be processed includes a first protection area; a plurality of sub-areas are included in the register of the chip to be processed, and the protection requirement level of the chip to be processed is a medium-level protection requirement;

[0077] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0078] According to the medium-level protection requirement of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode and a fourth-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, the third-level protection mode is sub-operation enable protection of the register, and the fourth-level protection mode is sub-area locking protection.

[0079] The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high-level protection requirement;

[0080] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0081] According to the high-level protection requirement of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area, and a fifth-level protection mode is generated in the second protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is overall operation enable protection of the register, the third-level protection mode is sub-operation enable protection of the register, and the fifth-level protection mode is overall area locking protection.

[0082] The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a higher-level protection requirement;

[0083] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0084] According to a higher protection requirement of the chip to be processed, a first protection mode, a second protection mode, a third protection mode and a fourth protection mode are generated in the first protection area; a fifth protection mode is generated in the second protection area; the first protection mode is register access protection, the second protection mode is overall operation enable protection of a register, the third protection mode is sub-operation enable protection of a register, the fourth protection mode is sub-area locking protection, and the fifth protection mode is overall area locking protection.

[0085] The target operation is executed on the chip to be processed when the target operation is verified by each sub-protection mode in the target protection mode in sequence, and the target operation is executed on the chip to be processed.

[0086] First, second, third and fourth identification bits corresponding to the first protection mode, the second protection mode, the third protection mode and the fourth protection mode are read from the first protection area.

[0087] A fifth identification bit of the fifth protection mode is read from the second protection area.

[0088] The first, second, third, fourth and fifth identification bits are verified in sequence, and the target operation is executed on the chip to be processed when all the identification bits pass the verification.

[0089] If any one of the first, second, third, fourth and fifth identification bits fails to pass the verification, subsequent verification is not performed, and the target operation is not executed on the chip to be processed.

[0090] As shown in Figure 4 The embodiment of the present application provides an electronic device for executing the on-chip firmware security protection method, the device comprises a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to realize the steps of the on-chip firmware security protection method.

[0091] Specifically, the memory and the processor can be general memory and processor, which are not specifically limited here, and when the processor runs the computer program stored in the memory, the on-chip firmware security protection method can be executed.

[0092] Corresponding to the method of on-chip firmware security protection in the application, the computer readable storage medium is also provided, and the computer readable storage medium stores the computer program. When the computer program is run by the processor, the steps of the method of on-chip firmware security protection are executed.

[0093] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, the method of on-chip firmware security protection can be executed.

[0094] In the embodiments provided in the application, it should be understood that the disclosed system and method can be implemented in other ways. The system embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, another division mode can be used. For another example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces. The coupling or communication connection can be electrical, mechanical or other forms.

[0095] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units. They can be located in one place or distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0096] In addition, the functional units in the embodiments provided in the application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0097] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the application essentially or the parts of the prior art that make contributions or parts of the technical solutions can be embodied in the form of software products. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0098] It should be noted that like reference numerals and letters refer to like elements throughout the several views of the drawings, and that, unless otherwise indicated, like reference numerals and letters are used consistently throughout the drawings and the description and have meanings ascribed to them even when doing so incurs redundancy. Furthermore, the terms "first", "second", "third", etc. are used merely as identifiers, and are not intended to signify or imply relative importance.

[0099] Finally, it should be noted that the above-described embodiments are merely exemplary of the application, which is not limited to them, but can be practiced with modification and alteration within the scope of the appended claims. Accordingly, the specification, including the examples, is to be regarded in an illustrative manner and not a restrictive one.

Claims

1. A method for on-chip firmware security protection, characterized in that, The method includes: Based on the protection requirement level of the chip to be processed, a target protection method corresponding to the protection requirement level is generated; wherein, the target protection method includes multiple sub-protection methods of different levels; the protection requirement level of the chip to be processed is determined according to the specific business performed by the chip to be processed; the sub-protection methods are set in different protection areas; When a target operation on the chip to be processed is detected, the target operation is detected using the target protection method; When the target operation passes the verification of each sub-protection method in the target protection method in sequence, the target operation is executed on the chip to be processed; The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high level of protection requirement; The step involves generating a target protection method corresponding to the protection requirement level of the chip to be processed; wherein the target protection method includes multiple sub-protection methods at different levels, including: Based on the higher level of protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode, and a fourth-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall register operation enable protection, the third-level protection mode is sub-register operation enable protection, the fourth-level protection mode is sub-region locking protection, and the fifth-level protection mode is overall region locking protection; When the target operation passes the verification of each sub-protection method in the target protection method in sequence, the target operation is executed on the chip to be processed, including: Read the first identifier bit, second identifier bit, third identifier bit, and fourth identifier bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode from the first protection area; Read the fifth identifier bit of the fifth level of protection mode from the second protection area; The first, second, third, fourth, and fifth flag bits are verified sequentially. When all flag bits pass verification, the target operation is performed on the chip to be processed.

2. The method according to claim 1, characterized in that, The chip to be processed includes a first protection area; the protection requirement level of the chip to be processed is low-level protection requirement; The step involves generating a target protection method corresponding to the protection requirement level of the chip to be processed; wherein the target protection method includes multiple sub-protection methods at different levels, including: Based on the low-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, and a third-level protection mode are generated in the first protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall register operation enable protection, and the third-level protection mode is sub-register operation enable protection.

3. The method according to claim 1, characterized in that, The chip to be processed includes a first protection area; the register of the chip to be processed includes multiple sub-regions; the protection requirement level of the chip to be processed is medium level protection requirement. The step involves generating a target protection method corresponding to the protection requirement level of the chip to be processed; wherein the target protection method includes multiple sub-protection methods at different levels, including: Based on the medium-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode, and a fourth-level protection mode are generated in the first protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall register operation enable protection, the third-level protection mode is sub-register operation enable protection, and the fourth-level protection mode is sub-region locking protection.

4. The method according to claim 1, characterized in that, The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is high-level protection requirement; The step involves generating a target protection method corresponding to the protection requirement level of the chip to be processed; wherein the target protection method includes multiple sub-protection methods at different levels, including: Based on the high-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, and a third-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall register operation enable protection, the third-level protection mode is sub-register operation enable protection, and the fifth-level protection mode is overall area locking protection.

5. The method according to claim 1, characterized in that, The method further includes: If any of the first, second, third, fourth, or fifth flag bits fails verification, further verification will not be performed, and the target operation will not be executed on the chip to be processed.

6. A device for on-chip firmware security protection, characterized in that, The device includes: The generation module is used to generate a target protection method corresponding to the protection requirement level of the chip to be processed; wherein, the target protection method includes multiple sub-protection methods of different levels; the protection requirement level of the chip to be processed is determined according to the specific business performed by the chip to be processed; the sub-protection methods are set in different protection areas; The detection module is used to detect the target operation using the target protection method when a target operation on the chip to be processed is detected. The verification module is used to execute the target operation on the chip to be processed when the target operation passes the verification of each sub-protection method in the target protection method in sequence; The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high level of protection requirement; The step involves generating a target protection method corresponding to the protection requirement level of the chip to be processed; wherein the target protection method includes multiple sub-protection methods at different levels, including: Based on the higher level of protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode, and a fourth-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein, the first-level protection mode is register access protection, the second-level protection mode is overall register operation enable protection, the third-level protection mode is sub-register operation enable protection, the fourth-level protection mode is sub-region locking protection, and the fifth-level protection mode is overall region locking protection; When the target operation passes the verification of each sub-protection method in the target protection method in sequence, the target operation is executed on the chip to be processed, including: Read the first identifier bit, second identifier bit, third identifier bit, and fourth identifier bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode from the first protection area; Read the fifth identifier bit of the fifth level of protection mode from the second protection area; The first, second, third, fourth, and fifth flag bits are verified sequentially. When all flag bits pass verification, the target operation is performed on the chip to be processed.

7. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, they perform the steps of the on-chip firmware security protection method as described in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the on-chip firmware security protection method as described in any one of claims 1 to 5.

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