Decoder for analog neural memory in deep learning artificial neural networks

Abstract

Various embodiments of a decoder for use with a vector-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoder comprises a bit line decoder, a word line decoder, a control gate decoder, a source line decoder and an erase gate decoder. In some embodiments, a high voltage pattern and a low voltage pattern of a decoder are used.

Description

[0001] This application is a divisional application of a patent application with an international application date of January 24, 2019, an international application number of PCT / US2019 / 015022, a Chinese national application date of January 24, 2019, an application number of 201980018434.5, and an invention name of "Decoder for Simulating Neural Memory in Deep Learning Artificial Neural Networks".

[0002] Priority declaration

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 642,884, filed on March 14, 2018, and entitled “Decoders for Analog Neuromorphic Memory in Artificial Neural Network,” and U.S. Patent Application No. 15 / 991,890, filed on May 29, 2018, and entitled “Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network.” Technical Field

[0004] The present invention discloses various embodiments of a decoder for use with vector-matrix multiplication (VMM) arrays in artificial neural networks. Background Art

[0005] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are usually unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0006] Figure 1 An artificial neural network is shown, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0007] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, i.e. very high computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0008] Applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application 15 / 594,439, which is incorporated herein by reference. The non-volatile memory array operates as an simulated neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed over a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0009] Each nonvolatile memory cell used in an analog neuromorphic memory system must be erased and programmed to hold a very specific and precise amount of charge in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, and 64.

[0010] Prior art decoding circuits used in conventional flash memory arrays, such as bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders, are not suitable for use with VMMs in analog neuromorphic memory systems. One reason for this is that in VMM systems, the verify portion of the programming and verify operations (which is a read operation) operates on a single selected memory cell, while the read operation operates on all memory cells in the array.

[0011] What is needed is an improved decoding circuit suitable for use with a VMM in an analog neuromorphic memory system. Summary of the invention

[0012] The present invention discloses various embodiments of a decoder for use with vector-matrix multiplication (VMM) arrays in artificial neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram showing an artificial neural network.

[0014] Figure 2 is a cross-sectional side view of a conventional 2-gate non-volatile memory cell.

[0015] Figure 3 is a cross-sectional side view of a conventional 4-gate non-volatile memory cell.

[0016] Figure 4 FIG. 4 is a side cross-sectional view of a conventional 3-gate non-volatile memory cell.

[0017] Figure 5 FIG. 4 is a cross-sectional side view of another conventional 2-gate non-volatile memory cell.

[0018] Figure 6 A schematic diagram showing different stages of an exemplary artificial neural network utilizing a non-volatile memory array.

[0019] Figure 7 is a block diagram showing a vector multiplier matrix.

[0020] Figure 8 is a block diagram showing the various stages of the vector multiplier matrix.

[0021] Fig. 9 An implementation of a vector multiplier matrix is ​​depicted.

[0022] Fig.10 Another implementation of a vector multiplier matrix is ​​depicted.

[0023] Fig.11 Another implementation of a vector multiplier matrix is ​​depicted.

[0024] Fig.12 Another implementation of a vector multiplier matrix is ​​depicted.

[0025] Fig.13 Another implementation of a vector multiplier matrix is ​​depicted.

[0026] Fig.14 An implementation of a bitline decoder for a vector multiplier matrix is ​​depicted.

[0027] Fig.15 Another implementation of a bitline decoder for a vector multiplier matrix is ​​depicted.

[0028] Fig.16 Another implementation of a bitline decoder for a vector multiplier matrix is ​​depicted.

[0029] Fig.17 A system for manipulating a vector multiplier matrix is ​​depicted.

[0030] Fig.18 Another system for operating a vector multiplier matrix is ​​depicted.

[0031] Fig.19 Another system for operating a vector multiplier matrix is ​​depicted.

[0032] Fig. 20 An implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0033] Fig.21 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0034] Fig. 22 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0035] Fig.23 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0036] Fig.24 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0037] Fig.25 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0038] Fig.26 Another implementation of a wordline driver for use with a vector multiplier matrix is ​​depicted.

[0039] Fig. 27 Depicted is a source line decoder circuit for use with a vector multiplier matrix.

[0040] Fig.28 Depicted are word line decoder circuits, source line decoder circuits, and high voltage level shifters for use with a vector multiplier matrix.

[0041] Fig.29Depicted are an erase gate decoder circuit, a control gate decoder circuit, a source line decoder circuit, and a high voltage level shifter for use with a vector multiplier matrix.

[0042] Fig.30 Depicted is a word line decoder circuit for use with a vector multiplier matrix.

[0043] Fig.31 Depicted is a control gate decoder circuit for use with a vector multiplier matrix.

[0044] Fig.32 Another control gate decoder circuit for use with a vector multiplier matrix is ​​depicted.

[0045] Fig.33 Another control gate decoder circuit for use with a vector multiplier matrix is ​​depicted.

[0046] Fig.34 Depicted is a current-to-voltage circuit for controlling word lines in a vector multiplier matrix.

[0047] Fig.35 Another current-to-voltage circuit for controlling word lines in a vector multiplier matrix is ​​depicted.

[0048] Fig.36 Depicted is a current-to-voltage circuit for controlling the control gate lines in a vector multiplier matrix.

[0049] Fig.37 Another current-to-voltage circuit for controlling control gate lines in a vector multiplier matrix is ​​depicted.

[0050] Fig.38 Another current-to-voltage circuit for controlling control gate lines in a vector multiplier matrix is ​​depicted.

[0051] Fig.39 Another current-to-voltage circuit for controlling word lines in a vector multiplier matrix is ​​depicted.

[0052] Fig.40 Another current-to-voltage circuit for controlling word lines in a vector multiplier matrix is ​​depicted.

[0053] Fig.41 Another current-to-voltage circuit for controlling word lines in a vector multiplier matrix is ​​depicted.

[0054] Fig.42 Depicted Fig. 9 The operating voltage of the vector multiplier matrix.

[0055] Fig.43 Depicted Fig.10The operating voltage of the vector multiplier matrix.

[0056] Fig.44 Depicted Fig.11 The operating voltage of the vector multiplier matrix.

[0057] Fig.45 Depicted Fig.12 The operating voltage of the vector multiplier matrix. DETAILED DESCRIPTION

[0058] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0059] Non-volatile memory cell

[0060] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent") discloses an array of split-gate non-volatile memory cells and is incorporated herein by reference for all purposes. Such memory cells are Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 16. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line 24 is coupled to the drain region 16.

[0061] The storage cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the word line terminal 22, which causes the electrons on the floating gate 20 to tunnel through the intermediate insulator via Fowler-Nordheim tunneling from the floating gate 20 to the word line terminal 22.

[0062] The memory cell 210 is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the word line terminal 22 and a positive voltage on the source 16. Electron current will flow from the source 16 to the drain 14. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide 26 onto the floating gate 20.

[0063] The memory cell 210 is read by placing a positive read voltage on the drain 14 and the word line terminal 22 (which turns on the channel region below the word line terminal). If the floating gate 20 is positively charged (i.e., electrons are erased and positively coupled to the drain 16), the portion of the channel region below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as the erased state or the "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through the channel region 18, which is sensed as the programmed state or the "0" state.

[0064] Table 1 depicts typical voltage ranges that may be applied to the terminals of the memory cell 210 for performing read, erase, and program operations:

[0065] Table 1: Figure 2 Operation of the flash memory unit 210

[0066] WL BL SL Read 2V-3V 0.6V-2V 0V Erase About 11V-13V 0V 0V programming 1V-2V 1μA-3μA 9V-10V

[0067] Other split-gate memory cell configurations are known. For example, Figure 3 A quad-gate memory cell 310 is depicted, which includes a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 28 (typically coupled to a word line) over a second portion of the channel region 18, a control gate 22 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is shown by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is shown by electrons tunneling from the floating gate 20 to the erase gate 30.

[0068] Table 2 depicts typical voltage ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0069] Table 2: Figure 3 Operation of the flash memory unit 310

[0070]

[0071] Figure 4 A split gate tri-gate memory cell 410 is depicted. The memory cell 410 is Figure 3 The memory cell 310 is the same as the memory cell 410 except that the memory cell 410 does not have a separate control gate. The erase operation (erasing through the erase gate) and the read operation are the same as Figure 3The operation is similar to that of , except that there is no control gate bias. The programming operation is also done without a control gate bias, so the programming voltage on the source line is higher to compensate for the lack of control gate bias.

[0072] Table 3 depicts typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0073] Table 3: Figure 4 Operation of the flash memory unit 410

[0074] WL / SG BL EG SL Read 0.7V-2.2V 0.6V-2V 0-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 2μA-3μA 4.5V 7V-9V

[0075] Figure 5 A stacked gate memory cell 510 is depicted. The memory cell 510 is similar to Figure 2 Memory cell 210 of the embodiment of the present invention is shown, except that floating gate 20 extends over the entire channel region 18, and control gate 22 extends over floating gate 20, separated by an insulating layer. Erase, program and read operations operate in a similar manner as previously described for memory cell 210.

[0076] Table 4 depicts typical voltage ranges that may be applied to the terminals of the memory cell 510 for performing read, erase, and program operations:

[0077] Table 4: Figure 5 Operation of the flash memory unit 510

[0078] CG BL SL P-sub Read 2V-5V 0.6–2V 0V 0V Erase -8V to -10V / 0V FLT FLT 8V-10V / 15-20V programming 8V-12V 3V-5V 0V 0V

[0079] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0080] Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all cells in the memory array, and this makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0081] Neural Network Using Non-Volatile Memory Cell Array

[0082] Figure 6 A non-limiting example of a neural network utilizing a non-volatile memory array is conceptually illustrated. This example uses the non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0083] For this example, S0 is the input, which is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5-bit precision per pixel). The synapse CB1 from S0 to C1 has both different sets of weights and shared weights, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to the synapse CB1, whereby these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of this multiplication, a single output value is determined and provided by the first neuron of CB1 for the pixels of one of the layers C1 of the feature map. The 3x3 filter is then shifted one pixel to the right (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, whereby they are multiplied by the same weights and a second single output value is determined by the associated neuron. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image. The process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are calculated.

[0084] At C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, the synapse CB1 is composed of a two-dimensional array of 16 layers (remember that the neuron layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, the arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0085] Before going from C1 to S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling stage is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). The synapses and associated neurons from S1 to C2 in CB2 scan the maps in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At C2, there are 22 12x12 feature maps. Before going from C2 to S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At S2, there are 22 6x6 feature maps. The activation function is applied to the synapse CB3 from S2 to C3, where each neuron in C3 is connected to each map in S2. At C3, there are 64 neurons. Synapse CB4 from C3 to output S3 fully connects S3 to C3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, this output may indicate recognition or classification of the content of the original image.

[0086] Each level of synapses is implemented using an array or portion of an array of non-volatile memory cells. Figure 7 A block diagram of a vector-matrix multiplication (VMM) array that includes nonvolatile memory cells and is used as a synapse between an input layer and the next layer. Specifically, VMM 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the input of the memory array 33. In this example, the source line decoder 37 also decodes the output of the memory cell array. Alternatively, the bit line decoder 36 can decode the output of the memory array. The memory array has two purposes. First, it stores weights to be used by the VMM. Second, the memory array effectively multiplies the input with the weights stored in the memory array and adds them for each output line (source line or bit line) to produce an output, which will serve as the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits, and is also highly power-efficient due to in-situ memory calculations.

[0087] The output of the memory array is provided to a differential adder (such as an adding operational amplifier) ​​38, which sums the output of the memory cell array to create a single value for the convolution. The differential adder is to achieve the sum of positive weights and negative weights with the positive input. The summed output value is then provided to an activation function circuit 39, which corrects the output. The activation function may include a sigmoid, tanh, or ReLU function. The corrected output value becomes an element of the feature map of the next layer (e.g., C1 in the above description) and is then applied to the next synapse to produce the next feature map layer or the final layer. Therefore, in this example, the memory array constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and the activation function circuit 39 constitute a plurality of neurons.

[0088] Figure 8 It is a block diagram of each level of VMM. Fig.14 As shown, the input is converted from digital to analog by a digital-to-analog converter 31 and provided to an input VMM 32a. The output generated by the input VMM 32a is provided as the input of the next VMM (hidden level 1) 32b, which in turn generates an output provided as the input of the next VMM (hidden level 2) 32b, and so on. The layers of the VMM 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM can be an independent non-volatile memory array, or multiple VMMs can utilize different portions of the same non-volatile memory array, or multiple VMMs can utilize overlapping portions of the same non-volatile memory array. Figure 8 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). Those of ordinary skill in the art will appreciate that this is merely exemplary and that the system may alternatively include more than two hidden layers and more than two fully connected layers.

[0089] Vector-Matrix Multiplication (VMM) Array

[0090] Fig. 9 Depicted is a Neuron VMM 900, which is particularly suitable for Figure 2Memory cells of the type shown, and used as synapses and components of neurons between the input layer and the next layer. VMM 900 includes a memory array 903 of non-volatile memory cells, a reference array 901 and a reference array 902. Reference arrays 901 and 902 are used to convert current inputs flowing into terminals BLR0-3 into voltage inputs WL0-3. As shown, reference arrays 901 and 902 are in the column direction. Generally speaking, the reference array direction is orthogonal to the input line. In practice, the reference memory cell is a diode connected to the current input flowing therein through a multiplexer (multiplexer 914, which includes a multiplexer and a cascade transistor VBLR for biasing the reference bit line). The reference cell is tuned to a target reference level.

[0091] The memory array 903 serves two purposes. First, it stores weights to be used by the VMM 900. Second, the memory array 903 effectively multiplies the inputs (current inputs provided in terminals BLR0-3; reference arrays 901 and 902 convert these current inputs into input voltages to be provided to word lines WL0-3) by the weights stored in the memory array to produce an output, which will be the input to the next layer or the input to the final layer. By performing a multiplication function, the memory array eliminates the need for a separate multiplication logic circuit and is also highly power efficient. Here, the voltage input is provided on the word line and the output appears on the bit line during a read (inference) operation. The current placed on the bit line performs a summing function of all currents from the memory cells connected to the bit line.

[0092] Fig.42 Depicted are operating voltages for VMM 900. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for unselected cells, the bit line for a selected cell, the bit line for unselected cells, the source line for a selected cell, and the source line for unselected cells. The rows indicate read, erase, and program operations.

[0093] Fig.10 Depicted is a neuron VMM 1000, which is particularly suitable for Figure 21 and 10. The VMM 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001, and a reference array 1002. The VMM 1000 is similar to the VMM 900, except that in the VMM 1000, the word lines extend in the vertical direction. There are two reference arrays 1001 (at the top, which provides a reference for converting the input current into a voltage for the even rows) and 1002 (at the bottom, which provides a reference for converting the input current into a voltage for the odd rows). Here, the input is provided on the word line, and the output appears on the source line during a read operation. The current placed on the source line performs a summing function of all the currents from the memory cells connected to the source line.

[0094] Fig.43 Depicted are operating voltages for VMM 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for unselected cells, the bit line for a selected cell, the bit line for unselected cells, the source line for a selected cell, and the source line for unselected cells. The rows indicate read, erase, and program operations.

[0095] Fig.11 A neuron VMM 1100 is depicted, which is particularly suitable for Figure 3 1 and 10. The VMM 1100 includes a memory array 1101 of nonvolatile memory cells, a reference array 1102 (which provides a reference for converting input current into input voltage for even rows), and a reference array 1103 (which provides a reference for converting input current into input voltage for odd rows). VMM 1100 is similar to VMM 900, except that VMM 1100 also includes a control line 1106 coupled to the control gates of a row of memory cells and a control line 1107 coupled to the erase gates of an adjacent row of memory cells. Here, the word lines, control gate lines, and erase gate lines have the same direction. The VMM also includes a reference bit line select transistor 1104 (part of mux 1114) that selectively couples the reference bit line to the bit line contact of a selected reference memory cell and a switch 1105 (part of mux 1114) that selectively couples the reference bit line to a control line 1106 for a particular selected reference memory cell. Here, the input is provided on the word line (of the memory array 1101) and the output appears on the bit line (such as bit line 1109) during a read operation. The current placed on the bit line performs a summing function of all the currents from the memory cells connected to the bit line.

[0096] Fig.44Depicted are operating voltages for the VMM 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0097] Fig.12 A neuron VMM 1200 is depicted, which is particularly suitable for Figure 3 1200 is similar to VMM 1100, except that in VMM 1200, the erase gate line (such as erase gate line 1201) extends in the vertical direction. Here, the input is provided on the word line, and the output appears on the source line. The current placed on the bit line performs the summing function of all the currents from the memory cells connected to the bit line.

[0098] Fig.45 Depicted are operating voltages for the VMM 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0099] Fig.13 Depicted is a neuron VMM 1300, which is particularly suitable for Figure 3 1300 and serves as a synapse and component of neurons between the input layer and the next layer. VMM 1300 includes a memory array 1301 of non-volatile memory cells and a reference array 1302 (at the top of the array). Alternatively, another reference array may be provided at the bottom, similar to Fig.10Reference array. In other respects, VMM 1300 is similar to VMM 1200, except that in VMM 1300, control gate lines (such as control gate lines 1303) extend in the vertical direction (therefore reference array 1302 is in the row direction orthogonal to the input control gate lines), and erase gate lines (such as erase gate lines 1304) extend in the horizontal direction. Here, input is provided on the control gate lines, and output occurs on the source lines. In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on the source lines performs the summing function of all currents of the memory cells connected to the source lines.

[0100] As described herein for neural networks, flash memory cells are preferably configured to operate in the subthreshold region.

[0101] The memory cell described in this article is weakly reverse biased:

[0102] Ids=Io*e (Vg-Vth) / kVt =w*Io*e (Vg) / kVt

[0103] w=e (-Vth) / kVt

[0104] For an I to V logarithmic converter that uses a memory cell to convert input current to input voltage:

[0105] Vg=k*Vt*log[Ids / wp*Io]

[0106] For a memory array used as a vector matrix multiplier VMM, the output current is:

[0107] Iout=wa*Io*e (Vg) / kVt ,Right now

[0108] Iout=(wa / wp)*Iin=W*Iin

[0109] W=e (Vthp-Vtha) / kVt

[0110] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0111] Alternatively, the flash memory cell can be configured to operate in the linear region:

[0112] Ids=beta*(Vgs-Vth)*Vds;beta=u*Cox*W / L

[0113] Wα(Vgs-Vth)

[0114] For an I to V linear converter, a memory cell operating in the linear region can be used to linearly convert the input / output current to the input / output voltage.

[0115] Other implementations of the ESF vector-matrix multiplier are described in US Patent Application 15 / 826,345, which is incorporated herein by reference. A source line or a bit line can be used as a neuron output (current summing output).

[0116] Fig.14 Depicted is an implementation of a bit line decoder circuit 1400. The bit line decoder circuit 1400 includes a column decoder 1402 and an analog neuromorphic neuron ("ANN") column decoder 1403, each of which is coupled to a VMM array 1401. The VMM array may be based on any of the previously discussed VMM designs (such as VMMs 900, 1000, 1100, 1200, and 1300) or other VMM designs.

[0117] One challenge with analog neuromorphic systems is that the system must be able to program and verify individually selected cells (which involves a read operation), and it must also be able to perform an ANN read, where all cells in the array are selected and read. In other words, the bitline decoder must sometimes select only one bitline, and in other cases must select all bitlines.

[0118] Bit line decoder circuit 1400 accomplishes this purpose. Column decoder 1402 is a conventional column decoder (program and erase or PE decoding path) and can be used to select individual bit lines, such as for programming and program verification (sensing operations). The output of column decoder 1402 is coupled to a program / erase (PE) column driver circuit for controlling programming, PE verification, and erasure (not shown). Fig.14 ). The ANN column decoder 1403 is a column decoder specifically designed to enable read operations on each bit line simultaneously. The ANN column decoder 1403 includes an exemplary selection transistor 1405 coupled to a bit line (here BL0) and an output circuit (e.g., a current adder and a function circuit such as tanh, sigmoid, ReLU) 1406. A set of identical devices is attached to each of the other bit lines. All selection transistors (such as selection transistor 1405) are coupled to selection line 1404. During an ANN read operation, selection line 1404 is enabled, which in turn turns on each of the selection transistors (such as selection transistor 1405), thereby then causing the current from each bit line to be received and output by the output circuit (such as circuit 1406).

[0119] Fig.15Depicted is an implementation of a bit line decoder circuit 1500. Bit line decoder circuit 1500 is coupled to a VMM array 1501. The VMM array may be based on any of the previously discussed VMM designs, such as VMMs 900, 1000, 1100, 1200, and 1300, or other VMM designs.

[0120] Select transistors 1502 and 1503 are controlled by a pair of complementary control signals (V0 and VB_0) and are coupled to a bit line (BL0). Select transistors 1504 and 1505 are controlled by another pair of complementary control signals (V1 and VB_1) and are coupled to another bit line (BL1). Select transistors 1502 and 1504 are coupled to the same output, such as for enabling programming, and select transistors 1503 and 1505 are coupled to the same output, such as for inhibiting programming. The output lines of transistors 1502 / 1503 / 1504 / 1505 (program and erase PE decoding paths) are coupled to PE column driver circuits, such as for controlling programming, PE verification, and erasing (not shown).

[0121] The select transistor 1506 is coupled to the bit line ( BL0 ) and to an output and activation function circuit 1507 (eg, a current adder and an activation function such as tanh, sigmoid, ReLU). The select transistor 1506 is controlled by a control line 1508 .

[0122] When only BL0 is activated, control line 1508 is deasserted and signal V0 is asserted, thereby reading only BL0. During an ANN read operation, control line 1508 is asserted, turning on select transistor 1506 and similar transistors, and all bit lines are read, such as for all neuron processing.

[0123] Fig.16 Depicted is an implementation of a bit line decoder circuit 1600. Bit line decoder circuit 1600 is coupled to a VMM array 1601. The VMM array may be based on any of the previously discussed VMM designs, such as VMMs 900, 1000, 1100, 1200, and 1300, or other VMM designs.

[0124] A select transistor 1601 is coupled to the bit line (BL0) and to the output and activation function circuit 1603. A select transistor 1602 is coupled to the bit line (BL0) and to the common output (PE decoding path).

[0125] When only BL0 is activated, select transistor 1602 is activated and BL0 is attached to a common output.During an ANN read operation, select transistor 1601 and similar transistors are turned on and all bit lines are read.

[0126] for Fig.14 , Fig.15 and Fig.16 For decoding in the , negative bias can be applied to unselected transistors to reduce transistor leakage so as not to affect memory cell performance. Alternatively, a negative bias can be applied to the PE decoding path when the array is in ANN operation. The negative bias can be from -0.1V to -0.5V or greater.

[0127] Fig.17 Depicted is a VMM system 1700. The VMM system 1700 includes a VMM array 1701 and a reference array 1720 (which may be based on any of the previously discussed VMM designs (such as VMM 900, 1000, 1100, 1200, and 1300), or other VMM designs), a low voltage row decoder 1702, a high voltage row decoder 1703, a reference cell low voltage column decoder 1704 (shown for the reference array in the column direction, which means providing input to output conversion in the row direction), a bit line PE driver 1712, a bit line multiplexer 1706, an activation function circuit and adder 1707, a control logic 1705, and an analog bias circuit 1708.

[0128] As shown, the reference cell low voltage column decoder 1704 is used for the reference array 1720 in the column direction, which means providing input to output conversion in the row direction. If the reference array is in the row direction, the reference decoder needs to be completed on the top and / or bottom of the array to provide input to output conversion in the column direction.

[0129] The low voltage row decoder 1702 provides bias voltages for read operations and program operations, and provides decoding signals for the high voltage row decoder 1703. The high voltage row decoder 1703 provides high voltage bias signals for program operations and erase operations. The reference cell low voltage column decoder 1704 provides decoding functions for reference cells. The bit line PE driver 1712 provides control functions for the bit lines in programming, verification and erasure. The bias circuit 1705 is a shared bias block that provides multiple voltages required for various programming, erasing, program verification and reading operations.

[0130] Fig.18VMM system 1800 is depicted. VMM system 1800 is similar to VMM system 1700, except that VMM system 1800 also includes a red array 1801, a bit line PE driver BLDRV1802, a high voltage column decoder 1803, an NVR sector 1804, and a reference array 1820. The high voltage column decoder 1803 provides a high voltage bias for the vertical decode lines. The red array 1802 provides array redundancy for replacing defective array portions. The NVR (non-volatile register also known as an information sector) sector 1804 is a sector that is an array sector for storing user information, device ID, password, security key, trim bit, configuration bit, manufacturing information, etc.

[0131] Fig.19 VMM system 1900 is depicted. VMM system 1900 is similar to VMM system 1800, except that VMM system 1900 also includes reference system 1999. Reference system 1999 includes reference array 1901, reference array low voltage row decoder 1902, reference array high voltage row decoder 1903, and reference array low voltage column decoder 1904. The reference system can be shared across multiple VMM systems. VMM system also includes NVR sector 1905.

[0132] Reference array low voltage row decoder 1902 provides bias voltages for read operations and programming operations involving reference array 1901, and also provides decoding signals for reference array high voltage row decoder 1903. Reference array high voltage row decoder 1903 provides high voltage bias for programming and operations involving reference array 1901. Reference array low voltage column decoder 1904 provides decoding functions for reference array 1901. Reference array 1901 is used, for example, to provide a reference target for program verification or cell margin trimming (searching for marginal cells).

[0133] Fig. 20A word line driver 2000 is depicted. The word line driver 2000 selects a word line (such as the exemplary word lines WL0, WL1, WL2, and WL3 shown here) and provides a bias voltage to the word line. Each word line is attached to a select transistor, such as a select iso (isolation) transistor 2002, which is controlled by a control line 2001. The iso transistor 2002 is used to isolate a high voltage, such as from erase (e.g., 8V-12V), from the word line decode transistor, which can be implemented with an IO transistor (e.g., 1.8V, 3.3V). Here, during any operation, the control line 2001 is activated and all select transistors, similar to the select iso transistor 2002, are turned on. An exemplary bias transistor 2003 (part of the word line decoding circuit) selectively couples the word line to a first bias voltage (such as 3V), and an exemplary bias transistor 2004 (part of the word line decoding circuit) selectively couples the word line to a second bias voltage (lower than the first bias voltage, including ground, a bias therebetween, a negative voltage bias for reducing leakage from unused memory rows). During an ANN read operation, all used word lines will be selected and tied to the first bias voltage. All unused word lines are tied to the second bias voltage. During other operations, such as for programming operations, only one word line will be selected and the other word lines will be tied to the second bias voltage, which can be a negative bias (e.g., -0.3V to -0.5V or greater) to reduce array leakage.

[0134] Fig.21 Depicted is word line driver 2100. Word line driver 2100 is similar to word line driver 2000, except that the top transistors, such as bias transistor 2103, can be individually coupled to a bias voltage and all such transistors are not tied together as in word line driver 2000. This allows all word lines to have different independent voltages in parallel at the same time.

[0135] Fig. 22 Word line driver 2200 is depicted. Word line driver 2200 is similar to word line driver 2100, except that bias transistors 2103 and 2104 are coupled to decoder circuit 2201 and inverter 2202. Thus, Fig. 22 A decoding subcircuit 2203 within the word line driver 2200 is depicted.

[0136] Fig.23Depicted is a word line driver 2300. Word line driver 2300 is similar to word line driver 2100, except that bias transistors 2103 and 2104 are coupled to the output of stage 2302 of shift register 2301. Shift register 1301 allows each row to be independently controlled by serial shifting in data (serially clocking the register), such as enabling one or more rows to be enabled simultaneously depending on the shift in the data pattern.

[0137] Fig.24 Word line driver 2400 is depicted. Word line driver 2400 is similar to word line driver 2000, except that each select transistor is further coupled to a capacitor (such as capacitor 2403). Capacitor 2403 can provide a pre-charge or bias to the word line at the beginning of operation, enabled by transistor 2401 to sample the voltage on line 2440. Capacitor 2403 is used to sample and hold (S / H) the input voltage of each word line. Transistor 2401 is disconnected during ANN operation (array current adder and activation function) of the VMM array, which means that the voltage on the S / H capacitor will be used as the (floating) voltage source for the word line. Alternatively, capacitor 2403 can be provided by the word line capacitance from the memory array.

[0138] Fig.25 Word line driver 2500 is depicted. Word line driver 2500 is similar to the previously described word line driver except that bias transistors 2501 and 2502 are connected to switches 2503 and 2504, respectively. Switch 2503 receives the output of opa (operational amplifier) ​​2505, and switch 2504 provides a reference input to the negative input of opa 2505, thereby essentially providing the voltage stored by capacitor 2403 through the action of the closed loop provided by opa 2505, transistor 2501, switch 2503, and switch 2504. In this way, when switches 2503 and 2504 are closed, the voltage on input 2506 is superimposed on capacitor 2403 through transistor 2501. Alternatively, capacitor 2403 can be provided by the word line capacitance from the memory array.

[0139] Fig.26 Depicted is a word line driver. The word line driver 2600 is similar to the previously described word line driver, except that an amplifier 2601 is added, which will act as a voltage buffer for the voltage on the capacitor 2604 to drive the voltage into the word line WL0, which means that the voltage on the S / H capacitor will act as a (floating) voltage source for the word line. This is, for example, to avoid word line to word line coupling affecting the voltage on the capacitor.

[0140] Fig. 27A high voltage source line decoder circuit 2700 is depicted. The high voltage source line decoder circuit includes transistors 2701, 2702, and 2703 configured as shown. Transistor 2703 is used to deselect the source line to a low voltage. Transistor 2702 is used to drive a high voltage into the source line of the array, and transistor 2701 is used to monitor the voltage on the source line. Transistors 2702, 2701 and driver circuits (such as opa) are configured in a closed loop manner (force / sensing) to maintain voltage (process, voltage, temperature) and changing current load conditions on the PVT. SLE (driven source line node) and SLB (monitored source line node) can be located at one end of the source line. Alternatively, SLE can be located at one end of the source line, and SLN can be located at the other end of the source line.

[0141] Fig.28 A VMM high voltage decoding circuit is depicted, the VMM high voltage decoding circuit including a circuit suitable for Figure 2 Memory cells of the type shown are used together with word line decoder circuit 2801, source line decoder circuit 2804 and high voltage level shifter 2808.

[0142] The word line decoder circuit 2801 includes a PMOS select transistor 2802 (controlled by signal HVO_B) and an NMOS deselect transistor 2803 (controlled by signal HVO_B) configured as shown.

[0143] The source line decoder circuit 2804 includes an NMOS monitor transistor 2805 (controlled by signal HVO), a drive transistor 2806 (controlled by signal HVO), and a deselect transistor 2807 (controlled by signal HVO_B) configured as shown.

[0144] The high voltage level shifter 2808 receives the enable signal EN and outputs a high voltage signal HV and its complementary signal HVO_B.

[0145] Fig.29 A VMM high voltage decoding circuit is depicted, the VMM high voltage decoding circuit including a circuit suitable for Figure 3 Memory cells of the type shown are used in conjunction with erase gate decoder circuit 2901, control gate decoder circuit 2904, source line decoder circuit 2907, and high voltage level shifter 2911.

[0146] The erase gate decoder circuit 2901 and the control gate decoder circuit 2904 use the same Fig.28 The word line decoder circuit 2801 has the same design.

[0147] Source line decoder circuit 2907 uses Fig.28The source line decoder circuit 2804 has the same design.

[0148] The high voltage level shifter 2911 is used with Fig.28 The high voltage level shifter 2808 has the same design.

[0149] Fig.30 A word line decoder 300 is depicted for exemplary word lines WLO, WL1, WL2, and WL3. Exemplary word line WLO is coupled to a pull-up transistor 3001 and a pull-down transistor 3002. When pull-up transistor 3001 is activated, WLO is enabled. When pull-down transistor 3002 is activated, WLO is disabled. Fig.30 The function is similar to that without the isolation transistor Fig.21 function.

[0150] Fig.31 A control gate decoder 3100 is depicted for exemplary control gate lines CG0, CG1, CG2, and CG3. Exemplary control gate line CG0 is coupled to a pull-up transistor 3101 and a pull-down transistor 3102. When pull-up transistor 3101 is activated, CG0 is enabled. When pull-down transistor 3102 is activated, CG0 is disabled. Fig.31 The selection and deselection functions are similar to Fig.30 The selection and deselection functions for the control grid.

[0151] Fig.32 Depicted is a control gate decoder 3200 for exemplary control gate lines CG0, CG1, CG2, and CG3. Control gate decoder 3200 is similar to control gate decoder 3100, except that control gate decoder 3200 includes capacitors (such as capacitor 3203) coupled to each control gate line. These sample-and-hold (S / H) capacitors can provide a precharge bias on each control gate line prior to operation, meaning that the voltage on the S / H capacitors will serve as a (floating) voltage source for the control gate lines. The S / H capacitors can be provided by the control gate capacitance from the memory cells.

[0152] Fig.33 A control gate decoder 3300 is depicted for exemplary control gate lines CG0, CG1, CG2, and CG3. Control gate decoder 3300 is similar to control gate decoder 3200, except that control gate decoder 3300 also includes a buffer 3301 (such as an opa).

[0153] Fig.34A current to voltage circuit 3400 is depicted. The circuit includes a configured diode connected reference cell circuit 3450 and a sample and hold circuit 3460. Circuit 3450 includes an input current source 3401, an NMOS transistor 3402, a cascode bias transistor 3403, and a reference memory cell 3404. The sample and hold circuit is composed of a switch 3405 and a S / H capacitor 3406. The memory 3404 is biased in a diode connected configuration with the bias on its bit line used to convert the input current into a voltage, such as for supplying a word line.

[0154] Fig.35 A current-to-voltage circuit 3500 is depicted, which is similar to the current-to-voltage circuit 3400, with an amplifier 3501 added after the S / H capacitor. The current-to-voltage circuit 3500 includes a configured diode-connected reference cell circuit 3550, a sample-and-hold circuit 3470, and an amplifier stage 3562.

[0155] Fig.36 A current to voltage circuit 3600 is depicted, which is designed the same as the current to voltage circuit 3400 with a control gate configured in a diode connection. The current to voltage circuit 3600 includes a diode connected reference cell circuit 3650 and a sample and hold circuit 3660 configured.

[0156] Fig.37 A current-to-voltage circuit 3700 is shown in which a buffer 3790 is placed between the reference circuit 3750 and the S / H circuit 3760.

[0157] Fig.38 Depicted is a current-to-voltage circuit 3800 that is similar to Fig.35 , wherein the control gate is connected in a diode connection configuration. The current to voltage circuit 3800 includes a configured diode connected reference cell circuit 3550, a sample and hold circuit 3870, and an amplifier stage 3862.

[0158] Fig.39 Depicted is a current-to-voltage circuit 3900 similar to that used in Figure 2 The memory cells in Fig.34 The current-to-voltage circuit 3900 includes a configured diode-connected reference unit circuit 3950 and a sample-and-hold circuit 3960 .

[0159] Fig.40 Depicted is a current-to-voltage circuit 4000 similar to that used in Figure 2 The memory cells in Fig.37, where the buffer 4090 is placed between the reference circuit 4050 and the S / H circuit 4060.

[0160] Fig.41 A current to voltage circuit 4100 is depicted, which is similar to the current to voltage circuit 4100 applied to Figure 2 The memory cells in Fig.38 The current-to-voltage circuit 4100 includes a configured diode-connected reference cell circuit 4150 , a sample-and-hold circuit 4170 , and an amplifier stage 4162 .

[0161] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intermediate material, element, or space is provided between) and "indirectly on" (intermediate material, element, or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space is provided between) and "indirectly adjacent" (intermediate material, element, or space is provided between), "mounted to" includes "directly mounted to" (no intermediate material, element, or space is provided between) and "indirectly mounted to" (intermediate material, element, or space is provided between), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element electrically connecting the elements together between) and "indirectly electrically coupled to" (intermediate material or element electrically connecting the elements together between). For example, forming an element "above a substrate" may include directly forming the element on the substrate without intermediate materials / elements between the two, and indirectly forming the element on the substrate with one or more intermediate materials / elements between the two.

Claims

1. A bit line decoder circuit coupled to a vector-matrix multiplication array, the vector-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line, the bit line decoder circuit comprising: a first circuit for enabling individual bit lines during programming and verifying operations; and A second circuit is provided for enabling all bit lines during a read operation.

2. The bit line decoder circuit of claim 1, wherein the second circuit comprises a select transistor and an activation function circuit coupled to each bit line.

3. The bit line decoder circuit of claim 2, wherein the gate of each select transistor is coupled to the same control line.

4. The bit line decoder circuit of claim 1, wherein a negative bias is applied to the word line of each unselected memory cell during a program and verify operation or a read operation.

5. The bit line decoder circuit of claim 1, wherein each of the nonvolatile memory cells is a split gate flash memory cell.

6. The bit line decoder circuit of claim 1, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

7. The bit line decoder circuit of claim 1, wherein each of the non-volatile memory cells is configured to operate in a sub-threshold region.

8. The bit line decoder circuit of claim 1, wherein each of the nonvolatile memory cells is configured to operate in a linear region.

9. The bit line decoder circuit of claim 1, wherein a negative bias is applied to a gate of each unselected bit line decoder during a program and verify operation or a read operation.

10. A bit line decoder circuit coupled to a vector-matrix multiplication array, the vector-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each column is connected to a bit line, the bit line decoder circuit comprising: A multiplexing circuit wherein in a first mode the multiplexing circuit enables individual bit lines during program and verify operations and in a second mode the multiplexing circuit enables all bit lines during read operations.

11. The bit line decoder circuit of claim 10, wherein the multiplexing circuit comprises a select transistor and an activation function circuit coupled to each bit line.

12. The bit line decoder circuit of claim 10, wherein a negative bias is applied to the word line of each unselected memory cell during a program and verify operation or a read operation.

13. The bit line decoder circuit of claim 10, wherein each of the non-volatile memory cells is a split gate flash memory cell.

14. The bit line decoder circuit of claim 10, wherein each of the non-volatile memory cells is a stacked gate flash memory cell.

15. The bit line decoder circuit of claim 10, wherein each of the non-volatile memory cells is configured to operate in a sub-threshold region.

16. The bit line decoder circuit of claim 10, wherein each of the non-volatile memory cells is configured to operate in a linear region.

17. The bit line decoder circuit of claim 10, wherein a negative bias is applied to a gate of each unselected bit line decoder during a program and verify operation or a read operation.

18. A word line driver coupled to a vector-matrix multiplication array, the vector-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each row is coupled to a word line and each word line is coupled to the word line driver, the word line driver comprising: a plurality of select transistors, each of the plurality of select transistors comprising a first terminal, a second terminal, and a gate, wherein the gate of each of the plurality of select transistors is coupled to a common control line, and wherein the first terminal of each of the plurality of select transistors is coupled to a different word line, and wherein the second terminal of each of the plurality of select transistors is coupled to one or more bias transistors; The bias transistor coupled to each of the plurality of select transistors is capable of providing a bias voltage to a single select transistor or to all of the select transistors.

19. The word line driver of claim 18, wherein at least one bias transistor coupled to each of the plurality of select transistors is coupled to a common control line.

20. The word line driver of claim 18, wherein each bias transistor coupled to each select transistor of the plurality of select transistors is coupled to a different control line.

21. The word line driver of claim 18, wherein each of the bias transistors is coupled to a circuit for decoding a word line address.

22. The word line driver of claim 18, wherein the bias transistor is coupled to a shift register.

23. The word line driver of claim 18, wherein each select transistor is coupled to a capacitor.

24. The word line driver of claim 18, wherein each bias transistor is coupled to a comparator.

25. A current-to-voltage circuit, the circuit comprising: a reference circuit, the reference circuit being configured to receive an input current and output a first voltage in response to the input current, the reference circuit comprising an input current source, an NMOS transistor, a cascode bias transistor, and a reference memory cell; A sampling and holding circuit is used to receive the first voltage and output a second voltage, wherein the second voltage constitutes a sampled value of the first voltage, and the sampling and holding circuit includes a switch and a capacitor.

26. The current-to-voltage circuit of claim 25, further comprising an amplifier for receiving the second voltage and outputting a third voltage.

27. The current-to-voltage circuit of claim 25, wherein the second voltage is provided to a word line in a flash memory system.

28. The current-to-voltage circuit of claim 26, wherein the third voltage is provided to a word line in a flash memory system.

29. The current-to-voltage circuit of claim 25, wherein the second voltage is provided to a control gate line in a flash memory system.

30. The current-to-voltage circuit of claim 26, wherein the third voltage is provided to a control gate line in a flash memory system.

31. A current-to-voltage circuit, the circuit comprising: a reference circuit, the reference circuit being configured to receive an input current and output a first voltage in response to the input current, the reference circuit comprising an input current source, an NMOS transistor, a cascode bias transistor, and a reference memory cell; an amplifier, the amplifier being configured to receive the first voltage and output a second voltage; A sampling and holding circuit is used to receive the second voltage and output a third voltage, wherein the third voltage constitutes a sampling value of the second voltage, and the sampling and holding circuit includes a switch and a capacitor.

32. The current-to-voltage circuit of claim 31, wherein the third voltage is provided to a word line in a flash memory system.

33. The current-to-voltage circuit of claim 31, wherein the third voltage is provided to a control gate line in a flash memory system.

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